Artificial synaptic device based on vertical nanowire array as well as preparation method and application of artificial synaptic device

Abstract

The invention belongs to the technical field of microelectronics, and particularly relates to an artificial synaptic device based on a vertical nanowire array and a preparation method and application of the artificial synaptic device. The synaptic device comprises a substrate, a bottom electrode layer, an insulating template, a vertex electrode layer and a nanowire array. And the bottom electrode layer, the insulating template and the top electrode layer form a sandwich structure. The insulating template internally comprises a large number of vertically through nanopores, and the nanowire array is filled in the nanopores and is formed by a chalcogenide semiconductor material or a topological insulator material with rich defect states; one end of the nanowire array is electrically contacted with the bottom electrode layer, and a barrier layer is arranged between the other end of the nanowire array and the top electrode layer. Reversible switching of the device between a volatile threshold switching mode and a non-volatile resistive random access memory mode can be realized by adjusting the magnitude and the direction of a scanning voltage and a limiting current applied between the top electrode and the bottom electrode; the device overcomes the defects of a traditional device in the aspects of functional flexibility and structural reliability.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to an artificial synaptic device based on a vertical nanowire array and its fabrication method, as well as the application of this artificial synaptic device in novel computing devices and intelligent bionic devices. Background Technology

[0002] With the explosive growth of artificial intelligence (AI), the Internet of Things (IoT), and big data technologies, society's demand for computing power and energy efficiency in computing systems is increasing exponentially. However, traditional computing systems based on the von Neumann architecture face severe "memory wall" bottlenecks and huge data transmission power consumption problems due to the physical separation of storage and computing units. Neuromorphic computing architecture, inspired by the working mechanism of the human brain, is considered a key technological route to overcome the above bottlenecks and realize the next generation of efficient intelligent computing systems by simulating the in-memory computing characteristics of biological neurons and synapses at the hardware level. Among the various components used to build neuromorphic hardware, memristors have become a research hotspot in academia and industry due to their simple structure, high integration density, and conductance tunability (plasticity) similar to biological synapses. Although memristor technology has made significant progress, existing device technologies still face several insurmountable key technological bottlenecks when facing complex biometric recognition and edge computing applications.

[0003] The first challenge lies in the contradiction between functional singularity and system complexity. The biological brain is a highly complex system capable of seamlessly integrating transient sensory information processing (corresponding to short-range plasticity, STP) and long-term memory storage (corresponding to long-range plasticity, LTP). However, existing memristor devices typically possess only a single physical characteristic. For volatile devices, namely threshold switches (TS), the state disappears once the voltage is removed. These devices are suitable for use as gates or to simulate the firing function of neurons, but cannot store weights. For non-volatile devices, namely resistive random access memories (RS), the state can be maintained for a long time. These devices are suitable for storing synaptic weights, but lack the ability to process temporal dynamic information. Currently, in order to simultaneously realize sensory and memory functions in a system, mainstream solutions have to adopt complex hybrid circuit architectures, such as connecting volatile and non-volatile devices in series and parallel, or introducing additional capacitors and transistors. This not only greatly increases the design complexity and chip area of ​​the circuit, but also severely sacrifices the system's energy efficiency. Therefore, how to achieve flexible switching (reconfigurability) between volatile and non-volatile functions in a single device through simple operation is a core problem that urgently needs to be solved in this field.

[0004] The second challenge lies in the physical limitations of planar thin-film structures. Most current mainstream memristors employ a "sandwich" planar thin-film structure. At the micro- and nano-scale, the formation and growth of conductive filaments in a planar thin film are inherently random. In high-density cross-arrays, the lack of physical isolation in planar structures allows conductive channels to potentially diffuse laterally, leading to electrical crosstalk and leakage current between adjacent devices, severely impacting recognition accuracy. Furthermore, the randomly generated conductive filaments result in significant performance differences between devices and between different cycles of the same device. These structural limitations make it difficult to achieve truly large-scale, high-reliability array integration of planar thin-film-based memristors.

[0005] The third challenge is the limitation of traditional material systems. Existing memristor materials are mainly concentrated in metal oxides (such as HfOx and TaOx). Although the processes are mature, these materials often exhibit problems such as high nonlinearity and poor intermediate state retention when simulating synaptic weight modulation. Summary of the Invention

[0006] To address the significant shortcomings of existing memristor-based artificial synapse devices in terms of functional flexibility and structural reliability, this invention provides an artificial synapse device based on a vertical nanowire array, its fabrication method, and its application in novel computing devices and intelligent biomimetic devices.

[0007] This invention is achieved using the following technical solution: An artificial synaptic device based on a vertical nanowire array includes: a substrate, a bottom electrode layer, an insulating template, a top electrode layer, and a nanowire array.

[0008] The structure comprises a bottom electrode layer located above the substrate; an insulating template located above the bottom electrode layer, containing multiple vertically interconnected nanopores arranged in an array; a top electrode layer located above the insulating template; and the bottom electrode layer, insulating template, and top electrode layer forming a sandwich structure. The nanowire array consists of nanowires filling the nanopores within the insulating template; the nanowires are formed from chalcogenide semiconductor materials or topological insulator materials with abundant defect states; one end of the nanowire array is electrically contacted with the bottom electrode layer, and the other end has a barrier layer between it and the top electrode layer; this barrier layer assists in the formation of the conductive metal filaments and restricts their lateral diffusion.

[0009] In the artificial synapse device provided by this invention, the scanning voltage V applied between the top electrode and the bottom electrode can be adjusted. sv With limiting current I cc The size and orientation of the device enable reversible switching between volatile threshold switching mode and non-volatile resistive switching memory mode.

[0010] As a further improvement of the present invention, the mode switching logic of the artificial synapse device based on the vertical nanowire array is as follows: (1) When the direction of the limiting current is positive and I cc When the current is ≤10 µA, the device is in volatile threshold switching mode: At this point, if the scanning voltage between the top electrode and the bottom electrode exceeds the threshold voltage V th The device is in a low-resistance state when the scan voltage is removed or the scan voltage is reduced to the holding voltage V. hold Below this, the device is in a high-impedance state; V th >V hold .

[0011] (2) When the limiting current I cc At ≥100 µA, the device is in non-volatile resistive switching storage mode; At this time, if the scanning voltage direction is positive, the device maintains a low resistance state; if the scanning voltage direction is negative, the device maintains a low resistance state; and the device resistance state remains unchanged after the scanning voltage is removed.

[0012] As a further improvement of the present invention, the substrate is made of ITO conductive glass or conductive silicon substrate.

[0013] As a further improvement of the present invention, the insulating template is an anodized aluminum template, the pore size of which ranges from 10 to 500 nm, the pore spacing is from 20 to 1000 nm, and the pore depth is from 2 to 15 μm.

[0014] As a further improvement of the present invention, the material of the nanowire array is any one or a combination of Bi2Se3, Bi2Te3, and Sb2Te3, and each nanowire has a large number of intrinsic vacancy defects composed of selenium vacancies or tellurium vacancies.

[0015] As a further improvement of the present invention, the material of the top electrode layer is selected from Ag, Cu or an alloy containing any one of the above elements; the material of the bottom electrode layer is selected from Pt, Au or an alloy containing any one of the above elements, titanium nitride or indium tin oxide.

[0016] As a further improvement of the present invention, the nanowire array is in direct contact with the top electrode to form a Schottky barrier or heterojunction interface, thereby constituting the desired barrier layer. Alternatively, an interface buffer layer is provided between the nanowire array and the top electrode to serve as the desired barrier layer.

[0017] As a further improvement of the present invention, the interface buffer layer is formed of any one or more materials selected from polymethyl methacrylate, polyvinyl alcohol, alumina, hafnium oxide and silicon dioxide.

[0018] The present invention also includes a method for fabricating an artificial synaptic device, which is used to fabricate the aforementioned artificial synaptic device based on a vertical nanowire array. The fabrication method includes the following steps: An insulating template with multiple vertically penetrating nanopores arranged in an array is prepared in advance. A metal thin film of a specified material is deposited on one side of the template as a bottom electrode layer. The deposition thickness is such that the opening of the nanopores on that side can be completely sealed and a continuous conductive layer is formed.

[0019] The insulating template forming the bottom electrode layer is transferred and fixed onto a pre-prepared substrate, so that the bottom electrode layer and the substrate are closely attached to form an electrical contact; and the edges of the insulating template are coated and cured.

[0020] Nanowires of a specified material are grown from the bottom up within nanopores using an electrochemical deposition method until their height meets the requirements.

[0021] The product from the previous step was heat-treated in an inert atmosphere to improve the crystallinity of the nanowires and induce the generation of intrinsic point defects with controllable density.

[0022] An electrochemically active metal array is deposited on the other side of an insulating template using a mask or photolithography lift-off process as the top electrode layer of the device, and the required barrier layer is formed using any process according to the structural design.

[0023] As a further improvement of the present invention, the metal thin film deposition method used for the bottom electrode layer and the top electrode layer is selected as magnetron sputtering, electron beam evaporation or thermal evaporation.

[0024] As a further improvement of the present invention, the inert atmosphere is high-purity nitrogen or argon; the heat treatment method is selected from tube furnace annealing or rapid hot annealing; the annealing time is 1~120min; and the annealing chamber pressure is atmospheric pressure or slightly positive pressure.

[0025] As a further improvement of this invention, when generating nanowires within an insulating template using electrochemical deposition, a three-electrode electrochemical deposition system is constructed using a bottom electrode layer as the working electrode, a platinum sheet or graphite as the counter electrode, and a saturated calomel electrode as the reference electrode; an acidic electrolyte containing functional layer metal ions and chalcogen element precursors is prepared; nanowire growth is controlled using a constant potential deposition method or a pulsed potential deposition method; the criteria for determining the termination of deposition are the observation of a significant current mutation in the current-time curve, or the control of the deposition time according to a pre-calibrated growth rate; As a further improvement of the present invention, a complexing agent or surfactant is added to the electrolyte to improve the growth morphology of the nanowires.

[0026] As a further improvement of the present invention, the barrier layer is an interface buffer layer composed of polymethyl methacrylate, polyvinyl alcohol, alumina, hafnium oxide, or silicon dioxide; the preparation process includes: First, an interface buffer layer of a specified thickness, made of polymethyl methacrylate or polyvinyl alcohol, is formed on top of an insulating template with a nanowire array by spin coating followed by etching; or an interface buffer layer of a specified thickness, made of alumina, hafnium oxide or silicon dioxide, is formed by atomic layer deposition or physical vapor deposition. An electrochemically active metal array is then deposited on the surface of the interface buffer layer as the top electrode layer of the device.

[0027] The present invention also includes the application of an artificial synaptic device based on a vertical nanowire array, as described above, in novel computing devices and intelligent bionic devices.

[0028] The technical solution provided by this invention has the following beneficial effects: 1. Breaking through the functional bottleneck of single devices and achieving flexible reconfiguration of "in-memory computing": This invention abandons the traditional approach of achieving different functions through complex circuit combinations. By simply changing the external limiting current, it can stimulate drastically different volatile and non-volatile characteristics in a single device. This greatly simplifies the circuit architecture of neuromorphic chips, enabling the same hardware unit to dynamically switch between "sensory neurons" and "memory synapses" according to task requirements.

[0029] 2. The vertical array structure completely solves the crosstalk problem in high-density integration: This invention utilizes the physical confinement effect of porous templates such as AAO to strictly restrict the growth of conductive filaments within the nanopores. This geometric structure physically cuts off the leakage current path between adjacent devices, eliminates the electrical crosstalk phenomenon commonly found in planar devices, significantly improves the consistency and yield of the device array, and provides a reliable hardware foundation for large-scale high-density integration.

[0030] 3. High-precision analog weight adjustment achieved through a synergistic mechanism: This invention utilizes the synergistic effect of active metal conductive filaments and the trap-dominated space charge confinement current (SCLC) mechanism in nanowire materials. Unlike the abrupt conduction of filaments in traditional oxide devices, the SCLC mechanism utilizes the defect states of the material itself to achieve smooth and continuous current adjustment, thereby endowing the device with extremely high analog linearity and multi-level storage capability, achieving a recognition accuracy of up to 93% in complex tasks such as fingerprint recognition.

[0031] 4. Low process cost and strong compatibility: The core nanowire array of this invention is prepared by electrochemical deposition process. Compared with expensive molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD), this method has simple equipment, low cost and is easy to achieve large-area preparation, and has extremely high potential for industrial application. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the artificial synapse device based on a vertical nanowire array provided in Embodiment 1 of the present invention.

[0033] Figure 2 This is a cross-sectional electron microscope image of the nanowire array in the artificial synaptic device fabricated in the test example.

[0034] Figure 3 This is a side electron microscope image of the nanowire array in the artificial synaptic device fabricated in the test example.

[0035] Figure 4 The bidirectional IV scan curves of the device under different limiting currents during the test experiment.

[0036] Figure 5 Statistical analysis of the key switching voltages of the device in different modes during the test experiment.

[0037] Figure 6 The bidirectional IV scan curve of the device in the test experiment with a current limit of 10 µA.

[0038] Figure 7 The bidirectional IV scan curve of the device in the test experiment with a current limit of 300 µA.

[0039] Figure 8 The device's cyclic characteristic curves after 40 cycles with a current limit of 10 µA in the test experiment.

[0040] Figure 9 The device's cyclic characteristic curves after 40 cycles at a current limit of 300 µA during the test experiment.

[0041] Figure 10 The resistance distribution of the device after more than 100 setup / reset cycles in the test experiment.

[0042] Figure 11 The bidirectional IV scan curves of the device under different reset voltages in the test experiment.

[0043] Figure 12 The retention characteristics of the device under different resistance states in the test experiment.

[0044] Figure 13 The device simulates the pairing pulse facilitation characteristic curve in a biological synapse during the test experiment.

[0045] Figure 14 The device simulates the pairing pulse suppression characteristic curve in a biological synapse during the test experiment.

[0046] Figure 15 The test experiment simulated the long-term enhancement and long-term inhibition characteristics of the device in biological synapses. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0048] Example 1 To address the problems of limited functionality, high crosstalk in planar structures, and low simulation accuracy in existing artificial synaptic devices, this embodiment provides an artificial synaptic device based on a vertical nanowire array. This novel device utilizes the physical confinement effect of the vertical nanowire array to solve the crosstalk problem in high-density integration, and controls the morphological stability of the conductive filaments by limiting the current. This allows for the simultaneous implementation of both volatile threshold switching and non-volatile resistive switching memory operating modes in a single device, with support for free switching between the two modes.

[0049] Specifically, such as Figure 1 As shown, this embodiment provides an artificial synapse device based on a vertical nanowire array, comprising: a substrate, a bottom electrode layer, an insulating template, a vertex electrode layer, and a nanowire array.

[0050] The bottom electrode layer is located above the substrate; the insulating template is located above the bottom electrode layer and contains multiple arrayed and vertically interconnected nanopores. The top electrode layer is located above the insulating template; the bottom electrode layer, insulating template, and top electrode layer constitute a sandwich structure. In practical applications, the substrate can be an ITO conductive glass or conductive silicon substrate with a certain thickness and good support. The insulating template can be an anodized aluminum template or other insulating template materials with a large number of vertical porous structures. In a typical embodiment, the pore size of the nanopores in the insulating template ranges from 10 to 500 nm, and the pore spacing is 20 to 1000 nm to achieve high-density physical isolation; the pore depth is equal to the template thickness, which is approximately 2 to 15 μm in this embodiment. In a more optimized scheme, the material of the top electrode layer can be an electrochemically active metal material, such as Ag (silver), Cu (copper), or an alloy containing any of the above elements; the material of the bottom electrode layer is also an excellent conductive material, and in order to ensure the weather resistance of the device, Pt (platinum), Au (gold), or an alloy containing any of the above elements, titanium nitride (TiN), or indium tin oxide (ITO) can be preferred.

[0051] The nanowire array is composed of nanowires filling nanopores within an insulating template. In this embodiment, the nanowires can be formed from a chalcogenide semiconductor material or a topological insulator material with abundant defect states. Optional chalcogenide semiconductor materials include any one or more of bismuth selenide (Bi₂Se₃), bismuth telluride (Bi₂Te₃), and antimony telluride (Sb₂Te₃), which possess a high concentration of intrinsic vacancy defects (such as selenium or tellurium vacancies) to aid in charge capture and release. Since the nanowire array is located within an insulating template between a sandwich-structured top electrode layer and a bottom electrode layer, the two ends of each nanowire are close to the top and bottom electrode layers, respectively.

[0052] Specifically, to achieve both volatile threshold switching and non-volatile resistive switching storage functions, one end of the nanowire array in this embodiment is electrically contacted with the bottom electrode layer, and the other end has a barrier layer between it and the top electrode layer. The barrier layer can regulate the growth of the conductive filaments and prevent excessive diffusion of the electrode material, thereby achieving functional switching and resistive state adjustment. In practical applications, the barrier layer between the nanowire array and the top electrode layer can be implemented in different ways. In the first implementation, the nanowire array and the top electrode can be fabricated using two specific materials, which are in direct contact and form a Schottky barrier or heterojunction interface under specific process conditions, thus constituting the desired barrier layer. In the second implementation, an interface buffer layer made of an insulating material can also be directly placed between the nanowire array and the top electrode as the desired barrier layer. In the typical scheme provided in this embodiment, the interface buffer layer is formed from any one or more of the following materials: polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), alumina (Al2O3), hafnium oxide (HfO2), and silicon dioxide (SiO2).

[0053] exist Figure 1 In the artificial synapse device shown, the scanning voltage V applied between the top and bottom electrodes can be adjusted. sv Compliance Current I cc The size and orientation of the device enable reversible switching between volatile threshold switching mode and non-volatile resistive switching memory mode. Specifically, the mode switching logic of the artificial synapse device based on a vertical nanowire array is as follows: (1) When the direction of the limiting current is positive and I cc When the current is ≤10 µA, the device is in volatile threshold switching mode: At this point, if the scanning voltage between the top electrode and the bottom electrode exceeds the threshold voltage V th The device is in a low-resistance state when the scan voltage is removed or the scan voltage is reduced to the holding voltage V. hold Below this, the device is in a high-impedance state; Vth >V hold .

[0054] Specifically, the limiting current of the external circuit is set to be in a low current range (e.g., I). cc A forward scan voltage (≤10 µA) is applied to the device. Under this condition, an extremely fine and thermodynamically unstable metallic conductive filament is formed inside the device. When the scan voltage exceeds the threshold voltage (V... th When the voltage is removed or the voltage drops to the holding voltage (V), the device transitions from a high-resistance state (HRS) to a low-resistance state (LRS); when the voltage is removed or the voltage drops to the holding voltage (V), the device transitions from a high-resistance state (HRS) to a low-resistance state (LRS). hold When the impedance is below a certain value, the unstable conductive filament spontaneously breaks, and the device automatically returns to a high-resistance state, exhibiting unidirectional threshold switching characteristics. This mode is used to simulate the short-range plasticity (STP) of biological synapses, and achieves double-pulse facilitation (PPF) and double-pulse suppression (PPD) functions by changing the pulse interval, for processing transient timing information.

[0055] (2) When the limiting current I cc At ≥100 µA, the device is in non-volatile resistive switching storage mode; At this time, if the scanning voltage direction is positive, the device maintains a low resistance state; if the scanning voltage direction is negative, the device maintains a low resistance state; and the device resistance state remains unchanged after the scanning voltage is removed.

[0056] Specifically, the limiting current of the external circuit is set to be in the high current range (e.g., I). cc A forward scanning voltage (≥100 µA) is applied to the device (equivalent to the SET process). Under this condition, a robust and thermodynamically stable conductive filament forms inside the device, which can overcome surface energy contraction and exist stably. After the device switches to the low-resistivity state (LRS), the resistance state remains unchanged even after the voltage is removed. A reverse voltage (RESET process) is required to melt or retract the conductive filament, restoring the device to the high-resistivity state. This mode is used to simulate the long-range plasticity (LTP / LTD) of biological synapses and to perform multi-level simulated weighted storage. In this mode, by adjusting the amplitude of the reverse reset voltage, the conductance can be continuously and linearly adjusted in conjunction with the trap-filled state (SCLC mechanism) inside the nanowire.

[0057] Based on the preceding text Figure 1 As can be seen from the description of the operating logic and functional principle of the artificial synaptic device, the device can switch from the current volatile operating cycle to a non-volatile operating cycle and vice versa, without changing its physical structure or connection method. Therefore, it has good reversible switching performance.

[0058] Example 2 This embodiment further provides a method for fabricating an artificial synaptic device, which is used to fabricate the artificial synaptic device based on a vertical nanowire array as provided in Example 1. The fabrication method includes the following steps: (1) Prepare an insulating template with multiple vertically penetrating nanopores arranged in an array, and deposit a metal thin film of a specified material on one side of the template as a bottom electrode layer. The deposition thickness is such that the nanopore openings on that side can be completely sealed and a continuous conductive layer can be formed.

[0059] In this embodiment, the insulating template can be any commercially available porous insulating template with vertical through-holes, such as anodized aluminum oxide (AAO) templates, where the hole diameter and density should be within the range specified above. The desired low electrode is formed by depositing a dense metal film on one side surface of the porous insulating template. In this embodiment, the thickness of the bottom electrode layer is approximately 200-1000 nm. The bottom electrode metal is selected from platinum, gold, titanium nitride, or indium tin oxide, and deposition is achieved through magnetron sputtering, electron beam evaporation, or thermal evaporation.

[0060] (2) Transfer and fix the insulating template forming the bottom electrode layer onto the prepared substrate so that the bottom electrode layer and the substrate are closely attached to form an electrical contact; and coat and cure the edges of the insulating template.

[0061] In this embodiment, after the side of the porous insulating template in which the bottom electrode layer is deposited is closely bonded to the ITO glass or silicon substrate, a good electrical contact can be formed. Subsequently, the edge of the insulating template can be coated and cured using an insulating sealant or polymer solution (such as PMMA solution) to prevent leakage or short circuit during subsequent electrochemical deposition.

[0062] (3) Nanowires of the specified material are grown from bottom to top in nanopores by electrochemical deposition until their height meets the requirements.

[0063] Specifically, in this embodiment, on the one hand, a three-electrode electrochemical deposition system is constructed using a bottom electrode layer (leading out through a conductive support substrate) as the working electrode, a platinum sheet or graphite as the counter electrode, and a reference electrode (such as a saturated calomel electrode) as the potential reference; on the other hand, a system containing functional layer metal ions (such as Bi) is prepared. 3+ An acidic electrolyte containing chalcogenide precursors (such as SeO2 or TeO2) is used; then, a constant potential deposition method or a pulsed potential deposition method is employed to control the deposition potential and time, so that the chalcogenide nanowires grow from the bottom up in the nanopores until the length of the nanowires is close to or slightly lower than the template thickness.

[0064] In practical applications, the electrochemical deposition process of nanowire arrays can be performed on an electrochemical workstation or a potentiostat. Complexing agents or surfactants can be added to the electrolyte to improve the growth morphology of the nanowires. During deposition, the system current changes with the growth height of the nanowires. The current change is small before the nanowires reach the top of the insulating template, but a sudden change occurs near the top. Therefore, the criterion for termination of deposition can be set by observing a significant current abrupt change in the current-time curve (it curve). Alternatively, the growth rate can be pre-calibrated under the current operating parameters, and the deposition time can be scientifically set based on the template height and growth rate.

[0065] (4) Heat-treat the product from the previous step in an inert atmosphere to improve the crystal quality of the nanowires and induce intrinsic point defects with controllable density.

[0066] In this embodiment, after the electrochemical deposition of the nanowire array is completed in the previous step, the sample can be placed in an annealing apparatus and heat-treated under an inert atmosphere. The annealing temperature and time are controlled to regulate the heat treatment effect. The heat treatment operation in this embodiment can improve the crystal quality of the nanowires on the one hand, and on the other hand, it can utilize the volatilization characteristics of elements (such as the volatilization of Se) to induce the generation of intrinsic point defects (such as vacancy defects) with controllable density inside or on the surface of the nanowires.

[0067] In practical applications, high-purity nitrogen (N2) or argon (Ar) is used as the inert atmosphere; heat treatment operations can be performed using tube furnace annealing or rapid thermal annealing (RTA); the annealing temperature is controlled between 200 and 500 ℃. Depending on the equipment, the annealing time can be controlled between 1 minute and 120 minutes; the annealing chamber pressure is atmospheric pressure or slightly positive pressure.

[0068] (5) An electrochemically active metal array is deposited on the other side of the insulating template as the top electrode layer of the device using a mask or photolithography lift-off process, and the required barrier layer is formed by any process according to the structural design.

[0069] In this embodiment, after forming the nanowire array, different process routes can be adopted according to the structural design of the artificial synapse device to obtain either a direct contact type between the top electrode layer and the nanowire array, or an isolation type where an interface buffer layer is also included between the top electrode layer and the nanowire array. The direct contact type involves directly depositing the top electrode layer on top of the insulating template forming the nanowire array, and then forming the required barrier layer between them through specific process conditions (such as high-temperature doping or ion implantation).

[0070] In practical applications, a low-cost method of setting an interface buffer layer is preferred to obtain the desired barrier layer. For example, the barrier layer in this embodiment is composed of polymethyl methacrylate, polyvinyl alcohol, alumina, hafnium oxide, or silicon dioxide. The fabrication process includes: firstly, forming an interface buffer layer of a specified thickness on top of an insulating template with a pre-formed nanowire array, covering the top of the nanowires, to assist in the formation of conductive metal filaments under a subsequent electric field and restrict their lateral diffusion. Then, an electrochemically active metal array is deposited on the surface of the interface buffer layer as the top electrode layer of the device. In practical applications, the top electrode layer can be formed in the form of units of different shapes and arranged in an array. The electrochemically active metal used in the top electrode layer is selected from silver (Ag), copper (Cu), or an alloy containing any one of these elements; the thickness of the top electrode is 50 nm to 500 nm.

[0071] Depending on the material, the formation method of the interface buffer layer also varies. For example, an interface buffer layer of a specified thickness made of polymethyl methacrylate or polyvinyl alcohol can be formed by spin coating followed by etching; or an interface buffer layer of a specified thickness made of alumina, hafnium oxide or silicon dioxide can be formed by atomic layer deposition or physical vapor deposition. The artificial synaptic device provided in this embodiment can achieve reconfigurable dual-mode operation in a single device and has better crosstalk immunity and linearity. Therefore, it can overcome the shortcomings of traditional devices and can be applied in novel computing devices or intelligent bionic devices.

[0072] To verify the performance and advantages of the artificial synaptic device provided by this invention, technicians developed an experimental plan to conduct sample trial production and performed performance tests on the manufactured samples.

[0073] Test Example 1 (a) Template preprocessing: A commercially available porous anodic aluminum oxide (AAO) template with a pore size of approximately 350 nm, a pore spacing of approximately 450 nm, and a thickness of 15 µm was selected. A dense platinum (Pt) film with a thickness of 500 nm was deposited on one side of the AAO template using magnetron sputtering. This Pt layer serves as the bottom electrode of the device, completely sealing one end of the nanopores while ensuring continuous conductivity of the metal layer.

[0074] (II) Template Transfer and Fixing: The AAO template with the Pt bottom electrode deposited in the previous step was transferred to a clean ITO glass substrate, ensuring that the Pt electrode surface was in close contact with the ITO conductive surface to form a good electrical connection. Subsequently, a polymethyl methacrylate (PMMA) solution was coated on the edges of the AAO template, and it was baked at 100 °C for 10 minutes for insulation curing to prevent subsequent leakage.

[0075] (III) Electrochemical deposition: A three-electrode system was constructed using the bottom electrode as the working electrode, a large-area platinum sheet as the counter electrode, and a saturated calomel electrode (SCE) as the reference electrode. An acidic electrolyte containing 3 mM bismuth nitrate (Bi(NO3)3•5H2O), 3 mM selenium dioxide (SeO2), and 1 M nitric acid (HNO3) was prepared. Bi2Se3 nanowires were grown from bottom to top at room temperature using pulsed potential deposition at a deposition potential of -0.03 V until a sudden current change was detected, indicating that the nanowires had filled the pores.

[0076] (iv) Annealing treatment: The deposited sample was placed in a tube furnace and heat-treated at 350°C for 40 minutes under an argon (Ar) atmosphere and normal pressure. During this process, the crystallinity of the Bi₂Se₃ nanowires increased, and due to the partial volatilization of Se, a high density of Se vacancy defects was induced inside the nanowires.

[0077] (v) Barrier layer deposition: A 2% PMMA solution was spin-coated onto the upper surface of the nanowire array (4000 rpm, 30 s), and then baked at 110 °C for 8 minutes to form an ultrathin interfacial barrier layer with a thickness of about 20 nm, which was used to regulate the conductive filament channels.

[0078] (vi) Fabrication of the top electrode layer: Using a metal mask with a circular opening (300 µm in diameter), a 300 nm thick silver (Ag) film was deposited on the surface of PMMA by magnetron sputtering as the top electrode, and the device was finally fabricated.

[0079] Test Example 2 (a) Template preprocessing: A commercially available porous anodic aluminum oxide (AAO) template with a pore size of approximately 50 nm, a pore spacing of approximately 100 nm, and a thickness of 5 µm was selected. A dense gold (Au) film with a thickness of 300 nm was deposited on one side of the AAO template using magnetron sputtering. This Au layer serves as the bottom electrode of the device, completely sealing one end of the nanopores while ensuring continuous conductivity of the metal layer.

[0080] (II) Template Transfer and Fixing: The AAO template with the Au bottom electrode deposited in the previous step was transferred onto a clean ITO glass substrate, ensuring close contact between the Au electrode surface and the ITO conductive surface to form a good electrical connection. Subsequently, a polymethyl methacrylate (PMMA) solution was coated onto the edges of the AAO template, and it was baked at 100 °C for 10 minutes for insulation curing to prevent subsequent leakage. (III) Electrochemical deposition: A three-electrode system was constructed using the bottom electrode as the working electrode, a large-area platinum sheet as the counter electrode, and a saturated calomel electrode (SCE) as the reference electrode. An acidic electrolyte containing 1.5 mM bismuth nitrate (Bi(NO3)3•5H2O), 1.5 mM selenium dioxide (SeO2), and 1 M nitric acid (HNO3) was prepared, with the electrolyte concentration adjusted to accommodate mass transfer limitations within the small pore size. Bi2Se3 nanowires were grown from bottom to top at room temperature using pulsed potential deposition (1 s deposition, 5 s resting) at a deposition potential of -0.03 V until a sudden current change was detected, indicating that the nanowires had filled the pores.

[0081] (iv) Annealing treatment: The deposited sample was placed in a tube furnace and heat-treated at 450°C for 20 minutes under a nitrogen (N2) atmosphere and normal pressure. During this process, the crystallinity of the Bi2Se3 nanowires increased, and due to the partial volatilization of Se, a high density of Se vacancy defects was induced inside the nanowires.

[0082] (v) Barrier layer deposition: A 2% PMMA solution was spin-coated onto the upper surface of the nanowire array (4000 rpm, 30 s), and then baked at 110 °C for 8 minutes to form an ultrathin interfacial barrier layer with a thickness of about 20 nm, which was used to regulate the conductive filament channels.

[0083] (vi) Fabrication of the top electrode layer: Using a metal mask with a circular opening (300 µm in diameter), a 300 nm thick silver (Ag) film was deposited on the surface of PMMA by magnetron sputtering as the top electrode, and the device was finally fabricated.

[0084] Test Example 3 (a) Template preprocessing: Same as Example 1.

[0085] (II) Template Transfer and Fixing: Same as Example 1.

[0086] (III) Electrochemical deposition: A three-electrode system was constructed using the bottom electrode as the working electrode, a large-area platinum sheet as the counter electrode, and a saturated calomel electrode (SCE) as the reference electrode. An acidic electrolyte containing 15 mM bismuth nitrate (Bi(NO3)3•5H2O), 10 mM tellurium dioxide (TeO2), and 1 M nitric acid (HNO3) was prepared. Bi2Te3 nanowires were grown from bottom to top at room temperature using pulsed potential deposition at a deposition potential of -0.04 V until a sudden current change was detected, indicating that the nanowires had filled the pores.

[0087] (iv) Annealing treatment: The deposited sample was placed in a tube furnace and heat-treated at 300°C for 40 minutes under an argon (Ar) atmosphere and normal pressure.

[0088] (v) Barrier layer deposition: Same as Example 1.

[0089] (vi) Fabrication of the top electrode layer: Same as Example 1.

[0090] Test Example 4 (a) Template preprocessing: Same as Example 1.

[0091] (II) Template Transfer and Fixing: Same as Example 1.

[0092] (III) Electrochemical deposition: Same as Example 1.

[0093] (iv) Annealing treatment: Same as Example 1.

[0094] (v) Barrier layer deposition: Same as Example 1.

[0095] (vi) Fabrication of the top electrode layer: Using a metal mask with a circular opening (150 µm in diameter), a 500 nm thick copper (Cu) thin film was deposited on the surface of PMMA by magnetron sputtering as the top electrode, and the device was finally fabricated.

[0096] Test Example 5 (a) Template preprocessing: Same as Example 1.

[0097] (II) Template Transfer and Fixing: Same as Example 1.

[0098] (III) Electrochemical deposition: Same as Example 1.

[0099] (iv) Annealing treatment: Same as Example 1.

[0100] (v) Barrier layer deposition: An aluminum oxide (Al2O3) film with a thickness of 15 nm was deposited on the upper surface of the nanowire array using atomic layer deposition technology to form an ultrathin interface barrier layer, which is used to regulate the conductive filament channels.

[0101] (vi) Fabrication of the top electrode layer: Same as Example 1.

[0102] Test Example 6 (a) Template preprocessing: Same as Example 1.

[0103] (II) Template Transfer and Fixing: Same as Example 1.

[0104] (III) Electrochemical deposition: A three-electrode system was constructed using the bottom electrode as the working electrode, a large-area platinum sheet as the counter electrode, and a saturated calomel electrode (SCE) as the reference electrode. An acidic electrolyte containing 3 mM bismuth nitrate (Bi(NO3)3•5H2O), 3 mM selenium dioxide (SeO2), and 1 M nitric acid (HNO3) was prepared. Bi2Se3 nanowires were grown from bottom to top at room temperature using pulsed potential deposition at a deposition potential of -0.03 V. The deposition time was precisely controlled so that the Bi2Se3 nanowires stopped growing at approximately 20 nm from the AAO surface, meaning the nanowires did not completely fill the pores and were slightly below the template surface.

[0105] (iv) Annealing treatment: Same as Example 1.

[0106] (V) Fabrication of the top electrode layer: Using a metal mask with a circular opening (300 µm in diameter), a 500 nm thick silver (Ag) film was directly deposited on the surface of the nanowire as the top electrode by magnetron sputtering, and the device was finally fabricated.

[0107] Performance testing 1. Microscopic morphology This experiment first used scanning electron microscopy (SEM) to observe the cross-section of the AAO template with Bi2Se3 nanowires deposited in Test Example 1, obtaining the following results: Figure 2 The image shown is an electron microscope photograph. The image shows that Bi2Se3 grows radially parallel along the pores.

[0108] This experiment further utilized potassium hydroxide solution to remove the AAO template, and then observed the lateral orientation of the Bi₂Se₃ nanowire array using SEM to obtain the following results: Figure 3The SEM image shown displays the high aspect ratio of the nanowires and reveals their dense arrangement.

[0109] 2. Functional testing (2.1) This experiment first tested the test example device under different limiting currents (I cc The electrical characteristics under the given conditions are plotted as follows, based on the experimental results. Figure 4 The bidirectional IV scan curves shown and as follows Figure 5 Statistical analysis of key switching voltages under different modes shown.

[0110] analyze Figure 4 The data shows that: at low I cc At values ​​(e.g., 1 µA and 10 µA), the device operates in unidirectional, volatile threshold switch (TS) mode. Increasing Icc to 100 µA or higher triggers a resistance transition, entering a non-volatile bipolar resistor switch (RS) storage mode.

[0111] Furthermore, statistical analysis of the key switching voltages of the device in different modes reveals that: in the threshold switching (TS) mode (Icc = 10 µA), the threshold voltage is concentrated at 1.39 V; while in the bipolar resistor switching (RS) mode (Icc = 300 µA), the set voltage and reset voltage are distributed around 2.76 V and -0.78 V, respectively.

[0112] (2.2) This experiment further tested the electrical characteristics of the device in the test case when the current limit was 10 µA and 300 µA, and the results are as follows: Figure 6 and Figure 7 The bidirectional IV scan curve is shown.

[0113] analyze Figure 6 The data shows that when the current limit is 10 µA, the device operates in unidirectional, volatile threshold switching (TS) mode. During the positive voltage scan, when the device reaches the threshold voltage (V... th When the voltage drops to zero, the current suddenly increases, and the device switches from a high-resistance state (HRS) to a low-resistance state (LRS). This LRS is unstable and spontaneously recovers to HRS when the voltage returns to zero without applying a negative bias. This self-resetting behavior is a fundamental characteristic of volatile switches, which is ideal for selector and artificial neuron applications.

[0114] analyze Figure 7The data shows that when the current limit is 300 µA, the device operates in a non-volatile bipolar resistive switch (RS) storage mode. In this mode, after a set transition (HRS → LRS), the LRS state is maintained, and a negative reset voltage is required to return the device to HRS. This is achieved through simple electrical parameters (e.g., ILRS). cc The ability to seamlessly switch between volatile and non-volatile states gives the device exceptional versatility.

[0115] 3. Reusability test This experiment further subjected the device in the test case to 40 cycles of testing in two operating modes with current limits of 10 µA and 300 µA, and obtained the following results: Figure 8 and Figure 9 The shown is a cyclic curve.

[0116] As can be seen from the data in the figure, both operating modes of the device exhibit excellent cyclic repeatability.

[0117] This experiment further performed more than 100 set / reset cycles on the device in bipolar resistive switch (RS) storage mode, obtaining the following results: Figure 10 The test results are shown in the figure. According to the data, the solution of this invention can maintain a stable high-resistivity / low-resistivity window even under continuous operation.

[0118] 4. Application Value This experiment further tested and plotted the bidirectional IV sweep curves of the device in the test case under different reset voltages, and the results are as follows: Figure 11 As shown in the diagram, analysis reveals that by precisely controlling the amplitude of the reset voltage scan at a fixed current of 300 µA, the device can be programmed to multiple different resistance states. A larger negative reset bias leads to a higher subsequent high-resistance state (HRS), thus progressively expanding the storage window. This simulated tunability is attributed to the synergistic effect of partial dissolution of the Ag conductive filaments and charge trapping / releasing in the Bi₂Se₃ nanowires.

[0119] This experiment further tested and plotted the retention characteristics of the device in the test case under different resistance states. The results are as follows: Figure 12 As shown in the figure, analysis reveals that the six different resistance levels remained stable with almost no degradation over a period of over 10,000 seconds. This reliable non-volatile multilevel storage capability demonstrates the enormous potential of TINW devices in high-density data storage and hardware-based neural network implementations.

[0120] This experiment further applies the testing to the devices in the test cases. Figure 13The device simulates the paired pulse facilitation (PPF) characteristics of a biological synapse, a fundamental short-term plasticity (STP) phenomenon in which the postsynaptic response to a second pulse is enhanced. When two consecutive presynaptic pulses (voltage amplitude 2 V, pulse width 1 µs) are applied, the current response produced by the second pulse (P2) is significantly greater than that of the first pulse (P1). Figure 14 The display shows the paired pulse suppression (PPD) characteristics of the device in a simulated biological synapse, where the synaptic response is suppressed. Successful simulations of PPF and PPD confirm that the device can replicate fundamental short-term synaptic dynamics at speeds from microseconds to nanoseconds.

[0121] Figure 15 The device's simulation curves demonstrate long-term potentiation (LTP) and long-term inhibition (LTD) characteristics in biological synapses. The foundation of brain learning and memory lies in long-term plasticity, the ability of synapses to continuously potentiate (LTP) or depress (LTD) their connection weights. In addition to short-term dynamics, this device effectively reproduces long-term plasticity. By applying 20 consecutive potentiation pulses (2.5 V, 500 µs) followed by 20 inhibition pulses (-2.5 V, 500 µs), the device's conductivity can be progressively and continuously modulated to multiple distinct states.

[0122] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An artificial synaptic device based on a vertical nanowire array, characterized in that, It includes: Substrate, The bottom electrode layer is located above the substrate; An insulating template, located above the bottom electrode layer, contains multiple arrayed and vertically interconnected nanopores. The top electrode layer is located above the insulating template; A nanowire array is composed of nanowires filling nanopores in an insulating template; the nanowires are formed of a chalcogenide semiconductor material or a topological insulator material with abundant defect states; one end of the nanowire array is electrically contacted with the bottom electrode layer, and the other end has a barrier layer between it and the top electrode layer; the barrier layer is used to assist in the formation of the metal conductive filaments and restrict their lateral diffusion. By adjusting the scanning voltage V applied between the top and bottom electrodes sv With limiting current I cc The size and orientation are adjusted to enable reversible switching of the device between volatile threshold switching mode and non-volatile resistive switching memory mode.

2. The artificial synaptic device based on a vertical nanowire array as described in claim 1, characterized in that: When the limiting current direction is positive and I cc When the current is ≤10 µA, the device is in volatile threshold switching mode; At this point, if the scanning voltage between the top electrode and the bottom electrode exceeds the threshold voltage V th The device is in a low-resistance state when the scan voltage is removed or the scan voltage is reduced to the holding voltage V. hold Below this, the device is in a high-impedance state; V th >V hold ; When the limiting current I cc At ≥100 µA, the device is in non-volatile resistive switching storage mode; At this time, if the scanning voltage direction is positive, the device maintains a low resistance state; if the scanning voltage direction is negative, the device maintains a low resistance state; and the device resistance state remains unchanged after the scanning voltage is removed.

3. The artificial synaptic device based on a vertical nanowire array as described in claim 1, characterized in that: The substrate is made of ITO conductive glass or a conductive silicon substrate; And / or, the insulating template is an anodized aluminum template, the pore size of which ranges from 10 to 500 nm, the pore spacing is from 20 to 1000 nm, and the pore depth is from 2 to 15 μm; And / or, the material of the nanowire array is any one or a combination of Bi2Se3, Bi2Te3, and Sb2Te3, and each nanowire has a large number of intrinsic vacancy defects composed of selenium vacancies or tellurium vacancies. And / or, the material of the top electrode layer is selected from Ag, Cu or an alloy containing any one of the above elements; the material of the bottom electrode layer is selected from Pt, Au or an alloy containing any one of the above elements, titanium nitride or indium tin oxide.

4. The artificial synaptic device based on a vertical nanowire array as described in claim 1, characterized in that: The nanowire array is in direct contact with the top electrode to form a Schottky barrier or heterojunction interface, thereby forming the desired barrier layer. Alternatively, an interface buffer layer can be placed between the nanowire array and the top electrode to serve as the desired barrier layer.

5. The artificial synaptic device based on a vertical nanowire array as described in claim 4, characterized in that: The interface buffer layer is formed of any one or more materials selected from polymethyl methacrylate, polyvinyl alcohol, alumina, hafnium oxide, and silicon dioxide.

6. A method for fabricating an artificial synaptic device, characterized in that: It is used to fabricate an artificial synaptic device based on a vertical nanowire array as described in any one of claims 1-5, comprising: An insulating template with multiple vertically penetrating nanopores arranged in an array is prepared in advance. A metal thin film of a specified material is deposited on one side of the template as a bottom electrode layer. The deposition thickness is such that the opening of the nanopores on that side can be completely sealed and a continuous conductive layer is formed. The insulating template forming the bottom electrode layer is transferred and fixed onto the pre-prepared substrate, so that the bottom electrode layer and the substrate are closely attached to form an electrical contact; and the edges of the insulating template are coated and cured. Nanowires of a specified material are grown from the bottom up in nanopores using an electrochemical deposition method until their height meets the requirements. The product from the previous step was heat-treated under an inert atmosphere to improve the crystallinity of the nanowires and induce the generation of intrinsic point defects with controllable density. An electrochemically active metal array is deposited on the other side of an insulating template using a mask or photolithography lift-off process as the top electrode layer of the device, and the required barrier layer is formed using any process according to the structural design.

7. The method for preparing the artificial synaptic device as described in claim 6, characterized in that: The metal thin film deposition methods used for the bottom electrode layer and the top electrode layer are magnetron sputtering, electron beam evaporation, or thermal evaporation. And / or, the inert atmosphere is high-purity nitrogen or argon; the heat treatment method is selected from tube furnace annealing or rapid hot annealing; the annealing time is 1~120min; the annealing chamber pressure is atmospheric pressure or slightly positive pressure.

8. The method for preparing the artificial synaptic device as described in claim 6, characterized in that: When nanowires are generated in an insulating template by electrochemical deposition, a three-electrode electrochemical deposition system is constructed with the bottom electrode layer as the working electrode, a platinum sheet or graphite as the counter electrode, and a saturated calomel electrode as the reference electrode; an acidic electrolyte containing functional layer metal ions and chalcogen element precursors is prepared. Nanowire growth is controlled by constant potential deposition or pulsed potential deposition. The criteria for termination of deposition are the observation of a significant current change in the current-time curve or the control of deposition time according to a pre-calibrated growth rate. And / or, complexing agents or surfactants are added to the electrolyte to improve the growth morphology of the nanowires.

9. The method for preparing the artificial synaptic device as described in claim 6, characterized in that: The barrier layer is an interface buffer layer composed of polymethyl methacrylate, polyvinyl alcohol, alumina, hafnium oxide, or silica; the preparation process includes: First, an interface buffer layer of a specified thickness, made of polymethyl methacrylate or polyvinyl alcohol, is formed on top of an insulating template with a nanowire array by spin coating followed by etching; or an interface buffer layer of a specified thickness, made of alumina, hafnium oxide or silicon dioxide, is formed by atomic layer deposition or physical vapor deposition. An electrochemically active metal array is then deposited on the surface of the interface buffer layer as the top electrode layer of the device.

10. The application of an artificial synaptic device based on a vertical nanowire array as described in any one of claims 1-5 in novel computing devices and intelligent bionic devices.

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