Method for realizing deep trench side wall doping

Abstract

The invention provides a method for realizing deep trench side wall doping. The method comprises the following steps: forming a deep trench on a substrate; forming a first dielectric layer on the inner surface of the deep trench; filling a solid-state doping source in the deep trench and removing an external redundant part; performing high-temperature annealing to enable the impurity ions to penetrate through the first dielectric layer to be diffused into the side wall substrate; removing the solid doping source and the first dielectric layer; and finally, forming a second dielectric layer and performing material backfilling. According to the method, a solid-state source high-temperature diffusion mechanism is utilized, the problem that the high-aspect-ratio deep groove, especially the side wall of the bottom of the groove, is difficult to effectively and uniformly dope is solved, and the method is suitable for manufacturing a low-cost and small-pitch super junction device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for achieving deep trench sidewall doping. Background Technology

[0002] With the rapid development of power semiconductor devices, especially superjunction (SJ) devices, the market demand for low on-resistance and high breakdown voltage characteristics is constantly increasing. Deep trench superjunction (DT-SJ) structures have become a research focus due to their superior performance. Currently, traditional DT-SJ ​​device manufacturing mainly relies on deep trench epitaxial filling (EPI) processes. However, this process is technically challenging, costly, and has a relatively narrow process window, limiting its large-scale application in low-cost products. Therefore, the industry has been actively exploring non-epitaxy deep trench superjunction (DT-SJ) manufacturing technologies.

[0003] In the non-epitaxy DT-SJ ​​process, a deep trench structure is typically formed on the substrate first. The core challenge then lies in achieving effective doping of the deep trench sidewalls (i.e., SJ doping process) to form the desired superjunction pillars. Especially for deep trenches with high aspect ratios (e.g., aspect ratio greater than 5), achieving uniform and controllable doping of the sidewalls, particularly the bottom sidewalls, is extremely difficult.

[0004] Common sidewall doping methods include tilted ion implantation, plasma vapor phase doping, or thin-layer epitaxy. However, these methods have limitations when dealing with high aspect ratio trenches, such as insufficient bottom doping due to the "shadowing effect," difficulty in controlling depth direction uniformity, or complex and costly processes.

[0005] Diffusion through an oxide layer using a solid-state source is one option, but the process requirements differ significantly depending on the conductivity type of the structure. When fabricating P-type pillars using an N-type substrate, a boron-containing P-type solid-state source is typically used. Boron exhibits a segregation coefficient in silicon oxide, readily exhibiting a "boron adsorption" phenomenon, allowing it to easily penetrate oxide layers of a certain thickness (e.g., below 1000 angstroms) into the silicon substrate. However, when fabricating N-type pillars using a P-type substrate, if conventional N-type impurities (such as phosphorus or arsenic) are used, the silicon oxide layer exhibits a "phosphorus repulsion" effect, making it difficult for the impurities to penetrate oxide layers of conventional thicknesses. Therefore, the design of the barrier dielectric layer thickness becomes crucial for different types of doping sources. Furthermore, to ensure device charge balance and breakdown voltage characteristics, the selection of subsequent filling materials for the trenches after doping is important if epitaxial processes are not employed.

[0006] Therefore, providing a method that can utilize a solid-state diffusion source to adapt to different conductivity types (especially N-type substrates with P-type sources, or P-type substrates with N-type sources) and effectively solve the problem of uniform doping on the sidewalls of high aspect ratio trenches is a technical problem that urgently needs to be solved in the current semiconductor manufacturing field. Summary of the Invention

[0007] This invention provides a method for achieving sidewall doping in deep trenches, in order to solve the technical problems in existing deep trench superjunction device manufacturing processes, such as the difficulty in achieving effective and uniform doping of deep trenches with high aspect ratios, especially the bottom sidewalls of the trenches, and the high cost and difficulty of epitaxial processes.

[0008] This invention provides a method for achieving deep trench sidewall doping, the method comprising the following steps:

[0009] Step 1: Form deep trenches on the substrate;

[0010] Step 2: Form a first dielectric layer on the inner surface of the deep trench;

[0011] Step 3: Fill the deep trench with a solid doping source and remove the solid doping source located outside the deep trench;

[0012] Step 4: Perform high-temperature annealing to allow impurity ions in the solid-state doped source to diffuse through the first dielectric layer into the sidewall substrate of the deep trench.

[0013] Step 5: Remove the solid doping source and the first dielectric layer from the deep trench;

[0014] Step 6: Form a second medium layer on the inner surface of the deep trench and backfill with filling material.

[0015] Preferably, in step one, the substrate is an N-type silicon substrate.

[0016] Preferably, in step three, the solid-state doping source is a P-type dopant.

[0017] Preferably, in step three, the doping element of the solid-state doping source is boron.

[0018] Preferably, in step two, the thickness of the first dielectric layer is no greater than 1000 angstroms.

[0019] Preferably, in step two, the thickness of the first dielectric layer is 400 to 600 angstroms.

[0020] Preferably, in step six, the filling material comprises N-type doped polycrystalline silicon.

[0021] Preferably, in step four, after the high-temperature annealing, the doping concentration formed in the sidewall substrate of the deep trench is from 5E16 atoms / cm³ to 8E17 atoms / cm³.

[0022] Preferably, in step four, the doped region formed on the sidewall of the deep trench is used to form a P-type pillar of a P-well or superjunction device.

[0023] Preferably, in step one, the substrate is a P-type silicon substrate.

[0024] Preferably, in step three, the solid-state doping source is an N-type dopant.

[0025] Preferably, in step two, the thickness of the first dielectric layer is 10 to 100 angstroms.

[0026] Preferably, in step one, the deep trench is formed by forming a hard mask layer on the substrate and etching based on the hard mask layer.

[0027] Preferably, in step one, the thickness of the hard mask layer is 1.5 micrometers to 2.5 micrometers.

[0028] Preferably, in step one, the material of the hard mask layer includes silicon oxide, silicon nitride, or a combination thereof.

[0029] Preferably, in step one, the aspect ratio of the deep trench is greater than 5.

[0030] Preferably, in step two, the material of the first dielectric layer is silicon oxide.

[0031] Preferably, in step two, the process for forming the first dielectric layer includes a furnace tube thermal oxidation process.

[0032] Preferably, in step two, the temperature of the thermal oxidation process is 1000 degrees Celsius to 1100 degrees Celsius.

[0033] Preferably, in step two, the thermal oxidation process takes 20 to 40 minutes.

[0034] Preferably, in step three, the material of the solid-state doping source is selected from any one of polycrystalline silicon, amorphous silicon, borosilicate glass, or borosilicate glass.

[0035] Preferably, in step three, the doping concentration of the solid-state doping source is at least 1E18 atoms / cm³.

[0036] Preferably, in step three, the doping concentration of the solid-state doping source is 2E20 atoms / cubic centimeter.

[0037] Preferably, in step three, the process of removing the solid dopant source located outside the deep trench includes a chemical mechanical polishing process.

[0038] Preferably, in step four, the high-temperature annealing temperature is between 1150 degrees Celsius and 1250 degrees Celsius.

[0039] Preferably, in step four, the high-temperature annealing time is greater than 30 minutes.

[0040] Preferably, in step five, the process of removing the solid dopant source is a dry etching process.

[0041] Preferably, in step five, the process of removing the first dielectric layer is a wet etching process.

[0042] Preferably, in step six, the second dielectric layer is a silicon oxide layer, and the thickness of the second dielectric layer is at least 1500 angstroms.

[0043] As described above, the method for achieving deep trench sidewall doping of the present invention has the following beneficial effects:

[0044] This invention successfully solves the problem of effective doping in high aspect ratio trenches, especially at the bottom sidewalls, by introducing a solid-state diffusion source within deep trenches and utilizing the ability of impurity ions to penetrate a thin oxide layer and enter the substrate sidewalls at high temperatures. Compared to traditional epitaxial filling processes, this invention significantly reduces process costs and complexity. Compared to tilted ion implantation or plasma doping, this invention achieves a more uniform doping distribution along the entire trench depth using solid-state source diffusion. Furthermore, by precisely controlling the thickness of the first dielectric layer for different conductivity types of doping sources (especially the boron absorption and phosphorus repulsion characteristics of P-type boron sources), the interface concentration and diffusion depth can be effectively controlled, making it suitable for fabricating small-pitch deep trench superjunction devices and forming high-performance P-type or N-type pillars. Attached Figure Description

[0045] Figure 1 The diagram shown is a flowchart illustrating a method for achieving deep trench sidewall doping according to the present invention.

[0046] Figure 2 The diagram shows a structural schematic of a method for achieving deep trench sidewall doping according to the present invention after forming a deep trench and a first dielectric layer.

[0047] Figure 3 The diagram shows a structural schematic of a method for achieving deep trench sidewall doping according to the present invention after filling with a solid doping source.

[0048] Figure 4 The diagram shows a structural schematic of a method for achieving deep trench sidewall doping according to the present invention after high-temperature annealing and diffusion.

[0049] Figure 5 The diagram shows a structural schematic of a method for achieving deep trench sidewall doping according to the present invention after removing the solid doping source and the first dielectric layer.

[0050] Figure 6 The diagram shows a structural schematic of a method for achieving deep trench sidewall doping according to the present invention, after forming a second dielectric layer and backfilling with filling material. Detailed Implementation

[0051] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] like Figure 1 As shown, the present invention provides a method for achieving deep trench sidewall doping.

[0053] like Figure 2 As shown, in step one, a deep trench is formed on the substrate 101.

[0054] In some embodiments, substrate 101 is an N-type silicon substrate. The N-type silicon substrate can serve as a drift region for a superjunction device, achieving charge balance through subsequently formed P-type doped pillars. In addition to an N-type silicon substrate, the substrate 101 material in other embodiments may also be selected from elemental semiconductors, including crystalline silicon, polycrystalline silicon, amorphous silicon, diamond, or germanium; compound semiconductors, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb); alloy semiconductors, including silicon germanium (SiGe), germanium tin (GeSn), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium arsenide phosphide indium (GaInAsP). Furthermore, substrate 101 may also include a silicon-on-insulator (SOI) structure, a strained silicon (SSI) structure, a germanium-on-insulator (GOI) structure, or a semiconductor layer with different crystal orientations (e.g., (100), (110), or (111) crystal orientations). Substrate 101 may also contain various doped regions, such as P-wells, N-wells, or pre-formed buried layer structures.

[0055] In some embodiments, substrate 101 is a P-type silicon substrate. When a P-type silicon substrate is used, subsequent processes are intended to form N-type doped pillars.

[0056] In some embodiments, the deep trench is formed by forming a hard mask layer 102 on a substrate 101 and etching based on the hard mask layer 102. For example... Figure 2 As shown, the hard mask layer 102 is used to define the opening region of the deep trench and protect the surface of the substrate 101 that does not need to be etched, ensuring that the etching process has sufficient selectivity.

[0057] In some embodiments, the thickness of the hard mask layer 102 is 1.5 micrometers to 2.5 micrometers. For example, the thickness can be approximately 2 micrometers. This thickness is sufficient to withstand long-term deep silicon etching without being depleted.

[0058] In some embodiments, the material of the hard mask layer 102 includes silicon oxide, silicon nitride, or a combination thereof. The hard mask layer 102 can be a monolayer structure or a composite layer structure of silicon oxide and silicon nitride. Its formation methods include chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma CVD (HDP-CVD), or atomic layer deposition (ALD). For example, tetraethoxysilane (TEOS), silane (SiH4), dichlorosilane (SiH2Cl2) are used with oxygen, ozone, or ammonia as reaction precursors for deposition. After depositing the hard mask layer 102, a pattern is defined using a photolithography process, and the hard mask layer 102 is opened using reactive ion etching (RIE).

[0059] In some embodiments, the aspect ratio of the deep trench is greater than 5. A high aspect ratio can significantly reduce the unit pitch of the device, improving the integration density and current density of the power device. The method of this application is particularly suitable for fabricating low-cost, small-pitch superjunction structures. For example, in a specific implementation scenario, the etch feature size (CD) of the formed deep trench is about 0.8 micrometers, and the depth is about 8 micrometers, at which point the aspect ratio reaches 10. Even for such trenches with extremely high aspect ratios, the solid-state source diffusion method of the present invention can still overcome the defect of insufficient doping at the bottom of the trench in conventional processes, achieving uniform sidewall doping. The etching process can employ anisotropic dry etching, such as deep reactive ion etching (DRIE) or the Bosch process, using alternating cycles of etching with fluorine-based gases (such as SF6, CF4, NF3) and sidewall passivation with fluorocarbon gases (such as C4F8, CHF3) to form deep trenches with vertical or near-vertical sidewalls in the silicon substrate 101.

[0060] like Figure 2 As shown, in step two, a first dielectric layer 103 is formed on the inner surface of the deep trench. The first dielectric layer 103 mainly functions as a screening layer and an interface protection layer, controlling the impurity diffusion rate and repairing etching damage.

[0061] In some embodiments, the first dielectric layer 103 is made of silicon oxide. Besides silicon oxide, the first dielectric layer 103 may also include other dielectric materials with functions for regulating impurity diffusion rates or providing interface protection in other embodiments. For example, the first dielectric layer 103 may include silicon oxynitride (SiON), silicon nitride (SiN), or combinations thereof. In some embodiments, the first dielectric layer 103 may also include high-k dielectric materials, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), or their silicates, aluminates, etc. The first dielectric layer 103 may also be a stacked structure of oxide / nitride / oxide. Different dielectric materials have different barrier capabilities; by selecting different materials or combinations of materials, the flux of impurities penetrating the dielectric layer into the substrate can be fine-tuned. If a material grown using non-thermal oxidation is employed, its formation process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0062] In some embodiments, the thickness of the first dielectric layer 103 is no greater than 1000 angstroms.

[0063] In some embodiments, when an N-type silicon substrate and a P-type doping source are used, the thickness of the first dielectric layer 103 is 400 angstroms to 600 angstroms. For example, it is about 500 angstroms. This thickness range is designed for P-type impurities such as boron that can easily penetrate the oxide layer, ensuring that the impurities can penetrate the dielectric layer into the silicon substrate at high temperatures, while preventing excessive impurity concentration on the substrate surface from causing lattice defects.

[0064] In some embodiments, when a P-type silicon substrate and an N-type doped source are used, the thickness of the first dielectric layer 103 is 10 to 100 angstroms. This extremely thin thickness range is designed for N-type impurities (such as phosphorus and arsenic). Because silicon oxide has a phosphorus-repelling effect, a thicker oxide layer would block N-type impurities from entering the silicon substrate, thus requiring an extremely thin dielectric layer, even close to the thickness of the native oxide layer, to reduce the interface barrier.

[0065] In some embodiments, the process of forming the first dielectric layer 103 includes a furnace tube thermal oxidation process. The thermal oxidation process can oxidize and consume the etched damage layer on the sidewalls of the deep trench, obtaining a high-quality Si / SiO2 interface. Thermal oxidation can employ dry oxygen oxidation or wet oxygen oxidation, or it can employ in-situ vapor generation (ISSG) or rapid thermal oxidation (RTO) processes.

[0066] In some embodiments, the temperature of the thermal oxidation process is between 1000 and 1100 degrees Celsius, for example, 1050 degrees Celsius.

[0067] In some embodiments, the thermal oxidation process takes 20 to 40 minutes, for example, 30 minutes.

[0068] like Figure 3 As shown, in step three, a solid doped source 104 is filled into the deep trench, and the solid doped source 104 located outside the deep trench is removed. The filling process needs to ensure that there are no significant voids inside the deep trench in order to provide a uniform diffusion source.

[0069] In some embodiments, the material of the solid-state doped source 104 is selected from polycrystalline silicon, amorphous silicon, borosilicate glass (BSG), or borosilicate phosphosilicate glass (BPSG). To suit different process nodes and thermal budget requirements, the specific material form and formation method of the solid-state doped source 104 can be diverse. In addition to the conventional polycrystalline silicon mentioned above, the solid-state doped source 104 may also include microcrystalline silicon, a single-crystal silicon epitaxial layer, or a doped amorphous carbon layer. The deposition process can use low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). For example, silane (SiH4), dichlorosilane (Si2H6), or dichlorosilane (SiH2Cl2) can be used as the silicon source gas. For doped glass-like materials (BSG / PSG / BPSG), atmospheric pressure CVD (APCVD) or sub-atmospheric pressure CVD (SACVD) processes can be used, generated by reacting tetraethoxysilane (TEOS), trimethylborate (TMB), trimethylphosphate (TMP), or triethylborate (TEB), triethylphosphate (TEPO) with ozone (O3) or oxygen. The solid-state doping source 104 can also be a doped dielectric layer formed by spin-coating glass (SOG).

[0070] In some embodiments, the solid-state doping source 104 is a P-type dopant. The P-type doping source is used to form P-type pillars in an N-type substrate.

[0071] In some embodiments, the doping element of the solid-state doping source 104 is boron. When the solid-state doping source 104 is configured to provide P-type conductivity, in addition to boron (B), the doping element may also include aluminum (Al), gallium (Ga), indium (In), or boron difluoride (BF2) in other embodiments. Different doping elements have different diffusion coefficients and segregation characteristics, and are selected according to the device's requirements for junction depth and steepness.

[0072] In some embodiments, the doping concentration of the solid-state doping source 104 is at least 1E18 atoms / cm³.

[0073] In some embodiments, the doping concentration of the solid-state doped source 104 is approximately 2E20 atoms / cm³. This high concentration of doped source ensures a constant surface source mode is maintained during diffusion, causing impurities to accumulate at the interface and diffuse inwards.

[0074] In some embodiments, the solid-state dopant source 104 is an N-type dopant. This is used when it is necessary to form N-pillars on a P-type substrate. In addition to phosphorus (P), the N-type dopant element may also include arsenic (As), antimony (Sb), nitrogen (N), or bismuth (Bi). The corresponding gaseous precursor may include phosphine (PH3), arsine (AsH3), or trimethylantimony (TMSb). For example, arsenic has a lower diffusion coefficient than phosphorus, making it suitable for forming shallow junctions; while phosphorus has high solid solubility, making it suitable for forming heavily doped contacts.

[0075] In some embodiments, the process for removing the solid dopant sources 104 located outside the deep trench includes a chemical mechanical polishing (CMP) process. CMP removes the polysilicon above the hard mask layer 102, isolating the solid dopant sources 104 within the trench and planarizing the wafer surface. The polishing slurry may be formulated with a high selectivity for silicon oxide, allowing polishing to automatically stop at the surface of the hard mask layer 102.

[0076] like Figure 4 As shown, in step four, high-temperature annealing is performed to allow impurity ions in the solid-state doping source 104 to diffuse through the first dielectric layer 103 into the sidewall substrate of the deep trench, forming a doped region 105. At high temperatures, doped ions (especially boron) utilize the adsorption effect of the oxide layer to penetrate the first dielectric layer 103, forming a high concentration accumulation at the interface between the first dielectric layer 103 and the silicon substrate 101, and then diffuse deeper into the substrate.

[0077] In some embodiments, the high-temperature annealing temperature is between 1150°C and 1250°C. For example, 1150°C. This temperature is typically higher than the growth temperature of the first dielectric layer 103 to activate impurity diffusion.

[0078] In some embodiments, the high-temperature annealing time is greater than 30 minutes.

[0079] In some embodiments, the high-temperature annealing time is 100 to 140 minutes, for example, 120 minutes. Annealing can be carried out in a furnace tube, and the atmosphere can be nitrogen (N2), argon (Ar), or other inert gases to prevent additional oxidation reactions from altering the interfacial state. Stepwise annealing can be employed, for example, pre-deposition diffusion can be performed at a lower temperature, followed by advanced diffusion at a higher temperature.

[0080] In some embodiments, after high-temperature annealing, the doping concentration of the doped region 105 formed in the sidewall substrate of the deep trench is from 5E16 atoms / cm³ to 8E17 atoms / cm³.

[0081] In some embodiments, the doped region 105 formed on the sidewall of the deep trench is used to form a P-type pillar of a P-well or superjunction device.

[0082] like Figure 5As shown, in step five, the solid doping source 104 and the first dielectric layer 103 in the deep trench are removed.

[0083] In some embodiments, the process for removing the solid-state dopant source 104 employs a dry etching process. For example, plasma etching can be performed using sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), hydrogen bromide (HBr), chlorine (Cl2), or mixtures thereof, in conjunction with oxygen (O2). This process can selectively remove polysilicon within the trench without damaging the oxide layer on the sidewalls. Wet etching can also be used, for example, with tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) solutions, but care must be taken to protect the silicon substrate. If the solid-state dopant source is BSG or BPSG glass, it can be removed using a hydrofluoric acid (HF)-based solution or vapor-phase HF etching.

[0084] In some embodiments, the process for removing the first dielectric layer 103 employs a wet etching process. For example, diluted hydrofluoric acid (DHF) or a buffered oxide etchant (BOE, a mixture of NH4F and HF) is used to completely remove the first dielectric layer 103, which serves as the sacrificial layer, and the remaining hard mask layer 102. Figure 5 The diagram shows the doped region 105 remaining on the sidewall after the removal of the sacrificial layer. This step not only removes the oxide layer that may have been contaminated during the doping process, but also provides a clean silicon surface for the subsequent growth of a high-quality insulating layer.

[0085] like Figure 6 As shown, in step six, a second medium layer 106 is formed on the inner surface of the deep trench, and the filling material 107 is backfilled.

[0086] In some embodiments, the second dielectric layer 106 is a silicon oxide layer, and the thickness of the second dielectric layer 106 is at least 1500 angstroms. The thickness of the second dielectric layer 106 is greater than that of the first dielectric layer 103, and it is used to withstand the high electric field during device operation. It can be formed by thermal oxidation growth or a combination of thermal oxidation and chemical vapor deposition (such as TEOS CVD, HDP CVD, SACVD) to ensure good thickness uniformity and step coverage. The second dielectric layer can also be a silicon oxide-silicon nitride-silicon oxide (ONO) stacked structure.

[0087] In some embodiments, the filler material 107 comprises N-type doped polysilicon. The backfilled N-type polysilicon can be part of the field plate structure or simply a charge-balancing structure electrically disconnected from it. The filling process can employ LPCVD, which utilizes its excellent trench-filling capability to avoid the formation of internal voids or seams, thereby improving device reliability. Afterward, etch-back or CMP planarization can be performed to facilitate subsequent fabrication of the source, gate, and metal interconnects. Alternatively, the filler material 107 can also be dielectric-filled using high-density plasma (HDP) deposited oxide, tetraethyl orthosilicate (TEOS) precursor-based oxide, or spin-on dielectric (SOD). In some embodiments, the filler material 107 may also include a micro-air gap structure to reduce parasitic capacitance.

[0088] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for achieving deep trench sidewall doping, characterized in that, At least including: Step 1: Form deep trenches on the substrate; Step 2: Form a first dielectric layer on the inner surface of the deep trench; Step 3: Fill the deep trench with a solid doping source and remove the solid doping source located outside the deep trench; Step 4: Perform high-temperature annealing to allow impurity ions in the solid-state doped source to diffuse through the first dielectric layer into the sidewall substrate of the deep trench. Step 5: Remove the solid doping source and the first dielectric layer from the deep trench; Step 6: Form a second medium layer on the inner surface of the deep trench and backfill with filling material.

2. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step one, the substrate is an N-type silicon substrate.

3. The method for achieving deep trench sidewall doping according to claim 2, characterized in that: In step three, the solid-state doping source is a P-type dopant.

4. The method for achieving deep trench sidewall doping according to claim 3, characterized in that: In step three, the doping element of the solid-state doping source is boron.

5. The method for achieving deep trench sidewall doping according to claim 3, characterized in that: In step two, the thickness of the first dielectric layer is no greater than 1000 angstroms.

6. The method for achieving deep trench sidewall doping according to claim 5, characterized in that: In step two, the thickness of the first dielectric layer is 400 to 600 angstroms.

7. The method for achieving deep trench sidewall doping according to claim 3, characterized in that: In step six, the filling material comprises N-type doped polycrystalline silicon.

8. The method for achieving deep trench sidewall doping according to claim 4, characterized in that: In step four, after the high-temperature annealing, the doping concentration formed in the sidewall substrate of the deep trench is from 5E16 atoms / cm³ to 8E17 atoms / cm³.

9. The method for achieving deep trench sidewall doping according to claim 3, characterized in that: In step four, the doped region formed on the sidewall of the deep trench is used to form the P-type pillar of the P-well or superjunction device.

10. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step one, the substrate is a P-type silicon substrate.

11. The method for achieving deep trench sidewall doping according to claim 10, characterized in that: In step three, the solid-state doping source is an N-type dopant.

12. The method for achieving deep trench sidewall doping according to claim 11, characterized in that: In step two, the thickness of the first dielectric layer is 10 to 100 angstroms.

13. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step one, the deep trench is formed by forming a hard mask layer on the substrate and etching based on the hard mask layer.

14. The method for achieving deep trench sidewall doping according to claim 13, characterized in that: In step one, the thickness of the hard mask layer is 1.5 micrometers to 2.5 micrometers.

15. The method for achieving deep trench sidewall doping according to claim 13, characterized in that: In step one, the material of the hard mask layer includes silicon oxide, silicon nitride, or a combination thereof.

16. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step one, the aspect ratio of the deep trench is greater than 5.

17. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step two, the material of the first dielectric layer is silicon oxide.

18. The method for achieving deep trench sidewall doping according to claim 17, characterized in that: In step two, the process for forming the first dielectric layer includes a furnace tube thermal oxidation process.

19. The method for achieving deep trench sidewall doping according to claim 18, characterized in that: In step two, the temperature of the thermal oxidation process is 1000 to 1100 degrees Celsius.

20. The method for achieving deep trench sidewall doping according to claim 18, characterized in that: In step two, the thermal oxidation process takes 20 to 40 minutes.

21. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step three, the material of the solid-state doping source is selected from any one of polycrystalline silicon, amorphous silicon, borosilicate glass, or borosilicate glass.

22. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step three, the doping concentration of the solid-state doping source is at least 1E18 atoms / cm³.

23. The method for achieving deep trench sidewall doping according to claim 22, characterized in that: In step three, the doping concentration of the solid-state doping source is 2E20 atoms / cubic centimeter.

24. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step three, the process of removing the solid dopant source located outside the deep trench includes a chemical mechanical polishing process.

25. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step four, the high-temperature annealing temperature is between 1150 degrees Celsius and 1250 degrees Celsius.

26. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step four, the high-temperature annealing time is greater than 30 minutes.

27. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step five, the process of removing the solid dopant source is a dry etching process.

28. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step five, the process of removing the first dielectric layer is a wet etching process.

29. The method for achieving deep trench sidewall doping according to claim 1, characterized in that: In step six, the second dielectric layer is a silicon oxide layer, and the thickness of the second dielectric layer is at least 1500 angstroms.

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