Semiconductor device and forming method thereof

Abstract

A device includes an interposer, a package attached to a first side of the interposer, and a plurality of passive devices and external connections attached to a second side of the interposer. The package includes an encapsulant and an integrated circuit device in the encapsulant. The interposer electrically connects the passive device and the external connection to the integrated circuit device. In a top view, the external connection is disposed outside the outer periphery of the package. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, these improvements in integration density are due to iterative reductions in the smallest component size, allowing more components to be integrated into a given area. With the increasing demand for miniaturized electronics, there has been a need for smaller and more innovative packaging technologies for semiconductor dies. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor device, comprising: an interposer; a package attached to a first side of the interposer, the package including a sealant and a plurality of integrated circuit devices located within the sealant; a plurality of passive devices attached to a second side of the interposer, the interposer electrically connecting the passive devices to the integrated circuit devices; and a plurality of first external connectors attached to the second side of the interposer, the interposer electrically connecting the first external connectors to the integrated circuit devices, wherein, in a top view, the first external connectors are disposed on the outer periphery of the package.

[0004] Another embodiment of this disclosure provides a semiconductor device, including: a cold plate; a frame including an opening; and a system package located between the cold plate and the frame, the system package including: an interposer; a wafer package attached to a first side of the interposer, the width of the interposer being greater than the width of the wafer package, the wafer package including a sealant and a plurality of integrated circuit devices located in the sealant; the system package further including a plurality of external connectors attached to a second side of the interposer, the interposer electrically connecting the external connectors to the integrated circuit devices, the opening of the frame exposing the external connectors. Another embodiment of this disclosure provides a method for forming a semiconductor device, comprising: attaching a package to a first side of an interposer, the package including a sealant and a plurality of integrated circuit devices located in the sealant; attaching a plurality of passive devices to a second side of the interposer, the interposer electrically connecting the passive devices to the integrated circuit devices, wherein, in a top view, the passive devices are disposed within the outer periphery of the package; and attaching a plurality of external connectors to the second side of the interposer, the interposer electrically connecting the external connectors to the integrated circuit devices, wherein, in a top view, the external connectors are disposed outside the outer periphery of the package. Attached Figure Description

[0005] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0006] Figure 1 This is a cross-sectional view of an integrated circuit die.

[0007] Figures 2A to 2B This is a cross-sectional view of the die stack.

[0008] Figures 3 to 13 This is a view of an intermediate stage in the manufacturing of a system package according to some embodiments.

[0009] Figure 14 This is a cross-sectional view of a system-on-a-wafer assembly according to some embodiments.

[0010] Figure 15 This is a cross-sectional view of a system-on-a-wafer assembly according to some embodiments.

[0011] Figure 16 This is a cross-sectional view of a system-on-a-wafer assembly according to some embodiments.

[0012] Figure 17 This is a cross-sectional view of a system-on-a-wafer assembly according to some embodiments.

[0013] Figures 18 to 23 This is a cross-sectional view of an intermediate stage in the manufacturing of a wafer package according to some other embodiments.

[0014] Figure 24 This is a cross-sectional view of a system-on-a-wafer assembly according to some embodiments.

[0015] Figure 25 This is a cross-sectional view of a system-on-a-wafer assembly according to some embodiments. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] According to various embodiments, a system package may include a wafer package and a rigid interposer. The system package may be a complete system, such as a system-on-a-wafer (SoW). The wafer package may include integrated circuit devices encapsulated in a sealant. The wafer package may be attached to the rigid interposer within the system package. Other components, such as passive devices and external interconnects, may also be attached to the rigid interposer. The rigid interposer may include routing elements, such as optical waveguides and / or conductive traces, to facilitate signal transmission between components of the system package. The rigid interposer may be larger than the wafer package, wherein, in a top view, the outer periphery of the rigid interposer extends beyond the outer periphery of the wafer package. A rigid interposer can provide advantages in a system package. It can serve as a stable platform for integrating multiple components and can allow efficient signal routing between different components of the system package. The rigidity of the interposer can help maintain the structural integrity of the system package and potentially reduce stress on the packaged components during handling or operation.

[0019] Figure 1 This is a cross-sectional view of integrated circuit die 50. Multiple integrated circuit dies 50 will be packaged in subsequent processing. Each integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC) die, microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or combinations thereof. Integrated circuit dies 50 may be formed in a wafer, which may include different die regions that are segmented in subsequent steps to form multiple integrated circuit dies 50. An integrated circuit die 50 includes a semiconductor substrate 52, interconnect structures 54, die connectors 56, and a dielectric layer 58.

[0020] Semiconductor substrate 52 may be a doped or undoped silicon substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Semiconductor substrate 52 has an active surface (e.g., Figure 1 (Surface facing upwards) and passive surfaces (e.g., Figure 1 (Surface facing downwards). Devices (not shown separately) are located on the active surface of the semiconductor substrate 52. These devices can be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The passive surface may be without devices.

[0021] Interconnect structure 54 is located above the active surface of semiconductor substrate 52 and is used to electrically connect devices on semiconductor substrate 52 together to form an integrated circuit. Interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers located within the dielectric layers. Acceptable dielectric materials for dielectric layers include oxides (such as silicon oxide or aluminum oxide), nitrides (such as silicon nitride), combinations thereof (such as silicon oxynitride), etc. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene-based polymers (BCB), etc. Metallization layers may include conductive vias and / or wires to interconnect devices on semiconductor substrate 52. Metallization layers may be formed of conductive materials, such as metals, such as copper, cobalt, aluminum, gold, combinations thereof, etc. The metallization layers of interconnect structure 54 may be formed by damascene processes, such as single damascene processes, dual damascene processes, etc.

[0022] The die connector 56 is located at the front side 50F of the integrated circuit die 50. The die connector 56 can be a conductive pillar, pad, etc., for external connection. The die connector 56 can be located in and / or on the interconnect structure 54. For example, the die connector 56 can be a portion of the upper metallization layer of the interconnect structure 54. The die connector 56 can be formed of a metal such as copper or aluminum, and can be formed by, for example, plating.

[0023] Optionally, during the formation of the integrated circuit die 50, a solder region (not shown separately) may be provided on the die connector 56. The solder region can be used to perform chip probe (CP) testing on the integrated circuit die 50. For example, the solder region may be a solder ball, solder bump, etc., for attaching the chip probe to the die connector 56. Chip probe testing can be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only KGD integrated circuit dies 50 that have undergone subsequent processing are packaged, and dies that fail the chip probe test are not packaged. After testing, the solder region can be removed.

[0024] Dielectric layer 58 is located at the front side 50F of integrated circuit die 50. Dielectric layer 58 may be located in and / or on interconnect structure 54. For example, dielectric layer 58 may be the upper dielectric layer of interconnect structure 54. Dielectric layer 58 laterally seals die connector 56. Dielectric layer 58 may be an oxide, nitride, polymer, or combination thereof, and may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The front surfaces of die connector 56 and dielectric layer 58 may be substantially coplanar at the front side 50F of integrated circuit die 50 (within process variations).

[0025] Figures 2A to 2B These are cross-sectional views of die stacks 60A and 60B, respectively. Each of die stacks 60A and 60B may have a single function (e.g., a logic device, a memory die, etc.) or each may have multiple functions. In some embodiments, die stack 60A is a logic device such as a system-on-a-chip (SoIC) device, and die stack 60B is a memory device such as a high-bandwidth memory (HBM) device.

[0026] like Figure 2AAs shown, the die stack 60A includes two bonded integrated circuit dies 50 (e.g., a first integrated circuit die 50A and a second integrated circuit die 50B). In some embodiments, the first integrated circuit die 50A is a logic die, and the second integrated circuit die 50B is an interface die. The interface die bridges the logic die to a memory die and translates commands between the logic die and the memory die. In some embodiments, the first integrated circuit die 50A and the second integrated circuit die 50B are bonded such that their active surfaces face each other (e.g., "face-to-face" bonding). A conductive via 62 may be formed through one of the integrated circuit dies 50, allowing an external connection to the die stack 60A to be made. The conductive via 62 may be a substrate via (TSV), such as a through-silicon via (TSV). In the illustrated embodiment, the conductive via 62 is formed in the second integrated circuit die 50B (e.g., the interface die). The conductive via 62 extends through the semiconductor substrate 52 of the respective integrated circuit die 50 to physically and electrically connect to the metallization layer of the interconnect structure 54.

[0027] like Figure 2B As shown, the die stack 60B is a stacked device comprising multiple semiconductor substrates 52. For example, the die stack 60B can be a stacked memory device comprising multiple memory dies, such as a hybrid memory cube (HMC) device, a high-bandwidth memory (HBM) cube, etc. Each semiconductor substrate 52 may (or may not) have a separate interconnect structure 54. The semiconductor substrates 52 are connected via conductive vias 62 (such as TSVs).

[0028] Figures 3 to 13 It is a system package 200 according to some embodiments (see Figures 12 to 13 A view of the intermediate stages in the manufacturing process of ( ). Figures 3 to 7 and Figures 10 to 12 It is a cross-sectional view, and Figures 8 to 9 and Figure 13 This is a top view. The system package is formed by initially forming a wafer package. The wafer package is a reconstructed wafer containing integrated circuit devices encapsulated in a sealant. The wafer package is attached to a rigid interposer. Other components, such as passive devices and external interconnects, may also be attached to the rigid interposer. The rigid interposer may include routing components, such as optical waveguides and / or conductive traces, to facilitate signal transmission between components of the system package. The rigid interposer may be larger than the wafer package, wherein, in the top view, the outer periphery of the rigid interposer extends beyond the outer periphery of the wafer package. Additionally, the interposer may have greater rigidity than the wafer package. The rigidity of the interposer helps maintain the structural integrity of the system package and potentially reduces stress on attached components.

[0029] The system package has multiple compute stations and multiple connectivity stations. The compute stations may include integrated circuit devices. Each integrated circuit device may have, for example, logic functions, memory functions, etc., and the system package may be a single computing system including compute stations and connectivity stations, such as a system-on-a-wafer (SoW). For example, the system package may be an artificial intelligence (AI) accelerator, and each compute station may be a neural network node for the AI ​​accelerator. Connectivity stations may include external connectors for connecting the compute stations to external systems. Example external systems that can implement the system package include AI servers, high-performance computing (HPC) systems, high-power computing devices, cloud computing systems, edge computing systems, etc.

[0030] exist Figure 3 In this process, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 can be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 can be a wafer.

[0031] Release layer 104 may be formed of a polymer-based material, which may be removed together with the carrier substrate 102 from the structure to be formed in subsequent steps. In some embodiments, release layer 104 is an epoxy-based thermal release material that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, release layer 104 may be a UV adhesive that loses its adhesiveness upon exposure to UV light. Release layer 104 may be dispensed and cured as a liquid, and may be a laminated film or the like laminated onto the carrier substrate 102. The top surface of release layer 104 may be flush and may have a high degree of flatness.

[0032] The integrated circuit device 70 is then attached to the release layer 104. The integrated circuit devices 70 of the desired type and number are placed adjacent to each other. In some embodiments, the integrated circuit device 70 includes a first type of integrated circuit device (such as a computing device 70A) and a second type of integrated circuit device (such as an interface device 70B). The computing device 70A and the interface device 70B can be formed in the same technology node process or in different technology node processes. For example, the computing device 70A can be formed using a more advanced process node than the interface device 70B.

[0033] Each computing device 70A may include logic dies, memory dies, etc. The computing device 70A may be an integrated circuit die (similar to...) Figure 1 The integrated circuit die 50 described in the document can be a die stack (similar to...). Figures 2A to 2BThe die stacks 60A and 60B described herein. In some embodiments, computing device 70A is a die stack, such as a system-on-a-chip (SoIC) device. Each die stack may include a system-on-a-chip (SoC) die and one or more HBM dies.

[0034] Each interface device 70B may include an input / output interface, a memory controller, a network interface, or other types of interface circuitry to bridge communication between the computing device 70A and external components. The interface device 70B can translate commands and data between the protocols used by the computing device 70A and the protocols used by the external components. The interface device 70B may be an integrated circuit die (similar to...) Figure 1 The integrated circuit die 50 described in the document can be a die stack (similar to...). Figures 2A to 2B (Die stacks 60A and 60B described herein). In some embodiments, interface device 70B is an I / O die.

[0035] Interface device 70B can be arranged around computing device 70A to facilitate connectivity with external systems. Specifically, interface device 70B can surround computing device 70A (described later) in a top view. This arrangement allows for a shorter electrical path between interface device 70B and external connectors (described later) that will be attached to the system package.

[0036] A sealant 106 is formed on and around various components. After formation, the sealant 106 can seal the integrated circuit device 70. The sealant 106 can be a molding compound, epoxy resin, etc., and can be applied by compression molding, transfer molding, etc. The sealant 106 can be applied in liquid or semi-liquid form and then subsequently cured. In some embodiments, the sealant 106 is formed over a carrier substrate 102 such that it buries or covers the integrated circuit device 70, and a planarization process can then be performed on the sealant 106 to expose the die connector 72 of the integrated circuit device 70. The planarization process can be, for example, chemical mechanical polishing (CMP), grinding, etc. After the planarization process, the top surfaces of the sealant 106 and the die connector 72 can be substantially coplanar (within process variations).

[0037] exist Figures 4 to 5 In this process, a redistribution structure 112 having a fine component portion 112A and a rough component portion 112B is formed above the sealant 106 and the integrated circuit device 70 (see...). Figure 6The redistribution structure 112 includes a metallization pattern and a dielectric layer. The metallization pattern may also be referred to as a redistribution layer, redistribution line, or trace. The fine component portion 112A includes a metallization pattern and dielectric layer of a different size than those in the rough component portion 112B. The redistribution structure 112 is shown as an example with six layers of metallization pattern. More or fewer dielectric layers and metallization patterns can be formed in the redistribution structure 112 by repeating or omitting the steps and processes discussed below.

[0038] exist Figure 4 In this redistribution structure 112, a fine component portion 112A is formed. The fine component portion 112A of the redistribution structure 112 includes dielectric layers 114, 118, 122, 126 and metallization patterns 116, 120, 124. In some embodiments, dielectric layers 118, 122, 126 are formed of the same dielectric material and are formed to the same thickness. Similarly, in some embodiments, the conductive components of the metallization patterns 116, 120, 124 are formed of the same conductive material and are formed to the same thickness. Dielectric layers 118, 122, 126 have a smaller thickness, and the conductive components of the metallization patterns 116, 120, 124 also have a smaller thickness.

[0039] As an example of forming a fine component portion 112A of the redistribution structure 112, a dielectric layer 114 is deposited on a sealant 106 and an integrated circuit device 70 (including a die connector 72). In some embodiments, the dielectric layer 114 is formed of a photosensitive material, such as PBO, polyimide, BCB, etc., which can be patterned using a photolithographic mask. The dielectric layer 114 can be formed by spin coating, lamination, CVD, etc., or combinations thereof. The dielectric layer 114 is then patterned. The patterning forms openings that expose portions of the die connector 72. Patterning can be performed by acceptable processes, such as exposing the dielectric layer 114 to light when it is a photosensitive material, or by etching, for example, using anisotropic etching. If the dielectric layer 114 is a photosensitive material, it can be developed after exposure.

[0040] Then, a metallization pattern 116 is formed. The metallization pattern 116 has a line portion (also called a conductor) located on and extending along the main surface of the dielectric layer 114, and a via portion (also called a conductive via) extending through the dielectric layer 116 to physically and electrically couple the die connector 72 of the integrated circuit device 70. As an example of forming the metallization pattern 116, a seed layer is formed above the dielectric layer 114 and in the opening extending through the dielectric layer 114. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD). A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 116. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, and aluminum. The combination of the conductive material and the underlying seed layer portions forms a metallization pattern 116. The photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer can be removed, for example, by using an acceptable etching process, such as wet or dry etching.

[0041] Then, a dielectric layer 118 is deposited on the metallization pattern 116 and the dielectric layer 114. The dielectric layer 118 can be formed in a similar manner and with similar materials as the dielectric layer 114.

[0042] Then, a metallization pattern 120 is formed. The metallization pattern 120 has a line portion located on and extending along the main surface of the dielectric layer 118, and a via portion extending through the dielectric layer 118 to physically and electrically couple the metallization pattern 116. The metallization pattern 120 can be formed in a similar manner and with similar materials as the metallization pattern 116.

[0043] Then, a dielectric layer 122 is deposited on the metallization pattern 120 and the dielectric layer 118. The dielectric layer 122 can be formed in a similar manner and with similar materials as the dielectric layer 114.

[0044] Then, a metallization pattern 124 is formed. The metallization pattern 124 has a line portion located on and extending along the main surface of the dielectric layer 122, and a via portion extending through the dielectric layer 122 to physically and electrically couple the metallization pattern 120. The metallization pattern 124 can be formed in a similar manner and with similar materials as the metallization pattern 116.

[0045] Dielectric layer 126 is deposited on metallization pattern 124 and dielectric layer 122. Dielectric layer 126 can be formed in a similar manner and with similar materials as dielectric layer 114.

[0046] exist Figure 5 In this process, a rough portion 112B of the redistribution structure 112 is formed. The rough portion 112B of the redistribution structure 112 includes dielectric layers 130, 134, and 138 and metallization patterns 128, 132, and 136. In some embodiments, dielectric layers 130, 134, and 138 are formed of the same dielectric material and are formed to the same thickness. Similarly, in some embodiments, the conductive components of the metallization patterns 128, 132, and 136 are formed of the same conductive material and are formed to the same thickness. Dielectric layers 130, 134, and 138 have a larger thickness, and the conductive components of the metallization patterns 128, 132, and 136 have a larger thickness. In particular, the thickness of dielectric layers 130, 134, and 138 is greater than that of dielectric layers 118, 122, and 126 (see...). Figure 4 The thickness of the conductive components in metallized patterns 128, 132, and 136 is greater than that in metallized patterns 116, 120, and 124 (see...). Figure 4 The thickness of the conductive components.

[0047] As an example of forming the rough component portion 112B of the redistribution structure 112, a metallization pattern 128 is formed. The metallization pattern 128 has a line portion located on and extending along the main surface of the dielectric layer 126, and a via portion extending through the dielectric layer 126 to physically and electrically couple the metallization pattern 124. As an example of forming the metallization pattern 128, a seed layer is formed above the dielectric layer 126 and in the opening extending through the dielectric layer 126. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 128. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, and aluminum. The combination of the conductive material and the underlying seed layer portions forms a metallization pattern 128. The photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer can be removed, for example, by using an acceptable etching process, such as wet or dry etching.

[0048] A dielectric layer 130 is then deposited on the metallization pattern 128 and the dielectric layer 126. In some embodiments, the dielectric layer 130 is formed of a photosensitive material, such as PBO, polyimide, BCB, etc., which can be patterned using a photolithographic mask. The dielectric layer 130 can be formed by spin coating, lamination, CVD, or combinations thereof. The dielectric layer 130 is then patterned. The patterning forms openings that expose portions of the metallization pattern 128. The patterning can be performed by acceptable processes, such as exposing the dielectric layer 130 to light when it is a photosensitive material, or by etching, for example, using anisotropic etching. If the dielectric layer 130 is a photosensitive material, it can be developed after exposure.

[0049] Then, a metallization pattern 132 is formed. The metallization pattern 132 has a line portion located on and extending along the main surface of the dielectric layer 130, and a via portion extending through the dielectric layer 130 to physically and electrically couple the metallization pattern 128. The metallization pattern 132 can be formed in a similar manner and with similar materials as the metallization pattern 128.

[0050] Then, a dielectric layer 134 is deposited on the metallization pattern 132 and the dielectric layer 130. The dielectric layer 134 can be formed in a similar manner and with similar materials as the dielectric layer 130.

[0051] Then, a metallization pattern 136 is formed. The metallization pattern 136 has a line portion located on and extending along the main surface of the dielectric layer 134, and a via portion extending through the dielectric layer 134 to physically and electrically couple the metallization pattern 132. The metallization pattern 136 can be formed in a similar manner and with similar materials as the metallization pattern 128.

[0052] Dielectric layer 138 is deposited on metallization pattern 136 and dielectric layer 134. Dielectric layer 138 can be formed in a similar manner and with similar materials as dielectric layer 130.

[0053] exist Figure 6 In this process, a UBM 140 is formed for external connections to the redistribution structure 112. The UBM 140 has bump portions located on and extending along the main surface of the dielectric layer 138, and via portions extending through the dielectric layer 138 to physically and electrically couple the metallization pattern 136. As a result, the UBM 140 is electrically coupled to the integrated circuit device 70. The UBM 140 can be formed in a similar manner and with similar materials to the metallization pattern 136. In some embodiments, the UBM 140 has different dimensions than the metallization pattern of the redistribution structure 112.

[0054] exist Figure 7 In this process, carrier substrate debonding can be performed to separate (or “debond”) the carrier substrate 102 from the redistribution structure 112. According to some embodiments, debonding involves projecting light, such as UV light, onto the release layer 104, causing the release layer 104 to decompose under the heat of the light, and the carrier substrate 102 can be removed. The remaining structure is the wafer package 100, which will then be attached to the rigid interposer. The wafer package 100 can be placed on a strip, a carrier substrate, or another suitable support structure (not shown separately) for subsequent processing.

[0055] refer to Figure 8 In a top view, the integrated circuit devices 70 of the wafer package 100 are arranged in a grid pattern. Computing devices 70A are arranged in an array in the central region of the wafer package 100. Interface devices 70B are located around the outer periphery of the wafer package 100, surrounding the computing devices 70A. Any desired number of interface devices 70B can be positioned along each edge of the wafer package 100. This arrangement allows the interface devices 70B to facilitate connections between the computing devices 70A and external components. A sealant 106 surrounds the integrated circuit devices 70, providing structural support and protection for the wafer package 100.

[0056] The wafer package 100 can have any desired size and shape (in top view) suitable for the intended application. In this embodiment, the wafer package 100 is a truncated circular wafer, wherein one or more edges of the circle are flattened. In other embodiments, the wafer package 100 can be a non-truncated circular wafer. The wafer package 100 can be any size, such as approximately 12 inches in diameter. The specific shape and size of the wafer package 100 can depend on factors such as manufacturing processes, packaging requirements, or compatibility with other system components. In some cases, the truncated circular shape allows for more efficient handling during manufacturing and assembly processes compared to wafers of other shapes.

[0057] Computing devices 70A can be positioned close to each other within the wafer package 100. The spacing between adjacent computing devices 70A can be small, with small gaps or possibly no gaps between them. This compact arrangement is possible due to the design of the wafer package 100, which eliminates the need to accommodate screws or other mechanical fasteners passing through it in the final package assembly. The lack of mechanical fasteners in the wafer package 100 can be achieved by subsequently including a rigid interposer layer (described later) in the system package. This design approach allows for a higher density of computing devices 70A within the wafer package 100, potentially improving overall system scale and efficiency. In some embodiments, the wafer package 100 may include more than eight computing devices 70A. Furthermore, computing devices 70A and interface devices 70B can also be positioned closer together, further increasing the component density within the wafer package 100.

[0058] refer to Figure 9 The image shows an array of computing devices 70A in the wafer package 100 in more detail. Each computing device 70A may include a logic die 50L surrounded by a plurality of memory dies 50M. In this example, the dies have a symmetrical layout, but they may optionally have an asymmetrical layout. The memory dies 50M may be arranged along multiple sides of the logic dies 50L. The configuration of the dies within each computing device 70A can improve space utilization and interconnect efficiency. It should be noted that, depending on the specific requirements of the system, the computing device 70A may have a variety of other die configurations, possibly including different numbers, sizes, or arrangements of logic dies and memory dies.

[0059] Because of the lack of mechanical fasteners in the wafer package 100, the computing devices 70A can be positioned close together, potentially allowing them to contact each other within the wafer package 100. This arrangement can allow for higher component density compared to a configuration with small gaps between the computing devices 70A. In some embodiments, in one direction (e.g., Figure 9 Logic dies 50L that are adjacent to each other in the vertical direction can be in physical contact, while in the other direction (e.g., Figure 9 50M memory dies that are adjacent to each other in the horizontal direction can be in physical contact.

[0060] Other components and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packaged or 3DIC devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D package or 3DIC using probes and / or probe cards. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to improve yield and reduce costs.

[0061] exist Figure 10 In this process, a rigid interposer 202 is received or formed. The previously formed wafer package 100 is attached to the rigid interposer 202. This rigid interposer 202 can be pre-obtained or formed using a suitable manufacturing process. Preparing the rigid interposer 202 before incorporating it into the system package allows for efficient assembly and integration of the packaged components. Specifically, the rigidity of the rigid interposer 202 enables it to support itself during processing while components such as the wafer package 100 are attached to it.

[0062] The rigid interposer 202 can possess rigid properties, contributing to the structural integrity of the resulting system package. It can be composed of a rigid dielectric material with high stiffness and resistance to stress deformation, such as a dielectric material with a Young's modulus of at least 10 GPa. Examples of rigid dielectric materials include glass, ceramics, undoped silicon, alumina, aluminum nitride, beryllium oxide, boron nitride, etc. In some embodiments, the rigid interposer 202 is formed of glass. Using such a material can provide mechanical stability, thermal management benefits, and electrical insulation properties, which can contribute to the overall performance and reliability of the system package.

[0063] The rigid interposer 202 includes routing components 204 for signal routing. Routing components 204 may include optical routing components (e.g., optical waveguides, fiber optic cables, etc.) and / or circuit routing components (e.g., wires, conductive vias, etc.). The exact type of routing component 204 utilized may depend on the specific requirements of the system package. Including these components enables complex signal paths and interconnections between different components of the system package (e.g., integrated circuit devices of wafer package 100, subsequently attached passive devices, subsequently attached external connectors, etc.), facilitating efficient data transmission and communication.

[0064] The rigid interposer 202 is relatively large. Specifically, it is larger than the wafer package 100. In the resulting system package, the outer periphery of the rigid interposer 202 will extend beyond the outer periphery of the wafer package 100. In other words, in a cross-sectional view, the width of the rigid interposer 202 can be greater than the width of the wafer package 100. The larger size of the rigid interposer 202 relative to the wafer package 100 allows for the integration of additional routing components and external connectors around the wafer package 100, including those that would dangle from the edges of the wafer package 100 if directly attached thereto. In some embodiments, the rigid interposer 202 can be a circular wafer (truncated or untruncated) larger than about 12 inches. This large form factor allows for the integration of many components and parts using a single interposer that is large and rigid enough to mechanically support the resulting system package.

[0065] The rigid interposer 202 includes conductive bumps 206, 208 on each side. Specifically, the rigid interposer 202 includes conductive bumps 206 on one side and conductive bumps 208 on the opposite side. These conductive bumps 206, 208 can be used as connection points for other components within the system package. In some embodiments, the wafer package 100 is attached to the conductive bumps 206, while passive devices and / or external connectors (described later) are attached to the conductive bumps 208. The inclusion of conductive bumps 206, 208 on both sides of the rigid interposer 202 enables vertical integration and electrical connectivity throughout the three-dimensional structure of the system package.

[0066] The strip 212 is initially provided on the side of the rigid interposer 202 having conductive bumps 208. The strip 212 can support the rigid interposer 202 during the initial stages of its processing, such as when attaching the wafer package 100 to the rigid interposer 202 (described later). It can provide protection for the conductive bumps 208, assist in processing the rigid interposer 202, or facilitate certain manufacturing steps in the overall package manufacturing process.

[0067] Attaching the wafer package 100 to one side of the rigid interposer 202 may include multiple steps, such as Figure 10 and Figure 11 As will be described. The wafer package 100 can be attached to one side of the rigid interposer 202 using an adhesive layer 214 and a plurality of reflowable connectors 216. In some embodiments, the adhesive layer 214 can be used to attach the rigid interposer 202 to dielectric components of the wafer package 100, such as the top dielectric layer 138 of a wafer redistribution structure (see...). Figure 7The reflowable connector 216 can be used to connect the UBM 140 of the wafer package 100 to the conductive bumps 206 of the rigid interposer 202. This attachment method using adhesive and reflowable connectors can provide a secure mechanical and electrical connection between the wafer package 100 and the rigid interposer 202.

[0068] Adhesive layer 214 can be a bonding material used to attach wafer package 100 to rigid interposer 202. Adhesive layer 214 can be applied over the surface of rigid interposer 202 to facilitate attachment of components including wafer package 100. In some embodiments, adhesive layer 214 can be a Class B adhesive film, such as a partially cured thermosetting resin. Class B adhesives are initially soft and tacky, allowing for easy application and positioning. They can then be fully cured with heat and / or pressure to create a strong bond between wafer package 100 and rigid interposer 202. Class B curing processes typically involve two stages: initial partial curing to produce a stable, handleable film, followed by final curing during assembly to form a permanent bond. Some Class B adhesives can be formed using epoxy, acrylic, or silicone chemicals. Adhesive layer 214 can also be die attachment film (DAF) or other suitable adhesive materials. Adhesive layer 214 can have dielectric properties, allowing it to provide electrical insulation and reduce the risk of bridging between conductive bumps 206.

[0069] The reflowable connector 216 may be a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, etc. The reflowable connector 216 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, tin, or combinations thereof. In some embodiments, the reflowable connector 216 is formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, or ball placement. Once the solder layer is formed, reflow can be performed to shape the material into a desired form.

[0070] The reflowable connector 216 can be formed by first patterning the adhesive layer 214 to have openings. The openings in the adhesive layer 214 can be formed using photolithography, in which photoresist is applied, exposed, and developed to create the pattern. The openings can then be etched into the adhesive layer 214 using a wet or dry etching process. Once the openings are formed, conductive material for the reflowable connector 216 can be formed in these openings using one of the suitable methods described above. The structure can then undergo a reflow process, in which heat is applied to melt and reshape the conductive material to form the final shape of the reflowable connector 216. This process allows for precise positioning and formation of the reflowable connector 216 within the adhesive layer 214.

[0071] exist Figure 11In this process, a reflowable connector 216 is used to connect the UBM 140 of the wafer package 100 to the conductive bumps 206 of the rigid interposer 202, thereby completing the attachment of the wafer package 100 to the rigid interposer 202. Therefore, the reflowable connector 216 provides an electrical connection between the wafer package 100 and the rigid interposer 202. Furthermore, the adhesive layer 214 provides a mechanical connection between the wafer package 100 and the rigid interposer 202.

[0072] The UBM 140 can be attached to the conductive bump 206 using a suitable bonding technique, such as eutectic bonding. In some embodiments, the reflowable connectors 216 can be heated until they reach a molten state. The UBM 140 of the wafer package 100 can then be inserted into the molten reflowable connector 216. That is, each UBM 140 can be inserted into a corresponding molten reflowable connector 216. Simultaneously, the top dielectric layer of the wafer package 100 can be pressed against the adhesive layer 214. As the reflowable connector 216 cools and solidifies, a bond can be formed between the UBM 140 and the conductive bump 206. This bonding process can result in the UBM 140 partially extending into the reflowable connector 216, creating electrical and mechanical connections.

[0073] The spacing and alignment of the conductive bumps 206 can affect the assembly of the rigid interposer 202 and the wafer package 100. In some embodiments, the conductive bumps 206 on the rigid interposer 202 may be arranged with a pitch ranging from 500 μm to 950 μm, such as about 800 μm. This pitch allows sufficient spacing between adjacent conductive bumps 206 while maintaining the desired connectivity density. During the bonding process from the wafer package 100 to the rigid interposer 202, bonding misalignment may occur. In some embodiments, bonding misalignment may range from 50 μm to 200 μm, such as about 100 μm. This misalignment may be due to various factors, such as thermal expansion, mechanical stress, or alignment tolerances during the bonding process.

[0074] After attaching the wafer package 100 to the rigid interposer 202, the strip 212 can be removed to expose the conductive bumps 208 on the opposite side of the rigid interposer 202. Removing the strip 212 prepares the exposed conductive bumps 208 for subsequent attachment of additional components to the rigid interposer 202.

[0075] exist Figure 12 In this configuration, passive components 222 and external connectors 224 are attached to the side of the rigid interposer 202 opposite to the wafer package 100. These components allow for efficient power distribution and external connectivity to the resulting system package. Placing these components on the side of the rigid interposer 202 opposite to the wafer package 100 facilitates easier system maintenance or upgrades.

[0076] Passive device 222 may include passive components such as capacitors, resistors, inductors, or combinations thereof. Passive device 222 may be substantially devoid of active components. Passive device 222 may be used for filtering, energy storage, impedance matching, power management, etc. In some embodiments, passive device 222 is a module comprising multiple passive components, possibly disposed on a substrate such as a circuit board. As an alternative to or complement to passive device 222, other types of devices may be attached to the side of rigid interposer 202 opposite to wafer package 100. In some embodiments, optical devices, memory devices, or other types of integrated circuit devices may be attached to rigid interposer 202. These other devices may include active components.

[0077] In some embodiments, passive device 222 may be a voltage regulator. A voltage regulator may be a power management device used to maintain a stable voltage level for various components within wafer package 100. These regulators may be implemented in various forms, such as integrated circuit dies, discrete components on a circuit board, multi-chip modules, etc. Depending on the specific power requirements of the system, the voltage regulator may also be implemented as a switching regulator, a linear regulator, or a combination of both. Other types of passive devices may be used as an alternative to or complement to the voltage regulator. In some embodiments, passive device 222 may be a system-in-package (SiP) device that combines multiple functions, including power regulation, current sensing, and thermal management.

[0078] External connectors 224 can serve as interfaces for connecting system components (e.g., wafer package 100) to external systems or components. These connectors can be implemented as ribbon cable receivers, flexible printed circuit receivers, or other types of high-density interconnects. In some embodiments, external connectors 224 can support various communication protocols, such as PCI Express, USB, InfiniBand, custom high-speed interfaces, etc. The design of these connectors allows for easy attachment and removal of external cables or modules, facilitating integration of the resulting system package with external systems.

[0079] Passive device 222 and external connector 224 can be attached to rigid interposer 202 using reflowable connector 226, which connects the components to conductive bumps 208 on rigid interposer 202. Reflowable connector 226 can be formed of a conductive material, such as solder, copper, aluminum, gold, nickel, silver, tin, or combinations thereof. In some embodiments, reflowable connector 226 can be solder balls, metal pillars, controlled-collapse chip connection (C4) bumps, etc. Reflowable connector 226 can be formed by initially forming the conductive material using methods such as evaporation, electroplating, printing, solder transfer, or ball placement. After forming the conductive material, a reflow process can be performed to shape the material into the desired connector structure.

[0080] Attaching passive device 222 and external connector 224 to rigid interposer 202 may involve placing components onto rigid interposer 201 (e.g., conductive bump 208) using pick-and-place techniques, followed by a reflow process to establish reliable electrical and mechanical connections with conductive bump 208. In some embodiments, jig 220 may be used to facilitate the attachment process. Jig 220 may include an adjustable portion that can be positioned to support rigid interposer 202 and the attached components during placement and reflow. Jig 220 may also incorporate components to reduce warpage and ensure proper alignment of the components with conductive bump 208 on rigid interposer 202. In some embodiments, jig 220 may include a bottom portion for supporting rigid interposer 202 and wafer package 100, a top portion having an opening exposing rigid interposer 202, and an intermediate portion located between the top and bottom portions. The intermediate portion of jig 220 may be magnetically adjustable to fine-tune its position. This adjustability allows the clamp 220 to adapt to minute variations in component thickness or surface irregularities, which helps maintain consistent contact pressure on the rigid interposer 202 during attachment of the passive device 222 and the external connector 224.

[0081] After attaching the passive device 222 and the external connector 224, the fixture 220 can be removed. The remaining structure is the system package 200, which can be a SoW (System-on-Wait). The SoW is a complete computing system, including computing stations (including computing devices of the wafer package 100 and associated passive devices 222) and connection stations (including interface devices of the wafer package 100 and associated external connectors 224).

[0082] Optionally, the external connector 224P may be attached to the same side of the rigid interposer 202 as the wafer package 100. In some embodiments, when the system package 200 is used for silicon photonics applications, some external connectors 224P (or additional connectors) may be attached to the bottom side of the rigid interposer 202. The external connector 224P may be an optical die that performs optical signal processing, transmission, or reception. For example, the optical die may include components such as lasers, photodetectors, modulators, or waveguides to enable optical communication capabilities. In some embodiments, the external connector 224P is optically coupled to the wafer package 100, and the routing components 204 of the rigid interposer 202 are not inserted between them. For example, the system package 200 may include an optical path (such as an optical fiber cable or waveguide, not shown separately) between the sidewall of the external connector 224P and the sidewall of the wafer package 100. This arrangement can facilitate direct optical connections between components within the system package 200.

[0083] External connector 224P can be attached to a number of conductive bumps 206 on the side of rigid interposer 202 facing wafer package 100. This attachment process may involve using reflowable connectors similar to those used for attaching wafer package 100 to rigid interposer 202. Therefore, in some embodiments, a first subset of the conductive bumps 206 is attached to wafer package 100, while a second subset of the conductive bumps 206 is attached to external connector 224P. In some embodiments, clamps or securing devices may be employed to support rigid interposer 202 and ensure proper alignment of external connector 224P during the attachment process.

[0084] refer to Figure 13 The system package 200 is shown in more detail. Although for clarity, Figure 13 All the components discussed are shown in the diagram, but it should be understood that wafer package 100 may be located below rigid interposer 202 (e.g., going to page), and passive device 222 and external connector 224 may be located above wafer package 100 (e.g., leaving page).

[0085] Passive devices 222 can be located directly above computing devices 70A of wafer package 100, with each passive device 222 corresponding to a specific computing device 70A below it. This one-to-one alignment allows for efficient power delivery and regulation for each individual computing device 70A. Each passive device 222 can supply power to its corresponding computing device 70A via routing components in rigid interposer 202. Positioning passive devices 222 close to their respective computing devices 70A reduces power loss and / or voltage drop.

[0086] The external connector 224 can be located on the outer periphery of the rigid interposer 202, positioned along its edge. This placement facilitates easier connection to external components or systems because the external connector 224 is easily accessible at the outer boundary of the system package 200.

[0087] Interface device 70B is located at the edge of wafer package 100, possibly very close to external connector 224. In a top view, interface device 70B is positioned between external connector 224 and the array of passive devices 222 and computing devices 70A. Interface device 70B can be positioned to reduce the signal path length between external connector 224 and computing devices 70A. Interface device 70B can facilitate communication between external connector 224 and internal computing devices 70A, performing signal routing and data transmission within system package 200.

[0088] In the top view, the layout of components within system package 200 can be arranged about the periphery of wafer package 100. Passive device 222 can be located within the periphery of wafer package 100. Meanwhile, external connectors 224 and 224P can be located outside the periphery of wafer package 100. Other variations are possible. In some cases, due to the large size of the interposer, external connectors 224 and passive device 222 can be placed on the rigid interposer 202 with less constraint.

[0089] In this embodiment, both the rigid interposer 202 and the wafer package 100 are truncated circular wafers. In the top view, the rigid interposer 202 may have a different shape than the wafer package 100. For example, the rigid interposer 202 may be a non-truncated circular wafer, while the wafer package 100 may be a truncated circular wafer.

[0090] In addition, Figure 13 In the example, the components of system package 200 are symmetrically arranged. In another embodiment, an asymmetrical layout may be used. The layout of system package 200 can be determined based on specific application requirements.

[0091] Figure 14 This is a cross-sectional view of a system-on-wafer assembly 300 according to some embodiments. The system-on-wafer assembly 300 is formed by fixing a system package 200 between a thermal module 302 and a frame 304. By fixing the system package 200 between the thermal module 302 and the frame 304, warpage of the system package 200 can be reduced.

[0092] The thermal module 302 may be attached to the bottom of the system package 200, located on the same side as the wafer package 100. The thermal module 302 is in thermal contact with the wafer package 100. The thermal module 302 may be a heat sink, heat plate, cold plate, or similar device designed to manage heat dissipation of components within the system assembly 300 on the wafer. The thermal module 302 physically bonds a portion of the adhesive layer 214. In some embodiments, the thermal module 302 may have a recess to receive the wafer package 100 and external connector 224P (if present). The recess may allow the thermal module 302 to make closer contact with heat-generating components while providing space for other protruding elements.

[0093] Frame 304 is attached to the top of system package 200, providing structural support and protection for internal components such as external connector 224 and passive device 222. Frame 304 is a rigid support and may be formed of a material with high stiffness, such as a metal, for example, steel, titanium, cobalt, etc. In some embodiments, the on-wafer system package 300 may include a spacer (not shown separately) located between frame 304 and rigid interposer 202. Frame 304 (or spacer, if present) physically engages portions of rigid interposer 202. Frame 304 has a recess 308 that accommodates passive device 222 and external connector 224 on this side of rigid interposer 202. Frame 304 also has an opening 310 that can accommodate connectors (e.g., wires, cables, etc.) from external systems to external connector 224.

[0094] Bolt 306 can be used to secure system package 200 between thermal module 302 and frame 304. Bolt 306 can extend into or pass through thermal module 302 and / or frame 304. Specifically, thermal module 302 and frame 304 can include corresponding bolt holes, which can be threaded or unthreaded. When the bolt hole is threaded, bolt 306 can be screwed directly into the threaded hole. When the bolt hole is unthreaded, bolt 306 can be secured with fasteners (not shown separately), such as nuts, washers, etc. Bolt 306 secures the components of system-on-wafer assembly 300 together, providing structural integrity and proper alignment of the various layers. Bolt 306 (or fasteners on it) can be tightened to a specific torque to apply the desired clamping force on system-on-wafer assembly 300.

[0095] In some embodiments, frame 304 is first attached to rigid intermediary layer 202. The frame-intermediary layer assembly can then be fastened to thermal module 302 using bolts 306. In some embodiments, additional manufacturing steps may be used to assemble the assembly. For example, thermal module 302 may be attached to rigid intermediary layer 202 before frame 304. Optionally, in some embodiments, frame 304 and thermal module 302 may be attached to rigid intermediary layer 202 simultaneously. The specific assembly sequence may depend on factors such as the materials used, thermal considerations, and available manufacturing equipment.

[0096] In some embodiments, a thermal interface material (not shown separately) may be applied between the thermal module 302 and the wafer package 100. The thermal interface material enhances the thermal conductivity between the component and the thermal module 302, improving the overall heat dissipation of the system component 300 on the wafer. The thermal interface material may be a film comprising materials such as indium or other thermally conductive substances.

[0097] Other variations are anticipated. For example, bolt 306 may be omitted. In some embodiments, the thermal module 302 and frame 304 may instead be directly attached to both sides of the rigid interposer 202. This direct attachment can be achieved using screws extending into the rigid interposer 202. Alternatively, adhesives can be used to bond the thermal module 302 and frame 304 to the rigid interposer 202. In some embodiments, a combination of screws and adhesives can provide mechanical fastening and sealing. The specific attachment method may depend on factors such as the materials used, thermal considerations, and the assembly requirements of the system-on-wafer assembly 300.

[0098] Figure 15 This is a cross-sectional view of a system-on-a-wafer assembly 300 according to some other embodiments. This embodiment is similar to... Figure 14 In this embodiment, the frame 304 and bolts 306 are omitted. Since the passive device 222 and external connector 224 are attached to the rigid interposer 202 rather than directly to the wafer package 100, the frame 304 can be omitted. Depending on its construction, the rigid interposer 202 can provide sufficient structural support and protection for the wafer package 100 without the need for an additional frame. In some cases, this can allow for a more compact monolithic component design. The thermal module 302 can be held in place to manage heat dissipation of the components of the system-on-wafer assembly 300.

[0099] Figures 16 to 17 This is a cross-sectional view of a system-on-a-wafer assembly 300 according to some other embodiments. These embodiments are respectively similar to Figures 14 to 15 In this embodiment, the external connector 224P is omitted. Omitting the external connector 224P can simplify the manufacturing process, reduce costs, and / or allow for a more compact design.

[0100] The embodiments offer advantages. The rigid interposer 202 can serve as a stable platform for integrating multiple components (including wafer package 100, passive devices 222, and external connectors 224) within the system package 200. The rigidity of the rigid interposer 202 helps maintain the structural integrity of the system package 200. The large size of the rigid interposer 202 relative to the wafer package 100 allows for the integration of additional routing components and external connectors 224 around the periphery of the system package 200. The rigid interposer 202 may include routing components 204, such as optical waveguides and / or conductive traces, to facilitate efficient signal transmission between different components of the system package 200. Overall, utilizing the rigid interposer 202 in the system package 200 enables high-performance computing capabilities with a dense form factor suitable for applications such as artificial intelligence accelerators and high-bandwidth memory systems.

[0101] Figures 18 to 23 It is a wafer package 100 according to some other embodiments (see Figure 23 A cross-sectional view of an intermediate stage in the manufacturing process of the wafer package 100. This wafer package 100 can also be used in any of the aforementioned system packages 200.

[0102] exist Figure 18 In this embodiment, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. A back-side redistribution structure 112 is formed on the release layer 104. The back-side redistribution structure 112 can be configured to... Figures 4 to 5 The same method can be used, except that it can be constructed on a carrier substrate 102.

[0103] A bump under-metallization layer (UBML) 152 is formed for subsequent connection to the back-side redistribution structure 112. The UBML 152 has bump portions on the main surface of the upper dielectric layer of the back-side redistribution structure 112 and extends along the main surface of the upper dielectric layer, and has via portions extending through the upper dielectric layer of the back-side redistribution structure 112 to physically and electrically couple the upper metallization layer of the back-side redistribution structure 112. The UBML 152 may be formed of the same material as the metallization layer and may be formed by a similar process to the metallization layer. In some embodiments, the UBML 152 has different dimensions than the metallization layer.

[0104] exist Figure 19In this configuration, a via 154 is formed on a first subset of UBML 152. Additionally, an interconnect die 160 is attached to a second subset of UBML 152. The second subset of UBML 152 remains without via 154. The first subset of UBML 152 and the via 154 will subsequently be used for connection to higher layers of the wafer package. The second subset of UBML 152 and the interconnect die 160 will subsequently be used for direct communication between integrated circuit devices within the resulting wafer package.

[0105] As an example of forming the via 154, photoresist is formed and patterned on UBML 152 and the back-side redistribution structure 112. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the via 154. The patterning forms openings through the photoresist to expose UBML 152. Conductive material is formed in the openings of the photoresist and on the exposed portions of UBML 152. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material of the via 154 can be directly plated from the conductive material of UBML 152. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist is then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. The remaining portion of the conductive material forms the via 154.

[0106] Each interconnect die 160 may be a local silicon interconnect (LSI), a large-scale integrated package, an interposer die, etc. Each interconnect die 160 includes a substrate 162, in which and / or on the substrate 162, conductive components are formed. The substrate 162 may include a semiconductor substrate, one or more dielectric layers, etc. Furthermore, each interconnect die 160 may include a through-substrate via (TSV) 164 extending into or through the substrate 162 and coupled to the conductive components of the interconnect die 160. The interconnect die 160 is attached to the UBML 152 using die connectors 166 disposed on the back side of the interconnect die 160. Some die connectors 166 may be electrically coupled to the front side of the interconnect die 160 via the TSV 164. As described in more detail later, the TSV 164 is small, such as smaller than the through-hole 154. Due to the small size of the TSV 164, they can have a higher density, thereby increasing the amount of connectivity to the interconnect die 160.

[0107] In embodiments where interconnect die 160 is an LSI, interconnect die 160 may be a bridge structure including die bridge 168. Die bridge 168 may be a metallization layer formed in and / or on, for example, substrate 162, and is used to interconnect the above-mentioned integrated circuit devices (described below) with each other. Die bridge 168 is located on the front side of interconnect die 160. Therefore, LSI can be used to directly connect integrated circuit devices and allow communication between integrated circuit devices. In such embodiments, interconnect die 160 may be placed in a region disposed between subsequently attached integrated circuit devices, such that each interconnect die 160 overlaps with a plurality of above-mentioned integrated circuit devices. In some embodiments, interconnect die 160 may also include logic devices and / or memory devices. In some embodiments, interconnect die 160 may not have logic devices and / or memory devices. Interconnect die 160 is attached to UBML 152 such that die bridge 168 faces away from the back-side redistribution structure 112.

[0108] In the illustrated embodiment, interconnect die 160 is attached to back-side redistribution structure 112 (via UBML 152) using solder bonding (such as using conductive connector 170). Conductive connector 170 may be a ball grid array (BGA) connector, solder ball, metal pillar, controlled collapse chip connection (C4) bump, microbump, bump formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. Conductive connector 170 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connector 170 is initially formed by forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed, reflow can be performed to shape the material into the desired bump shape. Attaching the interconnect die 160 to the UBML 152 may include placing the interconnect die 160 on the UBML 152 (e.g., using a pick-and-place process) and returning the conductive connector 170 to physically and electrically couple the die connector 166 to the UBML 152. In another embodiment, the interconnect die 160 is attached to the back-side redistribution structure 112 via direct bonding using the die connector 166.

[0109] In some embodiments, underfill 172 is formed around the conductive connector 170 and between the back-side redistribution structure 112 and the interconnect die 160. Underfill 172 can reduce stress and protect the joints created by backflow of the conductive connector 170. Underfill 172 can also be used to securely bond the interconnect die 160 to the back-side redistribution structure 112 and provide structural support and environmental protection. Underfill 172 can be formed from molding compounds, epoxy resins, etc. Underfill 172 can be formed by a capillary flow process after attaching the interconnect die 160, or it can be formed by a suitable deposition method before attaching the interconnect die 160. Underfill 172 can be applied in liquid or semi-liquid form and then subsequently cured.

[0110] Optionally, the interconnect die 160 may include a die connector 174 disposed on the front side of the interconnect die 160. The die connector 174 may be electrically coupled to the die bridge 168.

[0111] Interconnect die 160 can be an optional component in the wafer package. The inclusion or exclusion of interconnect die 160 may depend on specific design requirements, performance targets, or manufacturing considerations. Furthermore, while interconnect die 160 can be implemented as a local silicon interconnect (LSI) in some cases, optional components such as integrated voltage regulators (IVRs) or integrated passive devices (IPDs) can be used instead of an LSI. Depending on the specific requirements of the wafer package, these optional components can provide different functionalities or advantages. For example, an IVR can provide improved power management capabilities, while an IPD can provide enhanced passive component integration within the wafer package.

[0112] exist Figure 20 In this process, sealant 176 is formed on and around various components. After formation, sealant 176 seals UBML 152, through-hole 154, interconnect die 160, and / or underfill 172. Sealant 176 can be a molding compound, epoxy resin, etc. Sealant 176 can be applied by compression molding, transfer molding, etc., and can be formed over carrier substrate 102, such that it buries or covers through-hole 154 and / or interconnect die 160. Sealant 176 is also formed in the gap region between interconnect die 160 and through-hole 154. Sealant 176 can be applied in liquid or semi-liquid form and then subsequently cured.

[0113] Optionally, a planarization process can be performed on the sealant 176 to expose the through-hole 154 and the interconnect die 160 (e.g., die connector 174). The planarization process may remove material from the through-hole 154, the interconnect die 160, and / or the sealant 176 until the interconnect die 160 and the through-hole 154 are exposed. After the planarization process, the upper surfaces of the through-hole 154, the die connector 174, and the sealant 176 are substantially coplanar (within process variations). The planarization process can be, for example, chemical mechanical polishing (CMP), lapping, etc. In some embodiments, for example, if the through-hole 154 and / or the die connector 174 have already been exposed, planarization can be omitted. After the planarization process, the through-hole 154 extends through the sealant 176. Therefore, the through-hole 154 may be referred to as a molded through-hole (TMV).

[0114] exist Figure 21 In this configuration, a front redistribution structure 180 is formed on the front surface of the sealant 176, the interconnect die 160 (e.g., die connector 174), and the through-hole 154. The front redistribution structure 180 includes a dielectric layer 182 and a metallization layer 184 (sometimes referred to as a redistribution layer or redistribution line) located between the dielectric layers 182. Therefore, the front redistribution structure 180 includes metallization layers 184 spaced apart from each other by respective dielectric layers 182. The metallization layer 184 of the front redistribution structure 180 connects to the through-hole 154 and the interconnect die 160 (e.g., die connector 174).

[0115] In some embodiments, dielectric layer 182 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB-based polymers, etc., and can be patterned using a photomask. In other embodiments, dielectric layer 182 is formed of a nitride (such as silicon nitride), an oxide (such as silicon oxide), etc. Dielectric layer 182 can be formed by spin coating, lamination, CVD, etc., or combinations thereof. After forming dielectric layer 182, dielectric layer 182 can be patterned to expose underlying conductive components, such as via 154, die connector 174, and / or portions of metallization layer 184. Patterning can be performed by any acceptable process, such as exposing dielectric layer 182 to light when dielectric layer 182 is formed of a photosensitive material, or by etching, for example, anisotropic etching. If dielectric layer 182 is formed of a photosensitive material, dielectric layer 182 can be developed after exposure.

[0116] Each of the metallization layers 184 includes a conductive via and / or a wire. The conductive via extends through the corresponding dielectric layer 182, and the wire extends along the corresponding dielectric layer 182. As an example of forming the metallization layer 184, a seed layer (not shown separately) is formed over the corresponding underlying component. For example, the seed layer may be formed on the corresponding dielectric layer 182 and in any opening through the corresponding dielectric layer 182. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using a deposition process such as PVD. Photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 184. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating (such as electroless plating or electroplating) from the seed layer. The conductive material may include metals or metal alloys, such as copper, titanium, tungsten, aluminum, or combinations thereof. Then, the portions of the photoresist and seed layer where no conductive material has formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by an acceptable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization layer 184 of the front-side redistribution structure 180.

[0117] The front redistribution structure 180 is shown as an example. By performing the aforementioned steps any desired number of times, more or fewer dielectric layers 182 and metallization layers 184 can be formed than shown.

[0118] Under-bump metallization (UBM) 186 may be formed through the upper dielectric layer 182 of the front redistribution structure 180. UBM 186 is physically and electrically coupled to the upper metallization layer 184 of the front redistribution structure 180. Each of UBM 186 includes a conductive via and a conductive bump. The conductive via extends through the upper dielectric layer 182, and the conductive bump extends along the upper dielectric layer 182. UBM 186 may be formed of the same material as the metallization layer 184. In some embodiments, UBM 186 has different dimensions than the metallization layer 184.

[0119] exist Figure 22 In this configuration, integrated circuit device 70 is attached to the front redistribution structure 180. Integrated circuit device 70 can be arranged in any of the above patterns and can be arranged in a high-density configuration.

[0120] In the illustrated embodiment, the integrated circuit device 70 is attached to the front redistribution structure 180 using solder bonding (such as using conductive connector 192). The conductive connector 192 may be formed of a reflowable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive connector 192 is formed by initially forming a solder layer using methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed, reflow can be performed to shape the conductive connector 192 into a desired bump shape. Attaching the integrated circuit device 70 to the front redistribution structure 180 may include placing the integrated circuit device 70 on the front redistribution structure 180 and reflowing the conductive connector 192. The integrated circuit device 70 may be placed on the front redistribution structure 180 using, for example, pick-and-place tools. The return conductive connector 192 is used to attach the die connector 194 at the front side of the integrated circuit device 70 to the UBM 186 of the front redistribution structure 180, thereby electrically connecting the front redistribution structure 180 to the integrated circuit device 70. In another embodiment, the die connector 194 is used to attach the integrated circuit device 70 to the front redistribution structure 180 via direct bonding.

[0121] In some embodiments, underfill 196 is formed around the conductive connector 192 and between the front redistribution structure 180 and the integrated circuit device 70. Underfill 196 can reduce stress and protect the joints created by backflow of the conductive connector 192. Underfill 196 can be formed of an underfill material such as molding compound, epoxy resin, etc. Underfill 196 can be formed by a capillary flow process after the integrated circuit device 70 is attached to the front redistribution structure 180, or by a suitable deposition method before the integrated circuit device 70 is attached to the back redistribution structure 80. Underfill 196 can be applied in liquid or semi-liquid form and then subsequently cured.

[0122] A sealant 106 is formed around the various components. After formation, the sealant 106 laterally seals the underfill 196 (if present) and the integrated circuit device 70. The sealant 106 can be a molding compound, epoxy resin, etc. The sealant 106 can be applied by compression molding, transfer molding, etc., and can be formed over the front redistribution structure 180, thereby burying or covering the integrated circuit device 70. The sealant 106 is also formed in the gap region between the underfill 196 (if present) and / or the integrated circuit device 70. The sealant 106 can be applied in liquid or semi-liquid form and then subsequently cured.

[0123] Optionally, a removal process can be performed on the sealant 106 to expose the integrated circuit device 70. The removal process may include, for example, planarization processes, such as chemical mechanical polishing (CMP), grinding processes, etc. After the planarization process, the sealant 106 and the upper surface of the integrated circuit device 70 may be substantially coplanar (within process variations). For example, if the integrated circuit device 70 is already exposed, planarization may be omitted.

[0124] exist Figure 23 In this process, carrier substrate debonding can be performed to separate (or “debond”) the carrier substrate 102 from the back-side redistribution structure 112. According to some embodiments, debonding involves projecting light, such as UV light, onto the release layer 104, causing the release layer 104 to decompose under the heat of the light, and the carrier substrate 102 can be removed. The remaining structure is the wafer package 100. The wafer package 100 can be placed on a strip, a carrier substrate, or another suitable support structure (not shown separately) for subsequent processing.

[0125] A UBM 140 can be formed for subsequent connection to the back-side redistribution structure 112. The UBM 140 has a bump portion located on and extending along the main surface of the lower dielectric layer of the back-side redistribution structure 112, and a via portion extending through the lower dielectric layer of the back-side redistribution structure 112 to physically and electrically couple the lower metallization layer of the back-side redistribution structure 112. The UBM 140 can be formed of the same material as the metallization layer and can be formed using a similar process to the metallization layer. In some embodiments, the UBM 140 can have different dimensions than the metallization layer.

[0126] Figures 24 to 25 This is a cross-sectional view of a system-on-a-wafer assembly 300 according to some other embodiments. These embodiments are respectively similar to Figures 16 to 17 In this embodiment, the wafer package 100 is formed directly on the rigid interposer 202. That is, the back-side redistribution structure 112 can be constructed above the rigid interposer 202, rather than above a separate carrier substrate. As a result, the width of the rigid interposer 202 can be equal to (but not greater than) the width of the wafer package 100.

[0127] In some embodiments, the device includes: an interposer; a package attached to a first side of the interposer, the package including a sealant and an integrated circuit device located within the sealant; a plurality of passive devices attached to a second side of the interposer, the interposer electrically connecting the passive devices to the integrated circuit device; and a plurality of first external connectors attached to the second side of the interposer, the interposer electrically connecting the first external connectors to the integrated circuit device, wherein, in a top view, the first external connectors are disposed outside the outer periphery of the package. In some embodiments, the device further includes: an adhesive film attaching the package to the interposer; and a plurality of reflowable connectors extending through the adhesive film, the reflowable connectors engaging conductive bumps of the package to conductive bumps of the interposer. In some embodiments, the device further includes: a plurality of second external connectors attached to a first side of the interposer, wherein, in a top view, the second external connectors are disposed outside the outer periphery of the package. In some embodiments of the device, the second external connectors are optically connected to the integrated circuit device via a direct optical connection. In some embodiments of the device, the first external connector is a ribbon cable receiver, and the passive device is a voltage regulator. In some embodiments of the device, the package is a truncated circular wafer, and the interposer is a non-truncated circular wafer. In some embodiments of the device, corresponding passive devices overlap with corresponding integrated circuit devices. In some embodiments, the device further includes: a cold plate attached to a first side of the interposer, the cold plate being in thermal contact with the package; a frame attached to a second side of the interposer, the frame having an opening exposing a first external connector; and a plurality of bolts extending through the cold plate and the frame. In some embodiments of the device, the package includes more than eight integrated circuit devices, and each integrated circuit device includes a system-on-a-chip die and a plurality of memory dies.

[0128] In some embodiments, the device includes: a cold plate; a frame including an opening; and a system package located between the cold plate and the frame, the system package including: an interposer; a wafer package attached to a first side of the interposer, the width of the interposer being greater than the width of the wafer package, the wafer package including a sealant and an integrated circuit device located within the sealant; and a plurality of external connectors attached to a second side of the interposer, the interposer electrically connecting the external connectors to the integrated circuit device, the opening in the frame exposing the external connectors. In some embodiments, the device further includes: a plurality of bolts extending through the cold plate and the frame. In some embodiments of the device, the wafer package is a truncated circular wafer, and the interposer is a non-truncated circular wafer. In some embodiments of the device, the system package further includes: an adhesive film attaching the wafer package to the interposer. In some embodiments of the device, the external connectors are flexible printed circuit receivers.

[0129] In embodiments, the method includes: attaching a package to a first side of an interposer, the package including a sealant and an integrated circuit device located within the sealant; attaching a plurality of passive devices to a second side of the interposer, the interposer electrically connecting the passive devices to the integrated circuit device, the passive devices being disposed within the outer periphery of the package in a top view; and attaching a plurality of external connectors to the second side of the interposer, the interposer electrically connecting the external connectors to the integrated circuit device, the external connectors being disposed outside the outer periphery of the package in a top view. In some embodiments of the method, attaching the package to the first side of the interposer includes: forming an adhesive film on the first side of the interposer; and pressing a dielectric layer of the package against the adhesive film. In some embodiments of the method, attaching the package to the first side of the interposer further includes: forming a plurality of reflowable connectors through the adhesive film; and pressing conductive bumps of the package into the reflowable connectors while reflowing the reflowable connectors. In some embodiments of the method, attaching passive devices to the second side of the interposer includes: aligning the passive devices with the integrated circuit device in a top view. In some embodiments, the method further includes: placing the package on a cold plate; placing a frame on an interposer; and screwing the cold plate and the frame together. In some embodiments, the method further includes: placing the package and the interposer in a fixture while attaching passive devices and external connectors to a second side of the interposer.

[0130] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: Intermediate layer; A package is attached to a first side of the interposer, the package including a sealant and a plurality of integrated circuit devices located within the sealant; Multiple passive devices are attached to a second side of the interposer layer, and the interposer layer electrically connects the passive devices to the integrated circuit device. as well as Multiple first external connectors are attached to the second side of the interposer layer, which electrically connects the first external connectors to the integrated circuit device. In a top view, the first external connectors are disposed on the outer periphery of the package.

2. The semiconductor device according to claim 1, further comprising: An adhesive film is used to attach the package to the interlayer. as well as Multiple reflowable connectors extend through the adhesive film, the reflowable connectors engaging the conductive bumps of the package to the conductive bumps of the interposer layer.

3. The semiconductor device according to claim 1, further comprising: Multiple second external connectors are attached to the first side of the intermediary layer, and in the top view, the second external connectors are disposed outside the outer periphery of the package.

4. The semiconductor device according to claim 3, wherein, The second external connector is optically connected to the integrated circuit device via a direct optical connection.

5. The semiconductor device according to claim 1, wherein, The first external connector is a ribbon cable receiver, and the passive device is a voltage regulator.

6. The semiconductor device according to claim 1, wherein, The package is a truncated circular wafer, and the interposer is a non-truncated circular wafer.

7. The semiconductor device according to claim 1, wherein, The corresponding passive device overlaps with the corresponding integrated circuit device.

8. The semiconductor device according to claim 1, further comprising: A cold plate is attached to the first side of the intermediate layer, and the cold plate is in thermal contact with the package. A frame, attached to the second side of the intermediary layer, the frame having an opening that exposes the first external connector; as well as Multiple bolts extend through the cold plate and the frame.

9. A semiconductor device, comprising: Cold plate; The frame includes openings; as well as A system package, located between the cold plate and the frame, comprises: Intermediate layer; A wafer package is attached to a first side of an interposer layer, the width of which is greater than the width of the wafer package, the wafer package including a sealant and a plurality of integrated circuit devices located within the sealant; and Multiple external connectors are attached to a second side of the interposer layer, which electrically connects the external connectors to the integrated circuit device, and the openings in the frame expose the external connectors.

10. A method of forming a semiconductor device, comprising: The package is attached to a first side of the interposer, the package including a sealant and a plurality of integrated circuit devices located in the sealant; Multiple passive devices are attached to a second side of the interposer layer, which electrically connects the passive devices to the integrated circuit device. In a top view, the passive devices are disposed within the outer periphery of the package. as well as Multiple external connectors are attached to the second side of the interposer layer, which electrically connects the external connectors to the integrated circuit device. In a top view, the external connectors are disposed outside the outer periphery of the package.

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