Semiconductor device, chip, electronic equipment and preparation method of semiconductor device

Abstract

The present specification provides a semiconductor device, a chip, an electronic apparatus, and a method of manufacturing the semiconductor device, the semiconductor device comprising: a first wafer having a first arithmetic unit thereon; the second wafer is provided with a first input / output unit; and the bonding structure is arranged between the first wafer and the second wafer and is configured to electrically connect the first wafer with the second wafer. The semiconductor device has the effects of reducing the preparation cost and reducing the process difficulty; a chip applying the semiconductor device has relatively high calculation performance and relatively low power consumption.

Description

Technical Field

[0001] This specification relates to the field of semiconductor device technology, and in particular to a semiconductor device, chip, electronic device, and method for fabricating a semiconductor device. Background Technology

[0002] As integrated circuit (IC) manufacturing processes continue to evolve, traditional planar transistors and FinFET structures are gradually approaching their physical limits in terms of device size reduction, performance improvement, and power consumption control. To further improve transistor integration and area utilization efficiency, novel device solutions such as flip-FET structures have been proposed. This type of structure arranges N-channel metal-oxide-semiconductor transistors (NMOS) and P-channel metal-oxide-semiconductor transistors (PMOS) on opposite sides of the wafer, allowing complementary circuits using both NMOS and PMOS within the same intellectual property (IP) to be symmetrically arranged on both sides of the wafer, thus significantly improving layout area utilization.

[0003] In complementary logic implemented using the Flip-FET structure, since the NMOS and PMOS are positioned on opposite sides of the wafer, it's equivalent to distributing devices that were originally located on the same plane onto two surfaces. This reduces the layout area by almost 50%, nearly doubling the area utilization efficiency. Therefore, in scenarios requiring a large number of complementary transistor arrays, such as STC (System-to-Compute) cells and SRAM (Static Random Access Memory), the Flip-FET solution offers significant advantages in terms of area, performance, and power consumption.

[0004] However, in actual IC design, in addition to the core logic and memory modules such as STC and SRAM, it is usually necessary to arrange various input / output (I / O) devices such as power management units, interface transceiver units, and ESD protection units. These I / O devices often have an N / P asymmetric structure, and in some applications, only NMOS or only PMOS are used. For such unipolar or asymmetric devices, if the Flip-FET layout with NMOS and PMOS on both sides of the wafer is still used, it is difficult to achieve effective symmetrical arrangement on both sides. This will inevitably result in the wafer area on one side not being fully utilized, causing the original area advantage of Flip-FET to be basically lost, while also bearing the process complexity and cost burden associated with Flip-FET. Therefore, how to reduce process difficulty and improve yield while maintaining high area utilization while taking into account the integration requirements of core logic units, memory units, and input / output devices has become an urgent problem to be solved in related technical fields. Summary of the Invention

[0005] To overcome the problems existing in related technologies, this specification provides a semiconductor device, a chip, an electronic device, and a method for fabricating a semiconductor device.

[0006] According to a first aspect of the embodiments of this specification, a semiconductor device is provided, the semiconductor device comprising: The first wafer has a first computing unit on it; The second wafer has a first input / output unit on it; A bonding structure, disposed between the first wafer and the second wafer, is configured to electrically connect the first wafer and the second wafer. In some embodiments of this disclosure, the first wafer includes: A first semiconductor structure has a first side and a second side disposed opposite to each other; A first metal structure is electrically connected to a first side of the first semiconductor structure to form a plurality of first transistors, and the first metal structure has a first conductive electronic structure. A first metal structure is electrically connected to a second side of the first semiconductor structure to form a plurality of second transistors, and the second metal structure has a first conductive transistor structure. The first conductive structure is electrically connected to the second conductive structure, and the plurality of first transistors and the plurality of second transistors together constitute at least a part of the first computing unit.

[0007] In some embodiments of this disclosure, the first semiconductor structure has at least one fin, the fin including a channel region and a source / drain region corresponding to the channel region; The first metal structure is electrically connected to the gate structure corresponding to the channel region and the source / drain region to form the plurality of first transistors; The second metal structure is electrically connected to the gate structure corresponding to the channel region and the source / drain region to form the plurality of second transistors.

[0008] In some embodiments of this disclosure, the first transistor is an N-type transistor and the second transistor is a P-type transistor; Alternatively, the first transistor may be a P-type transistor and the second transistor may be an N-type transistor.

[0009] In some embodiments of this disclosure, the second wafer includes: Second semiconductor structure; A third metal structure is disposed on one side of the second semiconductor structure to form a row and column arrangement of third transistors on one side of the second semiconductor structure; The plurality of the third transistors constitute at least a portion of the first input / output unit.

[0010] In some embodiments of this disclosure, the plurality of third transistors are at least one type of N-type transistor and P-type transistor.

[0011] In some embodiments of this disclosure, a second input / output unit is further formed on the first wafer; The second input / output unit is electrically connected to the first arithmetic unit, and the second input / output unit is electrically connected to the first input / output unit through the bonding structure.

[0012] In some embodiments of this disclosure, a first memory cell is further formed on the first wafer; The first storage unit is electrically connected to the first arithmetic unit, and the first storage unit is electrically connected to the first input / output unit through the bonding structure.

[0013] In some embodiments of this disclosure, a second memory cell is further formed on the second wafer; The second storage unit is electrically connected to the first input / output unit, and the second storage unit is electrically connected to the first arithmetic unit through the bonding structure.

[0014] In some embodiments of this disclosure, a second computing unit is further formed on the second wafer; The second arithmetic unit is electrically connected to the first input / output unit, and the second arithmetic unit is electrically connected to the first arithmetic unit through the bonding structure.

[0015] According to a second aspect of the embodiments of this specification, a chip is provided, the chip comprising at least one of the semiconductor devices described herein.

[0016] According to a third aspect of the embodiments of this specification, an electronic device is provided, the electronic device including the aforementioned chip.

[0017] According to a fourth aspect of the embodiments of this specification, a method for fabricating a semiconductor device is provided, applicable to the semiconductor device, the method comprising: Provide the first wafer; Provide a second wafer; The first wafer and the second wafer are aligned and bonded.

[0018] In some embodiments of this disclosure, providing a first wafer includes: A first semiconductor structure is provided, the first semiconductor structure having a first side and a second side disposed opposite to each other; At least one fin is formed on a first semiconductor structure, the fin having a channel region and a source / drain region corresponding to the channel region; A first metal structure is fabricated on a first side of the first semiconductor structure. The first metal structure is electrically connected to the gate structure corresponding to the channel region and the source / drain region to form a plurality of first transistors arranged in rows and columns on the first side. A second metal structure is fabricated on the second side of the first semiconductor structure. The second metal structure is electrically connected to the gate structure corresponding to the channel region and the source / drain region to form a plurality of second transistors arranged in rows and columns on the second side. The plurality of first transistors and the plurality of second transistors together constitute at least a part of the first computing unit.

[0019] In some embodiments of this disclosure, providing a second wafer includes: Provide a second semiconductor structure; A third metal structure is fabricated on one side of the second semiconductor structure to form a row-and-column arrangement of third transistors on one side of the second semiconductor structure; a plurality of the third transistors constitute at least a portion of the first input / output unit.

[0020] In some embodiments of this disclosure, providing the first wafer further includes: The plurality of first transistors and the plurality of second transistors together constitute at least a portion of the first memory cell and / or the second input / output cell.

[0021] In some embodiments of this disclosure, providing a second wafer further includes: The plurality of the third transistors together constitute at least a portion of the second arithmetic unit and / or the second memory unit.

[0022] Beneficial effects: This solution establishes an electrical connection between a first arithmetic unit on the first wafer and a first input / output unit on the second wafer by setting a bonding structure between the first wafer and the second wafer. Since the signal transmission between the first arithmetic unit and the first input / output unit is directly carried by the inter-wafer bonding structure, the cross-wafer connection path is relatively shortened, and parasitic effects such as resistance and capacitance introduced by the interconnect are correspondingly reduced. Therefore, this improves the data interaction bandwidth and timing margin between the first arithmetic unit and the first input / output unit, while reducing interconnect losses and thus improving overall energy efficiency. Furthermore, since the first arithmetic unit and the first input / output unit are formed on different wafers, they can be independently optimized in terms of process and layout on their respective wafers, reducing functional coupling constraints within a single wafer and thus improving system integration flexibility and scalability. Moreover, the first and second wafers can be manufactured and tested separately before bonding integration, facilitating defect screening and grading, thereby helping to improve product yield and reduce overall manufacturing costs.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0025] Figure 1 This is a schematic diagram of a first wafer in some embodiments of this disclosure.

[0026] Figure 2 This is a schematic diagram of a second wafer in some embodiments of this disclosure.

[0027] Figure 3 This is a schematic diagram of the structure of a semiconductor device in some embodiments of this disclosure.

[0028] Figure 4 This is a schematic diagram of the first wafer in some other embodiments of this disclosure.

[0029] Figure 5 This is a schematic diagram of a second wafer in some other embodiments of this disclosure.

[0030] Figure 6 This is a schematic diagram of the structure of a semiconductor device in some other embodiments of this disclosure.

[0031] Figure 7 This is a schematic diagram of the first wafer in some other embodiments of this disclosure.

[0032] Figure 8 This is a schematic diagram of a second wafer in some other embodiments of this disclosure.

[0033] Figure 9 This is a schematic diagram of the structure of a semiconductor device in some other embodiments of this disclosure.

[0034] Figure 10 This is a schematic diagram of the structure of the first wafer in an embodiment of this disclosure.

[0035] Figure 11 This is a schematic diagram of the structure of the second wafer in an embodiment of this disclosure.

[0036] Figure 12 This is a schematic diagram illustrating the steps involved in fabricating a semiconductor device according to an embodiment of this disclosure.

[0037] Figure 13 This is a schematic diagram of the steps for fabricating the first wafer in an embodiment of this disclosure.

[0038] Figure 14 This is a schematic diagram of the steps for fabricating the second wafer in an embodiment of this disclosure.

[0039] Explanation of reference numerals in the attached figures: 1. First wafer; 11. First memory cell; 12. First arithmetic unit; 13. First semiconductor structure; 14. First metal structure; 15. Second metal structure; 16. Fin; 17. Second input / output unit; 2. Second wafer; 21. First input / output unit; 22. Second memory cell; 23. Second semiconductor structure; 24. Third metal structure; 25. Second arithmetic unit; 3. Bonding structure. Detailed Implementation

[0040] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0041] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0042] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0043] In related technologies, semiconductor devices, in addition to core logic units such as arithmetic and memory units, typically require various input / output units, including power management units, interface transceiver units, and protection units. Taking input / output units as an example, they often exhibit an N / P asymmetric structure, and in some applications, only NMOS or only PMOS are used. For such unipolar or asymmetric devices, if a flip-FET layout with NMOS and PMOS arranged on opposite sides of the wafer is still used, it is difficult to achieve effective symmetrical arrangement on both sides. This inevitably leads to insufficient utilization of the wafer area on one side, essentially negating the original area advantage of flip-FETs, while also incurring the process complexity and cost burden associated with flip-FETs.

[0044] Based on this, in a first aspect, a semiconductor device is provided.

[0045] See Figure 1 , Figure 2 and Figure 3 The semiconductor device includes a first wafer 1, a second wafer 2, and a bonding structure 3; the first wafer 1 has a first arithmetic unit 12; the second wafer 2 has a first input / output unit 21; the bonding structure 3 is disposed between the first wafer 1 and the second wafer 2 and is configured to electrically connect the first wafer 1 and the second wafer 2.

[0046] In this embodiment of the disclosure, the first arithmetic unit 12 integrated on the first wafer 1 performs arithmetic processing on the data to be processed during operation, and interacts with the first input / output unit 21 through the bonding structure 3 between the first wafer 1 and the second wafer 2; the first input / output unit 21 transmits the data input from the external circuit to the first arithmetic unit 12 through the bonding structure 3, and returns the calculation result output by the first arithmetic unit 12 to the first input / output unit 21 through the bonding structure 3 for external output. Since the electrical connection between the first arithmetic unit 12 and the first input / output unit 21 is directly achieved by the bonding structure 3, the cross-module signal path is relatively shortened, and the interconnection parasitic parameters are reduced accordingly. This is beneficial to improving the data interaction bandwidth between the first arithmetic unit 12 and the first input / output unit 21 and improving the timing margin, while reducing interconnection losses to improve overall energy efficiency. Furthermore, the arithmetic function and the input / output function are placed on the first wafer 1 and the second wafer 2 respectively, so that they can be optimized in terms of process and layout respectively, reducing the coupling constraints of single wafer integration, which is beneficial to improving the flexibility and scalability of system integration. Moreover, the first wafer 1 and the second wafer 2 can be manufactured and tested separately before integration, which helps to improve the yield of finished products and control manufacturing costs.

[0047] As an example, the bonding structure 3 can be an interconnect interface structure for realizing the electrical connection between the first wafer 1 and the second wafer 2. The bonding structure 3 may include a conductive bonding structure and / or a dielectric bonding structure. The conductive bonding structure may include conductive pads, conductive bumps, conductive pillars, metal interconnect layers and their mating structures disposed on the surface of the first wafer 1 and / or the second wafer 2. The dielectric bonding structure may include an oxide bonding layer, a dielectric layer and its surface activation structure. The conductive bonding structure and the dielectric bonding structure may be combined to form a hybrid bonding structure to realize electrical connection and signal transmission while providing mechanical connection strength.

[0048] Furthermore, the bonding method of the bonding structure 3 can include 3D bonding and / or 2.5D bonding: In 3D bonding, the first wafer 1 and the second wafer 2 are aligned and directly bonded in the wafer stacking direction to form a vertically stacked layer structure and achieve inter-wafer electrical connection. In 2.5D bonding, the first wafer 1 and the second wafer 2 are electrically connected through an interposer structure, which can be an interposer wafer, a silicon interposer, or a packaging substrate, thereby achieving lateral wiring expansion and external pin fan-out while maintaining modular integration.

[0049] Furthermore, the bonding method of the bonding structure 3 can also be a hybrid bonding method. Specifically, in the hybrid bonding method, the bonding structure 3 can be formed by a combination of conductive docking structures and dielectric docking structures. The conductive docking structures can include metal pads, metal interconnect layers, or metal pillars respectively disposed on the opposing surfaces of the first wafer 1 and the second wafer 2. The dielectric docking structures can include oxide layers or other dielectric layers respectively disposed on the opposing surfaces of the first wafer 1 and the second wafer 2. During the alignment bonding process, the conductive docking structures are aligned and docked with each other to form an electrical connection after bonding, thereby constituting a conductive path. The dielectric docking structures are aligned and docked with each other to provide mechanical connection and electrical isolation, so that the first wafer 1 and the second wafer 2 can achieve high-density electrical connection and signal transmission while obtaining reliable mechanical bonding.

[0050] It should be noted that the bonding method of the bonding structure 3 is not limited to the above-mentioned hybrid bonding method. Other wafer-level or chip-level bonding methods can also be used to connect the first wafer 1 and the second wafer 2. This application will not elaborate further.

[0051] Furthermore, a second input / output unit 17 may also be formed on the first wafer 1 (not specifically shown in the accompanying drawings). The second input / output unit 17 is electrically connected to the first storage unit 11 and the first arithmetic unit 12 on the first wafer 1 through the first metal structure 14, and is electrically connected to the first input / output unit 21 on the second wafer 2 through the bonding structure 3, thereby forming a three-dimensional layered input / output architecture between the first wafer 1 and the second wafer 2.

[0052] Furthermore, the second input / output unit 17 can implement functions such as a local bus interface, high-speed internal link, test interface or on-chip network port close to the first arithmetic unit 12 as needed, and together with the first input / output unit 21, undertake the transmission and reception of data signals and protocol processing.

[0053] A second input / output unit 17 is disposed on the first wafer 1. On the one hand, the second input / output unit 17 is integrated on the same side as the first storage unit 11 and the first arithmetic unit 12, which can shorten the connection length between the core logic and the corresponding input / output circuits, reduce the parasitic resistance and capacitance of the interconnection, thereby improving the bandwidth of the high-speed internal interface and reducing the latency, making it suitable for carrying local interfaces with high timing margin requirements. On the other hand, the first input / output unit 21 is centrally arranged on the second wafer 2, which can focus on realizing high-voltage, high-current or long-connection interfaces facing the package pads, while the second input / output unit 17 focuses on low-voltage, local communication interfaces inside the first wafer 1 and between wafers. The two work together through the inter-wafer electrical connection path established by the bonding structure 3, thereby achieving flexible sharing of input / output functions without significantly increasing the burden on the second wafer 2, and optimizing the allocation of input / output resources between the two wafers. In addition, when the first arithmetic unit 12 and the first storage unit 11 on the first wafer 1 need to be independently tested, debugged or partially independently applied, the second input / output unit 17 can also serve as a direct access path, improving testability and reusability, and helping to improve the flexibility and reliability of the overall design.

[0054] In some embodiments, a first storage cell 11 is formed on the first wafer 1. During operation, an external circuit loads data to be processed, instructions, and control information into the first input / output unit 21. The first input / output unit 21 transmits electrical signals to the first wafer 1 via the bonding structure 3. The first arithmetic unit 12 performs a write operation on the first storage cell 11, enabling the first storage cell 11 to cache input data, save intermediate results, and store instructions to be executed. During the arithmetic phase, the first arithmetic unit 12 reads data from the first storage cell 11 to complete the arithmetic processing and writes the arithmetic result back to the first storage cell 11, or transmits it back to the first input / output unit 21 via the bonding structure 3 for external output.

[0055] Furthermore, when the second input / output unit 17 is formed on the first wafer 1, the external circuit also loads electrical signals to the first arithmetic unit 12 and the first storage unit 11 through the second input / output unit 17, and exchanges data with the first input / output unit 21 through the bonding structure 3; when the second storage unit 22 is formed on the second wafer 2, the external circuit loads data to the second storage unit 22 through the first input / output unit 21, and forwards data to the first wafer 1 through the bonding structure 3; when the second arithmetic unit 25 is formed on the second wafer 2, the external circuit provides input data to the second arithmetic unit 25 through the first input / output unit 21 and obtains the processing result, and processes it collaboratively with the first arithmetic unit 12 through the bonding structure 3. Based on the above mechanism, the first storage unit 11 and the first arithmetic unit 12 form a close data proximity cooperation within the same first wafer 1, reducing cross-wafer round-trip transmission, thereby reducing access latency and interconnect power consumption and improving throughput. At the same time, the inter-wafer electrical connection capability provided by the bonding structure 3 supports the distributed integration of functional units, which is beneficial to improving the system integration flexibility and scalability.

[0056] In some implementations, see Figure 4 , Figure 5 and Figure 6 The first wafer 1 includes a first arithmetic unit 12 and a first storage unit 11; the second wafer 2 includes a first input / output unit 21; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0057] The data, instructions, and control signals to be processed by the external circuit are first loaded onto the first input / output unit 21 on the second wafer 2. After buffering and protocol / level matching of the received signals, the first input / output unit 21 transmits them to the first wafer 1 via the bonding structure 3. The first arithmetic unit 12 receives the input signals from the bonding structure 3 and writes the data into the first storage unit 11 to complete input buffering, instruction / parameter storage, or intermediate result temporary storage. In the arithmetic stage, the first arithmetic unit 12 reads the data / instructions from the first storage unit 11 to perform arithmetic processing and writes the arithmetic results back to the first storage unit 11 and / or transmits them back to the first input / output unit 21 via the bonding structure 3. The first input / output unit 21 outputs the arithmetic results to the external system or continues to forward them to the external system.

[0058] The first storage unit 11 and the first arithmetic unit 12 are co-integrated on the first wafer 1, enabling high-frequency read / write operations and intermediate result write-backs to be primarily completed within the first wafer 1 during computation. This reduces the number of cross-wafer round-trip transmissions, thereby lowering access latency and interconnect power consumption while increasing throughput. Simultaneously, the first arithmetic unit 12 and the first input / output unit 21 establish a direct inter-wafer electrical connection via the bonding structure 3, shortening the signal transmission path and reducing interconnect parasitic parameters. This improves the data interaction bandwidth and timing margin between the first arithmetic unit 12 and the first input / output unit 21. Furthermore, arranging the first input / output unit 21 on the second wafer 2 and the first arithmetic unit 12 and the first storage unit 11 on the first wafer 1 facilitates layout and process configuration according to requirements. Integration can also be performed after manufacturing and testing on both wafers separately, helping to improve yield and reduce overall manufacturing costs. In other embodiments, the first wafer 1 includes the first arithmetic unit 12 and the second input / output unit 17; the second wafer 2 includes the first input / output unit 21; and the first wafer 1 and the second wafer 2 are electrically connected via the bonding structure 3.

[0059] In other embodiments, the first wafer 1 includes a first arithmetic unit 12, a first storage unit 11, and a second input / output unit 17; the second wafer 2 includes a first input / output unit 21; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0060] The external circuit loads the data to be processed, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2. After the first input / output unit 21 completes the transmission and reception of the external interface and the protocol / level correlation processing, it transmits the electrical signals to the second input / output unit 17 on the first wafer 1 via the bonding structure 3. The second input / output unit 17 distributes the electrical signals within the first wafer 1 to the first arithmetic unit 12 and the first storage unit 11. The first storage unit 11 is used to buffer input data, save intermediate results, and store instructions to be executed. The first arithmetic unit 12 reads data from the first storage unit 11, performs the operation, and writes the result back to the first storage unit 11. The operation result is further aggregated by the second input / output unit 17 and then transmitted back to the first input / output unit 21 via the bonding structure 3 for external output.

[0061] The second input / output unit 17 is co-integrated with the first arithmetic unit 12 and the first storage unit 11 on the first wafer 1. This allows the high-speed signal loading, readback, and memory-to-memory interaction on the core side to be mainly completed within the first wafer 1. The local interconnects are shorter and the parasitic parameters are lower, which helps to reduce latency and interconnect power consumption and improve internal throughput. At the same time, the first input / output unit 21 and the second input / output unit 17 are directly connected to each other through the bonding structure 3. The cross-wafer path is shortened and the interconnect density can be increased, which helps to improve the bandwidth of data interaction between wafers and improve timing margin. In addition, the first input / output unit 21 is concentrated on the second wafer 2, and the memory-to-memory and local interfaces are concentrated on the first wafer 1. This facilitates the layout and process configuration according to requirements, and can be integrated after being manufactured and tested on the two wafers respectively, which helps to improve the yield of finished products and reduce the overall manufacturing cost.

[0062] In other embodiments, the first wafer 1 includes a first arithmetic unit 12; the second wafer 2 includes a first input / output unit 21 and a second storage unit 22; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0063] An external circuit loads the data to be processed, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2. After the first input / output unit 21 performs transmission and reception and interface-related processing on the external signals, it writes at least a portion of the data to be processed into the second storage unit 22 to complete buffering and queue management. It then transmits the data, instruction triggering information, or control information to be used in the calculation to the first arithmetic unit 12 on the first wafer 1 via the bonding structure 3. The first arithmetic unit 12 performs arithmetic processing based on the input data received via the bonding structure 3 and sends the calculation result back to the first input / output unit 21 via the bonding structure 3. The first input / output unit 21 writes the calculation result back to the second storage unit 22 for subsequent reading and scheduling, and / or outputs the calculation result to the outside.

[0064] The second storage unit 22 is located on the second wafer 2 and adjacent to the first input / output unit 21, enabling the interface side to perform data caching, burst absorption, and queue scheduling nearby. This reduces the instantaneous bandwidth pressure on the first computing unit 12 and improves system-level timing and throughput. The first computing unit 12 and the first input / output unit 21 are directly connected via a bonding structure 3, which shortens the cross-wafer interconnect path and reduces parasitic parameters, thus improving the data interaction bandwidth between the two and reducing interconnection losses. At the same time, concentrating the caching function and external interface function on the second wafer 2 allows the first wafer 1 to focus more on computing resource integration, facilitating layout and process configuration according to requirements, and supporting the separate manufacturing and testing of the two wafers before integration. This helps to improve the yield of finished products and reduce overall manufacturing costs.

[0065] In other implementations, see Figure 7 , Figure 8 and Figure 9 The first wafer 1 includes a first arithmetic unit 12 and a first storage unit 11; the second wafer 2 includes a first input / output unit 21 and a second storage unit 22; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0066] The external circuit loads the data to be processed, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2. After the first input / output unit 21 performs transmission and reception of external signals and interface-related processing, it writes at least a portion of the data into the second storage unit 22 to realize interface-side buffering and queue management. At the same time, the first input / output unit 21 transmits the data, instruction information, or control information to be used in the operation to the first wafer 1 via the bonding structure 3. The first arithmetic unit 12 preferentially reads the buffered input data or intermediate data from the first storage unit 11 to perform arithmetic processing, and writes the operation result back to the first storage unit 11 to form a near-end result buffer, and / or transmits the operation result back to the first input / output unit 21 via the bonding structure 3. The first input / output unit 21 outputs the returned result externally or writes it into the second storage unit 22 for subsequent reading, retransmission, or unified scheduling.

[0067] The first storage unit 11 and the first arithmetic unit 12 are co-integrated on the first wafer 1, enabling high-frequency read / write, data multiplexing, and intermediate result write-back during the arithmetic process to be completed within the wafer, thereby reducing the number of cross-wafer round-trip transmissions and lowering access latency and interconnect power consumption. The second storage unit 22 and the first input / output unit 21 are co-integrated on the second wafer 2, enabling data caching, burst absorption, and queue management to be completed locally on the interface side, thereby reducing the instantaneous bandwidth impact on the first wafer 1 and improving system-level throughput and timing margin. Furthermore, the first arithmetic unit 12 and the first input / output unit 21 are directly connected to each other via a bonding structure 3, which shortens the interconnect path and reduces parasitic parameters, thus improving data interaction bandwidth and reducing interconnect losses. At the same time, the functions on the storage and computing side and the interface side are implemented on two separate wafers, which facilitates layout and process configuration according to requirements and supports separate manufacturing and testing of the two wafers before integration, thereby helping to improve the yield of finished products and reduce overall manufacturing costs.

[0068] In other embodiments, the first wafer 1 includes a first arithmetic unit 12 and a second input / output unit 17; the second wafer 2 includes a first input / output unit 21 and a second storage unit 22; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0069] The external circuit loads the data to be processed, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2. After the first input / output unit 21 performs transmission and reception and interface-related processing on the external signals, it writes at least a portion of the data into the second storage unit 22 for interface-side caching, queue management, or data temporary storage. At the same time, the first input / output unit 21 transmits the data, instruction information, or control information to be processed to the first wafer 1 via the bonding structure 3, and can also send configuration parameters or scheduling information to the first wafer 1. The second input / output unit 17 on the first wafer 1 introduces the data from the bonding structure 3 into the first wafer 1 and provides a signal loading and readback path to the first arithmetic unit 12, enabling the first arithmetic unit 12 to perform arithmetic processing on the received data. The calculation result output by the first arithmetic unit 12 is returned to the bonding structure 3 via the second input / output unit 17, and then transmitted to the first input / output unit 21, which outputs the result externally or writes it into the second storage unit 22 for subsequent reading, retransmission, or unified scheduling.

[0070] A second input / output unit 17 is disposed on the first wafer 1 and electrically connected to the first arithmetic unit 12, enabling the signal loading, result readback, and local high-speed data path within the first wafer 1 to be established nearby. This shortens the connection length between the first arithmetic unit 12 and its supporting interface circuit and reduces parasitic parameters, which is beneficial for improving local link bandwidth, reducing latency, and improving timing margin. The second storage unit 22 is co-integrated with the first input / output unit 21 on the second wafer 2, enabling the interface side to complete caching and queue management nearby, reducing the impact on the instantaneous bandwidth of the first wafer 1 and improving system throughput. Furthermore, the first arithmetic unit 12 and the first input / output unit 21 are directly connected to each other through the bonding structure 3, which shortens the interconnection path and reduces the interconnection loss, thereby improving the efficiency of cross-wafer data interaction and reducing overall power consumption. At the same time, the functional units are placed on two wafers, which facilitates layout and process configuration according to requirements and supports separate manufacturing and testing before integration, thereby helping to improve the yield of finished products and reduce the overall manufacturing cost. In other embodiments, the first wafer 1 includes a first arithmetic unit 12, a first storage unit 11, and a second input / output unit 17; the second wafer 2 includes a first input / output unit 21 and a second storage unit 22; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0071] In other embodiments, the first wafer 1 includes a first arithmetic unit 12; the second wafer 2 includes a first input / output unit 21 and a second arithmetic unit 25; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0072] An external circuit loads the data to be processed, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2. The first input / output unit 21 distributes at least a portion of the data and control information to the second arithmetic unit 25, enabling the second arithmetic unit 25 to perform preprocessing, postprocessing, protocol-related operations, or control-related operations on the interface side, and returns the processing results to the first input / output unit 21. Simultaneously, the first input / output unit 21 transmits the data, instruction information, or scheduling information that needs to participate in the core operation to the first wafer 1 via the bonding structure 3, so as to drive the first arithmetic unit 12 on the first wafer 1 to perform arithmetic processing. The operation results output by the first arithmetic unit 12 are returned to the first input / output unit 21 via the bonding structure 3, and output by the first input / output unit 21, or further processed by the second arithmetic unit 25 for result shaping, packaging, verification, or control decision before being output.

[0073] The second arithmetic unit 25 and the first input / output unit 21 are co-integrated on the second wafer 2, enabling the interface side to complete operations, data shaping, and control decisions related to external protocols locally, reducing the burden of such processing on the first wafer 1. This reduces cross-wafer data round trips and scheduling overhead, and helps improve the throughput and response speed of the external interface. The first arithmetic unit 12 and the first input / output unit 21 are directly connected to each other through the bonding structure 3. The interconnection path is relatively shortened and the parasitic parameters are correspondingly reduced, which helps to improve the data interaction bandwidth between the first arithmetic unit 12 and the first input / output unit 21 and improve timing margin, while reducing interconnection losses to improve overall energy efficiency. Furthermore, the first arithmetic unit 12, the first input / output unit 21, and the second arithmetic unit 25 are placed on different wafers, which facilitates layout and process configuration according to requirements, and supports separate manufacturing and testing before integration, thereby helping to improve the yield of finished products and reduce the overall manufacturing cost.

[0074] In other embodiments, the first wafer 1 includes a first arithmetic unit 12 and a first storage unit 11; the second wafer 2 includes a first input / output unit 21 and a second arithmetic unit 25; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0075] Loading process: The external circuit loads the data to be processed, instruction information, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2; the first input / output unit 21 provides at least a portion of the data and control information to the second arithmetic unit 25, which performs preprocessing, postprocessing, protocol-related operations, or control-related operations on the interface side and returns the processing results to the first input / output unit 21; simultaneously, the first input / output unit 21 transmits the data, instructions, and / or scheduling information required for the operation to the first wafer 1 via the bonding structure 3, so that the first arithmetic unit 12 performs a write operation on the first storage unit 11 to cache the input data in the first storage unit 11 and store the intermediate results and instructions to be executed in the first storage unit 11; entering the operation stage, the first arithmetic unit 12 reads the data from the first storage unit 11 to complete the operation processing, and writes the operation results back to the first storage unit 11 and / or returns them to the first input / output unit 21 via the bonding structure 3; the first input / output unit 21 sends the returned results outwards, or hands the returned results over to the second arithmetic unit 25 for further processing before outputting them outwards.

[0076] The first storage unit 11 and the first arithmetic unit 12 are co-integrated on the first wafer 1, allowing the first arithmetic unit 12 to perform data reading, writing, and intermediate result storage locally, reducing the number of cross-wafer accesses, thereby reducing memory access latency and interconnect power consumption and improving throughput. The second arithmetic unit 25 and the first input / output unit 21 are co-integrated on the second wafer 2, allowing the interface side to perform protocol processing, data shaping, and control decisions locally, reducing the burden of interface-related processing to be transferred to the first wafer 1, thereby reducing cross-wafer scheduling and data round-trip overhead and improving external interface response. Furthermore, the first arithmetic unit 12 and the first input / output unit 21 are directly electrically connected through the bonding structure 3, which shortens the interconnect path and reduces parasitic parameters, which helps to improve the data interaction bandwidth and timing margin between the first arithmetic unit 12 and the first input / output unit 21, while reducing interconnect losses to improve overall energy efficiency. In addition, the different functional units are placed on two wafers, which facilitates layout and process configuration according to requirements, and supports separate manufacturing and testing before integration, thereby helping to improve the yield of finished products and reduce the overall manufacturing cost.

[0077] In other embodiments, the first wafer 1 includes a first arithmetic unit 12 and a second input / output unit 17; the second wafer 2 includes a first input / output unit 21 and a second arithmetic unit 25; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0078] An external circuit loads the data to be processed, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2. The first input / output unit 21 provides at least a portion of the data to the second arithmetic unit 25, which performs preprocessing, postprocessing, protocol-related operations, and / or control-related operations on the interface side, and returns the processing results to the first input / output unit 21. Simultaneously, the first input / output unit 21 transmits the data, instructions, and / or scheduling information required for the operation to the first wafer 1 via the bonding structure 3, enabling the first arithmetic unit 12 to perform core arithmetic processing. During this process, the second input / output unit 17 is electrically connected to the first arithmetic unit 12, used to load local high-speed signals to the first arithmetic unit 12, provide an on-chip / near-end data exchange path, and read back the operation results output by the first arithmetic unit 12 to the second input / output unit 17. The second input / output unit 17 then exchanges data with the first input / output unit 21 via the bonding structure 3, so that the operation results are output by the first input / output unit 21 or transferred by the first input / output unit 21 to the second arithmetic unit 25 for further processing before being output.

[0079] The second input / output unit 17 is co-integrated with the first arithmetic unit 12 on the first wafer 1. It can provide a local high-speed signal loading and readback path near the first arithmetic unit 12, shorten the connection length between the first arithmetic unit 12 and its near-end interface circuit, reduce parasitic parameters, and thus help reduce local data exchange latency and improve on-chip / near-end bandwidth. The second arithmetic unit 25 is co-integrated with the first input / output unit 21 on the second wafer 2, so that the interface side can complete protocol processing, data shaping and control decisions nearby, reduce cross-wafer scheduling and data round-trip overhead and improve external interface response. Furthermore, the first arithmetic unit 12 and the first input / output unit 21 are directly electrically connected through the bonding structure 3. The interconnection path is relatively shortened and the parasitic parameters are correspondingly reduced, which helps to improve the data interaction bandwidth between the first arithmetic unit 12 and the first input / output unit 21 and improve timing margin, while reducing interconnection loss to improve overall energy efficiency. In addition, the different functional units are distributed on two wafers, which facilitates layout and process configuration according to requirements, and supports separate manufacturing and testing before integration, thereby helping to improve the yield of finished products and reduce the overall manufacturing cost.

[0080] In other embodiments, the first wafer 1 includes a first arithmetic unit 12, a first storage unit 11, and a second input / output unit 17; the second wafer 2 includes a first input / output unit 21 and a second arithmetic unit 25; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0081] An external circuit loads the data to be processed, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2. The first input / output unit 21 provides at least a portion of the data to the second arithmetic unit 25, which performs preprocessing, post-processing, protocol-related operations, and / or control-related operations on the interface side, and returns the processing results to the first input / output unit 21. Simultaneously, the first input / output unit 21 transmits target data, instructions, and / or scheduling information to the first wafer 1 via the bonding structure 3, enabling the first arithmetic unit 12 to perform core arithmetic processing on the received data and, based on the arithmetic process, to process the data in the first storage unit 1. 1. Write, read, and update operations are performed so that the first storage unit 11 can be used to cache input data, store instructions, and / or save intermediate results; the second input / output unit 17 is electrically connected to the first arithmetic unit 12 and the first storage unit 11, and is used to provide a local high-speed signal loading path to the first arithmetic unit 12, perform near-end access to the first storage unit 11 and / or read back the operation results, and exchange data with the first input / output unit 21 through the bonding structure 3, so that the operation results of the first arithmetic unit 12 are output to the outside by the first input / output unit 21, or are transferred by the first input / output unit 21 to the second arithmetic unit 25 for further processing and then output to the outside.

[0082] The first storage unit 11 and the first arithmetic unit 12 are co-integrated on the first wafer 1, enabling the first arithmetic unit 12 to perform higher-frequency near-end read and write operations on data and instructions within the wafer, reducing cross-wafer data round-trip transmission, thereby helping to reduce access latency and interconnect power consumption and improve throughput; the second input / output unit 17 is co-integrated with the first arithmetic unit 12 and the first storage unit 11, providing a local high-speed signal loading and readback path near the core computing area, shortening the local interconnect length, reducing parasitic parameters, thereby helping to improve near-end bandwidth and timing margin; the second arithmetic unit 25 is co-integrated with the first input / output unit 21. On the second wafer 2, protocol processing, data shaping, and control decisions can be completed locally on the interface side, reducing the resource occupation of the first wafer 1 by the interface side processing and reducing cross-wafer scheduling overhead. Furthermore, the first computing unit 12 and the first input / output unit 21 are directly electrically connected through the bonding structure 3, which shortens the cross-wafer interconnection path and reduces parasitic parameters accordingly, which helps to improve data interaction bandwidth and reduce interconnection losses to improve overall energy efficiency. In addition, different functional units are distributed on two wafers, which facilitates layout and process configuration according to requirements and supports separate manufacturing and testing before integration, thereby helping to improve the yield of finished products and reduce the overall manufacturing cost.

[0083] In other embodiments, the first wafer 1 includes a first arithmetic unit 12; the second wafer 2 includes a first input / output unit 21, a second storage unit 22, and a second arithmetic unit 25; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0084] An external circuit loads the data to be processed, instructions, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2; the first input / output unit 21 writes the target data into the second storage unit 22, so that the second storage unit 22 can be used to buffer input data, save instructions, and / or store intermediate results, and read data from the second storage unit 22 according to scheduling needs and provide it to the second arithmetic unit 25 and the first arithmetic unit 12 respectively; the second arithmetic unit 25 performs interface-side preprocessing on the data from the first input / output unit 21 and / or the second storage unit 22, The system performs post-processing, control-related operations, and / or task scheduling operations, and writes the processing results back to the second storage unit 22 and / or returns them to the first input / output unit 21. Simultaneously, the first input / output unit 21 transmits target data, instructions, and / or scheduling information to the first wafer 1 via the bonding structure 3, enabling the first arithmetic unit 12 to perform core arithmetic processing on the received data, and transmits the arithmetic results back to the first input / output unit 21 via the bonding structure 3, or writes them to the second storage unit 22 for further processing by the second arithmetic unit 25 before outputting them to the outside by the first input / output unit 21.

[0085] The second storage unit 22 is co-integrated with the first input / output unit 21 and the second arithmetic unit 25 on the second wafer 2, enabling data caching, queue management, and control-related operations to be performed locally on the interface side. This reduces the frequency of cross-wafer access and alleviates the storage and scheduling burden on the first wafer 1, thereby improving system scheduling efficiency and interface-side throughput. The first arithmetic unit 12 and the first input / output unit 21 are directly electrically connected through the bonding structure 3, which shortens the cross-wafer interconnect path and reduces parasitic parameters. This helps to increase the data interaction bandwidth between the first arithmetic unit 12 and the first input / output unit 21 and improve timing margin, while reducing interconnect losses to improve overall energy efficiency. Furthermore, concentrating storage and interface-side operations on the second wafer 2 and core operations on the first wafer 1 facilitates layout and process configuration according to requirements. The two wafers can be manufactured and tested separately before integration, which helps to improve product yield and reduce overall manufacturing costs.

[0086] In other embodiments, the first wafer 1 includes a first arithmetic unit 12 and a first storage unit 11; the second wafer 2 includes a first input / output unit 21, a second storage unit 22, and a second arithmetic unit 25; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0087] The external circuit loads the data to be processed, instructions, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2. The first input / output unit 21 writes the target data into the second storage unit 22, so that the second storage unit 22 can be used to cache external input data, store instructions to be executed, and / or save intermediate results. According to scheduling needs, it can read data from the second storage unit 22 and provide it to the second arithmetic unit 25 to perform interface-side preprocessing, postprocessing, control-related operations, and / or task orchestration operations. The first input / output unit 21 simultaneously transmits the target data, instructions, and / or scheduling information to the first wafer 1 via the bonding structure 3, so that the first arithmetic unit 12 performs core arithmetic processing on the received data and writes the operation results into the first storage unit 11 for subsequent iterative operation calls, and / or sends them back to the first input / output unit 21 via the bonding structure 3. The second arithmetic unit 25 can write its processing results back to the second storage unit 22, and the first input / output unit 21 can read them from the second storage unit 22 and output them externally, or, when needed, perform collaborative processing and result exchange with the first arithmetic unit 12 via the bonding structure 3.

[0088] The first storage unit 11 and the first arithmetic unit 12 are co-integrated on the first wafer 1, allowing the reading and writing of core computational data and the storage of intermediate results to be completed locally within the same wafer, reducing cross-wafer round trips, thereby reducing access latency and interconnect power consumption and improving core computational throughput; the second storage unit 22 is co-integrated with the first input / output unit 21 and the second arithmetic unit 25 on the second wafer 2, allowing the interface side to complete external data caching, queue management and control-related operations locally, reducing the burden on the first wafer 1 in terms of interface protocols, buffering and scheduling, which is conducive to improving external bandwidth utilization and system scheduling efficiency; At the same time, the first wafer 1 and the second wafer 2 are directly electrically connected through the bonding structure 3, which shortens the cross-wafer interconnect path between the first computing unit 12 and the first input / output unit 21 and reduces the parasitic parameters accordingly. This is beneficial to improve data interaction bandwidth and timing margin, while reducing interconnection loss to improve overall energy efficiency. Furthermore, the core computing and near-end storage are deployed on the first wafer 1, while the interface and interface-side storage and computing are deployed on the second wafer 2. This facilitates layout and process configuration according to requirements, and the two wafers can be manufactured and tested separately before integration, which helps to improve the yield of finished products and reduce the overall manufacturing cost.

[0089] In other embodiments, the first wafer 1 includes a first arithmetic unit 12 and a second input / output unit 17; the second wafer 2 includes a first input / output unit 21, a second storage unit 22, and a second arithmetic unit 25; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0090] An external circuit loads the data to be processed, instructions, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2. The first input / output unit 21 writes at least a portion of the data into the second storage unit 22, so that the second storage unit 22 can be used to cache external input data, store instructions to be executed, and / or save intermediate results. Data is also read from the second storage unit 22 according to scheduling needs and provided to the second arithmetic unit 25 for interface-side preprocessing, post-processing, control-related operations, and / or task orchestration operations. Simultaneously, the first input / output unit 21 transmits the target data, instructions, and / or control information to the second wafer 2 via the bonding structure 3. The first wafer 1 is connected to the first arithmetic unit 12, and the second input / output unit 17 loads electrical signals to the first arithmetic unit 12 so that the first arithmetic unit 12 performs core arithmetic processing on the received data. The calculation result of the first arithmetic unit 12 is transmitted back to the first input / output unit 21 via the second input / output unit 17 through the bonding structure 3. The first input / output unit 21 can write the calculation result into the second storage unit 22 and output it externally. When needed, the second arithmetic unit 25 can also perform cross-wafer collaborative processing with the first arithmetic unit 12 based on the data in the second storage unit 22, and the first input / output unit 21 realizes external transmission and reception and result output.

[0091] The second input / output unit 17 is integrated into the first wafer 1 and electrically connected to the first arithmetic unit 12. This allows the signal loading and readback of the first arithmetic unit 12 to have a local path close to the arithmetic array, which can shorten the length of critical interconnects within the first wafer 1, reduce parasitic resistance and capacitance, thereby improving the bandwidth of local high-speed signals and reducing latency, and enhancing the testability and debugging convenience of the first arithmetic unit 12. The second storage unit 22 and the second arithmetic unit 25 are both integrated into the second wafer 2, allowing the interface side to perform external data caching, queue management, and control / preprocessing operations nearby, reducing the burden on the first wafer 1 in interface protocol processing and caching management. This reduces the burden on the management aspect, thereby improving the utilization rate of external bandwidth and the efficiency of system scheduling. At the same time, the first wafer 1 and the second wafer 2 are directly electrically connected through the bonding structure 3, which shortens the cross-wafer interconnection path between the first input / output unit 21 and the first arithmetic unit 12 and reduces parasitic parameters accordingly. This helps to improve data interaction bandwidth and timing margin, while reducing interconnection loss to improve overall energy efficiency. Furthermore, the distribution of each functional unit on the two wafers can be adjusted as needed, which facilitates layout and process configuration according to requirements. The two wafers can be manufactured and tested separately before integration, which helps to improve the yield of finished products and reduce the overall manufacturing cost.

[0092] In other embodiments, the first wafer 1 includes a first arithmetic unit 12, a first storage unit 11, and a second input / output unit 17; the second wafer 2 includes a first input / output unit 21, a second storage unit 22, and a second arithmetic unit 25; the first wafer 1 and the second wafer 2 are electrically connected by a bonding structure 3.

[0093] An external circuit loads the data to be processed, instructions, control signals, and clock signals onto the first input / output unit 21 on the second wafer 2. The first input / output unit 21 selectively writes at least a portion of the data into the second storage unit 22 for external data caching, instruction temporary storage, and / or intermediate result temporary storage. Based on task scheduling, it transmits the target data to the first wafer 1 via the bonding structure 3. The second input / output unit 17 on the first wafer 1 receives electrical signals from the bonding structure 3 and loads them into the first arithmetic unit 12. The first arithmetic unit 12 can read data from the first storage unit 11 or write input data into the first storage unit 11 to form a near-end cache, and then executes the core on the data. The calculation is processed, and the calculation result is written back to the first storage unit 11 and / or transmitted back to the first input / output unit 21 via the bonding structure 3 through the second input / output unit 17. The first input / output unit 21 can write the transmitted result into the second storage unit 22 and output it externally. At the same time, the second calculation unit 25 on the second wafer 2 can perform interface-side preprocessing, postprocessing, control-related calculations and / or task scheduling calculations based on the data in the second storage unit 22, and send the generated control information, scheduling information and / or preprocessed data to the second input / output unit 17 via the bonding structure 3 through the first input / output unit 21 to form a cross-wafer collaborative processing flow with the first calculation unit 12.

[0094] The first storage unit 11 and the first arithmetic unit 12 are co-integrated on the first wafer 1, allowing read and write operations between the first storage unit 11 and the first arithmetic unit 12 to be completed within the same wafer. This reduces the frequency of cross-wafer access, shortens critical data paths, and reduces interconnect power consumption, which helps to reduce access latency and improve throughput. The second input / output unit 17 is co-integrated with the first arithmetic unit 12 and the first storage unit 11, and can serve as a local high-speed signal loading and readback path close to the core unit. This further shortens the interconnect length within the first wafer 1 and reduces parasitic parameters, which helps to improve local interface bandwidth, timing margin, and testability. The second storage unit 22 and the second arithmetic unit 25 are arranged on the second wafer 2, making the interface side... It can perform external data caching, queue management, and preprocessing / postprocessing / control operations locally, reducing the burden on the first wafer 1 in terms of protocol processing and cache management, which is conducive to improving external bandwidth utilization and system scheduling efficiency. Furthermore, the first wafer 1 and the second wafer 2 are directly electrically connected through the bonding structure 3, which shortens the cross-wafer interconnection path between the first input / output unit 21 and the second input / output unit 17 and the first arithmetic unit 12, and reduces parasitic effects accordingly. This is conducive to improving the data interaction bandwidth between wafers and reducing interconnection losses to improve overall energy efficiency. At the same time, it is convenient to configure the layout and process according to the requirements, and the two wafers can be manufactured and tested separately before integration, which helps to improve the yield of finished products and reduce the overall manufacturing cost.

[0095] It is understood that in the above embodiments, the first wafer 1 necessarily includes a first arithmetic unit 12 to provide core computing capabilities. Based on this, whether the first wafer 1 further includes a first storage unit 11 and / or a second input / output unit 17 can be selected and adjusted according to the bandwidth, latency, power consumption and interface requirements of the target application. The first storage unit 11 is used to provide data caching and near-end read / write support for the first arithmetic unit 12, and the second input / output unit 17 is used to provide local high-speed signal loading and readback paths for the first arithmetic unit 12. The above selection does not constitute a limitation on the integrated content of the first wafer 1.

[0096] Accordingly, the second wafer 2 necessarily includes a first input / output unit 21 to provide external signal transmission and reception and interface functions. On this basis, whether the second wafer 2 further includes a second storage unit 22 and / or a second arithmetic unit 25 can also be selected and adjusted according to the system architecture and functional allocation. The second storage unit 22 is used to provide interface-side buffering and queue management capabilities, and the second arithmetic unit 25 is used to undertake interface-side preprocessing, post-processing or control-related operations. The above selection does not constitute a limitation on the integrated content of the second wafer 2. The first wafer 1 and the second wafer 2 are electrically connected through the bonding structure 3, thereby establishing a signal interaction path between the first arithmetic unit 12 and the first input / output unit 21, and supporting the flexible distribution and combination of different functional units between the two wafers.

[0097] In some embodiments of this disclosure, see Figure 10 The first wafer 1 includes a first semiconductor structure 13, a first metal structure 14, and a second metal structure 15. The first semiconductor structure 13 has a first side and a second side disposed opposite to each other. The first metal structure 14 is disposed on the first side of the first semiconductor structure 13 to form a plurality of first transistors arranged in rows and columns on the first side. The second metal structure 15 is disposed on the second side of the first semiconductor structure 13 to form a plurality of second transistors arranged in rows and columns on the second side. The plurality of first transistors and the plurality of second transistors together constitute at least a portion of the first operational unit 12 on the first wafer 1.

[0098] Furthermore, a first conductive structure (not shown in the accompanying drawings) is formed on the first metal structure 14, and a second conductive structure (not shown in the accompanying drawings) is formed on the second metal structure 15. The first conductive structure and the second conductive structure are aligned and electrically connected to establish an electrical connection path between the first metal structure 14 and the second metal structure 15. Thus, the first metal structure 14 and the second metal structure 15 can achieve conductive interconnection on both sides of the fin 16, enabling the first transistor formed on the first side and the second transistor formed on the second side to achieve coordinated wiring and signal or power path connection at the electrical connection level. This provides higher density interconnect resources for the cross-side interconnection, signal aggregation and distribution within the first computing unit 12, and helps to shorten local interconnection paths, reduce interconnection parasitic effects, and improve layout wiring flexibility and area utilization.

[0099] Furthermore, the first semiconductor structure 13 has at least one fin 16; the fin 16 includes a channel region and a source / drain region corresponding to the channel region; the first metal structure 14 is electrically connected to the gate structure corresponding to the channel region and the source / drain region to form a plurality of first transistors; the second metal structure is electrically connected to the gate structure corresponding to the channel region and the source / drain region to form a plurality of second transistors.

[0100] Understandably, in this embodiment, the first transistor and the second transistor share the same fin (i.e., the channel region provided by the shared fin and its corresponding source-drain region), which can realize the construction of dual-sided transistors without adding additional independent fins, thereby improving device integration and reducing layout area. At the same time, since the dual-sided devices use the same fin as a common semiconductor body and geometric reference, the structural dispersion caused by the forming and alignment of the front and back sides can be reduced, improving device parameter matching and consistency of computing units. In addition, the shared fin can also reduce the repetitive active boundaries and isolation boundaries, reduce related parasitic capacitance, and shorten the equivalent interconnect path and reduce interconnect overhead in dual-sided electrical connection scenarios, thereby helping to improve speed, reduce power consumption, and simplify the process to a certain extent, improve process stability and yield.

[0101] In this embodiment, the first conductive structure on the first metal structure 14 and the second conductive structure on the second metal structure 15 are aligned and electrically connected to each other, thereby forming a conductive interconnection path between the first metal structure 14 and the second metal structure 15 for crossing both sides of the fin 16. This conductive interconnection path corresponds to the via structure and is used to realize the through-hole of the double-sided metal interconnection. Thus, the first transistor located on the first side and the second transistor located on the second side can realize the cross-side connection and cooperative wiring of the power path and / or signal path through the conductive interconnection path, so that the cross-side interconnection, signal convergence and distribution inside the first computing unit 12 can be completed on a smaller interconnection scale. This achieves higher interconnection density and larger available wiring resources without additional vertical interconnection structures such as silicon vias, and is beneficial for shortening local interconnection paths, reducing interconnection parasitic parameters and interconnection losses, improving timing margins and improving layout wiring flexibility and area utilization, thereby improving the integration and overall performance efficiency of the first computing unit 12.

[0102] It should be noted that, in some embodiments, in addition to achieving electrical connection between the first metal structure 14 and the second metal structure 15 through the conductive interconnection path formed by the first conductive structure and the second conductive structure, additional through-silicon vias (TSVs) can be formed on the first wafer 1 and / or the second wafer 2 to establish electrical connection paths, for example, to achieve longer-distance cross-layer lead-out, outward fan-out, or electrical connection with other metal interconnect layers; at the same time, the location, number, and connection relationship between the TSVs and the bonding structure 3 and the metal interconnect layers can be adjusted according to power distribution, signal integrity, and layout routing requirements, and this application does not impose any limitations on this. In some embodiments of this disclosure, the first semiconductor structure 13 may include a semiconductor substrate and a first semiconductor layer formed on the semiconductor substrate. The semiconductor substrate may be a single-crystal silicon substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, or other semiconductor substrates suitable for the fabrication of logic operation units and memory units. The first semiconductor layer can be an epitaxial layer made of the same material as the substrate, or it can be an epitaxial layer made of a different material than the substrate, such as a silicon-germanium epitaxial layer or a strained silicon epitaxial layer, so as to optimize the channel carrier mobility according to the performance requirements of the first memory cell 11 and the first arithmetic cell 12. Preferably, the active region in the first semiconductor structure 13 is made of a single-crystal semiconductor material to ensure the consistency of the device threshold voltage and mobility.

[0103] In some specific embodiments, a first transistor can be fabricated on the first side of the first semiconductor structure 13. Specifically, a photoresist pattern can be formed on the first semiconductor layer, defining several strip-shaped regions in a first direction. Using the photoresist pattern as a mask, anisotropic etching is performed on the first semiconductor layer to etch away the areas not covered by the photoresist, thereby forming multiple fins extending along the first direction in the first semiconductor layer. Afterward, the photoresist is removed, dielectric material is filled between the fins and chemical mechanical polishing is performed to form a shallow trench isolation structure between the fins, so that the fins are electrically isolated from each other in the lateral direction. Subsequently, a gate dielectric layer and a gate conductive layer can be deposited sequentially on the first side of the fins, and a gate structure is formed by patterning, and a sidewall gap layer is formed. Then, the source and drain regions of the fin 16 are ion implanted and activated annealed to open on the first side and form contact holes connected to the active region and the gate structure. Finally, a first metal structure 14 is stacked on the first side, so that multiple first transistors are arranged in rows and columns on the first side, constituting at least a part of the first memory cell 11 and the first arithmetic cell 12.

[0104] After completing the first-side transistor and the first metal structure 14, a process window can be reserved for fabricating the second transistor on the other side of the fin 16 through back-side processes such as thinning. Specifically, the first wafer 1 can be bonded to the carrier substrate or another wafer through a dielectric bonding layer or a metal bonding layer. Then, the original substrate is thinned and polished from the back side to remove excess substrate material to a position close to the fin 16 and the shallow trench isolation structure, so that the second-side region of the fin 16 can be exposed and accessed by subsequent processes. On this basis, a gate dielectric layer and a gate conductive layer are sequentially formed on the second-side region of the fin 16 to complete the fabrication of the second-side gate patterning and sidewall structure. Then, source / drain implantation and annealing are performed on the second side of the fin 16 to open and form a second-side contact hole that is electrically connected to the active region and gate structure in the fin 16. Finally, a second metal structure 15 is stacked on the second side to form a second-side transistor arranged in rows and columns on the second side. By leading out gate and source / drain contacts from the first and second sides of the fin 16 respectively and connecting them to the metal structures on their respective sides, the same fin 16 can operate on two opposite sides. Multiple first transistors and multiple second transistors together constitute at least a part of the first memory cell 11 and the first arithmetic cell 12 on the first wafer 1. In a specific implementation, complementary devices can be flipped on the same fin 16 by preferentially forming one type of polarized transistor on the first side and another type of polarized transistor on the second side.

[0105] As examples, the fin 16 is not necessarily shared between the first and second sides. Specifically, at least one first side fin 16 is fabricated on the first side, and at least one second side fin 16 is fabricated on the second side at a position corresponding to the first side fin 16, such that the second side fin 16 corresponds to or overlaps with the first side fin 16 in a planar position; second side transistors are formed on the second side fins 16 and stacked to form a second metal structure 15, so that the second side transistors are arranged in rows and columns on the second side. In this example, a first conductive structure is formed on the first metal structure 14, and a second conductive structure is formed on the second metal structure 15. The first conductive structure and the second conductive structure are aligned with each other and electrically connected to establish an interconnection path between the first metal structure 14 and the second metal structure 15, thereby realizing signal transmission and / or power coupling between the first-side circuit and the second-side circuit, improving the wiring flexibility and integration adaptability of the dual-side devices.

[0106] In some embodiments of this disclosure, the first transistor is an N-type transistor and the second transistor is a P-type transistor.

[0107] In other embodiments of this disclosure, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0108] In some embodiments, the first transistor is uniformly set as an N-type transistor and the second transistor is uniformly set as a P-type transistor, or in other embodiments, the first transistor is uniformly set as a P-type transistor and the second transistor is uniformly set as an N-type transistor. This ensures that the transistors formed on the same side fin 16 have the same polarity. Devices on the same side can use consistent process formulations and layout rules in terms of channel doping, threshold voltage setting, source / drain injection conditions, and annealing processes. This avoids increasing process steps and mask complexity by mixing transistors of different polarities on the same side, which helps to simplify the process flow, reduce process difficulty, and improve device consistency and fabrication yield.

[0109] In some embodiments of this disclosure, see Figure 11 The second wafer 2 includes a second semiconductor structure 23 and a third metal structure 24; the third metal structure 24 is disposed on one side of the second semiconductor structure 23 to form a row and column arrangement of third transistors on one side of the second semiconductor structure 23; wherein, a plurality of third transistors constitute at least a portion of the first input / output unit 21.

[0110] Specifically, the second semiconductor structure 23 may include a semiconductor substrate and a second semiconductor layer formed on the semiconductor substrate. The semiconductor substrate may be a single-crystal silicon substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, or other semiconductor substrates suitable for fabricating the first input / output unit 21. The second semiconductor layer may be an epitaxial layer of the same material as the substrate, or it may be an epitaxial layer of a different material, such as a silicon-germanium epitaxial layer or a high-resistivity silicon epitaxial layer, to optimize the electrical characteristics of the active region according to the requirements of the first input / output unit 21 for breakdown voltage, current carrying capacity, and noise characteristics. In some preferred embodiments, the active region in the second semiconductor structure 23 is made of a single-crystal semiconductor material to ensure the consistency of the threshold voltage and long-term reliability of the third transistor.

[0111] In terms of specific processes, planar metal-oxide-semiconductor (MOS) technology or fin field-effect transistor (FET) technology can be used to fabricate the third transistor on one side of the second semiconductor structure 23. For example, firstly, a well region and an isolation structure are formed in the second semiconductor layer, a gate dielectric layer is grown or deposited above a predetermined active region, and a polysilicon layer or metal gate material is deposited on the gate dielectric layer. The gate structure is formed by photolithography and etching, and sidewall gap layers are formed on both sides of the gate. Subsequently, ion implantation and annealing are performed on the source and drain regions to form the required doping profile and junction depth. Then, contact holes are formed, and a third metal structure 24 is stacked on this side, so that multiple third transistors are arranged in rows and columns on one side of the second semiconductor structure 23. The multiple third transistors are electrically connected to the gate, power node, and signal node through the third metal structure 24, thereby constituting at least a part of the first input / output unit 21.

[0112] In some implementations, to meet the requirements of high-voltage drive or electrostatic protection, the third transistor can be specially designed in terms of gate dielectric thickness, drift region length and source-drain electrode structure to form a high-voltage third transistor suitable for the first input-output unit 21.

[0113] Regarding the type of the third transistor, multiple third transistors can be N-type metal-oxide-semiconductor transistors used to implement a drive stage or pull-down stage using only N-type devices; or they can be P-type metal-oxide-semiconductor transistors used to implement a pull-up stage using only P-type devices.

[0114] In a further embodiment, N-type and P-type third transistors are simultaneously arranged on one side of the second semiconductor structure 23, so that multiple third transistors form a complementary structure for the first input / output unit 21 to meet functional requirements such as differential signal interface, power level conversion, and electrostatic discharge protection. By integrating multiple third transistors on the second wafer 2 and flexibly selecting the type and structure of the third transistors according to the voltage, current, and reliability requirements of the first input / output unit 21, the area utilization and process implementation difficulty of the first input / output unit 21 can be optimized without affecting the layout of the high-density first memory unit 11 and the first arithmetic unit 12 on the first wafer 1.

[0115] In this disclosure, a chip is also provided, which includes at least one semiconductor device. In application, this chip can be used as a functional chip in an integrated circuit product, such as a logic chip, memory chip, signal processing chip, or power management chip. It can be packaged and soldered onto a printed circuit board, working with other electronic components on the board to form a target electronic device. The electronic device can be a mobile terminal, wearable device, server, industrial control device, or various smart terminals, etc. The chip provides corresponding signal processing and control functions during operation. By integrating the semiconductor device from Embodiment 1 or Embodiment 2 into the chip, on the one hand, the electrical performance and operational stability of the device can be maintained or improved without significantly increasing the chip area and process complexity, which is beneficial for reducing the overall power consumption of the chip and improving operational reliability; on the other hand, it can reduce the dispersion of device parameters and improve the consistency between devices, enabling the chip to maintain good performance even under high-frequency operation, long-term continuous operation, and complex working environments, thereby improving the overall performance and lifespan of the electronic device equipped with the chip.

[0116] This application also provides an electronic device including the aforementioned chip. In terms of application scenarios, the electronic device can be a mobile phone, tablet computer, laptop computer, desktop computer, server, network communication equipment, wearable device, industrial control device, IoT terminal, smart home appliance, or vehicle electronic control unit, etc. The chip is packaged and soldered onto the printed circuit board of the electronic device, and works in conjunction with power modules, storage modules, sensor modules, communication modules, and other functional circuits to perform functions such as data processing, signal acquisition and conversion, arithmetic control, power management, or protocol processing, to meet the application requirements of different electronic devices in terms of performance, size, and power consumption.

[0117] After integrating the aforementioned chip, this electronic device leverages improvements in the electrical performance, stability, and consistency of the semiconductor devices contained within the chip. This allows for enhanced reliability and response speed during high-frequency operation, prolonged continuous work, and complex environments, while maintaining a compact structure and controllable power consumption. It also reduces failure rates and performance fluctuations. Furthermore, it facilitates increased functional integration and optimized overall energy efficiency, thereby improving the overall performance and lifespan of the electronic device.

[0118] This application also provides a method for fabricating a semiconductor device, used to fabricate the semiconductor devices in Examples 1 and 2. See also Figure 12 , Figure 13 and Figure 14 The preparation method includes: S1: Provide the first wafer 1.

[0119] Specifically, in S1, providing the first wafer 1 specifically includes: S11: Provide a first semiconductor structure 13, the first semiconductor structure 13 having a first side and a second side disposed opposite to each other.

[0120] S12: At least one fin 16 is formed on the first semiconductor structure 13, the fin 16 having a channel region and a source / drain region corresponding to the channel region.

[0121] S13: A first metal structure 14 is prepared on the first side of the first semiconductor structure 13. The first metal structure 14 is electrically connected to the gate structure corresponding to the channel region and the source / drain region to form a plurality of first transistors arranged in rows and columns on the first side.

[0122] S14: A second metal structure 15 is prepared on the second side of the first semiconductor structure 13. The second metal structure 15 is electrically connected to the gate structure corresponding to the channel region and the source and drain regions to form a plurality of second transistors arranged in rows and columns on the second side. The plurality of first transistors and the plurality of second transistors together constitute at least a part of the first operational unit 12.

[0123] In some embodiments, multiple first transistors and multiple second transistors may also jointly constitute at least a portion of the first memory unit 11 and the second input / output unit 17.

[0124] S2: Provide a second wafer 2.

[0125] Specifically, in S2, providing the second wafer 2 specifically includes: S21: Provides a second semiconductor structure 23; S22: A third metal structure 24 is prepared on one side of the second semiconductor structure 23 to form a row and column arrangement of third transistors on one side of the second semiconductor structure 23; a plurality of third transistors constitute at least a portion of the first input / output unit 21.

[0126] In this way, the plurality of the third transistors can also collectively constitute at least a part of the second arithmetic unit 25 and the second storage unit 22.

[0127] S3: Align and bond the first wafer 1 and the second wafer 2.

[0128] Specifically, the process of aligning and bonding the first wafer 1 and the second wafer 2 can include: planarizing and cleaning the bonding surfaces of the first wafer 1 and the second wafer 2 to form alignment marks and perform surface activation; subsequently, using an alignment device based on the alignment marks, the first wafer 1 and the second wafer 2 are aligned and their angles are corrected in the plane, and pre-bonding is performed under controlled pressure and temperature conditions to fix their relative positions; then, annealing and curing are used to form a stable bonding interface and establish an electrical connection path. Alternatively, in a 3D bonding method, the first wafer 1 and the second wafer 2 are directly aligned and bonded along the stacking direction. The bonding interface can be a metal-to-metal interface, a dielectric-to-dielectric interface, or a hybrid interface to achieve high-density interconnection between vertically stacked wafers. Secondly, in the 2.5D bonding method, the first wafer 1 and the second wafer 2 are aligned and bonded to the interposer structure, respectively. The interposer structure is used to provide lateral wiring and fan-out paths, so that the first wafer 1 and the second wafer 2 can be electrically connected through the interposer structure. The interposer structure can be a silicon interposer, a redistribution layer structure, or a packaging substrate, etc. The bonding connection can be completed by microbump interconnect, thermo-press bonding, hybrid bonding, or other chip-level interconnect methods.

[0129] The bonding method is not limited to the 2.5D bonding method and 3D bonding method mentioned above. The first wafer 1 and the second wafer 2 can also adopt integration paths such as wafer-to-wafer bonding, chip-to-wafer bonding, and chip-to-chip bonding. Electrical and mechanical connections can be achieved by processes such as metal bonding, dielectric bonding, hybrid bonding, thermo-press bonding, eutectic bonding, solder bonding, and adhesive bonding. The specific bonding path, bonding material, and process parameters can be selected and adjusted according to the interconnect density, reliability, and manufacturing conditions. This application does not limit these aspects.

[0130] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0131] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this specification are indicated by the following claims.

[0132] It should be understood that this specification is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is limited only by the appended claims.

[0133] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A semiconductor device, characterized in that: The semiconductor device includes: The first wafer has a first computing unit on it; The second wafer has a first input / output unit on it; A bonding structure is disposed between the first wafer and the second wafer and is configured to electrically connect the first wafer and the second wafer.

2. The semiconductor device according to claim 1, characterized in that: The first wafer includes: A first semiconductor structure has a first side and a second side disposed opposite to each other; A first metal structure is electrically connected to a first side of the first semiconductor structure to form a plurality of first transistors, and the first metal structure has a first conductive electronic structure. A first metal structure is electrically connected to a second side of the first semiconductor structure to form a plurality of second transistors, and the second metal structure has a first conductive transistor structure. The first conductive structure is electrically connected to the second conductive structure, and the plurality of first transistors and the plurality of second transistors together constitute at least a part of the first computing unit.

3. The semiconductor device according to claim 1, characterized in that: The first semiconductor structure has at least one fin, the fin including a channel region and a source / drain region corresponding to the channel region; The first metal structure is electrically connected to the gate structure corresponding to the channel region and the source / drain region to form the plurality of first transistors; The second metal structure is electrically connected to the gate structure corresponding to the channel region and the source / drain region to form the plurality of second transistors.

4. The semiconductor device according to claim 2 or 3, characterized in that: The first transistor is an N-type transistor, and the second transistor is a P-type transistor; Alternatively, the first transistor may be a P-type transistor and the second transistor may be an N-type transistor.

5. The semiconductor device according to claim 1, characterized in that: The second wafer includes: Second semiconductor structure; A third metal structure is disposed on one side of the second semiconductor structure to form a row and column arrangement of third transistors on one side of the second semiconductor structure; The plurality of the third transistors constitute at least a portion of the first input / output unit.

6. The semiconductor device according to claim 5, characterized in that: The plurality of third transistors are at least one type of N-type transistor and P-type transistor.

7. The semiconductor device according to claim 1, characterized in that: A second input / output unit is also formed on the first wafer; The second input / output unit is electrically connected to the first arithmetic unit, and the second input / output unit is electrically connected to the first input / output unit through the bonding structure.

8. The semiconductor device according to claim 1 or 7, characterized in that: A first memory cell is also formed on the first wafer; The first storage unit is electrically connected to the first arithmetic unit, and the first storage unit is electrically connected to the first input / output unit through the bonding structure.

9. The semiconductor device according to claim 1, characterized in that: A second memory cell is also formed on the second wafer; The second storage unit is electrically connected to the first input / output unit, and the second storage unit is electrically connected to the first arithmetic unit through the bonding structure.

10. The semiconductor device according to claim 1 or 9, characterized in that: A second computing unit is also formed on the second wafer; The second arithmetic unit is electrically connected to the first input / output unit, and the second arithmetic unit is electrically connected to the first arithmetic unit through the bonding structure.

11. A chip, characterized in that: It includes at least one semiconductor device as described in any one of claims 1 to 10.

12. An electronic device, characterized in that: Including the chip as described in claim 11.

13. A method for fabricating a semiconductor device, applied to the semiconductor device according to any one of claims 1 to 10, characterized in that: The preparation method includes: Provide the first wafer; Provide a second wafer; The first wafer and the second wafer are aligned and bonded.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that: The first wafer provided includes: A first semiconductor structure is provided, the first semiconductor structure having a first side and a second side disposed opposite to each other; At least one fin is formed on a first semiconductor structure, the fin having a channel region and a source / drain region corresponding to the channel region; A first metal structure is fabricated on a first side of the first semiconductor structure. The first metal structure is electrically connected to the gate structure corresponding to the channel region and the source / drain region to form a plurality of first transistors arranged in rows and columns on the first side. A second metal structure is fabricated on the second side of the first semiconductor structure. The second metal structure is electrically connected to the gate structure corresponding to the channel region and the source / drain region to form a plurality of second transistors arranged in rows and columns on the second side. The plurality of first transistors and the plurality of second transistors together constitute at least a part of the first computing unit.

15. The method for fabricating a semiconductor device according to claim 13, characterized in that: Providing a second wafer includes: Provide a second semiconductor structure; A third metal structure is fabricated on one side of the second semiconductor structure to form a row-and-column arrangement of third transistors on one side of the second semiconductor structure; a plurality of the third transistors constitute at least a portion of the first input / output unit.

16. The method for fabricating a semiconductor device according to claim 14, characterized in that: Providing the first wafer also includes: The plurality of first transistors and the plurality of second transistors together constitute at least a portion of the first memory cell and / or the second input / output cell.

17. The method for fabricating a semiconductor device according to claim 15, characterized in that: Providing a second wafer also includes: The plurality of the third transistors together constitute at least a portion of the second arithmetic unit and / or the second memory unit.

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