Preparation method of semiconductor device
By inducing plasmons in the MIM cavity structure and using a parallel beam of incoherent superposition of TM and TE modes to achieve self-aligned exposure, the problem of insufficient imaging contrast in three-dimensional structures in traditional photolithography methods is solved. This achieves nanoscale exposure far below the diffraction limit, reduces fabrication complexity, and is suitable for the fabrication of deep sub-meter wavelength three-dimensional structures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2026-02-28
- Publication Date
- 2026-05-19
AI Technical Summary
Traditional optical lithography methods are limited by the diffraction limit, making it difficult to achieve nanoscale pattern imaging in three-dimensional structures. In particular, the imaging contrast and morphological consistency are insufficient in high-depth structures such as three-dimensional through holes, which has become a bottleneck restricting the manufacturing accuracy of three-dimensional structures.
Parallel beams in TM and TE modes are incoherently superimposed and incident on the MIM cavity structure at a preset angle to induce plasmon resonance, thereby achieving self-aligned exposure of the intermediate photoresist layer and forming a dot matrix exposure pattern. This eliminates the need for nanoscale masks and combines conformal deposition of dielectric and metal layers to form a three-dimensional structure array.
It breaks through the physical limits of photolithography, achieving nanoscale exposure far below the diffraction limit, reducing fabrication complexity, eliminating overlay alignment errors, and possessing stable exposure quality with high contrast and high NILS, making it suitable for the fabrication of deep sub-meter wavelength three-dimensional structures.
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Figure CN122063818A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device fabrication technology, and more specifically, to a method for fabricating a semiconductor device. Background Technology
[0002] With the rapid development of semiconductor devices such as 3D integrated circuits, advanced memories, and nanoscale photonic devices, manufacturing processes have placed significantly higher demands on lithography resolution and 3D structure processing capabilities. Traditional optical lithography, limited by the diffraction limit, typically relies on the Rayleigh criterion for its imaging capabilities; that is, under projection exposure conditions, the minimum pattern size is difficult to be less than about one-quarter of the exposure wavelength. For commonly used visible or ultraviolet light sources, conventional lithography methods struggle to achieve nanoscale patterns in the deep subwavelength range, especially failing to maintain sufficient imaging contrast and morphological consistency in high-depth structures such as 3D vias. This has become a significant bottleneck restricting the precision of 3D structure manufacturing. Summary of the Invention
[0003] In view of this, this application provides a method for fabricating semiconductor devices, effectively solving the technical problems existing in the prior art. It allows for self-aligned exposure of the portion of the intermediate photoresist layer corresponding to the substrate protrusions to form a dot matrix exposure pattern without the need for a nanoscale mask, reducing the complexity of the fabrication method and eliminating the overlay alignment error problem in existing photolithography processes. Furthermore, the technical solution provided in this application achieves nanoscale exposure of the intermediate photoresist layer far below the diffraction limit, breaking through the physical limits of existing photolithography processes and providing a foundation for the fabrication of deep sub-meter wavelength three-dimensional structures. It also possesses stable exposure quality with high contrast and high NILS (Normalized Image Log Slope).
[0004] To achieve the above objectives, the technical solution provided in this application is as follows:
[0005] A method for fabricating a semiconductor device, comprising:
[0006] S1. Prepare a substrate, the substrate including a substrate body and at least one substrate boss located on one side of the substrate body;
[0007] S2. A MIM cavity structure is formed by sequentially stacking a first metal layer, an intermediate photoresist layer, and a second metal layer on one side surface of the substrate having the substrate protrusion, wherein the first metal layer is conformal to the surface of the substrate.
[0008] S3. A parallel beam of non-coherent superposition of TM mode and TE mode is incident from the surface of the MIM cavity structure away from the substrate at a preset angle to induce plasmons in the MIM cavity structure and expose the part of the intermediate photoresist layer corresponding to the substrate protrusion to form a dot matrix exposure pattern.
[0009] S4. Remove the second metal layer;
[0010] S5. The intermediate photoresist layer is developed to form an array structure with a pattern corresponding to the dot matrix exposure pattern.
[0011] S6. The substrate is etched based on the array structure to form a three-dimensional structure array in the substrate, while the array structure and the first metal layer are removed.
[0012] Optionally, step S1 includes:
[0013] S11, Provide a substrate to be processed;
[0014] S12. A photoresist layer is formed on one side surface of the substrate to be processed;
[0015] S13. Expose the upper photoresist layer based on the initial mask, and develop the upper photoresist layer.
[0016] S14. The substrate to be processed is etched based on the upper photoresist layer to obtain the desired substrate, and the upper photoresist layer is removed, wherein the substrate includes a substrate body and at least one substrate protrusion located on one side of the substrate body.
[0017] Optionally, after step S11 and before step S12, the preparation method further includes:
[0018] S11', An anti-reflective layer is formed on one side surface of the substrate to be processed;
[0019] Step S12 includes: forming an upper photoresist layer on the side of the anti-reflection layer away from the substrate to be processed; and step S14 includes: etching the substrate to be processed based on the upper photoresist layer to obtain the desired substrate, and removing the upper photoresist layer and the anti-reflection layer, wherein at least one substrate protrusion is formed on one side of the substrate.
[0020] Optionally, step S5 includes:
[0021] The intermediate photoresist layer is developed to form an array structure with a pattern corresponding to the dot matrix exposure pattern. The array structure includes an array of cutout holes corresponding to the dot matrix exposure pattern.
[0022] Step S6 includes: etching the substrate based on the array structure to form a three-dimensional through-hole array in the substrate, while removing the array structure and the first metal layer.
[0023] Optionally, step S6 includes: etching the substrate protrusions based on the array structure to form a three-dimensional via array in the substrate protrusions, while removing the array structure and the first metal layer;
[0024] Alternatively, step S6 includes: etching the substrate protrusion based on the array structure and extending the etching to a first preset depth in the substrate body to form a three-dimensional through-hole array in the substrate protrusion and the substrate body, while removing the array structure and the first metal layer.
[0025] Optionally, when etching the substrate protrusions based on the array structure and extending the etching to a first preset depth in the substrate body, after step S6, the fabrication method further includes:
[0026] S7. Remove the substrate protrusion.
[0027] Optionally, step S5 includes:
[0028] The intermediate photoresist layer is developed to form an array structure with a pattern corresponding to the dot matrix exposure pattern. The array structure includes a solid column array corresponding to the dot matrix exposure pattern.
[0029] Step S6 includes: etching the substrate based on the array structure to form a three-dimensional columnar array in the substrate, while removing the array structure and the first metal layer.
[0030] Optionally, step S6 includes: etching the substrate protrusions based on the array structure to form a three-dimensional columnar array in the substrate protrusions, while removing the array structure and the first metal layer;
[0031] Alternatively, step S6 includes: etching the substrate protrusions based on the array structure and extending the etching to a second preset depth in the substrate body to form a three-dimensional columnar array in the substrate protrusions and the substrate body, while removing the array structure and the first metal layer.
[0032] Optionally, when etching the substrate protrusions based on the array structure and extending the etching to a second preset depth in the substrate body, after step S6, the fabrication method further includes:
[0033] S7. Remove the substrate protrusion.
[0034] Optionally, after step S1 and before step S2, the preparation method further includes:
[0035] S1' A dielectric layer is formed on the surface of the substrate having the substrate protrusion, the dielectric layer being conformal to the surface of the substrate;
[0036] Step S2 includes: forming a MIM cavity structure by sequentially stacking a first metal layer, an intermediate photoresist layer, and a second metal layer on the side of the dielectric layer away from the substrate, wherein the first metal layer is conformal to the surface of the substrate;
[0037] Step S6 includes: etching the substrate based on the array structure to form a three-dimensional structure array in the substrate, while removing the array structure, the first metal layer and the dielectric layer.
[0038] Compared with existing technologies, the technical solution provided in this application has at least the following advantages:
[0039] This application provides a method for fabricating a semiconductor device. By controlling a parallel beam of incoherent superposition of TM and TE modes and incident it at a preset angle from the surface of a MIM cavity structure away from the substrate, plasmons can be induced in the MIM cavity structure. Due to the special structure where the substrate protrusion is higher than the rest of the substrate body, the plasmon intensity induced in the part of the MIM cavity structure corresponding to the substrate protrusion is greater than the plasmon intensity induced in the rest of the substrate body. This allows for self-aligned exposure of the part of the intermediate photoresist layer corresponding to the substrate protrusion to form a dot matrix exposure pattern. The intermediate photoresist layer can be exposed without the need for a nanoscale mask, reducing the complexity of the fabrication method and eliminating the overlay alignment error problem in existing photolithography processes.
[0040] Furthermore, the parallel beam incident on the MIM cavity structure provided in this application induces plasma evanescent waves, so that the interference fringe period is no longer limited by the free space wavelength, thereby enabling nanoscale exposure of the intermediate photoresist layer at a level far below the diffraction limit. This not only breaks through the physical limits of existing photolithography processes and achieves super-resolution exposure, thus providing a foundation for the fabrication of deep sub-meter wavelength three-dimensional structures, but also has stable exposure quality with high contrast and high NILS. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0042] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application;
[0043] Figure 2 A flowchart illustrating another method for fabricating a semiconductor device provided in this application embodiment;
[0044] Figure 3 A flowchart illustrating another method for fabricating a semiconductor device provided in this application embodiment;
[0045] Figure 4 A flowchart illustrating another method for fabricating a semiconductor device provided in this application embodiment;
[0046] Figures 5 to 9 for Figure 4 A structural diagram corresponding to the relevant steps in the process;
[0047] Figure 10 The image shown is a schematic diagram of the imaging result of exposing an intermediate photoresist layer with a parallel beam of 436nm wavelength according to an embodiment of this application.
[0048] Figure 11 A schematic diagram of a two-dimensional imaging result of exposing an intermediate photoresist layer with parallel light beams based on wavelengths of 436nm and 532nm, provided for an embodiment of this application;
[0049] Figure 12 A simulation result of the light intensity at the substrate protrusion corresponding to the intermediate photoresist layer is provided in an embodiment of this application.
[0050] Figure 13 A light intensity distribution curve at the substrate protrusion corresponding to the intermediate photoresist layer is provided in an embodiment of this application.
[0051] Figure 14 A schematic diagram of a dot matrix exposure pattern provided in an embodiment of this application;
[0052] Figure 15 This is a schematic diagram of the structure of a substrate provided in an embodiment of this application;
[0053] Figure 16 This is a schematic diagram of another substrate structure provided in an embodiment of this application;
[0054] Figure 17 This is a schematic diagram of another substrate structure provided in an embodiment of this application;
[0055] Figure 18 This is a schematic diagram of another substrate structure provided in an embodiment of this application;
[0056] Figure 19 This is a schematic diagram of another substrate structure provided in an embodiment of this application;
[0057] Figure 20 This is a schematic diagram of another substrate structure provided in an embodiment of this application;
[0058] Figure 21 This is a schematic diagram of another substrate structure provided in an embodiment of this application.
[0059] Explanation of reference numerals in the attached figures:
[0060] 100 Substrate, 101 Substrate to be processed, 102 Anti-reflection layer, 103 Photoresist layer, 104 Substrate body, 105 Substrate protrusion, 106 Three-dimensional structure;
[0061] 200 dielectric layer;
[0062] The structure consists of a 300-meter cavity, a 301-meter first metal layer, a 302-meter intermediate photoresist layer, a 303-meter second metal layer, and a 302-meter dot matrix exposure pattern. Detailed Implementation
[0063] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0064] As described in the background section, with the rapid development of semiconductor devices such as 3D integrated circuits, advanced memories, and nanoscale photonic devices, manufacturing processes place significantly higher demands on lithographic resolution and 3D structure processing capabilities. Traditional optical lithography, limited by the diffraction limit, typically relies on the Rayleigh criterion for its imaging capabilities; that is, under projection exposure conditions, the minimum pattern size is difficult to be less than approximately one-quarter of the exposure wavelength. For commonly used visible or ultraviolet light sources, conventional lithography methods struggle to achieve nanoscale patterns in the deep subwavelength range, especially failing to maintain sufficient imaging contrast and morphological consistency in high-depth structures such as 3D vias, becoming a significant bottleneck restricting the precision of 3D structure manufacturing.
[0065] Based on this, embodiments of this application provide a method for fabricating semiconductor devices, effectively solving the technical problems existing in the prior art. It eliminates the need for nanoscale masks to perform self-aligned exposure on the portion of the intermediate photoresist layer corresponding to the substrate protrusions, forming a dot matrix exposure pattern. This reduces the complexity of the fabrication method and eliminates the overlay alignment error problem in existing photolithography processes. Furthermore, the technical solution provided by embodiments of this application achieves nanoscale exposure of the intermediate photoresist layer far below the diffraction limit, breaking through the physical limits of existing photolithography processes and providing a foundation for the fabrication of deep sub-meter wavelength three-dimensional structures. It also possesses stable exposure quality with high contrast and high NILS (Near-Intensity Interval).
[0066] To achieve the above objectives, the technical solutions provided in this application are as follows, in specific combination with... Figures 1 to 21 The technical solutions provided in the embodiments of this application will be described in detail.
[0067] refer to Figure 1 The diagram shown is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. The method for fabricating a semiconductor device according to an embodiment of this application includes:
[0068] S1. Prepare a substrate, the substrate including a substrate body and at least one substrate boss located on one side of the substrate body.
[0069] S2. A MIM cavity structure is formed by sequentially stacking a first metal layer, an intermediate photoresist layer, and a second metal layer on the side surface of the substrate having the substrate protrusion, wherein the first metal layer is conformal to the surface of the substrate.
[0070] S3. A parallel beam of non-coherent superposition of TM and TE modes is incident from the surface of the MIM cavity structure away from the substrate at a preset angle to induce plasmons in the MIM (metal-dielectric-metal) cavity structure, thereby exposing the portion of the intermediate photoresist layer corresponding to the substrate protrusion to form a dot matrix exposure pattern.
[0071] S4. Remove the second metal layer.
[0072] S5. The intermediate photoresist layer is developed to form an array structure with a pattern corresponding to the dot matrix exposure pattern.
[0073] S6. The substrate is etched based on the array structure to form a three-dimensional structure array in the substrate, while the array structure and the first metal layer are removed.
[0074] As can be seen from the above, the technical solution provided in this application, after controlling the parallel beams of incoherent superposition of TM and TE modes to be incident from the surface of the MIM cavity structure away from the substrate at a preset angle, can induce plasmons in the MIM cavity structure. Due to the special structure of the substrate protrusion being higher than the rest of the substrate body, the plasmon intensity induced by the part of the MIM cavity structure corresponding to the substrate protrusion is greater than the plasmon intensity induced by the rest of the MIM cavity structure corresponding to the substrate body. Thus, the part of the intermediate photoresist layer corresponding to the substrate protrusion can be self-aligned for exposure to form a dot matrix exposure pattern. The intermediate photoresist layer can be exposed without the need for a nanoscale mask, reducing the complexity of the preparation method and eliminating the overlay alignment error problem in the existing photolithography process. Furthermore, the parallel beam incident on the MIM cavity structure provided in this application induces plasma evanescent waves, so that the interference fringe period is no longer limited by the free space wavelength. This enables nanoscale exposure of the intermediate photoresist layer at a level far below the diffraction limit, breaking through the physical limits of existing photolithography processes and achieving super-resolution exposure. This provides a foundation for the fabrication of deep sub-meter wavelength three-dimensional structures, exhibiting stable and excellent exposure quality. In addition, numerical simulations of this photolithography operation were performed using the Finite Element Method (FEM) and Rigorous Coupled Wave Analysis (RCWA). The simulation imaging effects of the multiple algorithms showed good consistency, excellent contrast, and normalized image logarithmic slope, achieving effective region selectivity and super-resolution imaging.
[0075] To improve the exposure effect of the incoherently superimposed parallel beams of TM and TE modes on the intermediate photoresist layer, this embodiment can also form a dielectric layer between the substrate and the first metal layer. See details. Figure 2 The diagram shows a flowchart of another method for fabricating a semiconductor device according to an embodiment of this application. The method further includes, after step S1 and before step S2:
[0076] S1': A dielectric layer is formed on the surface of the substrate having the substrate protrusion, the dielectric layer being conformal to the surface of the substrate; wherein, step S2 includes: forming a MIM cavity structure by sequentially stacking a first metal layer, an intermediate photoresist layer, and a second metal layer on the side of the dielectric layer away from the substrate, the first metal layer being conformal to the surface of the substrate; and step S6 includes: etching the substrate based on the array structure to form a three-dimensional structure array in the substrate, while removing the array structure, the first metal layer, and the dielectric layer.
[0077] In some embodiments, the substrate provided in this application can be fabricated using a photolithography process. See details. Figure 3 The diagram shows a flowchart of another method for fabricating a semiconductor device according to an embodiment of this application. Step S1 provided in this embodiment includes:
[0078] S11, Provide a substrate to be processed.
[0079] S12. A photoresist layer is formed on one side surface of the substrate to be processed.
[0080] S13. Expose the upper photoresist layer based on the initial mask, and then develop the upper photoresist layer.
[0081] S14. The substrate to be processed is etched based on the upper photoresist layer to obtain the desired substrate, and the upper photoresist layer is removed, wherein the substrate includes a substrate body and at least one substrate protrusion located on one side of the substrate body.
[0082] Furthermore, to improve the optical imaging quality during exposure, an anti-reflection layer can be formed on the surface of the substrate to be processed. (Reference) Figure 4 The diagram shows a flowchart of another method for fabricating a semiconductor device according to an embodiment of this application. The method further includes, after step S11 and before step S12:
[0083] S11', An anti-reflective layer is formed on one side surface of the substrate to be processed;
[0084] Step S12 includes: forming an upper photoresist layer on the side of the anti-reflection layer away from the substrate to be processed; and step S14 includes: etching the substrate to be processed based on the upper photoresist layer to obtain the desired substrate, and removing the upper photoresist layer and the anti-reflection layer, wherein at least one substrate protrusion is formed on one side of the substrate.
[0085] The following is in conjunction with the appendix Figures 4 to 9 The preparation method provided in the embodiments of this application will be described in more detail. Figures 5 to 9 for Figure 4 A schematic diagram of the corresponding structure for some of the steps.
[0086] like Figure 5 As shown, corresponding to steps S11, S11' and S12, a substrate 101 to be processed is provided, an anti-reflection layer 102 is formed on one side surface of the substrate 101 to be processed, and an upper photoresist layer 103 is formed on the side of the anti-reflection layer 102 opposite to the substrate 101 to be processed.
[0087] In some embodiments, the substrate 100, serving as the basis for subsequent plasma super-resolution imaging structures, needs to possess high flatness, low roughness, and good optical stability to ensure stable boundary conditions during light field propagation and interference at the interface. Therefore, the substrate 101 to be processed can be made of single-crystal silicon or other semiconductor materials with high refractive index and strong stability. Its surface can be chemically and mechanically polished to meet the flatness requirements of deep subwavelength lithography. Before further fabrication of the substrate 101, it can be surface-cleaned. The cleaning process may include stepwise ultrasonic cleaning with acetone, isopropanol, and deionized water to remove organic residues and microparticle contamination; subsequently, nitrogen drying or hot plate pre-baking is used to remove surface-adsorbed moisture.
[0088] Then, an anti-reflection layer 102 needs to be formed on the substrate 101 to be processed. The anti-reflection layer 102 can be an anti-reflection coating, which can be a thin film material coated on one side surface of the substrate 101 to be processed. It is mainly used to suppress the standing wave effect and pattern distortion caused by reflected light, thereby improving the exposure accuracy.
[0089] Subsequently, photoresist is spin-coated onto the side of the anti-reflective layer 102 facing away from the substrate 101. The upper photoresist layer 103 can be a photoresist material with a refractive index of 1.4-1.9, and a uniform thin film is formed on the anti-reflective layer 102 by spin-coating. The spin-coating step requires control of the rotation speed (e.g., 2000-4000 rpm), acceleration, and time to obtain the desired upper photoresist layer 103. Optionally, the thickness range of the upper photoresist layer 103 provided in this embodiment can be 20-100 nm. After spin-coating the upper photoresist layer 103, it can also be soft-baked to remove solvent and improve the film density. The soft-baking temperature can be 80-120°C, and the duration can be determined according to the thickness of the upper photoresist layer 103 and the solvent evaporation rate, which is not specifically limited in this application. Appropriate soft baking can improve the optical uniformity of the upper photoresist layer 103, ensuring that it has stable absorption and exposure threshold characteristics in subsequent processes.
[0090] like Figure 6 As shown, corresponding to steps S13 and S14, the upper photoresist layer 103 is exposed based on the initial mask, and the upper photoresist layer 103 is developed. Then, the substrate 101 to be processed is etched based on the upper photoresist layer 103 to obtain the desired substrate 100, and the upper photoresist layer 103 and the anti-reflection layer 102 are removed. At least one substrate bump 105 is formed on one side of the substrate 100. That is, the substrate 100 provided in this embodiment includes a substrate body 104 and at least one substrate bump 105 located on one side of the substrate body 104.
[0091] During the exposure of the photoresist layer 103, a large-size initial mask can be selected for exposure processing to construct the substrate protrusions 105 required for subsequent steps. In subsequent steps, the substrate protrusions 105 not only serve as the growth interface for the conformal film system of the MIM cavity but also as a natural physical boundary to define the exposure area in step S3, ensuring that super-resolution interference fringes form only on the corresponding area of the substrate protrusions 105 facing away from the substrate body 104 during the exposure process in step S3. The feature size of the large-size initial mask provided in this embodiment can be on the order of hundreds of nanometers to micrometers, and the resulting substrate protrusions 105 are much larger than the three-dimensional structure formed in subsequent step S6. The fabrication method provided in this embodiment does not require the fabrication of substrate protrusions 105 with finer dimensions; it only requires the substrate protrusions 105 to define the geometric boundary positions, thus significantly reducing the fabrication difficulty and cost of the initial mask. The initial mask provided in this embodiment can be made of quartz or other high-transmittance carriers, and its patterned area can be formed by electron beam exposure or existing photolithography processes, without requiring high resolution.
[0092] The photoresist layer 103 can be exposed using ultraviolet (UV) exposure. Exposure parameters (such as dosage, light intensity uniformity, and exposure time) can be optimized based on the type of photoresist layer 103 to ensure a clear pattern with sufficient fidelity. After exposure, development is performed to ensure the pattern formed by the photoresist layer 103 is presented on the substrate 101 with a predetermined morphology. Then, a dry etching process (such as reactive ion etching or deep silicon etching) or a wet etching process is used to transfer the pattern formed by the photoresist layer 103 to the substrate 101, thereby forming substrate bumps 105. During etching, parameters such as etching rate, plasma power, working pressure, and gas flow rate can be optimized to avoid pattern distortion or sidewall chamfering, and to ensure the etching depth meets the requirements for conformal deposition of the subsequent dielectric layer and first metal layer. After etching, residual photoresist can be removed using photoresist stripping or oxygen plasma ashing, resulting in a clear pattern with good surface quality. Optionally, the thickness of the substrate protrusion 105 can be 50-200 nm. The substrate protrusion 105 provides a natural geometric boundary, enabling it to define the sidewall growth regions of the dielectric layer and the first metal layer during subsequent conformal deposition, and guide the position of localized surface plasmon excitation during exposure in step S3, achieving a self-aligned selected area imaging process. This allows for precise exposure control in step S3 without relying on high-precision overlay, laying the foundation for subsequent self-aligned lithography.
[0093] like Figure 7As shown, corresponding to steps S1' and S2, a dielectric layer 200 is formed on the side surface of the substrate 100 having the substrate protrusion 105, and the dielectric layer 200 is conformal to the surface of the substrate 100; then, a MIM cavity structure 300 consisting of a first metal layer 301, an intermediate photoresist layer 302, and a second metal layer 303 is sequentially stacked on the side of the dielectric layer 200 away from the substrate 100, and the first metal layer 301 is conformal to the surface of the substrate 100.
[0094] After the substrate 100 is fabricated, multiple film layers need to be conformally deposited on the surface of the substrate 100 with the substrate protrusion 105 using a deposition process with unidirectional growth characteristics, thereby fabricating a metal-dielectric-metal nanostructure, namely the MIM cavity structure 300. This MIM cavity structure 300 covers the surface of the substrate 100 and ultimately constitutes a key structure that can support surface plasmon resonance excitation, which is the core structure for realizing subsequent self-alignment and selected area super-resolution imaging.
[0095] First, a dielectric layer 200 and a first metal layer 301 need to be conformally fabricated on the substrate 100. Optionally, this application can employ deposition methods with conformal thin film growth capabilities, such as atomic layer deposition or magnetron sputtering, to achieve uniform coverage of the dielectric layer 200 in the micrometer-level grooves, sidewalls, and top. The dielectric layer 200 provided in this embodiment can be an oxide layer, such as a silicon oxide layer; the thickness of the dielectric layer 200 can range from 20 to 70 nm. Then, a deposition method with conformal thin film growth capabilities, such as atomic layer deposition or magnetron sputtering, can be used to fabricate the first metal layer 301 on the dielectric layer 200. The first metal layer 301 is also conformally fitted to the surface of the substrate 100; optionally, the first metal layer 301 can be an Ag metal layer with a thickness ranging from 30 to 100 nm. When fabricating the first metal layer 301 in the MIM cavity structure 300, it is necessary to strictly control the deposition rate, film density, and thickness uniformity to ensure that the metal layer has good optical reflection characteristics, a negative permittivity distribution, and low surface roughness, thereby ensuring effective coupling of the plasma mode. Furthermore, by optimizing the thickness of the metal layer, a strong interference field and localized energy enhancement can be generated during the exposure process in step S3. The dielectric layer 200 needs to maintain a stable refractive index and low absorption to facilitate the propagation of evanescent waves in the photoresist region. The conformally formed dielectric layer 200 and first metal layer 301 enable the MIM cavity structure 300 to precisely replicate the sidewall of the substrate protrusion 105, thereby forming a natural light field confinement region in space (i.e., the corresponding area of the substrate protrusion 105 facing away from the substrate body 104), providing a controllable "selective excitation window" for subsequent exposure. This window generates plasma evanescent waves only in the corresponding area of the MIM cavity structure 300 on the surface of the substrate protrusion 105 facing away from the substrate body 104, enabling this application to achieve region-selective nanoscale lithography without the need for array structure alignment, thereby significantly improving the pattern consistency and imaging stability of the three-dimensional structure.
[0096] After the conformal deposition of the dielectric layer 200 and the first metal layer 301 is completed, the intermediate photoresist layer 302 and the second metal layer 303 need to be prepared. Firstly, the intermediate photoresist layer 302 needs to be spin-coated to construct the imaging dielectric layer required for the exposure to form the dot matrix exposure pattern 3021. The intermediate photoresist layer 302 is not only the imaging carrier for the subsequent super-resolution interferometry field, but its thickness, refractive index, and optical loss parameters also directly affect the distribution of surface plasmon evanescent waves. Therefore, strict control of the photoresist material selection and spin-coating parameters is required. Specifically, the intermediate photoresist layer 302 can be selected as a refractive index material of 1.4-1.9 to match the optical environment of the conformally formed dielectric layer 200 and meet the incident conditions of the super-resolution interferometry mode. The spin coating process can achieve the desired thickness by adjusting the rotation speed, acceleration, and spin coating time, and can be optimized according to the exposure wavelength (i.e., the wavelength of the parallel beam, such as 436nm, 532nm, or 633nm) to achieve the optimal distribution of interference fringes within the intermediate photoresist layer 302; optionally, the thickness of the intermediate photoresist layer 302 can range from 20-80nm. After spin coating of the photoresist material, soft baking is required to improve the film density of the intermediate photoresist layer 302 and reduce solvent residue.
[0097] Subsequently, after spin-coating the intermediate photoresist layer 302, a second metal layer 302 is prepared using a metal thin film deposition process. The material for the second metal layer 302 is optimized; for example, materials with excellent negative permittivity and high reflectivity in the visible and near-ultraviolet bands are ideal for constructing the MIM cavity structure 300 to excite surface plasmon evanescent waves. The second metal layer 302 can be prepared by processes such as electron beam evaporation, magnetron sputtering, or thermal evaporation. During preparation, a low deposition rate and appropriate substrate temperature must be maintained to avoid damaging the intermediate photoresist layer 302 and ensure a smooth film surface. Optionally, the second metal layer 303 provided in this embodiment can be an Ag metal layer. In some embodiments, the first metal layer 301 and the second metal layer 303 provided in this application can also be other metal materials, such as Al, etc., and this application does not impose specific limitations on this. The thickness of the second metal layer 302 is crucial for the formation of the interference field. The thickness of the second metal layer 303 can range from 20 to 80 nm and needs to be optimized according to the exposure wavelength to ensure the coupling efficiency between the incident parallel beam and the MIM cavity structure 300, so that the evanescent wave is generated only in the area defined by the substrate protrusion 105. The second metal layer 303 acts as a light field confinement layer during the exposure process, enabling optical energy to form deep subwavelength periodic fringes in the intermediate photoresist layer 302, thereby achieving self-aligned imaging.
[0098] like Figure 8As shown, corresponding to step S3, a parallel beam of non-coherent superposition of TM mode and TE mode is controlled to be incident from the surface of the MIM cavity structure 300 away from the substrate 100 at a preset angle to induce plasmons in the MIM cavity structure 300, and to expose the portion of the intermediate photoresist layer 302 corresponding to the substrate protrusion 105 to form a dot matrix exposure pattern 3021.
[0099] After fabrication of the MIM cavity structure 300, a parallel beam of incoherently superimposed TM and TE modes is incident on the MIM cavity structure 300 at a preset angle (e.g., perpendicular angle) for exposure. This induces surface plasmon polaritons (surface plasmon evanescent waves) in the region defined by the substrate protrusion 105 corresponding to the MIM cavity structure 300, thereby achieving self-aligned super-resolution imaging with selected area characteristics. This process does not require an array structure and is considered array-free exposure, with the imaging area naturally defined only by the geometric boundaries provided by the substrate protrusion 105. Using a parallel beam incident on the MIM cavity structure 300 can excite surface plasmon polariton modes within the sandwich structure of the MIM cavity structure 300. Parallel light irradiating the MIM cavity structure 300 at a preset angle allows the light field to expand along the MIM cavity structure 300, generating enhanced interference. With a suitable configuration of metal layer thickness, intermediate photoresist layer 302 thickness and parallel beam wavelength, a spatial evanescent wave with a period much smaller than the exposure wavelength can be formed inside the intermediate photoresist layer 302, thereby generating a super-resolution imaging structure with a key size of 20-50nm. That is, in the three-dimensional structure array provided in the embodiments of this application, the size of the three-dimensional structure can be 20-50nm.
[0100] In other words, the exposure of the intermediate photoresist layer 302 provided in this application has the advantages of selective excitation, self-alignment, and super-resolution. Selective excitation: The surface plasmon evanescent wave is excited only in the area defined by the substrate protrusion 105. Outside this area, due to the lack of suitable structural support, no interference fringes are generated, thus enabling the exposure of the intermediate photoresist layer 302 without an array structure. Self-alignment: Since the evanescent wave excitation area is defined by the geometric boundary of the substrate protrusion 105, no overlay operation is required, completely avoiding the alignment error accumulation problem in traditional photolithography processes. Super-resolution: The period of the interference fringes is determined by the plasma mode, not by the wavelength of the parallel beam, which is much smaller than the propagation limit of light waves in free space, enabling the fabrication method provided in this application to overcome the diffraction limit. During the exposure of the intermediate photoresist layer 302, the light field generates a periodic intensity distribution within the intermediate photoresist layer 302, and its contrast and NILS can meet the requirements of subsequent development and image transfer. Experiments have shown that when optimizing the thickness of each layer of the MIM cavity structure 300, a contrast of over 0.7 can be obtained under parallel beam exposure conditions of different wavelengths, ensuring the clarity of the image. Therefore, the technical solution provided in this application embodiment can form a high-contrast, deep subwavelength periodic light intensity distribution within the area confined by the substrate protrusion 105 corresponding to the MIM cavity structure 300, laying the foundation for obtaining nanoscale patterns through subsequent development, and realizing the core function of area-selective, self-aligned super-resolution lithography of this application.
[0101] The exposure process of the intermediate photoresist layer 302 provided in the embodiments of this application is analyzed using simulation algorithms. (Reference) Figure 10 The diagram shown illustrates the imaging results of exposing an intermediate photoresist layer using a parallel beam with a wavelength of 436 nm, according to an embodiment of this application. For a structure with a half-cycle of 800 nm, super-resolution imaging can be generated in the intermediate photoresist layer 302, exhibiting good imaging characteristics. Here, PR represents the intermediate photoresist layer 302, and... Figure 10 (a) and Figure 10 (b) shows the one-dimensional simulation results based on the FEM algorithm. Figure 10 (c) and Figure 10 (d) shows the one-dimensional simulation results based on the RCWA algorithm, indicating that 14 nanometer-scale periodic stripes were formed in the intermediate photoresist layer 302. Figure 10 (a) The imaging light intensity at different positions (20% depth, intermediate depth, and 80% depth) in the intermediate photoresist layer 302 is analyzed. Figure 10 (b) indicates that when the optical power threshold is 1×10 8 (V / m) 2 Up to 2×10 8 (V / m) 2When selecting between different locations, the imaging light power at different positions of the intermediate photoresist layer 302 is relatively the same. Therefore, removing the top 20% of the material of the intermediate photoresist layer 302 during processing still results in good optical performance in the imaging results. Specifically, the critical dimension of its fringes is 28.5 nm, the fringe resolution is reduced to 1 / 15.3 of the wavelength, and super-resolution patterns are only generated in the area defined by the substrate protrusion 105. Furthermore, through the contrast formula... and NILS formula The contrast and NILS values were obtained, showing that the worst contrast was 0.83 and the NILS value at the boundary of ideal imaging was 2.05. Therefore, it can be concluded that by combining the substrate protrusion 105, the MIM cavity structure 300, and the parallel beam, self-excited lithography and resolution enhancement of the specified area were achieved, with enhancement effects far exceeding those of traditional lithography processes.
[0102] To analyze the feasibility of the exposure process for the intermediate photoresist layer 302 provided in this application in practical applications, its effect on the selective imaging of generating two-dimensional strip structures is further analyzed. (Reference) Figure 11 The image shown is a schematic diagram of a two-dimensional imaging result obtained by exposing an intermediate photoresist layer with parallel light beams at wavelengths of 436nm and 532nm, according to an embodiment of this application. Combined with... Figure 10 Based on the analysis and simulation results, the structural periodicity is 228nm under a parallel beam with a wavelength of 436nm and 320nm under a parallel beam with a wavelength of 532nm. Figure 11 (a) Figure 11 (b) and Figure 11 (c) is a schematic diagram of the two-dimensional imaging results under a parallel beam at a wavelength of 436 nm. The results show that it can achieve imaging with a critical size of 28.5 nm in a specific region, with a contrast ratio of 0.53 and an NILS ratio of 1.71. Similarly, Figure 11 (d) Figure 11 (e) and Figure 11 (f) is a schematic diagram of the two-dimensional imaging results under a parallel beam at a wavelength of 532 nm. The results show that it can achieve imaging with a critical size of 40 nm in a specific region, and its contrast ratio can reach above 0.94, with an NILS of 2.15. In particular, this application can also achieve super-resolution selected area lithography on parallel beams of other optical wavelengths. Therefore, there is reason to believe that this super-resolution imaging lithography process based on the MIM cavity structure 300 can be reliably applied in practice.
[0103] Further analysis of the exposure process for the intermediate photoresist layer 302 provided in this application yields a simulated three-dimensional structure. Combined with... Figures 12 to 14 As shown, Figure 12This image shows a simulation result of the light intensity at the substrate protrusion corresponding to the intermediate photoresist layer, as provided in an embodiment of this application. Figure 13 This is a light intensity distribution curve at the substrate protrusion corresponding to the intermediate photoresist layer, provided as an embodiment of this application. Figure 14 This is a schematic diagram of a dot matrix exposure pattern provided in an embodiment of this application. Figure 12 It can be seen that the exposure process for the intermediate photoresist layer 302 provided in this application can effectively produce a uniform and high-contrast rectangular via structure. Figure 13 It can be seen that it can produce 16 optical apertures with a contrast ratio of about 0.75 and a NILS ratio of about 1.5. Figure 14 To select a certain light intensity threshold, a schematic diagram of the generated three-dimensional light intensity through-hole structure is shown, which forms a corresponding dot matrix exposure pattern 3021 of 13×13=169. The critical dimension (CD) of each exposure point is about 25nm, and the period is about 50nm, achieving an aperture resolution of 1 / 17.44 of the exposure wavelength.
[0104] like Figure 9 As shown, corresponding to steps S4, S5 and S6, the second metal layer 303 is removed, the intermediate photoresist layer 302 is developed to form an array structure with a pattern corresponding to the dot matrix exposure pattern 3021, the substrate 100 is etched based on the array structure to form a three-dimensional structure array in the substrate 100, and the array structure, the first metal layer 301 and the dielectric layer 200 are removed at the same time.
[0105] After the exposure process of the intermediate photoresist layer 302 is completed, the removal of the second metal layer 303, the development of the intermediate photoresist layer 302, post-baking, and pattern transfer etching of the multilayer thin film need to be performed sequentially to ultimately form a deep sub-meter wavelength three-dimensional structure array in the substrate 100. The three-dimensional structure array includes multiple three-dimensional structures 106 arranged in an array. The three-dimensional structure 106 can be a three-dimensional via or a three-dimensional pillar, which needs to be determined based on the development results of the intermediate photoresist layer 302. Specifically, the second metal layer 303 can first be removed by selective wet etching (such as a metal removal solution based on nitric acid or peroxide system) or ion etching. Since the second metal layer 303 acts as an optical field confinement layer in the MIM cavity structure 300, its removal process must ensure that the pattern energy threshold distribution exhibited by the intermediate photoresist layer 302 is not destroyed. After the removal of the second metal layer 303, the exposed and unexposed areas in the intermediate photoresist layer 302 exhibit different dissolution rates, which can be used for the development step. During the development process of the intermediate photoresist layer 302, a periodic deep subwavelength groove structure can be formed. After development, post-baking is performed to enhance pattern stability, improve sidewall strength, and reduce the molecular chain expansion effect caused by development.
[0106] Then, the nanoscale pattern of the intermediate photoresist layer 302 (i.e., the pattern corresponding to the dot matrix exposure pattern 3021) is transferred to the underlying multilayer structure (first metal layer 301, dielectric layer 200, and substrate 100). Pattern transfer etching can employ processes such as reactive ion etching, deep silicon etching, or atomic layer etching to ensure high etching selectivity and directionality in the vertical direction, allowing the etched structure to extend continuously along the depth direction. Etching parameters (such as power, gas ratio, and pressure) need to be optimized according to the material system to ensure steep sidewalls and uniform dimensions.
[0107] Continue as Figure 9 As shown, the three-dimensional structure array provided in this application embodiment can be a three-dimensional via array, that is, the three-dimensional structure 106 provided in this application embodiment can be a three-dimensional via. In this regard, step S5 provided in this application embodiment includes: developing the intermediate photoresist layer 302 to form an array structure having a pattern corresponding to the dot matrix exposure pattern 3021, the array structure including a perforated array corresponding to the dot matrix exposure pattern; wherein, step S6 includes: etching the substrate 100 based on the array structure to form a three-dimensional via array in the substrate 100, while removing the array structure and the first metal layer 301. Furthermore, when a dielectric layer 200 is included between the substrate 100 and the first metal layer 301, the dielectric layer 200 needs to be removed after removing the first metal layer 301. That is, when developing the intermediate photoresist layer 302, the portion corresponding to each dot of the dot matrix exposure pattern 3021 is removed, thereby enabling the formation of a three-dimensional via array in the substrate 100 when etching the substrate 100.
[0108] In some embodiments of this application, when etching the substrate 100, only the substrate protrusion 105 portion may be etched; that is, continuing as follows... Figure 9 As shown, step S6 provided in this embodiment includes: etching the substrate protrusion 105 based on the array structure to form a three-dimensional via array in the substrate protrusion 105, while removing the array structure and the first metal layer 301. Alternatively, in this embodiment, when etching the substrate 100, not only can the substrate protrusion 105 be etched, but the etching can also extend to the substrate body 104; see reference. Figure 15 The diagram shows a schematic representation of a substrate structure provided in an embodiment of this application. Specifically, step S6 in this embodiment includes: etching the substrate protrusion 105 based on the array structure, extending the etching to a first preset depth in the substrate body 104, to form a three-dimensional via array in the substrate protrusion 105 and the substrate body 104, while simultaneously removing the array structure and the first metal layer 301. The first preset depth can be less than the thickness of the substrate body 104, such as... Figure 15The three-dimensional via shown does not penetrate the substrate body 104; or, the first preset depth can also be equal to the thickness of the substrate body 104, such as... Figure 16 The three-dimensional through-hole shown penetrates the substrate body 104, but this application does not impose specific limitations on this.
[0109] Furthermore, during the etching of the substrate 100, and extending the etching to a first preset depth, based on the desired morphology of the substrate 100, after obtaining the three-dimensional via array, the substrate protrusions 104 can be partially removed. For example... Figure 17 The diagram shown is a schematic diagram of another substrate structure provided in the embodiment of this application. In the preparation method provided in the embodiment of this application, when the substrate protrusion 105 is etched based on the array structure and the etching extends to a first preset depth in the substrate body 104, after step S6, the preparation method further includes: S7, removing the substrate protrusion 105.
[0110] In some embodiments, the three-dimensional structure array provided in this application can also be a three-dimensional columnar array, that is, the three-dimensional structure 106 is a three-dimensional columnar array. For example... Figure 18 The diagram shows a schematic representation of another substrate structure provided in this application embodiment. Specifically, step S5 in this application embodiment includes: developing the intermediate photoresist layer 302 to form an array structure with a pattern corresponding to the dot matrix exposure pattern 3021, wherein the array structure includes a solid column array corresponding to the dot matrix exposure pattern; wherein step S6 includes: etching the substrate 100 based on the array structure to form a three-dimensional column array in the substrate 100, while simultaneously removing the array structure and the first metal layer 301. Furthermore, when a dielectric layer 200 is included between the substrate 100 and the first metal layer 301, the dielectric layer 200 needs to be removed after removing the first metal layer 301. It can be understood that when developing the intermediate photoresist layer 302, the portion outside each dot of the dot matrix exposure pattern 3021 is removed, thereby enabling the formation of a three-dimensional column array in the substrate 100 during etching.
[0111] In some embodiments of this application, when etching the substrate 100, only the substrate protrusion 105 portion may be etched; that is, continuing as follows... Figure 18 As shown, step S6 provided in this application embodiment includes: etching the substrate protrusion 105 based on the array structure to form a three-dimensional columnar array in the substrate protrusion 105, while removing the array structure and the first metal layer 301. Alternatively, in this application embodiment, when etching the substrate 100, not only can the substrate protrusion 105 be etched, but the etching can also extend to the substrate body 104; see reference. Figure 19The diagram shows a schematic representation of another substrate structure provided in this application embodiment. Specifically, step S6 in this application embodiment includes: etching the substrate protrusions 105 based on the array structure, extending the etching to a second preset depth in the substrate body 104, to form a three-dimensional columnar array in the substrate protrusions 105 and the substrate body 104, while simultaneously removing the array structure and the first metal layer 301. The second preset depth can be less than the thickness of the substrate body 104, such as... Figure 19 The three-dimensional via shown does not penetrate the substrate body 104; or, the second preset depth can also be equal to the thickness of the substrate body 104, such as... Figure 20 The three-dimensional through-hole shown penetrates the substrate body 104, but this application does not impose specific limitations on this.
[0112] Furthermore, during the etching of the substrate 100, and extending the etching to a first preset depth, based on the desired morphology of the substrate 100, after obtaining the three-dimensional via array, the substrate protrusions 104 can be partially removed. For example... Figure 21 The diagram shown is a schematic diagram of another substrate structure provided in the embodiment of this application. In the preparation method provided in the embodiment of this application, when the substrate protrusion 105 is etched based on the array structure and the etching extends to the second preset depth in the substrate body 104, after step S6, the preparation method further includes: S7, removing the substrate protrusion 105.
[0113] In some embodiments, the semiconductor devices provided in this application may be devices such as memory, three-dimensional interconnects, and photonic crystals.
[0114] In summary, this application provides a method for fabricating a semiconductor device. By controlling a parallel beam of incoherent superposition of TM and TE modes and incident it at a preset angle from the surface of the MIM cavity structure away from the substrate, plasmons can be induced in the MIM cavity structure. Due to the special structure where the substrate protrusion is higher than the rest of the substrate body, the plasmon intensity induced by the portion of the MIM cavity structure corresponding to the substrate protrusion is greater than the plasmon intensity induced by the rest of the substrate body. This allows for self-aligned exposure of the portion of the intermediate photoresist layer corresponding to the substrate protrusion to form a dot matrix exposure pattern. The intermediate photoresist layer can be exposed without the need for a nanoscale mask, reducing the complexity of the fabrication method and eliminating the overlay alignment error problem in existing photolithography processes. Furthermore, the parallel beam incident on the MIM cavity structure provided in this application induces plasma evanescent waves, so that the interference fringe period is no longer limited by the free space wavelength, thereby enabling nanoscale exposure of the intermediate photoresist layer at a level far below the diffraction limit. This not only breaks through the physical limits of existing photolithography processes and achieves super-resolution exposure, thus providing a foundation for the fabrication of deep sub-meter wavelength three-dimensional structures, but also has stable exposure quality with high contrast and high NILS.
[0115] In the description of the embodiments of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0116] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0117] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0118] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0119] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0120] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: S1. Prepare a substrate, the substrate including a substrate body and at least one substrate boss located on one side of the substrate body; S2. A MIM cavity structure is formed by sequentially stacking a first metal layer, an intermediate photoresist layer, and a second metal layer on one side surface of the substrate having the substrate protrusion, wherein the first metal layer is conformal to the surface of the substrate. S3. A parallel beam of non-coherent superposition of TM mode and TE mode is incident from the surface of the MIM cavity structure away from the substrate at a preset angle to induce plasmons in the MIM cavity structure and expose the part of the intermediate photoresist layer corresponding to the substrate protrusion to form a dot matrix exposure pattern. S4. Remove the second metal layer; S5. The intermediate photoresist layer is developed to form an array structure with a pattern corresponding to the dot matrix exposure pattern. S6. The substrate is etched based on the array structure to form a three-dimensional structure array in the substrate, while the array structure and the first metal layer are removed.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, Step S1 includes: S11, Provide a substrate to be processed; S12. A photoresist layer is formed on one side surface of the substrate to be processed; S13. Expose the upper photoresist layer based on the initial photomask and develop the upper photoresist layer. S14. The substrate to be processed is etched based on the upper photoresist layer to obtain the desired substrate, and the upper photoresist layer is removed, wherein the substrate includes a substrate body and at least one substrate protrusion located on one side of the substrate body.
3. The method for fabricating a semiconductor device according to claim 2, characterized in that, After step S11 and before step S12, the preparation method further includes: S11', An anti-reflective layer is formed on one side surface of the substrate to be processed; Step S12 includes: forming an upper photoresist layer on the side of the anti-reflection layer away from the substrate to be processed; and step S14 includes: etching the substrate to be processed based on the upper photoresist layer to obtain the desired substrate, and removing the upper photoresist layer and the anti-reflection layer, wherein at least one substrate protrusion is formed on one side of the substrate.
4. The method for fabricating a semiconductor device according to claim 1, characterized in that, Step S5 includes: The intermediate photoresist layer is developed to form an array structure with a pattern corresponding to the dot matrix exposure pattern. The array structure includes an array of cutout holes corresponding to the dot matrix exposure pattern. Step S6 includes: etching the substrate based on the array structure to form a three-dimensional through-hole array in the substrate, while removing the array structure and the first metal layer.
5. The method for fabricating a semiconductor device according to claim 4, characterized in that, Step S6 includes: etching the substrate protrusions based on the array structure to form a three-dimensional via array in the substrate protrusions, while removing the array structure and the first metal layer; Alternatively, step S6 includes: etching the substrate protrusion based on the array structure and extending the etching to a first preset depth in the substrate body to form a three-dimensional through-hole array in the substrate protrusion and the substrate body, while removing the array structure and the first metal layer.
6. The method for fabricating a semiconductor device according to claim 5, characterized in that, When etching the substrate protrusions based on the array structure, and extending the etching to a first preset depth in the substrate body, after step S6, the fabrication method further includes: S7. Remove the substrate protrusion.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that, Step S5 includes: The intermediate photoresist layer is developed to form an array structure with a pattern corresponding to the dot matrix exposure pattern. The array structure includes a solid column array corresponding to the dot matrix exposure pattern. Step S6 includes: etching the substrate based on the array structure to form a three-dimensional columnar array in the substrate, while removing the array structure and the first metal layer.
8. The method for fabricating a semiconductor device according to claim 7, characterized in that, Step S6 includes: etching the substrate protrusions based on the array structure to form a three-dimensional columnar array in the substrate protrusions, while removing the array structure and the first metal layer; Alternatively, step S6 includes: etching the substrate protrusions based on the array structure and extending the etching to a second preset depth in the substrate body to form a three-dimensional columnar array in the substrate protrusions and the substrate body, while removing the array structure and the first metal layer.
9. The method for fabricating a semiconductor device according to claim 8, characterized in that, When etching the substrate protrusions based on the array structure, and extending the etching to a second preset depth in the substrate body, after step S6, the fabrication method further includes: S7. Remove the substrate protrusion.
10. The method for fabricating a semiconductor device according to any one of claims 1-9, characterized in that, After step S1 and before step S2, the preparation method further includes: S1' A dielectric layer is formed on the surface of the substrate having the substrate protrusion, the dielectric layer being conformal to the surface of the substrate; Step S2 includes: forming a MIM cavity structure by sequentially stacking a first metal layer, an intermediate photoresist layer, and a second metal layer on the side of the dielectric layer away from the substrate, wherein the first metal layer is conformal to the surface of the substrate; Step S6 includes: etching the substrate based on the array structure to form a three-dimensional structure array in the substrate, while removing the array structure, the first metal layer and the dielectric layer.