SSD cache control device supporting processing acceleration
By accelerating GC, word line writing, and secondary programming operations in the SSD storage controller through a cache control module independent of the CPU, the problem of high CPU load is solved, resulting in improved processing efficiency and reduced power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HEFEI DATANG STORAGE TECH CO LTD
- Filing Date
- 2026-01-30
- Publication Date
- 2026-05-19
AI Technical Summary
Existing SSD storage controllers suffer from high CPU load and low processing efficiency, leading to degraded system performance, especially increased read latency and data transfer latency during GC operations and word line writing.
By using a cache control module independent of the CPU, the reading and secondary programming operations during GC and word line writing are accelerated. The scanning, backup and verification operations are automatically completed by units such as TAPU and backup DMA, reducing CPU resource consumption.
It reduces CPU load and internal bandwidth usage, improves processing efficiency, reduces power consumption, and ensures the response speed of read and write commands and the accuracy of data.
Smart Images
Figure CN122064291A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of storage controller technology, and in particular to an SSD cache control device that supports processing acceleration. Background Technology
[0002] In existing SSD storage controller architectures, operations such as QLC NAND flash memory reprogramming, garbage collection (GC), and reading during word line writes primarily rely on CPU firmware code. GC operations require frequent block scanning and data migration, reprogramming requires continuous retention of intermediate data, and reading during word line writes requires waiting for programming to complete. These operations consume significant CPU resources, causing the CPU to be unable to respond promptly to host core commands, resulting in overall system performance degradation. For example, write data from the host needs to form a word line before being transmitted to the NAND controller; a word line consists of several pages, each page being 4096 bytes long; the number of pages is determined by the NAND flash memory characteristics, varying in length depending on the NAND flash memory, denoted as n; each word line consists of n pages, and programming n pages by the NAND controller takes a considerable amount of time. If data being programmed is read during word line writes, the word line must be programmed first, leading to prolonged read command return times and impacting normal system operation.
[0003] In addition, when the CPU processes the above operations, it needs to frequently interact with the Nand controller and cache, which consumes a lot of internal bandwidth, resulting in increased data transmission latency and slower response speed of read and write commands.
[0004] To address these issues, some manufacturers have mitigated the problems by increasing the number of CPUs or improving the bandwidth of memory access interfaces. However, this leads to a significant increase in hardware costs, and the collaboration of multiple CPUs requires even more resources, resulting in low cost-effectiveness. Summary of the Invention
[0005] This application provides an SSD cache control device that supports processing acceleration, solving the problems of high CPU load and low processing efficiency in existing SSD storage controllers. By accelerating secondary programming, garbage collection (GC), and read operations during word line writing through a cache control module independent of the CPU, it effectively reduces CPU load and internal bandwidth usage, thereby reducing the power consumption of the SSD storage controller.
[0006] This application provides an SSD cache control device that supports processing acceleration, including: a host interface, a cache control module, a Nand controller, a CPU, DRAM, and SRAM; the cache control module has a built-in logical address cache area, a buffer management table, a TAPU (Address Table Lookup Coprocessor Unit), and a backup DMA; the DRAM is divided into an independent secondary programming backup area, a word line programming backup area, and a GC read backup area; the SRAM is divided into a host data cache area and a GC read working area; the cache control module independently implements at least one of the following processing accelerations: automatic read backup and write processing of GC data, automatic backup and read acceleration processing of host write word line data, and automatic backup processing of secondary programming data.
[0007] The beneficial effects of the above embodiments are that resource-intensive operations such as GC, word line processing, and secondary programming are transferred from the CPU to the cache control module. The CPU only needs to complete the initialization configuration, which can reduce the CPU load, reduce the internal bandwidth usage, and reduce the overall power consumption of the SSD.
[0008] Based on the above embodiments, this application can be further improved as follows: In one embodiment of this application, the automatic read, backup, and write processing of GC data includes the following associated steps: The CPU configures the cache control module to specify the number N of blocks that need to be garbage collected. TAPU scans the valid data count (VPC) of all candidate blocks and selects the N blocks with the fewest valid data based on the VPC sorting, marking them as GC candidate blocks; The cache control module requests SRAM buffer space from the Buffer management table in batches, reads valid data of GC candidate blocks through the Nand controller, and the backup DMA automatically backs up the data to the GC read backup area of the DRAM. After completion, the SRAM buffer resources are released. Before writing to the Nand controller, TAPU compares the GC read backup area data with the latest L2P table mapping, checks whether HOSTwrite has modified the backed-up data, and whether the trim operation has invalidated the backed-up data. If it has been modified or invalidated, it is marked as invalid data; otherwise, GC write processing is performed normally.
[0009] Technical benefits: TAPU automatically performs GC block filtering and address consistency verification, replacing the complex calculations of the CPU; it automatically updates buffer management data to avoid GC operations blocking normal read and write operations, improving GC processing efficiency, while avoiding invalid data writing and ensuring data accuracy.
[0010] In one embodiment of this application, the automatic backup and read acceleration processing of the host writing word line data includes: When the cache control module detects that a word line data is sent to the Nand controller, the backup DMA automatically backs up the word line data to the word line programming backup area of the DRAM and updates the buffer management table to point to the backup area. During word line programming, if the host initiates a command to read the word line data, the cache control module directly retrieves the data from the backup area through the Buffer management table and returns it to the host.
[0011] Technical effects: It solves the read latency problem during word line writing, shortens the read command response time, ensures stable read performance in write-intensive scenarios, and avoids host command timeouts.
[0012] In one embodiment of this application, the automatic backup processing of the secondary programming data includes: When the cache control module detects that a word line data is sent to the NAND controller, it determines whether the word line data needs to be reprogrammed based on the firmware flag configured by the CPU; if so, the backup DMA automatically backs up the data to the reprogramming backup area of the DRAM. After the NAND controller completes its first programming, it retrieves data from the secondary programming backup area through the cache control module for a second programming.
[0013] Technical benefits: It enables automated data backup for the secondary programming needs of QLC particles, eliminating the need for the CPU to continuously retain intermediate data, thus improving the efficiency of secondary programming while ensuring that data is not lost. It is suitable for scenarios with mixed QLC and TLC / SLC particles.
[0014] In one embodiment of this application, the cache management process of the cache control module includes: The logical addresses of host read and write commands are stored in the logical address buffer, which corresponds one-to-one with the data segment addresses in the host data buffer. For read commands, if the same logical address exists in the logical address buffer, the data is read directly from the host data buffer. For write commands, if the same logical address exists in the logical address buffer, the old data in the host data buffer is replaced, and invalid data in other backup areas is automatically updated. The buffer management table records the status of each buffer, and the buffer control module determines the data transmission direction accordingly.
[0015] Technical effects: Improves cache hit rate, reduces the number of data interactions with the Nand controller, improves read and write command response speed, and ensures consistency between cached data and backup data.
[0016] In one embodiment of this application, the physical addresses of the secondary programming backup area, word line programming backup area, and GC read backup area of the DRAM are isolated from each other; the host data cache area and GC read work area of the SLAM are independently scheduled through a buffer management table to avoid data conflicts.
[0017] Technical benefits: Enables categorized storage and independent management of data from different scenarios, avoids data overwriting between backups, improves cache resource utilization, and reduces processing latency caused by data contention.
[0018] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: 1. Automatically complete scanning, backup, and verification operations through units such as TAPU and backup DMA, freeing up CPU resources to focus on core command processing; 2. Data consistency guarantee: Real-time synchronization of cached data and backup data is ensured through Buffer management table and TAPU address consistency checks to avoid data conflicts; 3. Performance improvement is achieved through architecture optimization without increasing the number of CPUs or bandwidth, resulting in high cost-effectiveness. Attached Figure Description
[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.
[0020] Figure 1 This is a structural block diagram of an SSD cache control device that supports processing acceleration, as described in an embodiment of this application. Figure 2 This is a flowchart illustrating the automatic read, backup, and write processing of GC data in an embodiment of this application; Figure 3 A flowchart illustrating the automatic backup and accelerated reading process of word line data in host programming in this application embodiment; Figure 4 This is a flowchart illustrating the automatic backup process of secondary programming data in an embodiment of this application. Detailed Implementation
[0021] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading the present invention, any modifications of the present invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.
[0022] Example: like Figure 1 As shown, an SSD cache control device that supports processing acceleration includes: a host interface, a cache control module, a Nand controller, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and a CPU; The cache control module includes a logical address cache, a buffer management table, a TAPU (Address Table Lookup Coprocessor Unit), and a backup DMA (Direct Memory Access). The DRAM contains separate secondary programming backup areas, word line programming backup areas, and GC read backup areas. The DRAM contains a host data cache and a GC read working area. The GC read working area is a reserved area in the DRAM for GC reads to improve efficiency; a portion of the DRAM storage is dedicated to GC reads, making data reads to the DRAM faster than those to the DRAM. GC data is first sent to the GC read working area, and then copied to the GC read backup area by the backup DMA. DMA copying and GC read operations to the DRAM can be performed simultaneously, creating a pipelined processing effect.
[0023] The host interface receives read, write, and memory management requests from the host; it also sends and receives host commands and data, caches data through the cache control module, and writes data to the Nand controller under CPU control. The Nand controller operates the Nand storage chips through the interface, writing received data to the Nand storage chips or reading data from the Nand storage chips into the cache. DRAM is used to store long-term backup data, and SRAM is used to store temporary working data; dynamic data scheduling is achieved through the cache control module.
[0024] In read / write commands sent by the host, the logical address is stored in the logical address cache. The base address of the logical address in the logical address cache corresponds one-to-one with the segment address of the host data in the host data cache. The data sent by the host is a fixed-length data segment, which is stored in the host data cache.
[0025] The cache control module, as the core processing unit, manages the SSD's internal cache, including logical address and cache mapping management, and handles read / write cache hits. The Buffer management table stores the current state of each buffer in the host data cache, indicating the data source, destination, and read / write count. It uses TAPU for block scanning and address verification, and backup DMA for automatic data backup. The cache control module determines the data transfer direction based on the Buffer management table. Each read / write command from the host queries the logical address cache. For read commands, if a matching logical address is found in the logical address cache, it's called a read hit, and the read command reads data from the buffer. For write commands, if a matching logical address is found in the logical address cache, it's called a write hit, and new data is written to replace the old data in the host data cache. Simultaneously, invalid data in other backup areas is automatically updated.
[0026] This cache controller is used to receive host data and cache it in SRAM or DRAM. It works with the firmware to write the cached data to the NAND controller, or works with the firmware to read the stored data into the cache through the NAND controller and return it to the host through the host interface.
[0027] This cache controller sets up different working areas or backup areas in DRAM and SRAM. Through a buffer management table, backup DMA, and TAPU (Address Table Lookup Coprocessor Unit), it handles data movement in different scenarios, achieving at least one of the following processing acceleration functions: automatic read / backup and write processing of GC data, automatic backup and read acceleration processing of host-written word line data, and automatic backup processing of secondary programming data. Specifically, GC data refers to the processing operations involved in storage granular garbage collection; word line data is written data cached to improve data access efficiency; and secondary programming data processing is the processing operation required for QLC granularities.
[0028] The automatic read, backup, and write process for GC data is as follows: Figure 2 As shown, it includes: 1.1: The firmware configures the number of blocks that need to be GC to the cache control module for processing acceleration, let's say it's N; 1.2: The cache control module scans the valid page count (VPC) of all candidate blocks through the TAPU (Address Table Lookup Coprocessor Unit). The VPC of the corresponding block is automatically updated by the hardware each time a host write / trim operation is performed. 1.3: Based on VPC sorting, select the N blocks with the least amount of valid data (N is the configured number of blocks), and mark the selected blocks as GC candidate blocks; 1.4: After the GC candidate block selection is completed, the Buffer management table is requested in batches to allocate SRAM buffer space for GCread operations. The effective data is read out through the NAND controller, and the Buffer management table records the buffer allocation information. 1.5: After detecting a successful read of Nand data, the backup DMA inside the cache control module automatically backs up the read data to the GC read backup area of the DRAM. After the operation is completed, the buffer management table automatically releases the SRAM buffer resources. 1.6: Before writing GC data to the NAND controller, the cache control module uses TAPU (Address Table Lookup Coprocessor Unit) to perform address consistency checks; 1.7: TAPU compares the GCread backup data with the latest L2P table mapping, checks whether the HOSTwrite operation has modified the backed-up data, and checks whether the trim operation has invalidated the backed-up data. If any modification or invalidation is found, the data is marked as invalid. That is, if the host writes new data to an already backed-up address during GCread backup, the corresponding GCread backup data is marked as invalid; similarly, if data within the address range cleared by the trim command has already been backed up to the GCread backup area, the backup data needs to be marked as invalid. Data marked as invalid undergoes invalidation processing, meaning that subsequent GC writes will automatically skip these data and no longer perform GC writes. The TAPU processing result is returned, the cache control module updates the buffer management table, and releases the invalid GC data in the GC read backup area. Non-invalid data undergoes normal GC write processing.
[0029] The trim operation refers to the host informing the storage which data blocks can be erased. When the host sends this command, it tells the SSD to clear the range of invalid L2P mapping tables and delete the data at the corresponding addresses. For GC mentioned in the article, the trim command clears data within the address range without performing GC operations.
[0030] 2. Automatic backup and accelerated retrieval of word line data in host programming, the process is as follows: Figure 3 As shown, it includes: 2.1: Writing data to the host interface; 2.2: The backup DMA inside the cache control module will automatically back up the written data to the word line programming backup area of the DRAM when it detects that a word line data is sent to the Nand controller; 2.3: While writing word line data, the cache control module updates the Buffer management table information to point to the backup area; 2.4: During word line programming, if the host needs to read data from the word line, the cache control module directly obtains the backup data from the backup area through the pointer in the Buffer management table and reads it back to the host, thereby speeding up the host's read command processing.
[0031] 3. Automatic backup processing of secondary programming data, the process is as follows: Figure 4 As shown, it includes: 3.1: Writing data to the host interface; 3.2: When the backup DMA inside the cache control module detects a word line data being sent to the NAND controller, it determines whether the word line data needs to be backed up to the secondary programming backup area based on the firmware configuration flags. The existing SSD chips considered include those supporting QLC (Quick Cell) architecture, which requires two programming operations for the same page. Data already programmed in the first stage needs to be retained and released only after the second programming is complete. Because QLC architecture coexists with TLC and SLC architectures that do not require secondary programming in SSD chips, only a portion of the data needs to be backed up using secondary programming.
[0032] 3.3: Backup DMA automatically backs up SRAM data that requires reprogramming to the reprogramming backup area; 3.4: After the NAND controller completes its first programming, it obtains the backed-up secondary programming data through the cache control module and performs secondary programming.
[0033] The technical solutions described in the embodiments of this application above have at least the following technical effects or advantages: 1. This invention solves the problem of low efficiency caused by frequent CPU interactions during GC data processing, realizes automatic backup processing of host programming word line data and secondary programming data, speeds up command processing, and solves the problem of slow data reading during data writing, which can accelerate the reading of data being written; effectively reduces CPU load, speeds up host read and write command processing speed, thereby reducing internal bandwidth usage and thus reducing SSD control power consumption.
[0034] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. An SSD cache control device supporting processing acceleration, characterized in that, include: The system includes a host interface, a cache control module, a Nand controller, a CPU, DRAM, and SRAM. The cache control module has a built-in logical address cache, a buffer management table, a TAPU, and a backup DMA. The DRAM is divided into independent secondary programming backup areas, word line programming backup areas, and GC read backup areas. The SRAM is divided into a host data cache area and a GC read working area. The cache control module independently implements at least one of the following processing accelerations: automatic read backup and write processing of GC data, automatic backup and read acceleration processing of host write word line data, and automatic backup processing of secondary programming data.
2. The SSD cache control device according to claim 1, characterized in that: The automatic read, backup, and write processing of GC data includes the following related steps: The CPU configures the cache control module with the number N of blocks that need to be GC; The TAPU scans the effective data count (VPC) of all candidate blocks and selects the N blocks with the least effective data based on the VPC sorting, marking them as GC candidate blocks. The cache control module requests SRAM buffer space from the Buffer management table in batches, reads the valid data of the GC candidate block through the Nand controller, and the backup DMA automatically backs up the data to the GC read backup area of the DRAM. After completion, the SRAM buffer resources are released. Before writing to the Nand controller, the TAPU compares the GC read backup area data with the L2P table mapping, checks whether the HOST write has modified the backed-up data, and whether the trim operation has invalidated the backed-up data. If it has been modified or invalidated, it is marked as invalid data; otherwise, the GC write process is performed normally.
3. The SSD cache control device according to claim 1, characterized in that: The automatic backup and accelerated reading process for the host-written word line data includes: When the cache control module detects that a word line data is sent to the Nand controller, the backup DMA automatically backs up the word line data to the word line programming backup area of the DRAM and updates the buffer management table to point to the backup area. During word line programming, if the host initiates a command to read the word line data, the cache control module directly retrieves the data from the backup area through the Buffer management table and returns it to the host.
4. The SSD cache control device according to claim 1, characterized in that: The automatic backup process for the secondary programming data includes: When the cache control module detects that a word line data is sent to the Nand controller, it determines whether the word line data needs to be reprogrammed based on the firmware flag configured by the CPU; if so, the backup DMA automatically backs up the data to the secondary programming backup area of the DRAM. After the Nand controller completes its first programming, it retrieves data from the secondary programming backup area through the cache control module for a second programming.
5. The SSD cache control device according to claim 1, characterized in that: The cache management process of the cache control module includes: The logical addresses of host read and write commands are stored in the logical address cache, which corresponds one-to-one with the data segment addresses of the host data cache. For read commands, if the logical address cache contains the same logical address, the data is read directly from the host data cache. For write commands, if the logical address cache contains the same logical address, the old data in the host data cache is replaced, and invalid data in other backup areas is automatically updated. The buffer management table records the status of each buffer, and the buffer control module determines the data transmission direction accordingly.
6. The SSD cache control device according to claim 1, characterized in that: The physical addresses of the secondary programming backup area, word line programming backup area, and GC read backup area of the DRAM are isolated from each other; the host data cache area and GC read work area of the SLAM are independently scheduled through the Buffer management table.