Simulation system and method
By introducing a concurrent timing arbitration module and a deep feature response generation unit, the problem of low simulation accuracy in embedded systems is solved, achieving high-fidelity reproduction of hardware behavior and improving the coverage and accuracy of simulation tests.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHUODAO MEDICAL TECH (ZHEJIANG) CO LTD
- Filing Date
- 2026-04-14
- Publication Date
- 2026-05-19
AI Technical Summary
In the agile development process of embedded systems, existing simulation methods cannot effectively handle resource contention conflicts caused by high-frequency calls of multiple processes, and the simulation interface cannot reflect the nonlinear physical characteristics of hardware under continuous workload caused by heat accumulation or power fluctuations, resulting in insufficient test coverage and difficulty in exposing deep-seated logical defects.
By introducing a concurrent timing arbitration module and a deep feature response generation unit, and by encapsulating function libraries and simulation hardware systems, conflict-free scheduling of external instructions and nonlinear physical feedback are achieved. Artificial neural network modeling is combined to improve simulation accuracy.
It improves the accuracy of software development simulation, can more accurately reflect hardware behavior, expose potential timing-related logic defects, and enhances the coverage and fidelity of simulation tests.
Smart Images
Figure CN122064339A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of software development, and more specifically, to a simulation system and method. Background Technology
[0002] In the agile development process of embedded systems, software functions are often highly coupled in terms of timing and logic with specific peripheral hardware.
[0003] Traditional development models heavily rely on the readiness of physical hardware, causing software development cycles to be constrained by the production and delivery schedules of the hardware. Although some instruction set-based simulation methods exist in existing technologies, they are usually configured as simple static feedback mechanisms, unable to handle resource contention conflicts caused by high-frequency calls from multiple processes. Furthermore, the fixed values returned by their simulation interfaces cannot reflect the nonlinear physical characteristics of the hardware under continuous workloads caused by heat accumulation or power consumption fluctuations. This results in insufficient test coverage in the simulation environment, making it difficult to expose deep-seated timing-related logical defects. Summary of the Invention
[0004] This invention provides a simulation system and method to at least solve the problem of low simulation accuracy in software development under high concurrency loads in related technologies.
[0005] According to one embodiment of the present invention, a simulation system is provided, comprising: The encapsulated function library includes a function set and a concurrent timing arbitration module, wherein the function set includes several function interfaces; The simulation hardware system includes simulation hardware and a deep feature response generation unit, wherein the deep feature response generation unit is used to generate response data based on a conflict-free scheduling sequence; Upon receiving an external instruction, the simulation hardware is instructed to provide a simulation function interface to execute the external instruction via a function set; the concurrent timing arbitration module generates a conflict-free scheduling sequence based on the concurrent external instructions.
[0006] In one exemplary embodiment, it further includes: A hardware system, including hardware and a driver program for driving the identification of said hardware; Upon receiving external instructions, the driver is instructed via a function set to drive the hardware to provide a function interface to execute the external instructions.
[0007] In one exemplary embodiment, it further includes: A simulation driver is used to drive the simulated hardware to perform actions upon receiving instructions from the function set.
[0008] In one exemplary embodiment, it further includes: The visual end is used to display the execution process of external commands when they are received.
[0009] In an exemplary embodiment, the concurrent timing arbitration module generates a conflict-free scheduling sequence according to the external instruction, including: Obtain the arrival timestamps and standard execution cycles of concurrent external instructions, and calculate the estimated time overlap length between instructions; The conflict degree coefficient is determined based on the ratio of the estimated time overlap length to the standard execution cycle. If the conflict degree coefficient exceeds a preset threshold, an additional backoff delay is added to the conflict command, and the backoff delay includes a protection interval.
[0010] In one exemplary embodiment, generating response data based on the conflict-free scheduling sequence includes: Perform historical sequence accumulation to obtain the macroscopic state tensor; Deep spatial encoding is performed on the macroscopic state tensor, and global temporal dependency analysis is performed to obtain the prediction vector.
[0011] According to another embodiment of the present invention, a simulation method is provided, comprising: Obtain external commands; Based on external commands, send interface call commands to the function set and concurrent timing arbitration module; The function set is based on interface call instructions, which instruct the simulated hardware to provide simulated function interfaces to execute the external instructions. The concurrent timing arbitration module generates a conflict-free scheduling sequence based on the concurrent external instructions.
[0012] In one exemplary embodiment, after sending the interface call instruction to the function set based on external instructions, the method further includes: The function set is based on interface call instructions, which instruct the hardware to provide function interfaces to execute the external instructions.
[0013] In one exemplary embodiment, after sending an interface call instruction to the function set, the method further includes: Get configuration information; The control object is determined based on the configuration information, and the control object can be either hardware or simulated hardware.
[0014] In one exemplary embodiment, the method further includes: Upon receiving the instruction of the function set, the simulated hardware is driven to perform actions via a simulation driver.
[0015] According to yet another embodiment of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.
[0016] According to yet another embodiment of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.
[0017] This invention achieves high-fidelity reproduction of hardware behavior by introducing a timing arbitration mechanism at the function library layer and combining it with nonlinear response prediction logic at the hardware simulation layer. Therefore, it can solve the problem of low simulation accuracy in software development and improve simulation accuracy. Attached Figure Description
[0018] Figure 1 This is a structural block diagram of a simulation system according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the principle according to a specific embodiment of the present invention. Figure 1 ; Figure 3 This is a schematic diagram of the principle according to a specific embodiment of the present invention. Figure 2 ; Figure 4 This is a schematic diagram of the principle according to a specific embodiment of the present invention. Figure 3 ; Figure 5 This is a schematic diagram of the principle according to a specific embodiment of the present invention. Figure 4 . Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0020] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0021] Furthermore, in this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and may change accordingly depending on the orientation of the components in the accompanying drawings.
[0022] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled" can refer to an electrical connection that enables signal transmission.
[0023] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).
[0024] This embodiment also provides an apparatus for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.
[0025] Example 1 Figure 1 This is a structural block diagram of a simulation system according to an embodiment of the present invention, such as... Figure 1 As shown, the system includes: The encapsulated function library 11 is programmed as a middleware logic layer, suitable for abstracting the underlying hardware register operations into a standardized function set through a function set parsing engine; The simulation hardware system 12 includes simulation hardware and simulation driver. The simulation driver is used to drive the simulation hardware to perform actions when it receives the instruction of the function set. Specifically, the simulation driver simulates the instruction response behavior of the target physical hardware through memory address mapping technology. A communication link based on a high-speed data bus is established between the encapsulation function library 11 and the analog hardware system 12. In response to concurrent or single external instructions originating from the application layer, the encapsulation function library 11, through its internal function set parsing engine, instructs the analog hardware system 12 to dynamically allocate corresponding analog function interfaces, thereby enabling the logical execution and result feedback of external instructions even when the physical hardware is not ready.
[0026] In this embodiment, an intermediate layer (i.e., a simulated hardware system) is added between the software and the peripheral hardware / hardware driver to decouple the software from the peripheral hardware / hardware driver. When the peripheral hardware is not present, the hardware is simulated internally by the intermediate layer program, thus eliminating the software's dependence on the peripheral hardware / hardware driver. At the same time, the intermediate layer program still retains the ability to use the peripheral hardware / hardware driver.
[0027] like Figure 2 As shown, typically, installing the corresponding driver for peripheral hardware ensures that the peripheral can be recognized by the operating system and function properly. Software communicates with hardware peripherals precisely through these drivers. However, drivers are highly dependent on hardware; without the hardware, this working mode fails. Therefore, as... Figure 3 As shown, we added a simulated hardware system, which includes software and drivers for simulating the hardware, while retaining the hardware system, which includes hardware and drivers for identifying the hardware. Upon receiving external instructions, the driver is instructed via a function set to drive the hardware to provide a functional interface to execute the external instructions.
[0028] To unify the two working modes mentioned above, such as Figures 4-5 As shown, we abstract a set of functions from the hardware driver. Through this set of functions and in combination with the hardware, we realize hardware simulation. The simulated hardware will simulate the return value after receiving external instructions and send it to the device that provided the external instructions.
[0029] It's important to note that hardware emulation includes simulating the original machine's CPU, input device mapping, memory, I / O devices, and even some devices like a mouse and keyboard. Driver emulation, on the other hand, involves simulating the behavior of hardware devices at the system kernel level. A driver can manipulate I / O ports within the kernel, sending instructions to the integrated circuit connected to the keyboard to generate a key press notification. In this way, the simulated input appears to all programs as if it were originating from a real device. This approach can bypass many protection mechanisms, enabling deeper levels of emulation.
[0030] In an optional embodiment, it further includes: The visual end is used to display the execution process of external commands when they are received.
[0031] In this embodiment, the UI interface simulates the effects of some visual peripherals. For example, the RGB and Hall sensors are simulated, so that the working process of the simulated hardware can be viewed intuitively, and the working status can be fed back in a timely manner.
[0032] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.
[0033] To achieve the above-mentioned decoupling simulation process, the present invention provides a simulation method, which is implemented by running the following data-driven logic steps in a processor: S100, the data access interface of the encapsulated function library 11 captures external commands and performs protocol consistency verification.
[0034] In response to receiving an external command trigger signal, the data access interface acquires the raw command bit stream through the DMA (Direct Memory Access) channel. During this process, the internal verification unit of the interface performs a cyclic redundancy check (CRC) on the command payload to filter out random noise interference generated by the transmission link.
[0035] For example, external commands can be JSON-formatted Remote Procedure Call (RPC) packets transmitted via a network service interface. For external commands that read temperature sensors, the access interface extracts the command code 0x01 and sampling channel parameter 0x05 defined in its byte stream and stores them in a preset input circular buffer to achieve smooth buffering of burst command streams.
[0036] S200, the parsing engine of the function set inside the encapsulation function library 11 parses the semantics of external instructions and maps them to specific interface call sequences.
[0037] In response to a data-ready interrupt in the input circular buffer, the parsing engine uses a built-in hash map to associate the command code of an external instruction with a specific functional unit in the function set.
[0038] For example, for a temperature readout instruction, the parsing engine determines that the instruction corresponds to an ADC sampling simulation unit. Based on this, the system generates a sequence of sub-instructions containing configuration of the analog register address, setting of sampling precision, and initialization of the interrupt vector table. During this process, the parameter validity checker performs boundary constraint checks on the sampling channel parameters. If parameter 0x05 is detected to be outside the physically supported range, the parsing engine is configured to immediately trigger an error feedback interrupt and output the error code ERR_INVALID_CH, thereby ensuring the physical validity of the simulation instruction.
[0039] S300, the analog hardware system 12 responds to the instructions of the function set by dynamically providing an analog function interface through a memory paging management mechanism.
[0040] After receiving the interface call instruction sequence, the simulated hardware system 12 allocates a contiguous address region in the simulated memory space through its internal virtual MMU to simulate the register set of the target hardware.
[0041] For example, for ADC sampling simulation, the simulation hardware system 12 establishes a virtual register group including a data register (DR), a status register (SR), and a configuration register (CR) in the address range 0x40012400-0x400124FF. After setting the start bit of the configuration register, the simulation hardware system 12 loads a preset hardware behavior model to achieve a millisecond-level simulation response to the logical behavior of the target hardware registers.
[0042] The S400 system is also equipped with an API redirection unit, which enables transparent switching between physical hardware and analog hardware by introducing a control object switching mechanism based on configuration information.
[0043] Specifically, during the system initialization phase, the encapsulated function library 11 reads the configuration file stored in non-volatile storage. If the configuration file defines "[Simulated Hardware: Yes]", the API redirection unit routes the function set's call instruction stream to the simulated hardware system 12. Conversely, if the configuration file specifies that the controlled object is physical hardware, the API redirection unit switches the underlying hardware driver mode, directly driving the physical peripherals through the hardware abstraction layer. Because this redirection mechanism is located within the function library, the application layer software can seamlessly switch between "simulated development" and "real-world debugging" modes.
[0044] The S500, an embedded arbitration unit, performs quality assessment and status monitoring on the output of the analog hardware system 12.
[0045] The system includes a state evaluation algorithm, which is based on the communication result C, the configuration parameter matrix P, and the feedback value R, and uses the formula... Calculate the interface status value S.
[0046] For example, the evaluation unit performs statistical analysis on the feedback value R, if The variance fluctuation exceeds the threshold If so, the simulated interface is determined to be in a metastable state. Further, the evaluation algorithm is as follows: In the formula, b is the adjustment base, and w is the corresponding weight. It should be noted that this formula is only a simulation result under a specific environment; in different environments, the results may vary. It can be adjusted according to actual needs, thereby realizing autonomous monitoring of the operating quality of the simulated environment and automatic reset of anomalies.
[0047] Specifically, the weighting benchmark can be determined through the following steps: S521, System-based device type identifier for analog hardware The initial weights are retrieved from the preset weight sensitivity matrix.
[0048] Specifically, the weighting logic includes: for devices with extremely high real-time communication requirements (such as interrupt-triggered sensors), the system increases the weight of the communication result. The initial proportion; for high-precision analog output devices (such as 16-bit ADCs), the system increases the feedback numerical weight. The initial percentage.
[0049] The weight sensitivity matrix can be constructed based on the following physical property indices: Characteristic time constant This metric characterizes how quickly the hardware responds to external stimuli, measured in milliseconds. Small... Values (such as photodiodes, This indicates that the hardware state changes rapidly, and its feedback value... Real-time performance is crucial. Large A value indicates that its state changes slowly and has inertia, such as a temperature sensor with a large heat capacity. value .
[0050] Inherent signal-to-noise ratio This metric represents the relative strength of the effective signal and noise components in the hardware output signal, measured in decibels (dB). High... Values (such as high precision) ) represents its feedback value High credibility; low credibility Values (such as those of an unshielded Hall sensor) This indicates the feedback value. Contains significant random noise For example, for a high-precision pressure sensor simulation task, the system will Initial assignment is , for , for Here, the non-equilibrium initial allocation mechanism ensures that the evaluation algorithm can prioritize monitoring the technical dimensions that contribute the most to the simulation fidelity.
[0051] It should be noted that the following constraints need to be applied when determining the initial weights: Communication weight The baseline setting: Successful communication is the foundation for all subsequent operations; therefore... The range is usually set within [0.4, 0.6] to ensure the stability of the communication link.
[0052] Feedback numerical weights Dynamic calculation: The assigned value is directly linked to the physical characteristics of the hardware, and its assignment is usually related to... Proportional to, with Inversely proportional. That is, the more reliable the signal and the faster the response, the higher the weight of its feedback value in the overall evaluation.
[0053] Configuration parameter weights Balance allocation: The weights used to monitor the rationality of the configuration are determined by normalization constraints: .
[0054] The S522 system, through an adaptive weight adjustment loop, can dynamically correct for real-time deviations during the simulation process. The function mapping relationship.
[0055] When the system detects the feedback value The instantaneous jump rate exceeds the preset differential threshold. When noise interference or logic drift is detected in the current simulation environment, the system executes a "weight reduction-gain" conversion logic. Specifically, the system automatically reduces the weighting of the fluctuating signal. And increase the communication weight by the same amount. The detection intensity is used to verify whether the jump originates from instability of the physical layer communication link.
[0056] For example, if Unexpected results A step change will cause the system to... from Dynamically downgraded to At the same time from Upgraded to Adjusted Able to strengthen against The detection of (communication stability) is used to determine whether the error originates from an analog driver logic error or data link packet loss.
[0057] S523, in the evaluation score Falling below the preset reset safety threshold In the event of an error, the system will automatically trigger an automatic reset sequence.
[0058] This section transforms "autonomous monitoring" into "closed-loop intervention," that is, when... Below (For example When this occurs, the monitoring module of the encapsulated function library 11 sends a hard reset command directly to the simulated hardware system 12 without external manual intervention. .
[0059] For example, in analog sensors due to parameter configuration conflicts (i.e. Vector magnitude anomaly caused Down to In this scenario, the monitoring module detects an abnormal score and immediately triggers a reset sequence: first, it suspends all current interface call threads; then it sends a message to the simulated memory address space. The fill signal is used to clear the virtual register cache; finally, the initialized behavior model is reloaded based on the aforementioned configuration information.
[0060] Based on the above The function-driven dynamic evolution reset mechanism enables the system to eliminate metastability of the analog logic in a short time, thereby ensuring the continuous availability of the analog environment under long-term high-load operation.
[0061] The S600 system uses a visual interface to achieve real-time mapping of instruction execution trajectory and hardware state changes.
[0062] The visual module, as an independently running UI rendering entity, synchronizes data with the analog hardware system 12 through an inter-process communication mechanism. In response to changes in the values of the analog registers, the visual module dynamically refreshes the corresponding virtual instruments or waveforms on the screen.
[0063] For example, in response to RGB light control commands, the visual module receives PWM duty cycle parameters generated by the analog hardware system and maps them to the color brightness changes of virtual indicator lights on the screen, thereby providing developers with an intuitive verification environment.
[0064] Example 2 The difference from Embodiment 1 is that, in order to provide functional support for the aforementioned analog hardware system under high-load concurrent scenarios, the encapsulated function library 11 resolves instruction conflicts through an embedded concurrent timing arbitration module, while the analog hardware system 12 implements nonlinear physical feedback through a deep feature response generation unit.
[0065] Specifically, after receiving concurrent external instructions from different software processes, the encapsulation function library 11 does not directly pass them through to the simulation hardware. Instead, it first simulates the system's trigger concurrency timing arbitration module. This module, acting as the input front-end of the simulation hardware system 12, is responsible for de-conflicting the timing of the instruction stream. Simultaneously, in this embodiment, a deep feature response generation unit is used to enable the simulation hardware to provide a simulation function interface for executing external instructions. This module is embedded in the simulation hardware system and uses artificial neural networks to model the physical characteristics of the hardware. This allows the simulation function interface to return dynamic feedback data with temporal continuity and physical realism, rather than simple static values. Specifically, this includes the following steps: Step S700: The encapsulation function library 11 receives concurrent external instruction streams to generate a multidimensional instruction feature tensor, specifically: The S710, with its encapsulated function library 11, features an asynchronous data access interface. This interface intercepts instruction bus interrupt signals to capture concurrent calls from different software processes in real time. It also polls the kernel interrupt vector table to capture instruction packets from these processes. The parsing unit within the interface then performs a bitmasking operation on the binary header of each instruction packet based on the captured instruction interrupt signals, extracting three core raw parameters: the global arrival timestamp stored in the instruction timestamp register, and the global arrival timestamp. (in microseconds), unique identifier for instruction type and the load size defined in the command payload segment (in bytes). Specifically, to quantize and capture concurrent states, the system maintains a configurable sampling time window. The window length here is This is to support subsequent conflict determination.
[0066] While capturing instructions, the system synchronously calls a hardware specification mapping table stored in non-volatile memory via bus address mapping. This mapping table is structured as a hash lookup table. The key stores the standard execution cycle corresponding to different instruction types. .
[0067] For example, within a sampling window, the system detects the arrival of 10 concurrent commands; wherein, the global arrival timestamp associated with the first command... Parsed as Its instruction type identifier was confirmed as "register data read" after looking up the table, and its standard execution cycle was obtained from the mapping table. for The global arrival timestamp of the second instruction. for Its type identifier is identified as "Flash parameter write", and its standard execution cycle is then retrieved from the table. for And so on.
[0068] The S711, with its integrated dedicated preprocessing unit and concurrent timing arbitration module, performs normalization mapping on the raw parameters extracted by the S710 to eliminate dimensional differences and adapt to the input requirements of subsequent algorithms. Specifically, for the timestamp parameter, the preprocessing unit uses a linear normalization formula based on the starting point of the sampling time window to calculate the normalized time offset. : in, The formula converts the absolute time point into a timestamp at the start of the current sampling time window. The relative temporal position within the interval.
[0069] For example, if the current sampling time window The duration is Its starting time for Regarding the aforementioned first instruction... The calculation process for its normalized time offset is as follows: This value encodes the physical arrival time of the instruction within the window into a mathematical expression of its relative temporal position, thus providing an unbiased data foundation for subsequent temporal dependency analysis.
[0070] S712, the concurrent timing arbitration module, maps discrete instruction events to a structured tensor space based on the normalized parameters generated by S711. In this step, for events identified within a sampling time window... A concurrent instruction, a concurrent timing arbitration module dynamically allocates memory blocks and constructs them into a shape of... The initial instruction feature tensor, whose second dimension (feature dimension) consists of three elements, is filled sequentially with: normalized time offset. Instruction type encoding after one-hot encoding and the load size after standardization by maximum and minimum values. .
[0071] For example, in a sampling window containing 5 concurrent instructions, the system will generate a shape of A three-dimensional tensor. The eigenvector corresponding to the first instruction is calculated and filled with... This tensor, as an atomic data unit, encapsulates the spatiotemporal characteristics of all concurrent events within the sampling period and is pushed as input to the computational unit that subsequently performs timing conflict arbitration.
[0072] Step S800: The concurrent timing arbitration module performs concurrent timing conflict arbitration based on the multi-dimensional instruction feature tensor to generate a conflict-free scheduling sequence; specifically: S810, the conflict determination unit of the concurrent timing arbitration module iteratively calculates the conflict degree coefficient based on the overlap of the physical execution intervals between instructions. In this step, for any two instructions in the instruction buffer... and The conflict determination unit first calculates the estimated time overlap length. The overlap length is calculated using the following logical formula for determining interval intersection: in, and These are the absolute arrival timestamps of the instructions. and These represent their respective standard execution cycles. The physical meaning of this formula is to calculate the length of the intersection of two time intervals; if there is no intersection, the result is zero.
[0073] For example, using the aforementioned first instruction With the second instruction For example, the estimated execution interval of the first instruction is... The estimated execution interval for the second instruction is Based on the above formula, the calculation performed by the unit is as follows: .
[0074] After obtaining the overlap length, the conflict determination unit further calls an instruction compatibility evaluation formula to calculate the conflict degree coefficient. : in, The preset value is extracted from the mutual exclusion weight matrix that represents the mutual exclusion relationship between resources of different instruction types. Here, the value is taken as an example. .
[0075] S820, the scheduling unit within the concurrent timing arbitration module, performs backoff scheduling based on the conflict degree coefficient calculated by S810. The scheduling unit internally has a hard conflict threshold. Here it is set to an example. Due to the conflict coefficient calculated above. If the value exceeds the threshold, the scheduling unit determines that there is an intolerable resource contention for this pair of instructions and timing adjustments must be performed.
[0076] To resolve this conflict, the scheduling unit adds a backoff delay to the second instruction with lower priority. The calculation logic for this delay is configured as follows: ,in As a protective interval to prevent adjacent collisions caused by clock synchronization errors, it is exemplarily set here. Based on this logic, the calculation performed is as follows: .
[0077] After this adjustment, the scheduled start timestamp for the second instruction was forcibly modified to... Through iterative processing of such conflict pairs, the module ultimately outputs a conflict-free scheduling sequence in which all instructions are completely isolated in the time domain.
[0078] S830, the system's time series tensor reconstruction module connects the encapsulation function library 11 and the analog hardware system 12 to solve the problem of mismatch in the dimension and structure of the input data.
[0079] The internal hardware of the time-series tensor reconstruction module consists of a rolling history buffer containing 16 independent FIFO (First-In-First-Out) queues, each logically corresponding to an independent simulation process channel. For each channel, the time-series tensor reconstruction module accumulates and stores the conflict-free instruction characteristics scheduled for execution within the past 32 time steps. This is achieved by reconstructing the discrete data generated within a single sampling window... Tensors are allocated to corresponding FIFO queues based on their source process IDs and concatenated along the time dimension. The module ultimately constructs and outputs a shape of... The macroscopic state tensor.
[0080] For example, the first dimension (size 16) of the macroscopic state tensor corresponds to the parallel state of 16 concurrent processing channels, the second dimension (size 32) corresponds to the time-series trajectory composed of the 32 most recent historical instructions of each channel, and the third dimension (size 3) corresponds to the three core normalized features of each instruction.
[0081] In step S900, after receiving the macroscopic state tensor output by S830, the deep feature response generation unit of the simulation hardware system 12 generates dynamic response features for the current state by executing an artificial neural network model. This model contains a multi-layer heterogeneous network structure, specifically: S910, the first layer of this neural network model, is the sequential feature extraction module, which processes the input... Macroscopic state tensors perform deep spatial encoding based on one-dimensional convolution.
[0082] Within this module, a one-dimensional convolutional layer (Conv1D) with 64 filters is first deployed. The kernel size of this convolutional layer is hard-coded as follows: Step size set to The input tensor, in the time dimension, is slid-scanned by the convolution kernel. This operation is physically equivalent to weighted aggregation of instruction features from three adjacent time steps.
[0083] For example, for a shape of The input is processed by convolution, which aggregates weights across three feature dimensions and expands the channel depth from 3 to 64. After this convolution, the output feature map tensor changes shape. In this process, the convolutional layer effectively extracts the nonlinear coupling relationships between different features within a single instruction (e.g., high load and long latency), as well as the short-range temporal patterns between adjacent instructions. Following the convolutional layer is a batch normalization layer and a LeakyReLU activation function to enhance the model's ability to nonlinearly represent complex physical fluctuations (such as power supply noise spikes).
[0084] S920, the second layer of the model, namely the sequence response mapping module, performs global temporal dependency analysis on the intermediate state feature tensor output by S910. The core component of this module is a multi-head self-attention sublayer.
[0085] In the specific implementation, the number of headers in this sub-layer Forced to be set to 8, this sublayer receives The intermediate state tensor is mapped to a query matrix, a key matrix, and a value matrix through three independent fully connected layers. By performing scaled dot product attention computation in parallel across eight heads, this layer is able to identify which critical, non-adjacent instruction events contribute most to the overall hardware state at the current moment (e.g., the heat accumulation effect caused by prolonged high-load operation) in a sequence of 32 historical time steps.
[0086] For example, by analyzing the attention scoring matrix, a very high correlation can be found between a high-load write command at time step 10 and a simulated temperature spike event at time step 30 (the attention weight coefficient is calculated as follows). After attention computation and residual connections, the output tensor still retains... The shape is different, but at this point, the feature vectors of each time step have already incorporated global temporal context information.
[0087] S930, the final stage of the model, is the regression unit, which performs the final numerical regression mapping on the output of the attention layer. This regression unit consists of two consecutive fully connected linear layers: the first linear layer, configured with 128 neurons, non-linearly maps the 64-dimensional fusion features to a 128-dimensional hidden representation space; the second linear layer linearly reduces this 128-dimensional vector to a 2-dimensional output, and these two dimensions directly correspond to specific physical quantities.
[0088] Ultimately, the module outputs a tensor with the following shape: The result matrix. Among them, the two elements of the result dimension uniquely determine the physical feedback of the simulation hardware at a specific time during a specific simulation process.
[0089] For example, the output feature vector of the first simulation process channel at the current time is calculated as follows: , where the numerical value This represents the instantaneous voltage fluctuation value of the simulated hardware core power supply pin; numerical value. This represents the instantaneous temperature feedback value of the simulated core area of the chip. These dynamic values are encapsulated in real time into the return values of the simulation function interface, thereby providing external software with extremely realistic and time-series continuous feedback data, effectively improving the fidelity of simulation testing.
[0090] In the S1000 system, the concurrent timing arbitration module periodically performs adaptive updates of model parameters based on error feedback to ensure scheduling accuracy during continuous operation.
[0091] After a complete simulated instruction cycle (e.g., every 1000 instructions processed), the monitoring unit within the system captures the actual hardware interface response latency by reading hardware performance counters. Subsequently, the error calculation unit determines the prediction error using the following formula. .
[0092] The concurrent timing arbitration module then calls an update algorithm based on the hyperbolic tangent function to update the resource mutual exclusion weights stored in the hardware specification mapping table. Perform online correction: For example, if the measured average error within one cycle is for Learning rate Set as Smoothing factor Set as The updated weight calculation process is as follows: The updated weight values will be written back to the hardware specification mapping table and will take effect in the S810 step of the next batch of instructions. Through this mechanism, the system implements a "self-calibrating bus arbitration" logic that can sense and adapt to changes in system load, effectively eliminating timing drift accumulated over long-term operation due to model simplification or environmental changes.
[0093] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.
[0094] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.
[0095] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.
[0096] Embodiments of the present invention also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.
[0097] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.
[0098] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.
[0099] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0100] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0101] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0102] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A simulation system, characterized in that, include: The encapsulated function library includes a function set and a concurrent timing arbitration module, wherein the function set includes several function interfaces; The simulation hardware system includes simulation hardware and a deep feature response generation unit, wherein the deep feature response generation unit is used to generate response data based on a conflict-free scheduling sequence; Upon receiving an external instruction, the simulation hardware is instructed to provide a simulation function interface to execute the external instruction via a function set; The concurrent timing arbitration module generates a conflict-free scheduling sequence based on concurrent external instructions.
2. The simulation system according to claim 1, characterized in that, Also includes: A hardware system, including hardware and a driver program for driving the identification of said hardware; Upon receiving external instructions, the driver is instructed via a function set to drive the hardware to provide a function interface to execute the external instructions.
3. The simulation system according to claim 1, characterized in that, Also includes: A simulation driver is used to drive the simulated hardware to perform actions upon receiving instructions from the function set.
4. The simulation system according to claim 3, characterized in that, Also includes: The visual end is used to display the execution process of external commands when they are received.
5. The simulation system according to claim 1, characterized in that, The concurrent timing arbitration module generates a conflict-free scheduling sequence based on the external instructions, including: Obtain the arrival timestamps and standard execution cycles of concurrent external instructions, and calculate the estimated time overlap length between instructions; The conflict degree coefficient is determined based on the ratio of the estimated time overlap length to the standard execution cycle. If the conflict degree coefficient exceeds a preset threshold, an additional backoff delay is added to the conflict command, and the backoff delay includes a protection interval.
6. The simulation system according to claim 1, characterized in that, Generating response data based on the conflict-free scheduling sequence includes: Perform historical sequence accumulation to obtain the macroscopic state tensor; Deep spatial encoding is performed on the macroscopic state tensor, and global temporal dependency analysis is performed to obtain the prediction vector.
7. A simulation method, characterized in that, include: Obtain external commands; Based on external commands, send interface call commands to the function set and concurrent timing arbitration module; The function set is based on interface call instructions, which instruct the simulated hardware to provide simulated function interfaces to execute the external instructions. The concurrent timing arbitration module generates a conflict-free scheduling sequence based on the concurrent external instructions.
8. The method according to claim 7, characterized in that, After sending the interface call instruction to the function set, the method further includes: The function set is based on interface call instructions, which instruct the hardware to provide function interfaces to execute the external instructions.
9. The method according to claim 7, characterized in that, After sending the interface call instruction to the function set based on external instructions, the method further includes: Get configuration information; The control object is determined based on the configuration information, and the control object can be either hardware or simulated hardware.
10. The method according to claim 7, characterized in that, The method further includes: Upon receiving the instruction of the function set, the simulated hardware is driven to perform actions via a simulation driver.