Memory hardware fault detection circuit
By designing a memory hardware fault detection circuit, and utilizing a microcontroller module and a signal judgment module to detect logic level states and compare voltages, the difficulty of detecting memory hardware anomalies in existing technologies is solved, and fast and accurate fault diagnosis is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN VITEM SEMICONDUCTOR CO LTD
- Filing Date
- 2026-01-22
- Publication Date
- 2026-05-19
AI Technical Summary
Existing technologies cannot quickly and intuitively determine whether memory hardware is malfunctioning during data storage and retrieval, and the detection methods are relatively cumbersome.
Design a memory hardware fault detection circuit, including a microcontroller module, a memory module, a port detection module, a signal judgment module, and a status judgment module. By detecting the logic level status and comparing the voltage, the circuit determines whether the high and low level status of the data signal and the number of branches in the read and write process are equal, thereby realizing fault display.
It achieves efficient, simple, and convenient memory hardware fault detection, and can quickly identify abnormal data read/write conditions, improving the accuracy and efficiency of detection.
Smart Images
Figure CN122064541A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory hardware technology, specifically a memory hardware fault detection circuit. Background Technology
[0002] Memory hardware is one of the important components of a computer. It is used to temporarily store data processed by the processor and exchanged with external memory such as hard drives. The memory controller is located inside the computer and is responsible for managing memory and data exchange between memory and the processor. To detect whether the memory hardware is properly processing and retrieving data during read and write operations, it is necessary to use relevant memory port detection devices to monitor the working status of the memory hardware. However, the detection methods are relatively cumbersome and cannot directly and quickly determine whether there are any abnormalities in the memory hardware during data storage and retrieval, so improvements are needed. Summary of the Invention
[0003] This invention provides a memory hardware fault detection circuit to solve the problems mentioned in the background art.
[0004] According to an embodiment of the present invention, a memory hardware fault detection circuit is provided, comprising: The microcontroller module, connected to the memory module, signal judgment module, and status judgment module, is used to provide a first data signal and transmit it to the memory module through three branches when a write signal is provided; to receive the second data signal transmitted by the memory module when a read signal is provided; to output a test signal when memory hardware testing is required; to perform voltage comparison based on the high-level status control signal of the three branches detected by the port detection module; and to receive the first fault signal output by the signal judgment module and the second fault signal output by the status judgment module. The memory module is used to store the first data signal when a write signal is received, and to extract the stored first data signal and output the second data signal when a read signal is received. The second data signal is then transmitted to the microcontroller module through three branches. The port detection module, connected to the microcontroller module and the memory module, is used to detect the logic level status of the three branches transmitting the first data signal or the second data signal when a test signal is received, and to perform voltage sampling processing on the branch that is in the high-level state when the logic level is high. The signal judgment module, connected to the port detection module, is used to sequentially compare the signal sampled by the port detection module with the set high voltage threshold and low voltage threshold, and to display the voltage fault and output the first fault signal when the sampled signal is greater than the high voltage threshold or less than the low voltage threshold. The status judgment module, connected to the port detection module, is used to detect the number of branches in the port detection module that are in a high-level state, and to detect whether the number of branches in the port detection module that are in a high-level state during the microcontroller's write process is equal to the number of branches in the port detection module that are in a high-level state during the microcontroller's read process. If they are not equal, a read / write fault is displayed and a second fault signal is output.
[0005] As a further embodiment of the present invention: the microcontroller module includes a first controller; the memory module includes memory hardware under test; and the port detection module includes a first analog switch. Preferably, the A0 terminal of the first controller is connected to the first data terminal of the memory hardware under test and the third terminal of the first analog switch; the A1 terminal of the first controller is connected to the second data terminal of the memory hardware under test and the eighth terminal of the first analog switch; the A2 terminal of the first controller is connected to the third data terminal of the memory hardware under test and the first terminal of the first analog switch; the IO1 terminal of the first controller is connected to the fifth, sixth and thirteenth terminals of the first analog switch; and the WE and OE terminals of the first controller are respectively connected to the write control terminal and the read control terminal of the memory hardware under test.
[0006] As a further embodiment of the present invention: the port detection module further includes a first capacitor, a first resistor, a second resistor, a first operational amplifier, a second operational amplifier, a third resistor, a fourth resistor, a first protection transistor, a first voltage regulator, a first switching transistor, and a fifth resistor; Preferably, the first terminal of the first capacitor is connected to the non-inverting terminal of the third operational amplifier and the ninth terminal of the first analog switch; the second terminal of the first capacitor is connected to the inverting terminal of the first operational amplifier and is connected to the output terminal of the first operational amplifier and the inverting terminal of the second operational amplifier through the first resistor; the non-inverting terminal of the first operational amplifier is connected to one end of the third resistor, one end of the first protection transistor, the first end of the fifth resistor, and ground through the second resistor; the non-inverting terminal of the second operational amplifier is connected to the other end of the third resistor; the output terminal of the second operational amplifier is connected to the other end of the first protection transistor and the base of the first switching transistor through the fourth resistor; the collector of the first switching transistor is connected to the first voltage regulator; and the emitter of the first switching transistor is connected to the other end of the fifth resistor.
[0007] As a further embodiment of the present invention: the port detection module further includes a third operational amplifier, a second analog switch, a first diode, a second diode, a sixth resistor, a fourth operational amplifier, and a second capacitor; Preferably, the non-inverting input of the third operational amplifier is connected to the first terminal of the first capacitor, the inverting input of the third operational amplifier is connected to the anode of the first diode and connected to the output terminal and the inverting input of the fourth operational amplifier through the sixth resistor, the non-inverting input of the fourth operational amplifier is connected to the cathode of the second diode and grounded through the second capacitor, the anode of the second diode is connected to the cathode of the first diode and the fourth terminal of the second analog switch, the output terminal of the third operational amplifier is connected to the third terminal of the second analog switch, and the fifth terminal of the second analog switch is connected to the base of the first switching transistor.
[0008] As a further embodiment of the present invention: the port detection module further includes a first detection device and a second detection device; Preferably, the input terminals of the first detection device and the second detection device are respectively connected to the second and fourth terminals of the first analog switch, and the grounding terminals of the first and second detection devices are both grounded.
[0009] As a further embodiment of the present invention: the signal determination module includes a third logic unit, a fourth logic unit, a fifth logic unit, a first comparator, a second comparator, a first reference power supply, a second reference power supply, and a first indicator light; Preferably, the third terminal of the third logic unit, the third terminal of the fourth logic unit, and the third terminal of the fifth logic unit are respectively connected to the first output terminal of the first detection device, the first output terminal of the second detection device, and the output terminal of the fourth operational amplifier. The fifth terminals of the third logic unit, the fifth terminals of the fourth logic unit, and the fifth terminal of the fifth logic unit are respectively connected to the IO4, IO2, and IO3 terminals of the first controller. The fourth terminal of the third logic unit is connected to the fourth terminal of the fourth logic unit, the fourth terminal of the fifth logic unit, the inverting terminal of the first comparator, and the non-inverting terminal of the second comparator. The non-inverting terminal of the first comparator and the inverting terminal of the second comparator are respectively connected to the first reference power supply and the second reference power supply. The output terminal of the first comparator is connected to the output terminal of the second comparator, the IO5 terminal of the first controller, and the anode of the first indicator light. The cathode of the first indicator light is grounded.
[0010] As a further embodiment of the present invention: the state determination module includes an in-phase adder, a sample-and-hold circuit, a first inverter, a second inverter, a sixth analog switch, a third comparator, a fourth comparator, and a second indicator light; Preferably, the first, second, and third input terminals of the in-phase adder are respectively connected to the second output terminal of the first detection device, the second output terminal of the second detection device, and the emitter of the first switching transistor. The output terminal of the in-phase adder is connected to the input terminal of the sample-and-hold circuit and the third terminal of the sixth analog switch. The output terminal of the sample-and-hold circuit is connected to the inverting terminal of the third comparator and the non-inverting terminal of the fourth comparator. The fourth terminal of the sixth logic unit is connected to the non-inverting terminal of the third comparator and the inverting terminal of the fourth comparator. The output terminals of the first and second inverters are respectively connected to the control terminal of the sample-and-hold circuit and the fifth terminal of the sixth logic unit. The input terminals of the first and second inverters are respectively connected to the WE and OE terminals of the first controller. The output terminal of the third comparator is connected to the output terminal of the fourth comparator, the IO9 terminal of the first controller, and the anode of the second indicator light. The cathode of the second indicator light is grounded.
[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: When the memory hardware fault detection circuit of the present invention is written by the microcontroller module, the memory module stores the data signal provided by the microcontroller module. During read control, the microcontroller module extracts the data signal stored in the memory module. The microcontroller module can also control the port detection module to perform voltage sampling processing on the data signal in the high-level state when the logic level of the transmitted data signal is high. The signal judgment module detects the relationship between the high-level data signal and the set high voltage threshold and low voltage threshold to determine whether there is a voltage abnormality in the data signal. The state judgment module detects whether the number of high-level data signals in the read and write states is equal, and then determines whether there is a data read / write abnormality. The detection method is efficient, simple and convenient. Attached Figure Description
[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figure 1 This is a schematic block diagram of a memory hardware fault detection circuit provided in an embodiment of the present invention.
[0014] Figure 2 This is a circuit diagram of a memory hardware fault detection circuit provided in an embodiment of the present invention.
[0015] Figure 3 The circuit diagram is provided for the signal judgment module in an embodiment of the present invention.
[0016] Figure 4 The circuit diagram is provided for the state determination module in the embodiment of the present invention. Detailed Implementation
[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0018] In one embodiment, see Figure 1 A memory hardware fault detection circuit, comprising: The microcontroller module 1 is connected to the memory module 2, the signal judgment module 4, and the status judgment module 5. When a write signal is provided, it provides a first data signal and transmits the first data signal to the memory module 2 through three branches. When a read signal is provided, it receives the second data signal transmitted by the memory module 2. When memory hardware testing is required, it outputs a test signal. Based on the high-level status control signal of the three branches detected by the port detection module 3, the judgment module 4 performs voltage comparison. It also receives the first fault signal output by the signal judgment module 4 and the second fault signal output by the status judgment module 5. Memory module 2 is used to store the first data signal when a write signal is received, and to extract the stored first data signal and output the second data signal when a read signal is received. The second data signal is then transmitted to microcontroller module 1 through three branches. The port detection module 3 is connected to the microcontroller module 1 and the memory module 2. When a test signal is received, it is used to detect the logic level status of the three branches transmitting the first data signal or the second data signal respectively, and to perform voltage sampling processing on the branch in the high-level state when the logic level is high. The signal judgment module 4 is connected to the port detection module 3. It is used to compare the signal sampled by the port detection module 3 with the set high voltage threshold and low voltage threshold in sequence. When the sampled signal is greater than the high voltage threshold or less than the low voltage threshold, it displays the voltage fault and outputs the first fault signal. The status judgment module 5 is connected to the port detection module 3. It is used to detect the number of branches in the port detection module 3 that are in a high-level state, and to detect whether the number of branches in the port detection module 3 that are in a high-level state when the microcontroller module 1 is writing is equal to the number of branches in the port detection module 3 that are in a high-level state when the microcontroller module 1 is reading. If they are not equal, a read / write fault is displayed and a second fault signal is output.
[0019] In a specific embodiment, the microcontroller module 1 can be a microcontroller circuit composed of an MCU, integrating many components such as an arithmetic logic unit (ALU), a controller, a memory, and input / output devices, to realize functions such as signal processing, data storage, module control, and timing control; the memory module 2 can be a memory circuit composed of memory hardware under test, capable of data interaction, data storage, and data retrieval with the microcontroller module 1; the port detection module 3 can be a port detection circuit composed of analog switches, operational amplifiers, capacitors, resistors, etc., capable of signal transmission control, detecting the logic level state of the transmitted data signal, that is, detecting whether the logic level of the data signal is high or low, and when the logic level is high, performing voltage sampling processing on the data signal transmitted in the high-level branch to detect the peak voltage of the data signal; the signal judgment module... 4. A signal judgment circuit composed of analog switches, comparators, and reference power supplies can be used. The microcontroller module 1 can detect the high-level state of the data signals transmitted by the three branches by the port detection module 3, and compare the signal sampled by the port detection module 3 with the set high voltage threshold and low voltage threshold in sequence. The high voltage threshold is the maximum voltage value of the data signal under normal conditions, and the low voltage threshold is the minimum voltage value of the data signal under normal conditions. The aforementioned state judgment module 5 can be a state judgment circuit composed of in-phase adders, sample-and-hold circuits, comparators, etc. It can perform addition processing on the input signal, sample-and-hold processing on the processed signal during write control, and sample-and-hold processing on the processed signal during read control. Then, it can detect whether the number of branches in the high-level state during write and read periods is equal. If they are not equal, it indicates that there is a read / write fault in the memory module 2.
[0020] In this embodiment, please refer to Figure 2 , Figure 3 and Figure 4 The microcontroller module 1 includes a first controller U1; the memory module 2 includes the memory hardware under test; and the port detection module 3 includes a first analog switch J1. Specifically, the A0 terminal of the first controller U1 is connected to the first data terminal of the memory hardware under test and the third terminal of the first analog switch J1; the A1 terminal of the first controller U1 is connected to the second data terminal of the memory hardware under test and the eighth terminal of the first analog switch J1; the A2 terminal of the first controller U1 is connected to the third data terminal of the memory hardware under test and the first terminal of the first analog switch J1; the IO1 terminal of the first controller U1 is connected to the fifth, sixth, and thirteenth terminals of the first analog switch J1; and the WE and OE terminals of the first controller U1 are connected to the write control terminal and read control terminal of the memory hardware under test, respectively.
[0021] In a specific embodiment, the first controller U1 can be an MCU chip; the first data terminal, second data terminal, and third data terminal of the memory hardware under test are respectively connected to the A0 terminal, A1 terminal, and A2 terminal of the first controller U1 through three branches. These three branches are data buses that transmit logic levels to complete data interaction with the first controller U1. The logic level can be a high level state, i.e., "1", or a low level state, i.e., "0". The write control terminal of the memory hardware under test receives the data signal to be stored, and the read control terminal of the memory hardware under test outputs the data signal to be read; the first analog switch J1 can be a CD4066 chip.
[0022] Furthermore, the port detection module 3 also includes a first capacitor C1, a first resistor R1, a second resistor R2, a first operational amplifier OP1, a second operational amplifier OP2, a third resistor R3, a fourth resistor R4, a first protection transistor VD1, a first voltage regulator VCC1, a first switching transistor V1, and a fifth resistor R5. Specifically, the first terminal of the first capacitor C1 is connected to the non-inverting terminal of the third operational amplifier OP3 and the ninth terminal of the first analog switch J1. The second terminal of the first capacitor C1 is connected to the inverting terminal of the first operational amplifier OP1 and is connected to the output terminal of the first operational amplifier OP1 and the inverting terminal of the second operational amplifier OP2 through the first resistor R1. The non-inverting terminal of the first operational amplifier OP1 is connected to one end of the third resistor R3, one end of the first protection transistor VD1, the first terminal of the fifth resistor R5, and ground through the second resistor R2. The non-inverting terminal of the second operational amplifier OP2 is connected to the other end of the third resistor R3. The output terminal of the second operational amplifier OP2 is connected to the other end of the first protection transistor VD1 and the base of the first switching transistor V1 through the fourth resistor R4. The collector of the first switching transistor V1 is connected to the first voltage regulator VCC1, and the emitter of the first switching transistor V1 is connected to the other end of the fifth resistor R5.
[0023] In a specific embodiment, the first operational amplifier OP1 and the second operational amplifier OP2 can both be selected as OP07 operational amplifiers. They are used in conjunction with the first capacitor C1, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the first protection transistor VD1 to detect the rising edge state of the input signal. The first protection transistor VD1 can be composed of two sets of diodes. The first switching transistor V1 can be selected as an NPN transistor.
[0024] Furthermore, the port detection module 3 also includes a third operational amplifier OP3, a second analog switch J2, a first diode D1, a second diode D2, a sixth resistor R6, a fourth operational amplifier OP4, and a second capacitor C2; Specifically, the non-inverting input of the third operational amplifier OP3 is connected to the first terminal of the first capacitor C1, the inverting input of the third operational amplifier OP3 is connected to the anode of the first diode D1 and connected to the output terminal and inverting input of the fourth operational amplifier OP4 through the sixth resistor R6, the non-inverting input of the fourth operational amplifier OP4 is connected to the cathode of the second diode D2 and grounded through the second capacitor C2, the anode of the second diode D2 is connected to the cathode of the first diode D1 and the fourth terminal of the second analog switch J2, the output terminal of the third operational amplifier OP3 is connected to the third terminal of the second analog switch J2, and the fifth terminal of the second analog switch J2 is connected to the base of the first switching transistor V1.
[0025] In a specific embodiment, both the third operational amplifier OP3 and the fourth operational amplifier OP4 can be selected as OP07 operational amplifiers, which, together with the second analog switch J2, the first diode D1, the second diode D2, the second capacitor C2 and the sixth resistor R6, perform voltage sampling and signal holding; the second analog switch J2 can be selected as a CD4066 chip.
[0026] Furthermore, the port detection module 3 also includes a first detection device and a second detection device; Specifically, the input terminals of the first detection device and the second detection device are respectively connected to the second and fourth terminals of the first analog switch J1, and the grounding terminals of the first and second detection devices are both grounded.
[0027] In a specific embodiment, the circuit structure of the first detection device and the circuit structure of the second detection device are the same as those of the first capacitor C1, the first resistor R1, the second resistor R2, the first operational amplifier OP1, the second operational amplifier OP2, the third resistor R3, the fourth resistor R4, the first protection tube VD1, the first voltage regulator VCC1, the first switching tube V1, the fifth resistor R5, the third operational amplifier OP3, the second analog switch J2, the first diode D1, the second diode D2, the sixth resistor R6, the fourth operational amplifier OP4, and the second capacitor C2. Therefore, when the second output terminal of the first detection device, the second output terminal of the second detection device, and the emitter of the first switching tube V1 are working, the output voltages are equal.
[0028] Furthermore, the signal judgment module 4 includes a third logic unit J3, a fourth logic unit J4, a fifth logic unit J5, a first comparator A1, a second comparator A2, a first reference power supply VF1, a second reference power supply VF2, and a first indicator LED1; Specifically, the third terminal of the third logic unit J3, the third terminal of the fourth logic unit J4, and the third terminal of the fifth logic unit J5 are respectively connected to the first output terminal of the first detection device, the first output terminal of the second detection device, and the output terminal of the fourth operational amplifier OP4. The fifth terminals of the third logic unit J3, the fourth logic unit J4, and the fifth logic unit J5 are respectively connected to the IO4, IO2, and IO3 terminals of the first controller U1. The fourth terminal of the third logic unit J3 is connected to the fourth terminal of the fourth logic unit J4, the fourth terminal of the fifth logic unit J5, the inverting terminal of the first comparator A1, and the non-inverting terminal of the second comparator A2. The non-inverting terminal of the first comparator A1 and the inverting terminal of the second comparator A2 are respectively connected to the first reference power supply VF1 and the second reference power supply VF2. The output terminal of the first comparator A1 is connected to the output terminal of the second comparator A2, the IO5 terminal of the first controller U1, and the anode of the first indicator LED1. The cathode of the first indicator LED1 is grounded.
[0029] In a specific embodiment, the third logic unit J3, the fourth logic unit J4 and the fifth logic unit J5 can all be CD4066 chips; the first comparator A1 and the second comparator A2 can both be LM358 comparators; the first reference power supply VF1 and the second reference power supply VF2 provide low voltage threshold and high voltage threshold respectively.
[0030] Furthermore, the state judgment module 5 includes an in-phase adder, a sample-and-hold circuit, a first inverter INV1, a second inverter INV2, a sixth analog switch J6, a third comparator A3, a fourth comparator A4, and a second indicator LED2. Specifically, the first, second, and third input terminals of the in-phase adder are connected to the second output terminal of the first detection device, the second output terminal of the second detection device, and the emitter of the first switching transistor V1, respectively. The output terminal of the in-phase adder is connected to the input terminal of the sample-and-hold circuit and the third terminal of the sixth analog switch J6. The output terminal of the sample-and-hold circuit is connected to the inverting terminal of the third comparator A3 and the non-inverting terminal of the fourth comparator A4. The fourth terminal of the sixth logic unit is connected to the non-inverting terminal of the third comparator A3 and the inverting terminal of the fourth comparator A4. The output terminals of the first inverter INV1 and the second inverter INV2 are connected to the control terminal of the sample-and-hold circuit and the fifth terminal of the sixth logic unit, respectively. The input terminals of the first inverter INV1 and the second inverter INV2 are connected to the WE and OE terminals of the first controller U1, respectively. The output terminal of the third comparator A3 is connected to the output terminal of the fourth comparator A4, the IO9 terminal of the first controller U1, and the anode of the second indicator LED2. The cathode of the second indicator LED2 is grounded.
[0031] In specific implementations, the above-mentioned in-phase adder can be composed of an operational amplifier and a resistor; the above-mentioned sample-and-hold circuit can be composed of an operational amplifier, a resistor, a capacitor, and an analog switch. When the control terminal of the sample-and-hold circuit is high, signal sampling is performed, and when the control terminal is low, signal holding is performed; the above-mentioned sixth analog switch J6 can be a CD4066 chip; the above-mentioned third comparator A3 and fourth comparator A4 can be LM358 comparators.
[0032] The working principle of a memory hardware fault detection circuit of the present invention is as follows: A write signal is output from the WE terminal of the first controller U1, causing the first, second, and third data terminals of the memory hardware under test to receive the first data signal transmitted through three branches from the A0, A1, and A2 terminals of the first controller U1. When the OE terminal of the first controller U1 outputs a read signal, the data signal stored in the memory hardware under test is retrieved. When memory hardware testing is required, the IO1 terminal of the first controller U1 outputs a test signal, the first analog switch J1 is turned on, the WE terminal of the first controller U1 outputs a write signal (low level), and the A0, A1, and A2 terminals output the first data signal. The first data signal transmitted through the three branches passes through the first analog switch J1. 1. Transmission: At this time, the signal output from terminal A1 is amplified and its rising edge is detected by the first capacitor C1, the first resistor R1, the first operational amplifier OP1, the second operational amplifier OP2, the second resistor R2, the third resistor R3, the fourth resistor R4, and the first protection transistor VD1. When the signal is high, the signal output from terminal A1 is "1". When the signal is high, the second operational amplifier OP2 triggers the second analog switch J2 to conduct. The third operational amplifier OP3, the first diode D1, the second diode D2, the sixth resistor R6, the fourth operational amplifier OP4, and the second capacitor C2 perform real-time signal sampling, thereby detecting the voltage peak value of the signal output from terminal A1, triggering the first switch V1 to conduct, and then providing a set of voltage signals to the third input terminal of the non-inverting adder. The controller U1 receives the signal at IO8. Similarly, the first and second detection devices detect the status of the output signals at terminals A2 and A0, respectively. When the output at terminal A2 is "1", the first output of the first detection device outputs the peak voltage of the output signal at terminal A2, and the second output of the first detection device provides a set of voltage signals, which are received by the controller U1 at IO6. The first output of the second detection device outputs the peak voltage of the output signal at terminal A0, and the second output of the second detection device provides a set of voltage signals, which are received by the controller U1 at IO7. At this time, the controller U1 can control terminals A0, A1, and A2 to output "011", that is, terminals A0, A1, and A2 provide low level, high level, and high voltage, respectively. When the voltage signal received from IO6 to IO8 is normal, the first controller U1 can sequentially compare the signal sampled by the port detection module 3 with the set high voltage threshold and low voltage threshold. Since A1 and A2 are at high levels, IO3 and IO4 of the first controller U1 sequentially control the fifth analog switch and the third analog switch to turn on. When the fifth analog switch is on, the voltage of the signal output from A1 can be detected by the first comparator A1, the second comparator A2, the first reference power supply VF1, and the second reference power supply VF2. If the voltage is greater than the high voltage threshold or lower than the low voltage threshold, it indicates that the signal voltage is abnormal. The first indicator LED1 is lit, and the first fault signal is received by the IO5 terminal of the first controller U1.Similarly, when the third analog switch is turned on, the voltage signal output from the second terminal of the second detection device and the voltage signal output from the emitter of the first switching transistor V1 are added by the in-phase adder. Since this is the addition of two sets of voltages, one set is considered as V1, which is 2V1. Because the storage function of the memory hardware under test can only be triggered by the WE terminal outputting a low level, the sample-and-hold circuit will sample 2V1 in real time. After the memory hardware under test has stored "011", the OE terminal of the first controller U1 can output a read signal, which is a low level. The sample-and-hold circuit will hold 2V1, and at the same time, the first controller U1 retrieves the memory under test. The hardware has just stored the data signal, and the second data signal, "011", is output from the first, second, and third data terminals. At this point, the signal judgment module 4 performs voltage peak state detection, and the in-phase adder performs addition again. The sixth analog switch J6 is then turned on. The third comparator A3 and the fourth comparator A4 check whether the signals held by the sixth analog switch J6 and the sample-and-hold circuit are equal, i.e., whether they are both 2V1. If they are not equal, it indicates that the output second data signal is not in the "011" state, indicating a data anomaly. The second indicator LED2 is illuminated and received by the IO9 terminal of the first controller U1.
[0033] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0034] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A memory hardware fault detection circuit, characterized in that, The circuit includes: The microcontroller module, connected to the memory module, signal judgment module, and status judgment module, is used to provide a first data signal and transmit it to the memory module through three branches when a write signal is provided; to receive the second data signal transmitted by the memory module when a read signal is provided; to output a test signal when memory hardware testing is required; to perform voltage comparison based on the high-level status control signal of the three branches detected by the port detection module; and to receive the first fault signal output by the signal judgment module and the second fault signal output by the status judgment module. The memory module is used to store the first data signal when a write signal is received, and to extract the stored first data signal and output the second data signal when a read signal is received. The second data signal is then transmitted to the microcontroller module through three branches. The port detection module, connected to the microcontroller module and the memory module, is used to detect the logic level status of the three branches transmitting the first data signal or the second data signal when a test signal is received, and to perform voltage sampling processing on the branch that is in the high-level state when the logic level is high. The signal judgment module, connected to the port detection module, is used to sequentially compare the signal sampled by the port detection module with the set high voltage threshold and low voltage threshold, and to display the voltage fault and output the first fault signal when the sampled signal is greater than the high voltage threshold or less than the low voltage threshold. The status judgment module, connected to the port detection module, is used to detect the number of branches in the port detection module that are in a high-level state, and to detect whether the number of branches in the port detection module that are in a high-level state during the microcontroller's write process is equal to the number of branches in the port detection module that are in a high-level state during the microcontroller's read process. If they are not equal, a read / write fault is displayed and a second fault signal is output.
2. The memory hardware fault detection circuit according to claim 1, characterized in that, The microcontroller module includes a first controller; the memory module includes memory hardware under test; and the port detection module includes a first analog switch. The A0 terminal of the first controller is connected to the first data terminal of the memory hardware under test and the third terminal of the first analog switch. The A1 terminal of the first controller is connected to the second data terminal of the memory hardware under test and the eighth terminal of the first analog switch. The A2 terminal of the first controller is connected to the third data terminal of the memory hardware under test and the first terminal of the first analog switch. The IO1 terminal of the first controller is connected to the fifth, sixth and thirteenth terminals of the first analog switch. The WE and OE terminals of the first controller are respectively connected to the write control terminal and read control terminal of the memory hardware under test.
3. The memory hardware fault detection circuit according to claim 2, characterized in that, The port detection module further includes a first capacitor, a first resistor, a second resistor, a first operational amplifier, a second operational amplifier, a third resistor, a fourth resistor, a first protection transistor, a first voltage regulator, a first switching transistor, and a fifth resistor; The first terminal of the first capacitor is connected to the non-inverting terminal of the third operational amplifier and the ninth terminal of the first analog switch. The second terminal of the first capacitor is connected to the inverting terminal of the first operational amplifier and is connected to the output terminal of the first operational amplifier and the inverting terminal of the second operational amplifier through the first resistor. The non-inverting terminal of the first operational amplifier is connected to one end of the third resistor, one end of the first protection transistor, the first end of the fifth resistor, and ground through the second resistor. The non-inverting terminal of the second operational amplifier is connected to the other end of the third resistor. The output terminal of the second operational amplifier is connected to the other end of the first protection transistor and the base of the first switching transistor through the fourth resistor. The collector of the first switching transistor is connected to the first voltage regulator, and the emitter of the first switching transistor is connected to the other end of the fifth resistor.
4. A memory hardware fault detection circuit according to claim 3, characterized in that, The port detection module also includes a third operational amplifier, a second analog switch, a first diode, a second diode, a sixth resistor, a fourth operational amplifier, and a second capacitor; The non-inverting input of the third operational amplifier is connected to the first terminal of the first capacitor. The inverting input of the third operational amplifier is connected to the anode of the first diode and connected to the output terminal and inverting input of the fourth operational amplifier through the sixth resistor. The non-inverting input of the fourth operational amplifier is connected to the cathode of the second diode and grounded through the second capacitor. The anode of the second diode is connected to the cathode of the first diode and the fourth terminal of the second analog switch. The output terminal of the third operational amplifier is connected to the third terminal of the second analog switch. The fifth terminal of the second analog switch is connected to the base of the first switching transistor.
5. A memory hardware fault detection circuit according to claim 4, characterized in that, The port detection module further includes a first detection device and a second detection device; The input terminals of the first detection device and the second detection device are respectively connected to the second and fourth terminals of the first analog switch, and the grounding terminals of the first and second detection devices are both grounded.
6. A memory hardware fault detection circuit according to claim 5, characterized in that, The signal determination module includes a third logic unit, a fourth logic unit, a fifth logic unit, a first comparator, a second comparator, a first reference power supply, a second reference power supply, and a first indicator light. The third terminal of the third logic unit, the third terminal of the fourth logic unit, and the third terminal of the fifth logic unit are respectively connected to the first output terminal of the first detection device, the first output terminal of the second detection device, and the output terminal of the fourth operational amplifier. The fifth terminals of the third logic unit, the fourth logic unit, and the fifth logic unit are respectively connected to the IO4, IO2, and IO3 terminals of the first controller. The fourth terminal of the third logic unit is connected to the fourth terminal of the fourth logic unit, the fourth terminal of the fifth logic unit, the inverting terminal of the first comparator, and the non-inverting terminal of the second comparator. The non-inverting terminal of the first comparator and the inverting terminal of the second comparator are respectively connected to the first reference power supply and the second reference power supply. The output terminal of the first comparator is connected to the output terminal of the second comparator, the IO5 terminal of the first controller, and the anode of the first indicator light. The cathode of the first indicator light is grounded.
7. A memory hardware fault detection circuit according to claim 6, characterized in that, The state determination module includes an in-phase adder, a sample-and-hold circuit, a first inverter, a second inverter, a sixth analog switch, a third comparator, a fourth comparator, and a second indicator light. The first, second, and third input terminals of the in-phase adder are respectively connected to the second output terminal of the first detection device, the second output terminal of the second detection device, and the emitter of the first switching transistor. The output terminal of the in-phase adder is connected to the input terminal of the sample-and-hold circuit and the third terminal of the sixth analog switch. The output terminal of the sample-and-hold circuit is connected to the inverting terminal of the third comparator and the non-inverting terminal of the fourth comparator. The fourth terminal of the sixth logic unit is connected to the non-inverting terminal of the third comparator and the inverting terminal of the fourth comparator. The output terminals of the first and second inverters are respectively connected to the control terminal of the sample-and-hold circuit and the fifth terminal of the sixth logic unit. The input terminals of the first and second inverters are respectively connected to the WE and OE terminals of the first controller. The output terminal of the third comparator is connected to the output terminal of the fourth comparator, the IO9 terminal of the first controller, and the anode of the second indicator light. The cathode of the second indicator light is grounded.