Cache system verification method and device, electronic equipment and storage medium
By constructing a cache verification model that interacts with a transaction-level simulation model, and utilizing a register-transfer-level circuit model to preserve the hardware details and actual timing of the cache system, the complexity of the cache system verification environment is solved, and efficient and accurate verification is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HYGON INFORMATION TECH CO LTD
- Filing Date
- 2026-01-15
- Publication Date
- 2026-05-19
AI Technical Summary
The verification environment of a caching system is complex and large, resulting in low verification efficiency and making it difficult to accurately and efficiently verify the interaction between the caching system and the downstream memory system.
A cache verification model is constructed, including a cache circuit model and general verification components. It interacts with the transaction-level simulation model through shared memory and uses a register-transfer level circuit model to preserve the hardware details and real timing of the cache system, thus simplifying the simulation of the memory system.
While ensuring verification accuracy, it significantly improves the verification efficiency of the caching system, simplifies the simulation configuration of the memory system, and enhances the speed and flexibility of verification.
Smart Images
Figure CN122064548A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip verification technology, and in particular to a verification method, apparatus, electronic device, and computer-readable storage medium for a cache system. Background Technology
[0002] A caching system is a storage technology used to improve data access speed, typically located between the processor and memory. Caching systems offer fast read and write speeds but relatively small capacities, allowing them to better match processor speeds and reduce memory access latency. Currently, the performance of caching systems is often a bottleneck for the overall performance of various processors (e.g., depth calculators). Therefore, verifying the performance of caching systems is crucial, and related technologies often require verification of the interaction between the caching system and the downstream memory system.
[0003] Generally, hardware circuit models can be used to verify cache systems and downstream memory systems because they preserve the detailed scenarios and actual timing of hardware simulations, thus more closely approximating real-world operation and resulting in more accurate simulation results. However, precisely because of this, the verification environment is extremely large and complex, significantly reducing verification efficiency. Summary of the Invention
[0004] In view of the above problems, embodiments of the present invention provide a verification method, apparatus, electronic device and computer-readable storage medium for a caching system, which can greatly improve verification efficiency while ensuring the accuracy of caching system verification.
[0005] In a first aspect, embodiments of the present invention provide a verification method for a caching system, comprising: A cache verification model is constructed for the cache system to be verified. The cache verification model includes a cache circuit model of the cache system and a general verification component, wherein the cache circuit model is a register transfer level circuit model of the cache system. The cache verification model is run so that the cache circuit model interacts with a transaction-level simulation model for simulating a memory system, based on the general verification components and preset shared memory.
[0006] In one implementation, constructing a cache verification model for the cache system to be verified includes: Obtain the cache circuit model of the cache system; The cache verification model is obtained by configuring the corresponding general verification component for the cache circuit model based on the general verification method.
[0007] In one implementation, the general verification component includes a monitor and a first transformation function; The step of running the cache verification model, enabling the cache circuit model to interact with the transaction-level simulation model used to simulate the memory system based on the general verification components and preset shared memory, includes: In response to receiving the command to start verification, the cache circuit model is run; The source output signal of the cache circuit model is acquired through the monitor, and the source output signal is converted into output transaction data; The output transaction data is converted into target output data using the first conversion function; The target output data is transmitted to the transaction-level simulation model used to simulate the memory system based on the shared memory.
[0008] In one implementation, the transmission of the target output data to the transaction-level simulation model for simulating the memory system based on the shared memory includes: The target output data is transmitted to the second programming interface through the first programming interface; The target output data is written to the shared memory through the second programming interface, so that the transaction-level simulation model for simulating the memory system reads the target output data from the shared memory.
[0009] In one implementation, writing the target output data into the shared memory via the second programming interface includes: The target output data is written to the shared memory using the request retrieval function set in the second programming interface.
[0010] In one implementation, the general verification component includes a driver, a sequencer, and a second transformation function; The step of running the cache verification model, enabling the cache circuit model to interact with the transaction-level simulation model used to simulate the memory system based on the general verification components and preset shared memory, includes: In response to receiving the command to start verification, the cache circuit model is run; The source input data is transmitted to the second transformation function via the shared memory, wherein the source input data comes from the transaction-level simulation model used to simulate the memory system; The source input data is converted into input transaction data by the second conversion function, and the input transaction data is transmitted to the sequencer in the form of an input sequence. The input sequence is transmitted to the driver via the sequencer; The input sequence is transmitted to the buffer circuit model via the driver.
[0011] In one implementation, transmitting the source input data to the second transformation function via the shared memory includes: The shared memory receives the source input data written by the transaction-level simulation model used to simulate the memory system; The source input data is obtained from the shared memory through the second programming interface; The source input data is transmitted from the second programming interface to the second conversion function through the first programming interface.
[0012] In one implementation, obtaining the source input data from the shared memory via the second programming interface includes: The source input data is read from the shared memory using the response retrieval function set in the second programming interface.
[0013] Secondly, embodiments of the present invention provide an apparatus, comprising: The model building module is used to build a cache verification model for the cache system to be verified. The cache verification model includes a cache circuit model of the cache system and a general verification component, wherein the cache circuit model is a register transfer level circuit model of the cache system. The model running module is used to run the cache verification model so that the cache circuit model interacts with the transaction-level simulation model for simulating the memory system based on the general verification components and preset shared memory.
[0014] In one implementation, the model building module includes: The acquisition unit is used to acquire the cache circuit model of the cache system; The configuration unit is used to configure the corresponding general verification component for the cache circuit model based on the general verification method, so as to obtain the cache verification model.
[0015] In one implementation, the general verification component includes a monitor and a first transformation function; the model running module includes: The first operating unit is used to run the cache circuit model in response to receiving a command to start verification; The first conversion unit is used to acquire the source output signal of the cache circuit model through the monitor and convert the source output signal into output transaction data; The second conversion unit is used to convert the output transaction data into target output data through the first conversion function; The first transmission unit is used to transmit the target output data to the transaction-level simulation model used to simulate the memory system based on the shared memory.
[0016] In one embodiment, the first transmission unit includes: The first transmission subunit is used to transmit the target output data to the second interface through the first programming interface; The write subunit is used to write the target output data to the shared memory through the second programming interface, so that the transaction-level simulation model for simulating the memory system can read the target output data from the shared memory.
[0017] In one implementation, the writing subunit is specifically used to write the target output data into the shared memory through a request retrieval function set in the second programming interface.
[0018] In one implementation, the general verification component includes a driver, a sequencer, and a second transformation function; the model running module includes: The second operating unit is used to run the cache circuit model in response to receiving a command to start verification; The second transmission unit is used to transmit source input data to the second conversion function through the shared memory, wherein the source input data comes from the transaction-level simulation model for simulating the memory system; The fourth conversion unit is used to convert the source input data into input transaction data through the second conversion function, and transmit the input transaction data to the sequencer in the form of an input sequence; The third transmission unit is used to transmit the input sequence to the driver via the sequencer. The fourth transmission unit is used to transmit the input sequence to the buffer circuit model via the driver.
[0019] In one embodiment, the second transmission unit includes: A receiving subunit is configured to receive the source input data written by the transaction-level simulation model for simulating a memory system via the shared memory; A subunit is configured to acquire the source input data from the shared memory via the second programming interface; The second transmission subunit is used to transmit the source input data from the second programming interface to the second conversion function through the first programming interface.
[0020] In one implementation, the acquisition subunit is specifically used to read the source input data from the shared memory through a response acquisition function set in the second programming interface.
[0021] Thirdly, an electronic device includes a memory and a processor; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the verification method of the cache system described in any of the foregoing embodiments.
[0022] Fourthly, a computer-readable storage medium stores one or more programs that can be executed by one or more processors to implement the verification method of the caching system in any of the foregoing embodiments.
[0023] The embodiments of the present invention provide a method, apparatus, electronic device, and computer-readable storage medium for verifying a cache system. This method can construct a cache verification model for a cache system to be verified, and run the cache verification model so that the cache circuit model interacts with a transaction-level simulation model used to simulate the memory system, based on the general verification components and preset shared memory. Since the cache circuit model is a register-transfer level circuit model of the cache system, it can retain the detailed scenarios and actual timing of the cache system's hardware circuitry. Furthermore, since the memory system, which interacts with the cache system and is downstream of it, is modeled using a transaction-level simulation model, the simulation of the memory system does not require actual circuit operation scenarios and timing information, resulting in relatively small data volume and easy configuration. Thus, by implementing the interaction between the cache circuit model and the transaction-level simulation model based on the general verification components and preset shared memory, it is convenient to quickly and easily configure the transaction-level simulation model to simulate the impact of different states of the memory system on the cache system. On the other hand, it can utilize the register-transfer level circuit model of the cache system to retain the operational details and actual timing of the cache system's hardware circuitry. Therefore, it can significantly improve verification efficiency while ensuring the accuracy of cache system verification. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 A flowchart of a caching system verification method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the interaction between the cache circuit model and the transaction-level simulation model in an embodiment of the present invention; Figure 3 This is a flowchart illustrating the operation of a cache verification model in an embodiment of the present invention; Figure 4 This is another flowchart illustrating the operation of the cache verification model in an embodiment of the present invention; Figure 5 A schematic diagram of a cache system verification device provided in an embodiment of the present invention; Figure 6 A schematic diagram of an electronic device provided as an embodiment of the present invention. Detailed Implementation
[0026] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0027] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0028] In a first aspect, embodiments of the present invention provide a verification method for a caching system, which can greatly improve verification efficiency while ensuring the accuracy of caching system verification.
[0029] like Figure 1 As shown, the verification method for the caching system provided in the embodiments of the present invention includes: Step S10: Construct a cache verification model for the cache system to be verified. The cache verification model includes a cache circuit model of the cache system and a general verification component, wherein the cache circuit model is a register transfer level circuit model of the cache system. The caching system to be verified can be a caching system (cache) whose functionality or performance needs to be verified. In one embodiment of the present invention, the caching system may include multiple caching levels, such as Level 1 cache (L1), Level 2 cache (L2), and Level 3 cache (L3).
[0030] To verify the caching system, this step involves constructing a cache verification model. This model can include a cache circuit model of the caching system and general verification components. The cache circuit model can refer to the circuit structure model of the caching system itself, while the general verification components can refer to components provided in the verification environment that interact with the cache circuit model.
[0031] Step S20: Run the cache verification model so that the cache circuit model interacts with the transaction-level simulation model used to simulate the memory system based on the general verification components and the preset shared memory.
[0032] After constructing the cache verification model, this step allows running the cache verification model. This enables the cache circuit model within the cache verification model to interact with the transaction-level simulation model used to simulate the memory system via general verification components and pre-defined shared memory. Here, the memory system can refer to a memory system downstream of the cache system that interacts with it.
[0033] In embodiments of the present invention, to verify the interaction between the caching system and the memory system, in addition to constructing a cache verification model for the caching system, a transaction-level simulation model is also constructed for the memory system. The transaction-level simulation model employs a discrete event-driven mechanism, supports periodic-level precision modeling, and can perform detailed simulations of hardware functional modules in the computer system. For example, in one instance, the transaction-level simulation model may include a GEM5 model, a Sparta simulation model, etc. Unlike methods that perform simulations every clock cycle, periodic-level precision modeling advances the simulation using instruction cycles as the basic unit, thereby reducing the number of events during the simulation process, significantly improving simulation efficiency, and shortening simulation time.
[0034] In embodiments of the present invention, the cache verification model and the transaction-level simulation model used to simulate memory can interact through shared memory. Here, shared memory refers to computer memory that can be accessed by both the cache verification model and the transaction-level simulation model used to simulate the memory system during the verification process.
[0035] The cache system verification method provided by the embodiments of the present invention can construct a cache verification model for the cache system to be verified, and run the cache verification model so that the cache circuit model interacts with the transaction-level simulation model used to simulate the memory system based on the general verification components and preset shared memory. Since the cache circuit model is the register-transfer level circuit model of the cache system, it can retain the detailed scene and actual timing of the cache system hardware circuit. Furthermore, since the memory system, which interacts with the cache system and is downstream of the cache system, is modeled using a transaction-level simulation model, the simulation of the memory system does not require actual circuit operation scenes and timing information, resulting in a relatively small data volume and easy configuration. Thus, after realizing the interaction between the cache circuit model and the transaction-level simulation model used to simulate the memory system based on the general verification components and preset shared memory, it is convenient to quickly and easily configure the transaction-level simulation model to simulate the impact of different states of the memory system on the cache system. On the other hand, it can utilize the register-transfer level circuit model of the cache system to retain the operational details and actual timing of the cache system hardware circuit. Therefore, it can greatly improve verification efficiency while ensuring the accuracy of cache system verification.
[0036] Specifically, in one embodiment of the present invention, in step S10, constructing a cache verification model for the cache system to be verified may include: obtaining a cache circuit model of the cache system; configuring the corresponding general verification component for the cache circuit model based on a general verification method to obtain the cache verification model.
[0037] In this embodiment, a cache circuit model corresponding to the cache system can be obtained. This cache circuit model can, for example, describe the circuit structure of the cache system using a hardware description language. For instance, the cache circuit model can be a register-transfer level circuit model of the cache system. In integrated circuit design, general verification methods provide complete verification libraries and frameworks for creating complex chip verification environments. In one embodiment of this invention, verification components can be configured for the cache circuit model based on general verification methods to obtain a runnable cache verification model. By constructing a cache circuit model and using general verification methods to build the corresponding verification components, a cache verification model can be obtained.
[0038] Once the cache verification model is obtained, it can be run. During the operation of the cache verification model, the cache circuit model can interact with the transaction-level simulation model used to simulate the memory system, based on general verification components and preset shared memory.
[0039] Please see Figure 2 In embodiments of the present invention, the interaction between the cache circuit model (e.g., an RTL (Register Transfer Level) model) and the transaction-level simulation model used to simulate the memory system (e.g., a GEM5 model) can include two types: one is data transmission from the cache circuit model to the transaction-level simulation model used to simulate the memory system (data output from the perspective of the cache system to be verified), and the other is data transmission from the transaction-level simulation model used to simulate the memory system to the cache circuit model (data input from the perspective of the cache system to be verified). In embodiments of the present invention, when verifying the cache system, only one type of interaction may exist, or both types of interactions may exist; the embodiments of the present invention do not limit this.
[0040] Depending on the direction of data transmission during the above interaction, the general verification components configured for the cache circuit model can also differ accordingly. These will be explained below.
[0041] First, the transfer of data from the cache circuit model to the transaction-level simulation model used to simulate the memory system is explained in detail.
[0042] In some embodiments, the general verification component may include a monitor and a first transformation function; based on this, combined with Figure 2 and Figure 3 Step S20, running the cache verification model to enable the cache circuit model to interact with the transaction-level simulation model used to simulate the memory system based on the general verification components and preset shared memory, may specifically include: Step S2011: In response to receiving the command to start verification, the cache circuit model is run; Step S2012: Acquire the source output signal of the cache circuit model through the monitor, and convert the source output signal into output transaction data; Step S2013: Convert the output transaction data into target output data using the first conversion function; Step S2014: Based on the shared memory, transmit the target output data to the transaction-level simulation model used to simulate the memory system.
[0043] In this embodiment, during the operation of the cache verification model, the cache circuit model can interact with the transaction-level simulation model used to simulate the memory system via a general verification component. Specifically, after receiving the verification start command, the cache circuit model starts running and generates various signals, such as source output signals. The monitor in the general verification component can collect the source output signals of the cache circuit model and convert them into output transaction data. Here, output transaction data refers to the output transaction data. After obtaining the output transaction data, the target output data can be obtained by further parsing and transforming the output transaction data by calling a first transformation function. For example, the first transformation function can be the trans2str function. After obtaining the target output data, it can be transmitted to the transaction-level simulation model used to simulate the memory system via shared memory.
[0044] In one implementation, the transmission of the target output data to the transaction-level simulation model for simulating the memory system based on the shared memory may specifically include: The target output data is transmitted to the second programming interface through the first programming interface; The target output data is written to the shared memory through the second programming interface, so that the transaction-level simulation model for simulating the memory system reads the target output data from the shared memory.
[0045] In this embodiment, the first programming interface can be a Direct Programming Interface (DPI), which supports function calls between Verilog programs and C (or C++) programs. The general verification component can transmit the target output data issued by the cache circuit model and converted through the first programming interface to the second programming interface. The second programming interface can be a C language interface, which can include one or more interface functions encapsulated by C language programs. At least one of the interface functions can be used to write the target output data into shared memory, so that the transaction-level simulation model used to simulate the memory system can obtain the target output data from the shared memory.
[0046] In one implementation, writing the target output data into the shared memory via the second programming interface may specifically include: writing the target output data into the shared memory via a request retrieval function (getReq) set in the second programming interface.
[0047] The above describes the transfer of data from the cache circuit model to the transaction-level simulation model used to simulate the memory system. The following section will provide a more detailed explanation of the transfer of data from the transaction-level simulation model used to simulate the memory system to the cache circuit model.
[0048] In some embodiments, the general verification component may include a driver, a sequencer, and a second transformation function; based on this, combined with Figure 2 and Figure 4 Step S20, running the cache verification model to enable the cache circuit model to interact with the transaction-level simulation model used to simulate the memory system based on the general verification components and preset shared memory, may specifically include: Step S2021: In response to receiving the command to start verification, run the cache circuit model; Step S2022: Transmit the source input data to the second conversion function through the shared memory, wherein the source input data comes from the transaction-level simulation model used to simulate the memory system; Step S2023: Convert the source input data into input transaction data using the second conversion function, and transmit the input transaction data to the sequencer in the form of an input sequence; Step S2024: Transmit the input sequence to the driver through the sequencer; Step S2025: Transmit the input sequence to the buffer circuit model through the driver.
[0049] In this embodiment, the general verification component may further include a driver and a sequencer. During the operation of the cache verification model, source input data transmitted by the transaction-level simulation model used to simulate the memory system can be obtained from shared memory through a second conversion function. The second conversion function can convert the source input data into input transaction data. Here, input transaction data can refer to input transaction data. Input transaction data with multiple execution steps can be transmitted to the sequencer in the form of an input sequence. The sequencer can further transmit the input sequence to the driver, and then the driver transmits the input sequence to the cache circuit model to stimulate the cache circuit model to perform corresponding actions. Through the driver, sequencer, and second conversion function of the general verification component, the data sent from the transaction-level simulation model used to simulate the memory system to the cache circuit model can undergo a series of transmission conversions and be transmitted to the cache circuit model.
[0050] Specifically, in one embodiment of the present invention, transmitting the source input data to the second conversion function via the shared memory may include: receiving the source input data written by the transaction-level simulation model for simulating the memory system via the shared memory; obtaining the source input data from the shared memory via the second programming interface; and transmitting the source input data from the second programming interface to the second conversion function via the first programming interface.
[0051] In this embodiment, the second programming interface can be a C language interface, which may include one or more interface functions encapsulated by C language programs. At least one of the interface functions can be used to read target input data from shared memory, so that the target input data written to the shared memory by the transaction-level simulation model used to simulate the memory system can be read.
[0052] In this embodiment, during the process of transmitting data from the transaction-level simulation model used to simulate the memory system to the cache circuit model, the source input data is obtained from the shared memory by calling the second programming interface of the general verification component interacting with the transaction-level simulation model, and the source input data is forwarded to the second conversion function (e.g., the trans2str function) by calling the first programming interface of the general verification component interacting with the cache circuit model, so that the source input data is converted into input transaction data by the second conversion function.
[0053] In some embodiments, obtaining the source input data from the shared memory through the second programming interface may specifically include: reading the source input data from the shared memory through a response acquisition function (getResp) set in the second programming interface.
[0054] Secondly, embodiments of the present invention provide a verification device for a caching system, such as... Figure 5 As shown, it may include: The model building module 501 is used to build a cache verification model for the cache system to be verified. The cache verification model includes a cache circuit model of the cache system and a general verification component, wherein the cache circuit model is a register transfer level circuit model of the cache system. The model running module 502 is used to run the cache verification model so that the cache circuit model interacts with the transaction-level simulation model for simulating the memory system based on the general verification components and the preset shared memory.
[0055] The caching system verification device provided in this embodiment can construct a caching verification model for the caching system to be verified. The caching verification model includes a caching circuit model of the caching system and general verification components. Running the caching verification model allows the caching circuit model to interact with a transaction-level simulation model used to simulate the memory system, based on the general verification components and preset shared memory. Since the caching circuit model is a register-transfer level circuit model of the caching system, it can retain the detailed scenarios and actual timing of the caching system's hardware circuitry. Furthermore, since the memory system, which interacts with the caching system and is downstream of it, is modeled using a transaction-level simulation model, the simulation of the memory system does not require actual circuit operation scenarios and timing information, resulting in relatively small data volume and easy configuration. Thus, after the caching circuit model interacts with the transaction-level simulation model used to simulate the memory system based on the general verification components and preset shared memory, it facilitates convenient and rapid configuration of the transaction-level simulation model to simulate the impact of different states of the memory system on the caching system. On the other hand, it can utilize the register-transfer level circuit model of the caching system to retain the operational details and actual timing of the caching system's hardware circuitry. Therefore, it can significantly improve verification efficiency while ensuring the accuracy of caching system verification.
[0056] In one implementation, the model building module includes: The acquisition unit is used to acquire the cache circuit model of the cache system; The configuration unit is used to configure the corresponding general verification component for the cache circuit model based on the general verification method, so as to obtain the cache verification model.
[0057] In one implementation, the general verification component includes a monitor and a first transformation function; the model running module includes: The first operating unit is used to run the cache circuit model in response to receiving a command to start verification; The first conversion unit is used to acquire the source output signal of the cache circuit model through the monitor and convert the source output signal into output transaction data; The second conversion unit is used to convert the output transaction data into target output data through the first conversion function; The first transmission unit is used to transmit the target output data to the transaction-level simulation model used to simulate the memory system based on the shared memory.
[0058] In one embodiment, the first transmission unit includes: The first transmission subunit is used to transmit the target output data to the second interface through the first programming interface; The write subunit is used to write the target output data to the shared memory through the second programming interface, so that the transaction-level simulation model for simulating the memory system can read the target output data from the shared memory.
[0059] In one implementation, the writing subunit is specifically used to write the target output data into the shared memory through a request retrieval function set in the second programming interface.
[0060] In one implementation, the general verification component includes a driver, a sequencer, and a second transformation function; the model running module includes: The second operating unit is used to run the cache circuit model in response to receiving a command to start verification; The second transmission unit is used to transmit source input data to the second conversion function through the shared memory, wherein the source input data comes from the transaction-level simulation model for simulating the memory system; The fourth conversion unit is used to convert the source input data into input transaction data through the second conversion function, and transmit the input transaction data to the sequencer in the form of an input sequence; The third transmission unit is used to transmit the input sequence to the driver through the sequencer; The fourth transmission unit is used to transmit the input sequence to the buffer circuit model via the driver.
[0061] In one embodiment, the second transmission unit includes: A receiving subunit is configured to receive the source input data written by the transaction-level simulation model for simulating a memory system via the shared memory; A subunit is configured to acquire the source input data from the shared memory via the second programming interface; The second transmission subunit is used to transmit the source input data from the second programming interface to the second conversion function through the first programming interface.
[0062] In one implementation, the acquisition subunit is specifically used to read the source input data from the shared memory through a response acquisition function set in the second programming interface.
[0063] Thirdly, such as Figure 6 As shown, this embodiment of the invention also provides an electronic device, including a memory 601 and a processor 602; the memory 601 is used to store executable program code; the processor 602 runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the verification method of the cache system described in any of the foregoing embodiments.
[0064] This electronic device exists in various forms, including but not limited to: (1) Personal computer devices: These devices fall under the category of personal computers, have computing and processing functions, and generally also have mobile internet access capabilities.
[0065] (2) Server: A device that provides computing services. The components of a server include a processor, hard disk, memory, system bus, etc. Servers are similar to general computer architectures, but because they need to provide highly reliable services, they have higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.
[0066] (3) Other electronic devices with data interaction functions.
[0067] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement the verification method of the caching system described in any of the foregoing embodiments.
[0068] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0069] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A verification method for a caching system, characterized in that, include: A cache verification model is constructed for the cache system to be verified. The cache verification model includes a cache circuit model of the cache system and a general verification component, wherein the cache circuit model is a register transfer level circuit model of the cache system. The cache verification model is run so that the cache circuit model interacts with a transaction-level simulation model for simulating a memory system, based on the general verification components and preset shared memory.
2. The verification method for the caching system according to claim 1, characterized in that, The construction of a cache verification model for the cache system to be verified includes: Obtain the cache circuit model of the cache system; The cache verification model is obtained by configuring the corresponding general verification component for the cache circuit model based on the general verification method.
3. The verification method for the caching system according to claim 1, characterized in that, The general verification component includes a monitor and a first transformation function; The step of running the cache verification model, enabling the cache circuit model to interact with the transaction-level simulation model used to simulate the memory system based on the general verification components and preset shared memory, includes: In response to receiving the command to start verification, the cache circuit model is run; The source output signal of the cache circuit model is acquired through the monitor, and the source output signal is converted into output transaction data; The first conversion function is used to convert the output transaction data into the target output data. The target output data is transmitted to the transaction-level simulation model used to simulate the memory system based on the shared memory.
4. The verification method for the caching system according to claim 3, characterized in that, The step of transmitting the target output data to the transaction-level simulation model used to simulate the memory system based on the shared memory includes: The target output data is transmitted to the second programming interface through the first programming interface; The target output data is written to the shared memory through the second programming interface, so that the transaction-level simulation model for simulating the memory system reads the target output data from the shared memory.
5. The verification method for the caching system according to claim 4, characterized in that, The step of writing the target output data into the shared memory through the second programming interface includes: The target output data is written to the shared memory using the request retrieval function set in the second programming interface.
6. The verification method for the caching system according to any one of claims 1 to 5, characterized in that, The general verification components include a driver, a sequencer, and a second transformation function; The step of running the cache verification model, enabling the cache circuit model to interact with the transaction-level simulation model used to simulate the memory system based on the general verification components and preset shared memory, includes: In response to receiving the command to start verification, the cache circuit model is run; The source input data is transmitted to the second transformation function via the shared memory, wherein the source input data comes from the transaction-level simulation model used to simulate the memory system; The source input data is converted into input transaction data by the second conversion function, and the input transaction data is transmitted to the sequencer in the form of an input sequence. The input sequence is transmitted to the driver via the sequencer; The input sequence is transmitted to the buffer circuit model via the driver.
7. The verification method for the caching system according to claim 6, characterized in that, The step of transmitting the source input data to the second conversion function via the shared memory includes: The shared memory receives the source input data written by the transaction-level simulation model used to simulate the memory system; The source input data is obtained from the shared memory through a second programming interface; The source input data is transmitted from the second programming interface to the second conversion function through the first programming interface.
8. The verification method for the caching system according to claim 7, characterized in that, The step of obtaining the source input data from the shared memory through the second programming interface includes: The source input data is read from the shared memory using the response retrieval function set in the second programming interface.
9. A verification device for a caching system, characterized in that, include: The model building module is used to build a cache verification model for the cache system to be verified. The cache verification model includes a cache circuit model of the cache system and a general verification component, wherein the cache circuit model is a register transfer level circuit model of the cache system. The model running module is used to run the cache verification model so that the cache circuit model interacts with the transaction-level simulation model for simulating the memory system based on the general verification components and preset shared memory.
10. An electronic device, characterized in that, It includes a memory and a processor; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the verification method of the cache system according to any one of claims 1-8.
11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs that can be executed by one or more processors to implement the verification method of the caching system according to any one of claims 1 to 8.