Cooperative verification debugging method and device for processor core, and storage medium
By capturing verification events and generating trace files and interface specification files in processor core co-simulation, an independent verification framework is automatically generated, solving the problems of high debugging overhead and lack of independent debugging in the prior art. This enables efficient independent debugging of the verification framework, improving the efficiency and flexibility of processor design verification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INST OF COMPUTING TECH CHINESE ACAD OF SCI
- Filing Date
- 2026-01-28
- Publication Date
- 2026-05-19
AI Technical Summary
Existing technologies suffer from problems such as excessive debugging overhead, inability to reuse execution results, and lack of independent debugging mechanisms in processor design verification, resulting in low verification efficiency.
By capturing verification events and generating trace files and interface specification files during co-simulation, an independent verification framework compatible with the processor core interface is automatically generated. The framework is then driven by the trace files, allowing for independent debugging and iteration independent of the processor core under test.
It significantly reduced verification costs and time, improved debugging efficiency and flexibility, reduced resource consumption, and shortened the design cycle.
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Figure CN122064549A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design verification technology, and in particular to a processor core collaborative verification and debugging method, apparatus, and storage medium. Background Technology
[0002] In modern processor design flows, co-simulation verification is a crucial step in ensuring processor functional correctness. Its basic structure typically includes a Design Under Test (DUT) on the hardware side and a Reference Model (REF) on the software side. In this structure, the verification framework is responsible for extracting architectural state information from the DUT after each instruction execution and transmitting it to the REF via hardware-software communication. Upon receiving the corresponding input, the REF executes the instructions and updates its state, then compares it one-to-one with the DUT's state. This instruction-by-instruction state comparison mechanism effectively detects design errors and is a widely used verification method in processor development.
[0003] As processor complexity and scale continue to increase, the amount of data exchange between the DUT and REF increases significantly. To mitigate performance overhead during communication, existing technologies have proposed various communication optimization modules, such as compression, event packing, or cache alignment techniques, to reduce redundant transmissions and improve bandwidth utilization efficiency. However, in actual verification processes, the reference model, inspection module, and communication optimization modules themselves may all have defects or compatibility issues, requiring multiple debugging sessions during framework development and iteration. Since the correctness of these modules depends on the verification events output by the DUT, debugging must be driven by the execution results provided by the DUT.
[0004] In existing solutions, even if the DUT design remains unchanged during the debugging phase, verification personnel still need to recompile and run the DUT each time the framework is debugged to generate the corresponding verification event inputs. This results in the DUT compilation and execution process being repeatedly triggered, and DUT simulation itself has extremely high computational and resource consumption, becoming a major bottleneck in the verification process. Therefore, existing technologies have the following drawbacks:
[0005] First, the debugging overhead is too high. During the development and iteration of the verification framework, the communication optimization module, reference model, and inspection module may all require frequent modifications and debugging. However, existing solutions require rerunning the complete DUT simulation after each modification to generate verification events as input. DUT simulation itself is extremely computationally and resource-intensive, especially in scenarios with large-scale processors, often requiring long runs and consuming significant hardware resources, resulting in excessively long debugging cycles and severely limiting verification efficiency.
[0006] Second, the results of DUT execution cannot be reused. For processor cores with a fixed design, their instruction execution behavior and verification event output are deterministic and stable. However, existing solutions do not provide corresponding recording and reuse mechanisms, but instead rely on the DUT to run in real time to generate verification events each time, resulting in the same results being calculated repeatedly, increasing redundancy overhead.
[0007] Third, the verification framework debugging lacks independence. In the existing solution, the debugging of the reference model, inspection module, and communication optimization module all depend on the events output by the DUT in real time, and cannot be performed independently without the DUT running. This coupling makes the framework error localization inefficient and limits the flexibility of debugging work.
[0008] Therefore, existing technologies suffer from problems such as high debugging overhead, non-reusable execution results, and lack of independent debugging mechanisms, which are not conducive to improving the efficiency and reliability of large-scale processor design verification and need to be improved. Summary of the Invention
[0009] To address the shortcomings of existing technologies, this invention proposes a processor core collaborative verification and debugging method, apparatus, and storage medium. This method can avoid repeatedly running the processor core under test while keeping the processor design unchanged, enabling the verification framework to be debugged independently, thereby significantly reducing verification costs and improving overall efficiency.
[0010] This invention provides a processor core collaborative verification and debugging method, comprising:
[0011] During the co-simulation of the processor core under test, the output verification events are captured and standardized for storage, generating trace files and interface specification files;
[0012] An independent verification framework compatible with the core interface of the processor under test is automatically generated based on the interface specification document.
[0013] The trace file is loaded to drive the verification framework to run, and it can be debugged and iterated independently of the processor core under test.
[0014] In one embodiment of the present invention, the step of capturing the output verification events, standardizing and storing them, and generating trace files and interface specification files includes:
[0015] During the co-simulation of the processor core under test, verification events are extracted cyclically through the deployed event acquisition logic. The verification events include at least one of the following: instruction submission information, update results of general-purpose registers and control registers, address and data of memory access operations, and exception and interrupt information. The extracted verification events are written into the trace file in cyclical order to maintain the consistency of the event sequence on the timeline and generate time-series information of the verification events. The interface specification and the structural information of the verification events are organized to generate the interface specification file, which includes event type definitions, field names, field widths, numbering rules, and dependencies between events.
[0016] In one embodiment of the present invention, the step of automatically generating an independent verification framework compatible with the interface of the processor core under test based on the interface specification file includes:
[0017] The interface description information in the interface specification file is parsed to automatically match the communication protocol and data format of the processor core under test; a reference model, a checking module, and a communication optimization module are constructed based on the parsed interface description information; the reference model, the checking module, and the communication optimization module are integrated and encapsulated into a verification framework that can run independently.
[0018] In one embodiment of the present invention, the step of loading the trace file to drive the verification framework to run and performing independent debugging and iteration detached from the processor core under test includes:
[0019] The trace file is loaded into the verification framework to drive the reference model and the inspection module to run in a cycle-by-cycle manner;
[0020] Error location and logic modification are performed on the verification framework without rerunning the processor core under test;
[0021] After the modifications are completed, the trace file is reloaded to complete the test iteration and the verification framework is updated.
[0022] In one embodiment of the present invention, loading the trace file into the verification framework to drive the reference model and the inspection module to run in a cycle-by-cycle manner includes:
[0023] The trace file is loaded into the verification framework, and the timing information of the verification events is read periodically. Based on the timing information, the reference model is driven to update its own execution results, and the inspection module is triggered to perform a consistency comparison between the execution results of the reference model and the verification events of the processor core under test recorded in the trace file.
[0024] In one embodiment of the present invention, the processor under test core deployed on the FPGA hardware platform is run once to capture the output verification events and store them in a standardized manner to generate the trace file and the interface specification file.
[0025] On a general-purpose CPU platform: an independent verification framework compatible with the interface of the processor core under test is automatically generated based on the interface specification file; the trace file is loaded to drive the verification framework to run, and it is independently debugged and iterated independently of the processor core under test.
[0026] In one embodiment of the present invention, for processor cores under test with different architectures, interface adaptation is performed through the interface specification file of a unified format. The different architectures include at least one of scalar architecture, out-of-order architecture, single-core architecture, and multi-core architecture.
[0027] In one embodiment of the present invention, during the debugging process, the trace file and the execution results of the reference model are stored together to form a multi-round comparison dataset.
[0028] Another aspect of the present invention provides a processor core co-verification and debugging device, comprising:
[0029] The verification event acquisition module is used to capture and standardize the output verification events during the co-simulation of the processor core under test, and generate trace files and interface specification files.
[0030] The verification framework construction module is used to automatically generate an independent verification framework compatible with the core interface of the processor under test based on the interface specification file.
[0031] The verification framework execution module is used to load the trace file to drive the verification framework to run, and to perform independent debugging and iteration without the processor core under test.
[0032] In another aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the processor core collaborative verification and debugging method.
[0033] In another aspect, the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the processor core collaborative verification and debugging method.
[0034] As can be seen from the above solutions, the advantages of the present invention are:
[0035] The processor core co-simulation verification and debugging method provided by this invention captures and standardizes the output verification events during the co-simulation of the processor core under test (DUT), generating trace files and interface specification files. Based on the interface specification files, an independent verification framework compatible with the interface of the DUT is automatically generated. The trace files are loaded to drive the verification framework to run, allowing for independent debugging and iteration independent of the DUT. This method ensures that verification events are recorded and replayed through trace files and interface specification files while the DUT remains unchanged, thereby supporting independent debugging and rapid iteration of the verification framework and significantly reducing the resource overhead and time cost of large-scale processor design verification. Attached Figure Description
[0036] Figure 1 A schematic diagram of the overall process of a processor core collaborative verification and debugging method provided in an embodiment of the present invention is shown;
[0037] Figure 2 It shows Figure 1 A detailed flowchart of step S1 is shown below;
[0038] Figure 3 It shows Figure 1 A detailed flowchart of step S2 is shown below;
[0039] Figure 4 It shows Figure 1 A detailed flowchart of step S3 is shown below;
[0040] Figure 5 A schematic diagram of the overall structure of a processor core co-verification and debugging device provided in an embodiment of the present invention is shown.
[0041] The attached figures are labeled as follows:
[0042] 300: Processor core co-verification and debugging device;
[0043] 310: Verification event acquisition module;
[0044] 320: Validation framework building block;
[0045] 330: Verify the framework's running module. Detailed Implementation
[0046] It should be noted that, in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.
[0047] In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0048] As mentioned earlier, existing technologies incur excessive overhead during the debugging phase. Research has revealed that the root cause lies in the fact that each modification to the verification framework requires rerunning the DUT to provide driving data. Since DUT simulation is the most time-consuming and resource-intensive part of the overall verification process, this repetitive running significantly reduces debugging efficiency. Furthermore, under a fixed design, the DUT's instruction execution behavior and verification event outputs exhibit determinism and stability, but existing technologies do not provide an effective mechanism for recording and reusing these results, instead generating the same event data multiple times, resulting in substantial redundant overhead. Moreover, framework components such as the reference model, inspection module, and communication module all rely on the DUT's real-time output for driving, lacking the conditions for independent operation, thus limiting the flexibility and efficiency of the debugging process.
[0049] To address the aforementioned issues, this invention considers capturing and saving the verification event results of the DUT during a single complete run, allowing these results to be directly reused in subsequent debugging, thus avoiding repeated DUT execution. The technical challenge lies in how to ensure complete and standardized storage and replay of the DUT output while maintaining timing consistency and interface compatibility. To address this, verification events transmitted by the DUT are captured during co-simulation and saved in two types of files. The first is a trace file, using trace file format, used to record event content cycle by cycle, ensuring the timing characteristics of the execution process are fully preserved. The second is an interface specification file, using JSON file format, used to describe the interface specifications and event format, ensuring the verification framework can correctly parse and use the recorded data. Based on this, a verification framework matching the DUT interface can be automatically generated according to the interface specification file, and the trace file can be used as input to drive the reference model and inspection module, thereby achieving independent debugging of the verification framework.
[0050] Specifically, refer to Figure 1 As shown, Figure 1 The diagram shows the overall flow of a processor core collaborative verification and debugging method provided in an embodiment of the present invention.
[0051] A processor core collaborative verification and debugging method includes the following steps:
[0052] Step S1: During the co-simulation of the processor core under test, capture the output verification events and store them in a standardized manner to generate trace files and interface specification files.
[0053] Step S2: Automatically generate an independent verification framework compatible with the interface of the processor core under test based on the interface specification file.
[0054] Step S3: Load the trace file to drive the verification framework to run, and detach it from the processor core under test for independent debugging and iteration.
[0055] This embodiment avoids repeatedly running the processor under test (DUT) while keeping the processor design unchanged. It enables the verification framework to perform independent debugging while maintaining consistency in DUT execution results, thereby significantly reducing verification costs and improving overall efficiency.
[0056] In one specific implementation, in step S1, refer to Figure 2 As shown, Figure 2 A detailed flowchart of step S2 is shown.
[0057] During the co-simulation of the processor core under test, the output verification events are captured, standardized, and stored to generate trace files and interface specification files. The specific steps include the following:
[0058] Step S11: During the co-simulation of the processor core under test (DUT), verification events are extracted cycle by cycle through the deployed event acquisition logic. These verification events include, but are not limited to, instruction commit information, update results of general-purpose registers and control registers, memory access addresses and data, and exception and interrupt information. By deploying event acquisition logic in the DUT, the architectural state related to verification can be accurately acquired in each cycle. Step S12: The extracted verification events are written sequentially into a trace file (using trace file format) to maintain the consistency of the event sequence on the timeline, generating time-series information of the verification events. The trace file is used to record the transmitted verification event content cycle by cycle, maintaining the consistency of the event sequence on the timeline to ensure that subsequent replay processes can completely restore the original execution process.
[0059] Step S13: Organize the interface specification and the structure information of the verification events to generate the interface specification file (in JSON format). The interface specification file includes event type definitions, field names, field widths, numbering rules, and dependencies between events. Using the JSON file, a verification framework consistent with the DUT interface can be accurately constructed without relying on the DUT.
[0060] In this embodiment, during the operation of the DUT, the verification events transmitted by it are captured and stored, and recorded in trace format on a cycle to retain complete timing information. At the same time, an interface specification file in JSON format is generated to describe the interface specification and event format, ensuring that different verification frameworks can correctly parse and reuse them.
[0061] In one specific implementation, in step S2, refer to Figure 3 As shown, Figure 3 A detailed flowchart of step S2 is shown.
[0062] Based on the interface specification file, an independent verification framework compatible with the interface of the processor core under test is automatically generated, which specifically includes the following steps:
[0063] Step S21: Parse the interface description information in the interface specification file and automatically match the communication protocol and data format of the processor core under test.
[0064] Step S22: Construct a reference model, an inspection module, and a communication optimization module based on the parsed interface description information. Step S23: Integrate and encapsulate the reference model, inspection module, and communication optimization module into a stand-alone verification framework.
[0065] In this embodiment, a verification framework matching the DUT interface is automatically generated based on the interface description information provided in the JSON-formatted interface specification file. This verification framework includes a reference model, an inspection module, and a communication optimization module. It can be built and run normally without relying on the real-time operation of the DUT and can run independently in the software environment. The interface configuration of the verification framework is automatically imported from the JSON-formatted interface specification file, thereby avoiding ambiguity or inconsistency caused by manual configuration.
[0066] In one specific implementation, in step S3, refer to Figure 4 As shown, Figure 4 A detailed flowchart of step S3 is shown.
[0067] Loading the trace file drives the verification framework to run, and allows it to be debugged and iterated independently of the processor core under test. Specifically, this includes the following steps:
[0068] Step S31: Load the trace file into the verification framework to drive the reference model and inspection module to run in a cycle-by-cycle manner.
[0069] Specifically, the trace file is loaded into the verification framework, and the timing information of the verification events is read periodically. Based on the timing information, the reference model is driven to update its execution results according to the input instructions and status, and the checking module is triggered to compare the execution results of the reference model with the verification events of the processor core under test recorded in the trace file, thereby completing the consistency check.
[0070] Step S32: Without rerunning the processor core under test, perform error localization and logic modification on the verification framework. During the operation of the verification framework, errors in the reference model, communication optimization module, and checking module can be repeatedly located and debugged without relying on the real-time output of the DUT.
[0071] Step S33: After modification, reload the trace file to complete the test iteration and update the verification framework. When the verification framework logic is modified, simply reload the existing trace file to drive the test, without having to run the time-consuming DUT simulation again. This method significantly improves debugging efficiency and flexibility.
[0072] In this embodiment, by loading the trace file and replaying the execution result of the DUT, the reference model and the inspection module are directly driven to run, thereby supporting the verification framework to independently complete debugging and functional verification without the DUT.
[0073] Furthermore, in one embodiment, under FPGA acceleration, the DUT is run once on the FPGA hardware platform, capturing and standardizing the output verification events to generate the trace file and the interface specification file. On a general-purpose CPU platform, an independent verification framework compatible with the interface of the DUT is automatically generated based on the interface specification file; the trace file is loaded to drive the verification framework to run, allowing for independent debugging and iteration independent of the DUT. In this embodiment, the DUT only needs to run once to generate complete trace and JSON files, and subsequent debugging can be completed on a general-purpose CPU, thereby freeing up valuable hardware resources.
[0074] In one embodiment, for processor cores under test with different architectures, interface adaptation is performed using the interface specification file in a unified format to achieve universal settings. The different architectures include at least one of scalar architecture, out-of-order architecture, single-core architecture, and multi-core architecture.
[0075] In addition, during the debugging process, the trace files and the execution results of the reference model are stored together to form a multi-round comparison dataset to support regression validation and result analysis.
[0076] In summary, the processor core co-simulation and debugging method provided by this invention captures and standardizes the output verification events during the co-simulation of the processor core under test (DUT), generating trace files and interface specification files. Based on the interface specification files, an independent verification framework compatible with the interface of the DUT is automatically generated. The trace files are loaded to drive the verification framework to run, allowing it to be debugged and iterated independently of the DUT. This method ensures that verification events are recorded and replayed through trace files and JSON files while the DUT remains unchanged, thus supporting independent debugging and rapid iteration of the verification framework. Recording and replaying the verification events output by the DUT avoids repeated DUT runs, significantly reducing the time and resource overhead of the debugging process. It decouples the verification framework from the DUT, enabling the reference model, inspection module, and communication module to be debugged independently under fixed input conditions. This method improves the flexibility and efficiency of debugging, accelerates the verification process, and helps shorten the processor design cycle. Practical verification shows that this invention can reduce the resource overhead during debugging to approximately 1 / 6 of the original solution; improve the recompilation speed of the verification framework by approximately 10 times; and improve the running speed during the independent debugging phase by approximately 7 times. These improvements effectively alleviate the resource overhead and time costs in large-scale processor verification, and significantly accelerate design iteration.
[0077] In one embodiment, a processor core collaborative verification and debugging apparatus is further provided. This embodiment is an apparatus embodiment corresponding to the above method embodiment, such as... Figure 5 As shown, Figure 5 A schematic diagram of a processor core collaborative verification and debugging device according to an embodiment of the present invention is shown. This device embodiment can be implemented in conjunction with the above-described method embodiment. The relevant technical details mentioned in the above method embodiment remain valid in this device embodiment, and will not be repeated here to avoid repetition.
[0078] A processor core co-verification and debugging device 300 includes:
[0079] The verification event acquisition module 310 is used to capture and standardize the output verification events during the co-simulation of the processor core under test, and generate trace files and interface specification files.
[0080] The verification framework construction module 320 is used to automatically generate an independent verification framework compatible with the core interface of the processor under test based on the interface specification file.
[0081] The verification framework running module 330 is used to load the trace file to drive the verification framework to run, and to perform independent debugging and iteration without the processor core under test.
[0082] This invention also provides a readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of the processor core collaborative verification and debugging method described above, and achieve the same technical effect.
[0083] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the processor core collaborative verification and debugging method described above, and achieves the same technical effect.
[0084] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.
Claims
1. A processor core collaborative verification and debugging method, characterized in that, Include: During the co-simulation of the processor core under test, the output verification events are captured and standardized for storage, generating trace files and interface specification files; An independent verification framework compatible with the core interface of the processor under test is automatically generated based on the interface specification document. The trace file is loaded to drive the verification framework to run, and it can be debugged and iterated independently of the processor core under test.
2. The method according to claim 1, characterized in that, The steps of capturing and standardizing the output verification events, and generating trace files and interface specification files include: During the co-simulation of the processor core under test, verification events are extracted cyclically through the deployed event acquisition logic. The verification events include at least one of the following: instruction submission information, update results of general-purpose registers and control registers, address and data of memory access operations, and exception and interrupt information. The extracted verification events are written into the trace file in a periodic order to maintain the consistency of the event sequence on the timeline and generate time-series information of the verification events. Organize the interface specifications and the structure information of the verification events to generate the interface specification file. The interface specification file includes event type definitions, field names, field widths, numbering rules, and dependencies between events.
3. The method according to claim 1, characterized in that, The steps of automatically generating an independent verification framework compatible with the interface of the processor core under test based on the interface specification document include: The interface description information in the interface specification file is parsed to automatically match the communication protocol and data format of the processor core under test; Based on the parsed interface description information, a reference model, an inspection module, and a communication optimization module are constructed. The reference model, inspection module, and communication optimization module are integrated and encapsulated into a stand-alone verification framework.
4. The method according to claim 3, characterized in that, The steps of loading the trace file to drive the verification framework to run and performing independent debugging and iteration without the processor core under test include: The trace file is loaded into the verification framework to drive the reference model and the inspection module to run in a cycle-by-cycle manner; Error location and logic modification are performed on the verification framework without rerunning the processor core under test; After the modifications are completed, the trace file is reloaded to complete the test iteration and the verification framework is updated.
5. The method according to claim 4, characterized in that, Loading the trace file into the verification framework to drive the reference model and inspection module to run in a cycle-by-cycle manner includes: The trace file is loaded into the verification framework, and the time-series information of the verification events is read periodically. The timing information drives the reference model to update the execution result, and triggers the inspection module to perform a consistency comparison between the execution result of the reference model and the verification events of the processor core under test recorded in the trace file.
6. The method according to claim 1, characterized in that, The processor under test core deployed on the FPGA hardware platform is run once, the output verification events are captured and stored in a standardized manner, and the trace file and the interface specification file are generated. On a general-purpose CPU platform: an independent verification framework compatible with the interface of the processor core under test is automatically generated based on the interface specification file; the trace file is loaded to drive the verification framework to run, and it is independently debugged and iterated independently of the processor core under test.
7. The method according to claim 1, characterized in that, For processor cores under test with different architectures, interface adaptation is performed through the interface specification file in a unified format. The different architectures include at least one of scalar architecture, out-of-order architecture, single-core architecture, and multi-core architecture.
8. The method according to claim 1, characterized in that, During the debugging process, the trace file and the execution results of the reference model are stored together to form a multi-round comparison dataset.
9. A processor core collaborative verification and debugging device, characterized in that, Include: The verification event acquisition module is used to capture and standardize the output verification events during the co-simulation of the processor core under test, and generate trace files and interface specification files. The verification framework construction module is used to automatically generate an independent verification framework compatible with the interface of the processor core under test based on the interface specification file. The verification framework execution module is used to load the trace file to drive the verification framework to run, and to perform independent debugging and iteration without the processor core under test.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.