FPGA (Field Programmable Gate Array) and embedded software online debugging method based on ZYNQ chip

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) based on a ZYNQ chip and an embedded software online debugging method, and belongs to the technical field of wireless communication. According to the method, each running thread of FPGA software and embedded software is endowed with a unique thread number, firstly, a debugged object is selected to send a debugging handshake instruction, and after handshake succeeds, the debugged object returns all the running threads; and after the returned thread is received, the corresponding thread is selected according to the uniquely identified ID number to send a debugging instruction, after the debugged object receives the debugging instruction, the instruction content is verified, and the tested content is returned after verification is passed. The method can be realized on an existing platform, intelligent control is provided for wireless measurement and control data, online debugging of an FPGA soft ring and embedded software can be realized, the method is designed and realized on an application layer, and possibility is provided for wireless communication which is intelligent, convenient and convenient to debug.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to an online debugging method for FPGA and embedded software based on a ZYNQ chip. Background Technology

[0002] The telemetry, tracking, and command (TT&C) link system is a crucial component of communication systems for UAVs, manned aircraft, and ships, enabling data transmission between command and control stations and remote devices. The increasing diversity of embedded platforms and the complex system requirements and signal flows pose significant challenges to online debugging for designers. With the development of intelligent and high-quality communication systems, a more stable and convenient debugging method is needed to ensure smooth project progress and efficient troubleshooting for designers. Therefore, a dual-channel debugging method based on ZYNQ platform FPGA and ARM software is urgently needed. This method will make troubleshooting more visual, convenient, and efficient, accelerate the programming progress of designers, and ensure the smooth progress of projects and the successful implementation of system plans. Summary of the Invention

[0003] In view of this, the present invention proposes an online debugging method for FPGA and embedded software based on ZYNQ chip, which can make the debugging of measurement and control link more flexible, convenient and stable, improve the generalization level of wireless communication link system and the smooth and stable progress of project.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows: An online debugging method for FPGA and embedded software based on ZYNQ chips includes the following steps: When content is reported from embedded software and FPGA software to a PC, the following steps are included: Step 101: Initialize the embedded software, FPGA software, and the threads and memory in the embedded software and FPGA software respectively; Step 102: The PC sends a debug handshake command to the FPGA software and the embedded software. If the handshake fails, the PC continues to send debug handshake commands. Step 103: After the handshake is successful, the FPGA software and embedded software report all running thread IDs and queue IDs to the PC. Among them, a project has one or more threads, a thread is a process, a thread has one or more queues, a queue is applied to one or more threads, each queue corresponds to an input and an output, and each thread ID contains the source ID number and destination ID number of the thread. The source ID number and destination ID number correspond to all the inputs and all the outputs of the thread. Step 104: After the PC identifies all the thread IDs, it selects the corresponding thread to send the test command according to the test requirements. The test command contains the source ID number or destination ID number to be viewed. When the embedded software and FPGA software receive the test command, they identify the corresponding command content and match it with their own ID number. Step 105: After successful matching, the FPGA software and embedded software store the corresponding queue content into memory. Then, the FPGA software sends the corresponding queue content in memory to the PC for display through the embedded software, and the embedded software directly sends the corresponding queue content in memory to the PC for display. When a PC sends analog data to embedded software and FPGA software, the following steps are included: Step 201: Initialize the embedded software, FPGA software, and the threads and memory in the embedded software and FPGA software respectively; Step 202: The PC sends a debug handshake command to the FPGA software and the embedded software. If the handshake fails, the PC continues to send debug handshake commands. Step 203: After the handshake is successful, the FPGA software and embedded software report all running thread IDs and queue IDs to the PC. Among them, a project has one or more threads, one thread is a process, one thread has one or more queues, one queue is applied to one or more threads, each queue corresponds to one input and one output, and each thread ID contains the source ID number and destination ID number of the thread. The source ID number and destination ID number correspond to all inputs and all outputs of the thread. Step 204: The PC sends simulated data to the embedded software. Each piece of simulated data includes a thread ID, a queue ID, and data content. The embedded software identifies the thread ID and queue ID in each piece of simulated data and matches them with its own ID and the ID of the FPGA software. If it matches its own ID, it sends the data content to its corresponding queue. If it matches the ID of the FPGA software, it sends the data content to the corresponding queue of the FPGA software.

[0005] The advantages of this invention compared to the prior art are: This invention can be implemented on existing hardware platforms without adding extra hardware, providing a more convenient means for the joint testing of wireless communication link systems and improving the progress of system projects. Attached Figure Description

[0006] Figure 1 This is a system cross-linking diagram in this invention.

[0007] Figure 2 This is a flowchart illustrating the process of reporting content from embedded software and FPGA software to the PC in an example of the present invention.

[0008] Figure 3 This is a flowchart illustrating the process of sending analog data from a PC to embedded software and FPGA software in an example of the present invention. Detailed Implementation

[0009] The present invention will be further explained below with reference to the accompanying drawings.

[0010] An online debugging method for FPGA and embedded software based on ZYNQ chips is disclosed. This method utilizes multi-factor criteria, including whether all threads have been created, object selection, successful handshake, identification of all thread numbers, and the validity of debugging commands, to perform debugging processing. This enables stable and efficient debugging and testing of the measurement and control link. This invention is applicable to data debugging and processing of FPGA and embedded software. The system interconnection diagram is shown below. Figure 1 As shown, the PC can directly transmit data with the embedded software, while the PC needs to transmit data with the FPGA software through the embedded software.

[0011] like Figure 2 As shown, the process of reporting content from embedded software and FPGA software to the PC includes the following steps: Step 101: Initialize the embedded software, FPGA software, and the threads and memory in the embedded software and FPGA software respectively; Step 102: The PC sends a debug handshake command to the FPGA software and the embedded software. If the handshake fails, the PC continues to send debug handshake commands. Step 103, Identify Thread Numbers: After a successful handshake, the FPGA software and embedded software report all running thread IDs and queue IDs to the PC. A project has one or more threads, a thread is a process, a thread has one or more queues, a queue is applied to one or more threads, each queue corresponds to one input and one output, and each thread ID contains the source ID and destination ID of the thread. The source ID and destination ID correspond to all inputs and all outputs of the thread. Step 104: After the PC identifies all the thread IDs, it selects the corresponding thread to send the test command according to the test requirements. The test command contains the source ID number or destination ID number to be viewed. When the embedded software and FPGA software receive the test command, they identify the corresponding command content and match it with their own ID number. Step 105, Reporting content in the channel: After a successful match, the FPGA software and embedded software store the corresponding queue content in memory. Then, the FPGA software sends the corresponding queue content in memory to the PC for display via the embedded software, and the embedded software directly sends the corresponding queue content in memory to the PC for display.

[0012] like Figure 3 As shown, when the PC sends analog data to the embedded software and FPGA software, the following steps are included: Step 201: Initialize the embedded software, FPGA software, and the threads and memory in the embedded software and FPGA software respectively; Step 202: The PC sends a debug handshake command to the FPGA software and the embedded software. If the handshake fails, the PC continues to send debug handshake commands. Step 203, Identify Thread Numbers: After a successful handshake, the FPGA software and embedded software report all running thread IDs and queue IDs to the PC. A project has one or more threads, a thread is a process, a thread has one or more queues, a queue is applied to one or more threads, each queue corresponds to an input and an output, and each thread ID contains the source ID and destination ID of the thread. The source ID and destination ID correspond to all the inputs and all the outputs of the thread. Step 204, Sending Simulated Data: The PC sends simulated data to the embedded software. Each simulated data entry includes a thread ID, a queue ID, and data content. The embedded software identifies the thread ID and queue ID in each simulated data entry and matches them with its own ID and the ID of the FPGA software. If the match is successful, the data content is sent to its corresponding queue. If the match is successful, the data content is sent to the corresponding queue of the FPGA software. This simulates the input data of the corresponding processing modules in the embedded software and FPGA software, enabling testing without physical components.

[0013] Furthermore, this invention allows for testing of corresponding test content even without physical equipment, simply by simulating input data. It is not limited to network port debugging; serial port testing is also possible. It should be noted that the above embodiments are intended to enable those skilled in the art to implement or use the present invention, and various modifications to these embodiments will be readily apparent to those skilled in the art. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for online debugging of FPGA and embedded software based on ZYNQ chip, characterized in that, Includes the following steps: When content is reported from embedded software and FPGA software to a PC, the following steps are included: Step 101: Initialize the embedded software, FPGA software, and the threads and memory in the embedded software and FPGA software respectively; Step 102: The PC sends a debug handshake command to the FPGA software and the embedded software. If the handshake fails, the PC continues to send debug handshake commands. Step 103: After the handshake is successful, the FPGA software and embedded software report all running thread IDs and queue IDs to the PC. Among them, a project has one or more threads, a thread is a process, a thread has one or more queues, a queue is applied to one or more threads, each queue corresponds to an input and an output, and each thread ID contains the source ID number and destination ID number of the thread. The source ID number and destination ID number correspond to all the inputs and all the outputs of the thread. Step 104: After the PC identifies all the thread IDs, it selects the corresponding thread to send the test command according to the test requirements. The test command contains the source ID number or destination ID number to be viewed. When the embedded software and FPGA software receive the test command, they identify the corresponding command content and match it with their own ID number. Step 105: After successful matching, the FPGA software and embedded software store the corresponding queue content into memory. Then, the FPGA software sends the corresponding queue content in memory to the PC for display through the embedded software, and the embedded software directly sends the corresponding queue content in memory to the PC for display. When a PC sends analog data to embedded software and FPGA software, the following steps are included: Step 201: Initialize the embedded software, FPGA software, and the threads and memory in the embedded software and FPGA software respectively; Step 202: The PC sends a debug handshake command to the FPGA software and the embedded software. If the handshake fails, the PC continues to send debug handshake commands. Step 203: After the handshake is successful, the FPGA software and embedded software report all running thread IDs and queue IDs to the PC. Among them, a project has one or more threads, one thread is a process, one thread has one or more queues, one queue is applied to one or more threads, each queue corresponds to one input and one output, and each thread ID contains the source ID number and destination ID number of the thread. The source ID number and destination ID number correspond to all inputs and all outputs of the thread. Step 204: The PC sends simulated data to the embedded software. Each piece of simulated data includes a thread ID, a queue ID, and data content. The embedded software identifies the thread ID and queue ID in each piece of simulated data and matches them with its own ID and the ID of the FPGA software. If it matches its own ID, it sends the data content to its corresponding queue. If it matches the ID of the FPGA software, it sends the data content to the corresponding queue of the FPGA software.

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