Method for caching address mapping table, solid state disk, electronic equipment and storage medium

Abstract

The method for caching the address mapping table is applied to a solid state disk, and comprises the following steps: acquiring an accessed logic block address sequence; inputting the logic block address sequence into a trained prediction model, and outputting one or more prediction logic block addresses by the prediction model; and based on the one or more predicted logical block addresses, caching the target address mapping table, so that the target address mapping table comprises a mapping relationship between the one or more predicted logical block addresses and the physical block addresses. Therefore, the pre-estimation accuracy of the cached address mapping table is improved, the reading delay is reduced, the reading speed is improved, and fewer cache resources can be occupied.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a method for caching address mapping tables, solid-state drives, electronic devices, and storage media. Background Technology

[0002] Solid-state drives (SSDs) are non-volatile storage devices based on memory chips. Currently, SSDs have become the mainstream storage devices in various electronic devices, widely used in personal computers, mobile phones, game consoles, data center servers, smart cars, and industrial embedded equipment. SSDs use a flash translation layer (FTL) to record the mapping relationship between logical blocks and physical blocks in the memory chips. To improve read and write speeds, some SSDs cache address mapping tables that represent this mapping relationship.

[0003] However, in some solutions known to the inventors of this application, the cached address mapping table consumes a large amount of cache resources; in other solutions, the cached address mapping table has poor prediction accuracy and is prone to read latency. Summary of the Invention

[0004] In view of this, some embodiments of this application provide a method, solid-state drive, electronic device and storage medium for caching address mapping tables, which can effectively improve the prediction accuracy of the cached address mapping table, reduce read latency, improve read speed, and occupy less cache resources.

[0005] In a first aspect, embodiments of this application provide a method for caching an address mapping table, applied to a solid-state drive. The method includes: obtaining a sequence of accessed logical block addresses; inputting the logical block address sequence into a trained prediction model, the prediction model outputting one or more predicted logical block addresses; and caching a target address mapping table based on the one or more predicted logical block addresses, so that the target address mapping table includes a mapping relationship between one or more predicted logical block addresses and physical block addresses.

[0006] In some embodiments, the prediction model includes a multi-head self-attention module for capturing the dependencies between any two logical block addresses in a sequence of logical block addresses.

[0007] In some embodiments, the method further includes: collecting multiple recently accessed logical block address sequences to construct training data; using the training data to train the prediction model online, and iteratively updating the weight parameters of the prediction model.

[0008] In some embodiments, the loss function includes the cross-entropy loss function.

[0009] In some embodiments, the method further includes post-processing the prediction model to compress its size.

[0010] In some embodiments, the aforementioned post-processing includes: Set the redundant weight parameter in the prediction model to 0, where the absolute value of the redundant weight parameter is less than or equal to a first threshold; and / or, The weight parameters in the prediction model are quantified.

[0011] In some embodiments, the method further includes: Receive the first access request; The address of the first logical block is determined based on the first access request; In response to the fact that the first logical block address exists in the target address mapping table, the first physical block address corresponding to the first logical block address is obtained from the target address mapping table to serve the first access request; In response to the first logical block address not existing in the target address mapping table, the first physical block address corresponding to the first logical block address is searched from the address mapping table backed up in the storage chip of the solid-state drive to serve the first access request.

[0012] Secondly, some embodiments of this application also provide a solid-state drive, including a storage chip and a control chip, wherein the storage chip is connected to the control chip, and the control chip is used to execute one or more computer programs stored in the storage chip, so that the solid-state drive implements the method of caching address mapping table as described in the first aspect.

[0013] Thirdly, some embodiments of this application also provide an electronic device, including the solid-state drive mentioned in the second aspect.

[0014] Fourthly, some embodiments of this application also provide a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a control chip, cause the control chip to perform the method of cached address mapping table in the first aspect.

[0015] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are not intended to limit the embodiments, and elements having the same reference numerals in the drawings are designated as similar elements.

[0017] Figure 1A This is a schematic diagram of the solid-state drive structure in some embodiments of this application; Figure 1B This is a schematic diagram of the solid-state drive structure in some other embodiments of this application; Figure 2 This is a flowchart illustrating the method for caching address mapping tables in some embodiments of this application; Figure 3 This is a schematic diagram illustrating the process of online training of the prediction model in some embodiments of this application; Figure 4 This is a schematic diagram of the post-processing of the prediction model in some embodiments of this application; Figure 5 This is a schematic diagram of the solid-state drive service access request process in some embodiments of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0019] It should be noted that when an element is described as "connected" to another element, it can be directly connected to the other element, or there may be one or more intervening elements. Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not constitute a conflict.

[0020] To facilitate understanding, the main terms used in this application will be explained first.

[0021] Solid-state drives (SSDs) are hard drives made using arrays of solid-state electronic storage chips. An SSD consists of a controller chip and storage chips. Storage chips include flash memory chips, dynamic random access memory (DRAM), static random access memory (SRAM), or 3D XPoint storage media. The controller chip is used to control read and write operations on the storage chips.

[0022] A memory chip consists of multiple physical blocks (PBAs), each of the same size, and each physical block contains multiple pages, each of the same size.

[0023] The control chip can control the reading and writing of the storage chip in units of physical blocks or physical pages. When an electronic device writes data to the storage chip, the control chip records the mapping relationship between physical block addresses and logical block addresses. When the electronic device reads the data, the control chip uses this mapping relationship to read the data from the storage chip and then returns it to the user.

[0024] A logical block address (LBA) indicates a logical block. The mapping between logical block addresses and physical block addresses is managed by the flash translation layer (FTL).

[0025] Flash Translation Layer (FTL): A software middleware layer that provides translation or mapping between logical block addresses and physical block addresses. FTL is also used for garbage collection, wear leveling, bad block management, power-down anomalies, read interference, and data retention.

[0026] As data is written and erased, the flash translation layer establishes and updates an address mapping table, which includes multiple mapping entries between logical block addresses and physical block addresses. In some embodiments, the complete address mapping table is stored in a non-volatile flash memory chip (e.g., a NAND chip) to ensure recovery after power failure. It is understood that, due to the hardware characteristics and read / write mechanism limitations of flash memory chips, the physical access latency of flash memory chips is in the microsecond range, resulting in slow read / write speeds.

[0027] To improve read and write speeds, in some embodiments, some solid-state drives cache a portion of the address mapping table that may be accessed frequently in volatile DRAM or RAM chips.

[0028] However, some solutions known to the inventors of this application employ page-level address mapping tables, which refine the mapping granularity to the individual page level, thus improving lookup accuracy. However, page-level address mapping tables occupy a large amount of storage space; caching the entire or part of the page-level address mapping table in the DRAM chip would consume significant cache resources.

[0029] Other methods known to the inventors of this application compress the cached address mapping table by learning the linear relationship of data access. However, they are ineffective for true random input / output (I / O) or complex nonlinear access, have poor prediction accuracy, and are prone to read latency.

[0030] To address the aforementioned technical problems, embodiments of this application provide a method for caching address mapping tables, a solid-state drive, an electronic device, and a storage medium, which can effectively improve the prediction accuracy of the cached address mapping table, reduce read latency, increase read speed, and consume less cache resources.

[0031] Before introducing the method of caching the address mapping table in this application, the structure of the solid-state drive in the embodiments of this application will be described in detail.

[0032] Please see Figure 1A The solid-state drive 100 includes a controller chip 10 and a storage chip 20, with the storage chip 20 connected to the controller chip 10. For example, the storage chip 20 is connected to the controller chip 10 via a bus 30.

[0033] The memory chip 20 is used to store or cache data, program code, or data generated during program code execution. Please refer to [link / reference]. Figure 1B The memory chip 20 includes a non-volatile flash memory chip, such as a NAND chip. In some embodiments, the memory chip also includes DRAM, which is short for Dynamic Random Access Memory. DRAM is a separate chip or integrated into the flash memory chip. In some embodiments, see 1B, the memory chip also includes RAM, which is short for Random Access Memory. RAM is integrated into the flash memory chip.

[0034] The memory chip 20 is also used to store non-volatile software programs, non-volatile computer executable programs, and modules, such as program instructions / modules corresponding to the cache address mapping table method in the embodiments of this application.

[0035] The control chip 10 executes various functional applications and data processing of the cache address mapping table method by running non-volatile software programs, instructions, and modules stored in the storage chip 20, that is, it implements the cache address mapping table method provided in the following method embodiments.

[0036] In some embodiments, such as Figure 1B As shown, the control chip integrates a miniature Neural Processing Unit (NPU) to provide machine learning and deep learning capabilities.

[0037] In some embodiments, the control chip integrates a hardware accelerator, which consists of logic circuits, for specific operations on the SSD, such as running programs, data compression, and additional compression, to improve the performance of the SSD.

[0038] The Flash Translation Layer (FTL) is a comprehensive software layer that includes firmware programs, algorithms, and address mapping tables. The firmware programs and algorithms include address mapping algorithms, garbage collection algorithms, and wear leveling algorithms, among others. The address mapping table contains the mapping relationship between logical block addresses and physical block addresses to manage flash memory data.

[0039] The flash translation layer is stored within the flash memory chip. For example, a dedicated, protected system block is carved out on the flash memory chip to store firmware programs, algorithms, and address mapping tables. When the solid-state drive (SSD) is powered on, some or all of the firmware programs and some or all of the address mapping tables are loaded and cached in DRAM or RAM to improve operating speed.

[0040] As can be seen from the above, in some schemes, the address mapping table occupies a lot of cache resources; in other schemes, the address mapping table of DRAM or RAM cache has low prediction accuracy and is prone to read latency.

[0041] The cached address mapping method provided in this application uses a pre-trained prediction model to predict the addresses of logical blocks that may be accessed in the future based on the sequence of logical block addresses that have already been accessed, and caches the mapping relationship of the predicted logical block addresses in DRAM or RAM. When the solid-state drive determines the next logical block address based on the access request, it can quickly determine the corresponding physical block address from the address mapping table cached in DRAM or RAM, thereby improving read speed; accurate caching also consumes less cache resources.

[0042] In other words, the inventive concept of this application is to use the prediction model as an intelligent prefetch engine to replace or enhance the address mapping algorithm in the flash memory translation layer, accurately outputting the logical block addresses used for caching. This improves the prediction accuracy of the cached address mapping table, reduces read latency, increases read speed, and also consumes less cache resources.

[0043] The method for caching the address mapping table in this application can be executed by the controller chip of the solid-state drive. For example, the controller chip loads the program module corresponding to the method for caching the address mapping table from the flash memory chip into the DRAM or NPU, runs the program module, and implements the method for caching the address mapping table.

[0044] Please see Figure 2 The method S100 for caching address mapping tables in this application includes at least the following steps: S10: Obtain the sequence of addresses of the accessed logical blocks.

[0045] Solid-state drives (SSDs) are installed in electronic devices, such as personal computers, mobile phones, game consoles, data center servers, smart cars, and industrial embedded devices. Electronic devices send data input / output requests (I / O requests) to the SSD, which then performs operations such as reading, writing, modifying, or deleting data based on these I / O requests.

[0046] Understandably, as data interacts between electronic devices and solid-state drives (SSDs), a series of I / O requests are generated, forming an I / O request trail. In some embodiments, the SSD's controller chip structures the I / O request trail, making it a series of time-ordered tuples, each representing an I / O request. The tuple includes (timestamp, command_type, LBA, size), where timestamp is the timestamp of the received I / O request, command_type is the command type, LBA is the logical block address corresponding to the physical block address being read or written, and size represents the data size.

[0047] Thus, the control chip extracts the LBAs arranged in timing from the I / O request trace to obtain the accessed logic block address sequence (LBA sequence for short).

[0048] Understandably, these visited LBA sequences effectively reflect the current working scenario of the electronic device, thus helping to predict the next LBA. In some work scenarios, electronic devices are frequently used for office work, so most of these visited LBA sequences are office-related LBAs, and the next visited LBA is likely to be an office-related LBA as well. In other work scenarios, electronic devices are frequently used for gaming, so most of these visited LBA sequences are gaming-related LBAs, and the next visited LBA is likely to be a gaming-related LBA as well.

[0049] In some embodiments, a cache region is allocated within the DRAM chip to record the LBA sequences corresponding to the most recent I / O requests in real time. The control chip then acquires the accessed LBA sequences. These LBA sequences serve as context or hints for subsequent prediction models.

[0050] In some embodiments, the LBA sequence is 128 bytes long, meaning the 128 most recent LBAs are used as the LBA sequence. This ensures that the LBA sequence remains up-to-date with the operating environment of the electronic device; compared to including all visited LBAs, it also effectively reduces the computational load of the prediction model and improves prediction speed.

[0051] S20: Input the sequence of logical block addresses into the trained prediction model, and the prediction model outputs one or more predicted logical block addresses.

[0052] The prediction model is a pre-trained neural network model. The prediction model and its weight parameters are stored in the flash memory chip of the solid-state drive (SSD). After the SSD powers on, the control chip loads the prediction model into a reserved DRAM or SRAM area to accelerate its operation. In some embodiments, if the control chip is equipped with an NPU, the prediction model is loaded into the NPU to further accelerate its operation.

[0053] The LBA sequence is input into the prediction model. Multiple layers of neural network components in the prediction model extract features and spatially map the LBA sequence, outputting a list of access probabilities for each LBA in the address mapping table. This access probability list shows the LBAs that may be accessed in the future and their probabilities. For example, LBA 0x5001, 70%; LBA 0x8F00, 20%.

[0054] In some embodiments, LBAs with access probabilities greater than or equal to a probability threshold are used as predicted logical block addresses. In other embodiments, the top K LBAs by access probability are used as predicted logical block addresses. Thus, the prediction model outputs one or more predicted logical block addresses.

[0055] S30: Based on one or more predicted logical block addresses, generate and cache a target address mapping table so that the target address mapping table includes the mapping relationship between one or more predicted logical block addresses and physical block addresses.

[0056] When the flash translation layer receives one or more predicted LBAs, it first checks whether these predicted LBAs have been cached in the DRAM chip. If some predicted LBAs are not in the DRAM chip, the flash translation layer sends an internal read command to the flash chip to load the mapping relationship between the predicted LBAs and PBAs into the DRAM chip.

[0057] Therefore, when an electronic device issues an I / O request later, the address mapping for this I / O request has already been cached in the high-speed DRAM chip. This allows the Flash Translation Layer (FTL) to quickly find the address mapping and complete the address translation without needing to access the slow NAND flash memory. This effectively reduces the latency of a single I / O request. In particular, for workloads with predictable but complex patterns, such as image traversal, database index scanning, or hierarchical loading of AI models, it can effectively reduce read latency.

[0058] Furthermore, the target address mapping table includes address mappings with high access probability. The DRAM chip can accurately cache these high-probability address mappings, thus consuming less cache resources. As a result, SSDs do not need to cache large DRAM chips, effectively reducing the hardware cost of SSDs.

[0059] In this embodiment, a pre-trained prediction model is integrated into the solid-state drive as the intelligent prefetch engine of the flash translation layer (FTL). This model accurately outputs predicted address base arguments (LBAs), incorporates the mapping relationships of the predicted LBAs into the target address mapping table, and caches it in the DRAM chip for fast access by the FTL to complete the translation. This effectively improves the prediction accuracy of the cached address mapping table, reduces read latency, increases read speed, and also consumes less cache resources, thus reducing hardware costs.

[0060] As is understandable, a predictive model is a trained neural network model whose structure contains components of a neural network, such as convolutional layers, pooling layers, and activation function layers. These components are commonly used in neural networks and will not be described in detail here.

[0061] In some embodiments, the prediction model includes a multi-head self-attention module for capturing the dependencies between any two logical block addresses in a sequence of logical block addresses.

[0062] The multi-head self-attention module comprises an input layer, a linear projection layer, a multi-head segmentation layer, a scaled dot-product attention layer, and a head merging layer. The input layer converts the LBA sequence into vectors, which are then mapped by the linear projection layer to a matrix of query Q, key K, and value V. The multi-head segmentation layer splits the projected Q, K, and V matrices along the feature dimension into multiple heads. The scaled dot-product attention layer independently calculates the scaled dot-product attention for each head, obtaining the attention weights for each head. These attention weights reflect the dependencies between LBAs. The head merging layer concatenates the attention weights of the multiple heads along the feature dimension and then projects them through a linear transformation layer to obtain the final output of the multi-head attention module. Different heads can focus on different aspects of information in the LBA sequence, thus capturing richer dependencies. The final output of the multi-head attention module integrates the different dependency information captured by multiple heads, providing a more comprehensive representation of the dependencies between LBAs in the LBA sequence. This improves the prediction accuracy of the prediction model.

[0063] In some embodiments, the prediction model is a Transformer decoder, which includes an input embedding layer, a positional encoding layer, a multi-head self-attention module, an encoder-decoder layer, a feedforward neural network, a normalization layer, a residual connection layer, and an output layer, connected in a sequential manner. Specifically, the input embedding layer converts the LBA sequence into a vector; the positional encoding layer adds temporal information to the vector; the multi-head self-attention module captures the dependencies between LBAs within the LBA sequence; the encoder-decoder layer encodes and then decodes the vector; the feedforward neural network performs a non-linear transformation on the decoder's output; the normalization layer standardizes the outputs of each module, accelerating training convergence; the residual connection layer preserves the original input features in some modules; and the output layer converts the high-dimensional vector output by the decoder into a probability distribution of the LBAs.

[0064] The prediction model is pre-trained by those skilled in the art and stored in the storage chip of the solid-state drive (SSD). It is understood that before the SSD leaves the factory, its internal prediction model is an initial model. As the SSD is used, this initial prediction model is continuously updated based on actual access to keep it adapted to the access patterns of electronic devices.

[0065] In some embodiments, the initial prediction model is trained using the following steps: a) Prepare training data, which includes multiple LBA sequences, each LBA sequence labeled with the next real LBA.

[0066] To improve the generalizability of the prediction model, these LBA sequences are derived from real-world application scenarios. These scenarios include machine learning workloads, database systems, high-performance computing, and general desktop applications.

[0067] An LBA sequence comprises multiple LBAs. In some embodiments, for computational convenience, each LBA in the LBA sequence is converted into a numeric identifier, or a range of LBAs is converted into a numeric identifier. The numeric identifier is equivalent to an independent term, thus transforming an LBA sequence into an integer sequence, facilitating input into the prediction model for computation.

[0068] b) Input the training data into the prediction model before training, and the prediction model outputs the predicted LBA.

[0069] After each LBA sequence is input into the prediction model, the prediction model outputs the corresponding predicted LBA. Thus, multiple predicted LBAs are obtained. In some embodiments, the predicted LBAs include the predicted probabilities of each LBA in the address mapping table.

[0070] c) Calculate the difference between each predicted LBA and its corresponding true LBA using a loss function, and adjust the weight parameters of the prediction model in reverse based on the difference until the prediction model converges, thus obtaining the pre-trained prediction model.

[0071] In some embodiments, the cross-entropy loss function is used to calculate the difference between the predicted LBA and the true LBA for each group. The weight parameters of the prediction model are adjusted using backpropagation to minimize the difference between the predicted LBA and the true LBA. When the difference is less than a certain threshold or fluctuates within a certain range, the prediction model converges, resulting in a well-trained prediction model.

[0072] It is evident that the initial prediction model built into a solid-state drive (SSD) before it leaves the factory is a general-purpose model suitable for various application scenarios. As the SSD is used, the initial prediction model is continuously trained online based on I / O trajectories, self-learning the most recent I / O trajectories. As a result, its prediction capabilities can match real-world application scenarios, maintaining high prediction accuracy.

[0073] In some embodiments, please refer to Figure 3 The method S100 is trained online in the following way: S40: Collect the address sequences of multiple recently accessed logical blocks to construct training data.

[0074] As described above, with the continuous generation of I / O request traces, the LBAs arranged in sequence are cached in the DRAM chip. The control chip uses a first preset number of logical block addresses as a logical block address sequence. For example, every 128 logical block addresses generated are used as a logical block address sequence. The last logical block address in the logical block address sequence is the tag, i.e., the next actual LBA.

[0075] When the number of logical block address sequences reaches the second preset number, for example, the second prediction number is 1, 2, 4, 10, or 50, the logical block addresses of this second preset number are used as the sequence data for online training to trigger online training.

[0076] It is worth noting that those skilled in the art can set a first preset number or a second preset number according to the actual needs of the scenario. This application does not impose any limitations on the first preset number or the second preset number.

[0077] S50: The prediction model is trained online using training data, and the weight parameters of the prediction model are updated iteratively.

[0078] The control chip uses training data to train the prediction model online, obtaining new weight parameters. These new weight parameters are then used to update the current weight parameters of the prediction model. This allows the prediction model to learn the current I / O trajectory of the electronic device and adapt to it, resulting in higher prediction accuracy.

[0079] The online training process can be referred to steps a) to c) above, and will not be repeated here. In some embodiments, the loss function configured for online training includes the cross-entropy loss function, which can accelerate model convergence and improve prediction accuracy.

[0080] In this embodiment, by training the prediction model online, the prediction model can learn the nearest I / O trajectory, thereby enabling its prediction capability to match the real application scenario and maintain high prediction accuracy.

[0081] In some embodiments, the method S100 further includes: S60: Post-process the prediction model to compress its size.

[0082] Understandably, to prevent the prediction model from being too large relative to the control chip and thus affecting the running speed, this embodiment performs post-processing on the prediction model to compress its size. This improves the running speed and prediction efficiency of the prediction model.

[0083] In some embodiments, please refer to Figure 4 The aforementioned post-processing includes: S61: Set the redundant weight parameter in the prediction model to 0, where the absolute value of the redundant weight parameter is less than or equal to the first threshold.

[0084] The first threshold is an empirical value set by those skilled in the art based on practical experience. Weight parameters less than or equal to the first threshold have little impact on the prediction results and can be used as redundant weight parameters. Setting the redundant weight parameters to 0 achieves model pruning, effectively compressing the model size without affecting prediction accuracy.

[0085] In some embodiments, the aforementioned post-processing includes: S62: Quantify the weight parameters in the prediction model.

[0086] Quantization refers to mapping high-precision values ​​to low-precision values ​​using mathematical rules, achieving a balance between precision trade-offs and information retention. For example, converting weight parameters from 32-bit high-precision floating-point numbers to 8-bit or 4-bit low-precision integers can significantly reduce model size and accelerate computation, making it suitable for running on embedded hardware.

[0087] In some embodiments, please refer to Figure 5 The method S100 further includes: S71: Receive the first access request.

[0088] The first access request is an I / O request, used to instruct either to write data to the solid-state drive (SSD) or to instruct the reading of data from the SSD.

[0089] Understandably, the first access request is sent from the electronic device to the solid-state drive (SSD), and the SSD's controller chip receives the first access request. The first access request includes (timestamp, command_type, LBA, size), where timestamp is the timestamp of the received I / O request, command_type is the command type, LBA is the logical block address corresponding to the physical block address to be read or written, and size represents the data size.

[0090] S72: Determine the address of the first logical block based on the first access request.

[0091] Based on the fact that the first access request includes an LBA, the control chip uses the LBA in the first access request as the address of the first logical block.

[0092] S73: In response to the fact that the first logical block address exists in the target address mapping table, the first physical block address corresponding to the first logical block address is obtained from the target address mapping table to serve the first access request.

[0093] The control chip checks whether the first logical block address exists in the target address mapping table cached by the DRAM chip. If the first logical block address exists in the target address mapping table, the first physical block address corresponding to the first logical block address is retrieved from the target address mapping table. Then, a command indicating a first access request is executed based on the first physical block address to serve the first access request.

[0094] S74: In response to the first logical block address not existing in the target address mapping table, look up the first physical block address corresponding to the first logical block address from the address mapping table backed up in the storage chip of the solid-state drive to serve the first access request.

[0095] If the first logical block address does not exist in the target address mapping table cached by the DRAM chip, the flash translation layer in the control chip sends an internal read command to the memory chip (e.g., the flash memory chip) to look up the first physical block address corresponding to the first logical block address in the address mapping table backed up by the memory chip. Then, a command indicating a first access request is executed based on the first physical block address to serve the first access request.

[0096] In addition, the flash translation layer loads the mapping relationship between the first logical block address and the first physical block address into the DRAM chip.

[0097] In this embodiment, if the prediction model is successful, when the electronic device later issues an I / O request in which the LBA-PBA address mapping has been successfully prefetched, the address mapping of the I / O request has been cached in the high-speed DRAM chip. Thus, the flash translation layer can complete the address translation immediately without accessing the slow flash chip to look up the mapping, thereby reducing the latency of a single I / O request.

[0098] If the prediction model fails to predict correctly, when the electronic device later issues an I / O request, the DRAM chip cache will not contain the address mapping for the I / O request. In this case, the control chip drives the flash translation layer to read the required LBA-PBA address mapping from the memory chip (e.g., the flash memory chip) and map it to the DRAM chip. This does not affect normal access and incurs no additional loss.

[0099] Understandably, the predictive model and the flash translation layer collaborate without interfering with each other, thus optimizing the read performance of the solid-state drive. When the flash translation layer performs garbage collection or a new write operation, the physical location of the data changes, and the flash translation layer updates the complete mapping table stored in the storage chip. This process does not interfere with the predictive model, which is responsible for predicting the LBA (Level of Detail). The flash translation layer then retrieves the latest LBA-PBA mapping from the complete mapping table based on the predicted LBA. This ensures that prefetching and mapping table updates occur synchronously, working collaboratively without interference.

[0100] Thus, by introducing a predictive model as the LBA prefetch engine, the flash translation layer is given initiative and predictability, which can effectively improve the LBA-PBA mapping cache hit rate, effectively reduce I / O latency under complex workloads, reduce dependence on large-capacity DRAM chips, and has advantages in both cost and performance.

[0101] Some embodiments of this application also provide an electronic device, including the solid-state drive described in the above embodiments.

[0102] Electronic devices can include personal computers, mobile phones, game consoles, data center servers, smart cars, and industrial embedded devices. Based on the same inventive concept, electronic devices have the functions and effects of solid-state drives, which will not be repeated here.

[0103] Some embodiments of this application also provide a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a control chip, cause the control chip to perform the method of cached address mapping table described above.

[0104] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A method for caching address mapping tables, applied to solid-state drives, characterized in that, The method includes: Obtain the sequence of addresses of the accessed logical blocks; The sequence of logical block addresses is input into a trained prediction model, and the prediction model outputs one or more predicted logical block addresses. Based on the one or more predicted logical block addresses, a target address mapping table is generated and cached, so that the target address mapping table includes the mapping relationship between the one or more predicted logical block addresses and physical block addresses.

2. The method according to claim 1, characterized in that, The prediction model includes a multi-head self-attention module, which is used to capture the dependency relationship between any two logical block addresses in the logical block address sequence.

3. The method according to claim 2 or 3, characterized in that, The method further includes: Collect the address sequences of multiple recently accessed logical blocks to construct training data; The prediction model is trained online using the training data, and the weight parameters of the prediction model are iteratively updated.

4. The method according to claim 3, characterized in that, The loss function configured for online training includes the cross-entropy loss function.

5. The method according to claim 3, characterized in that, The method further includes: The prediction model is post-processed to compress its size.

6. The method according to claim 5, characterized in that, The post-processing includes: Set the redundant weight parameter in the prediction model to 0, wherein the absolute value of the redundant weight parameter is less than or equal to a first threshold; and / or, The weight parameters in the prediction model are quantized.

7. The method according to any one of claims 1-6, characterized in that, The method further includes: Receive the first access request; The address of the first logical block is determined based on the first access request; In response to the first logical block address existing in the target address mapping table, the first physical block address corresponding to the first logical block address is obtained from the target address mapping table to serve the first access request; In response to the first logical block address not existing in the target address mapping table, the first physical block address corresponding to the first logical block address is searched from the address mapping table backed up in the storage chip of the solid-state drive to serve the first access request.

8. A solid-state drive, characterized in that, The solid-state drive includes a storage chip and a control chip, the storage chip being connected to the control chip, the control chip being used to execute one or more computer programs stored in the storage chip, causing the solid-state drive to implement the cache address mapping table method as described in any one of claims 1-7.

9. An electronic device, characterized in that, Including the solid-state drive as described in claim 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by the control chip, cause the control chip to perform the method of cache address mapping table as described in any one of claims 1-7.

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