Data processing method, device and equipment of system-on-chip, system-on-chip and medium

Abstract

The embodiment of the invention provides a data processing method and device of a system-on-chip, electronic equipment, the system-on-chip and a computer readable storage medium. The method specifically comprises the steps of obtaining first instruction information; the first instruction information is sent by an on-chip processor of the system on chip to an on-chip acceleration controller; the first instruction information comprises a task instruction and first attribute information; acquiring to-be-processed data from a memory of the system on chip according to the first attribute information; converting the first instruction information into a first instruction signal; the first instruction signal is matched with an on-chip accelerator of the system on chip; and sending the to-be-processed data and the first instruction signal to an on-chip accelerator of the system on chip, so that the on-chip accelerator executes a data processing task for the to-be-processed data according to the task instruction. The on-chip processor and the on-chip accelerator can be decoupled, and the maintainability and the expandability of the on-chip system are improved; the invalid communication between the on-chip processor and the on-chip accelerator is reduced, and the communication and data transmission delay is reduced.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing method, apparatus, electronic device, system-on-a-chip, and computer-readable storage medium for a system-on-a-chip. Background Technology

[0002] An accelerator is a specialized hardware module designed to efficiently perform specific types of tasks (such as matrix operations, encryption, and image processing). Accelerators typically outperform general-purpose processors. Accelerators can interact with the Central Processing Unit (CPU) via an accelerator interface, working in conjunction with the CPU to efficiently complete data processing tasks.

[0003] In related technologies, instructions or data are typically sent directly to the accelerator through the Rocket Chip Coprocessor (ROCC) interface of the Reduced Instruction Set Computer, and the accelerator returns the results directly to the CPU through the ROCC interface.

[0004] However, the method of accelerators and CPUs working together through the ROCC interface in related technologies is only applicable to architectures based on fifth-generation reduced instruction set computing (RISC-V) computers. It is not portable and uses instruction communication, which has a high degree of coupling with the CPU and requires significant modifications to the original CPU.

[0005] Application content This application provides a data processing method, apparatus, electronic device, system-on-a-chip, and computer-readable storage medium for a system-on-a-chip, which can decouple the CPU and accelerator, improve the maintainability and scalability of the system-on-a-chip, reduce invalid communication between the CPU and accelerator, and reduce communication and data transmission latency.

[0006] In a first aspect, this application provides a data processing method for a system-on-a-chip, applied to an on-chip acceleration controller of a system-on-a-chip, the method comprising: Obtain first instruction information; the first instruction information is sent by the on-chip processor of the on-chip system to the on-chip acceleration controller; the first instruction information includes task instructions and first attribute information; Based on the first attribute information, the data to be processed is obtained from the memory of the on-chip system; The first instruction information is converted into a first instruction signal; the first instruction signal is matched with the on-chip accelerator of the on-chip system. The system sends the data to be processed and the first instruction signal to the on-chip accelerator, so that the on-chip accelerator can perform data processing tasks on the data to be processed according to the task instructions.

[0007] Secondly, this application provides a system-on-a-chip, which includes an on-chip accelerator, an on-chip acceleration controller, and an on-chip processor; The on-chip processor is used to send first instruction information to the on-chip acceleration controller of the system-on-chip; the first instruction information includes task instructions and first attribute information. The on-chip accelerator controller is used to acquire first instruction information; acquire data to be processed from the memory of the on-chip system according to first attribute information; convert the first instruction information into a first instruction signal; match the first instruction signal with the on-chip accelerator of the on-chip system; and send the data to be processed and the first instruction signal to the on-chip accelerator of the on-chip system. The on-chip accelerator is used to perform data processing tasks on the data to be processed according to the task instructions.

[0008] Thirdly, this application provides a data processing apparatus for a system-on-a-chip, the apparatus comprising: an acquisition module, a conversion module, and a transmission module.

[0009] The acquisition module is used to acquire first instruction information; the first instruction information is sent by the on-chip processor of the on-chip system to the on-chip acceleration controller; the first instruction information includes task instructions and first attribute information; The acquisition module is also used to acquire the data to be processed from the memory of the on-chip system based on the first attribute information; A conversion module is used to convert the first instruction information into a first instruction signal; the first instruction signal is matched with the on-chip accelerator of the on-chip system. The sending module is used to send the data to be processed and the first instruction signal to the on-chip accelerator of the system-on-chip, so that the on-chip accelerator can execute the data processing task for the data to be processed according to the task instruction.

[0010] Fourthly, this application provides an electronic device including a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more processors as described above for system-on-a-chip data processing methods.

[0011] Fifthly, this application provides a computer-readable storage medium that, when the instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the data processing method of the aforementioned system-on-a-chip.

[0012] The embodiments of this application have the following advantages: This application embodiment obtains first instruction information sent by the on-chip processor of the on-chip system, and defines the first instruction information as including task instructions and first attribute information. The on-chip processor does not need to know the specific type, interface protocol, and execution logic of the accelerator. It only needs to send the first instruction information in a unified format, without the need for customized adaptation to different accelerators, which reduces the development and maintenance costs of the on-chip processor. Moreover, the first attribute information contains all the core resources (address, size, task identifier, etc.) required for task execution, ensuring the integrity of task information and avoiding execution errors caused by ambiguous task instructions or missing resource parameters. At the same time, the task identifier contained in the first attribute information can distinguish different tasks and schedule them independently when the processor issues multiple tasks at the same time. It can also accurately match the original task when the result is fed back, avoiding multi-task confusion. Subsequently, according to the first attribute information, the data to be processed is obtained from the memory of the on-chip system. The on-chip acceleration controller reads the data through an independent memory access path, i.e., direct memory access, based on the virtual address and data size in the first attribute information. It does not need to occupy the cache or bus resources of the on-chip processor, avoiding resource conflicts between the on-chip processor's data handling and the accelerator's computation, ensuring the parallel working efficiency of both. The on-chip processor only needs to issue instructions, which can improve the utilization of computing power. The first instruction information is then converted into a first instruction signal; the first instruction signal is matched with the on-chip accelerator of the on-chip system; the data to be processed and the first instruction signal are sent to the on-chip accelerator of the on-chip system so that the on-chip accelerator can execute the data processing task for the data to be processed according to the task instruction. This can decouple the on-chip processor and the on-chip accelerator, simplify the task scheduling logic of the on-chip processor, so that the on-chip processor does not need to be aware of the hardware characteristics of the on-chip accelerator (such as interface protocol, data format requirements, etc.), but only needs to generate instructions and send them to the on-chip accelerator controller. The on-chip accelerator controller realizes the data interaction between the on-chip processor and the on-chip accelerator, thereby improving the maintainability and scalability of the on-chip system; at the same time, the on-chip accelerator controller can reduce invalid communication (such as repeated handshakes, retransmission of format errors) between the on-chip processor and the on-chip accelerator through centralized instruction parsing and data acquisition and transmission, and reduce communication and data transmission latency. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a flowchart of the steps of a data processing method for a system-on-a-chip provided in an embodiment of the present invention; Figure 2This is a schematic diagram of data transmission between an on-chip processor and an on-chip acceleration controller provided in an embodiment of the present invention; Figure 3 This is a flowchart of another data processing method for a system-on-a-chip provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the virtual address to physical address conversion process provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of data transmission in a data processing method for a system-on-a-chip provided in an embodiment of this application; Figure 6 This is a schematic diagram of data transmission in another data processing method for a system-on-a-chip provided in this application embodiment; Figure 7 This is a schematic diagram of an on-chip acceleration controller write interface design provided in an embodiment of this application; Figure 8 This is a schematic diagram of an on-chip acceleration controller read interface design provided in an embodiment of this application; Figure 9 A schematic diagram illustrating the interaction between an on-chip acceleration controller and an on-chip accelerator provided in an embodiment of this application; Figure 10 This is a schematic diagram of an on-chip system architecture provided in an embodiment of this application; Figure 11 This is a structural block diagram of a data processing device for a system-on-a-chip provided in an embodiment of this application; Figure 12 This is a structural block diagram of an electronic device for data processing in a system-on-a-chip, provided in an embodiment of this application. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0017] An accelerator is a specialized hardware module designed to efficiently perform specific types of tasks (such as matrix operations, encryption, and image processing). Accelerators typically outperform general-purpose processors. Accelerators can interact with the Central Processing Unit (CPU) via an accelerator interface, working in conjunction with the CPU to efficiently complete data processing tasks.

[0018] In related technologies, instructions or data are typically sent directly to the accelerator through the Rocket Chip Coprocessor (ROCC) interface of the Reduced Instruction Set Computer, and the accelerator returns the results directly to the CPU through the ROCC interface.

[0019] However, the method of accelerators and CPUs working together through the ROCC interface in related technologies is only applicable to architectures based on fifth-generation reduced instruction set computing (RISC-V) computers. It is not portable and uses instruction communication, which has a high degree of coupling with the CPU and requires significant modifications to the original CPU.

[0020] For example, ROCC is primarily designed for on-chip accelerators and is a programmable accelerator interface designed to work in conjunction with RISC-V processors. Its core concept is to achieve efficient interaction between the kernel and the accelerator through four key interfaces: command (cmd) and response (resp) for communication between the kernel and the accelerator; cmd is responsible for sending requests to the processor, and resp is used by the accelerator to return computation results. In addition, the ROCC interface includes request and response interfaces for interacting with the L1 cache, allowing the accelerator to directly access cached data. Besides these four basic interfaces, ROCC also supports additional extension interfaces to meet more advanced functional requirements.

[0021] In the interaction between the CPU and the accelerator, the cmd interface is used to pass instructions and related data to the accelerator, while the accelerator returns the calculation results to the integer register through the resp interface. Both interfaces are decoupled to ensure independent data transmission. The cmd data bus mainly includes an instruction field (inst) and two source data fields (rs1 and rs2). Inst must be an R-type instruction, and its opcode must be one of four user-defined opcodes. The instruction provides three bit flags to indicate the validity of the destination register and the two source registers. When a user-defined instruction with a valid destination register is sent to the accelerator, the processor expects the accelerator to return a result later and write it to the specified destination register. The accelerator responds to this result with a valid signal and the data field; these signals constitute the main content of the resp interface.

[0022] For the interaction between the accelerator and the L1 cache, ROCC provides two independent channels: mem_req and mem_resp, allowing the accelerator to directly initiate memory load and store operations. The accelerator sends memory requests to the cache through the mem_req interface, while the cache returns the corresponding results through the mem_resp interface. Similar to the cmd and resp interfaces, mem_req also adopts a decoupled design, further improving the flexibility of the interface.

[0023] ROCC supports user-defined instruction scheduling. Commonly used instructions include `rocc_read` (reads data from the accelerator's registers into the kernel registers), `rocc_write` (writes data from the kernel registers to the accelerator registers), `rocc_load` (loads data into the accelerator), and `rocc_store` (stores data from the accelerator into memory). These instructions provide flexible operation methods for data interaction between the kernel and the accelerator, and between the accelerator and memory, effectively improving system scalability and performance.

[0024] However, the methods used in these technologies are only applicable to the RISC-V architecture and lack portability. They employ instruction communication, resulting in high coupling with the CPU and requiring significant modifications to the original CPU. Memory interaction is linked to the L1 cache, making it unsuitable for large-scale data transfers.

[0025] Against this background, embodiments of this application provide a data processing method for a system-on-a-chip (SoC), which can decouple the CPU and accelerator, improve the maintainability and scalability of the SoC, reduce invalid communication between the CPU and accelerator, and reduce communication and data transmission latency.

[0026] Figure 1This is a flowchart illustrating the steps of a data processing method for a system-on-a-chip provided in an embodiment of the present invention. Figure 1 As shown, the method may include steps 101-104.

[0027] Step 101: Obtain the first instruction information.

[0028] In this embodiment, the first instruction information is sent by the on-chip processor of the on-chip system to the on-chip acceleration controller; the first instruction information includes task instructions and first attribute information. The on-chip processor can be understood as a CPU, and the on-chip acceleration controller can be understood as an accelerator agent. When executing an acceleration task, the on-chip processor can construct an acceleration message packet and send it to the on-chip acceleration controller. The on-chip acceleration controller, as the receiving end, receives the acceleration message packet, parses the acceleration message packet, and obtains the first instruction information to complete the acquisition of the first instruction information.

[0029] For example, after the CPU constructs an acceleration message packet and sends it to the accelerator agent, the accelerator agent can parse the acceleration message packet to obtain the first instruction information. The first instruction information may include a task instruction and first attribute information. The task instruction is used to indicate the specific type of acceleration task, and the opcode describes the specific computational task that the accelerator needs to execute. The first attribute information is used to represent the key resources or parameters required to execute the acceleration task. For example, if the task instruction is Opcode: ACCELERATE, then the core instruction is: execute Gaussian blur acceleration task; the first attribute information may include task identifier (ID), source data address, source data size, result data address, and response data address.

[0030] Based on the above embodiments, for example, Figure 2 This is a schematic diagram illustrating data transmission between an on-chip processor and an on-chip acceleration controller, provided by an embodiment of the present invention. Figure 2As shown, the instructions sent by the CPU to the accelerator can include acceleration instructions, pause instructions, priority modification instructions, and status query instructions. These instructions can be distinguished by the Opcode field in the protocol packet. The accelerator will reply with response information according to the CPU's requirements. The specific protocol field design is as follows: For acceleration instructions, which are instructions from the CPU to command the accelerator to perform work, Length represents the instruction length; Opcode represents the opcode; ID represents the task identifier; Priority represents the priority; Src_Cnt represents the number of source operands, i.e., the number of data to be processed; Srcn_Addr represents the address of the nth source operand; Srcn_Size represents the size of the nth source operand; Is_StoreMem indicates whether the result should be stored in memory; Res_Addr represents the address where the result is stored; Rsp_Addr represents the address where the response message is stored. For pause instructions, which are instructions from the CPU to command the accelerator to forcibly stop a specified number, Length represents the instruction length; Opcode represents the opcode; ID represents the task identifier. For priority modification instructions, which are instructions that command the CPU accelerator to change the priority of a specified instruction number, Length represents the instruction length; Opcode represents the opcode; ID represents the task identifier; and Priority represents the priority to be changed. For status query instructions, which are instructions that the CPU queries the running status of an instruction with a specified number, Length represents the instruction length; Opcode represents the opcode; and ID represents the task identifier. For response instructions, Status represents the status code used to identify the current processing status of the transaction; ID represents the task identifier; Res_Size represents the result length; and Res represents the calculation result.

[0031] Step 102: Obtain the data to be processed from the memory of the on-chip system based on the first attribute information.

[0032] In this embodiment, the data to be processed can be understood as source data. The on-chip acceleration controller can read the data to be processed from memory in a streaming manner and temporarily store the data according to the source data address and source data size contained in the first attribute information, through the on-chip interconnect bus protocol bridge (AXIBridge), using the source data address and according to the source data size, in preparation for sending the data to the on-chip accelerator.

[0033] For example, the on-chip acceleration controller passes address 0x1234_5000 and data size 76800 bytes to the AXI Bridge. According to the AXI bus protocol, it initiates one or more data transfer requests to the chip's memory controller. Based on the data transfer requests, the data to be processed is continuously read in the form of data blocks. After reading 76800 bytes of data, the data to be processed can be temporarily stored in the on-chip acceleration controller's internal data buffer or First In First Out (FIFO) queue.

[0034] Step 103: Convert the first instruction information into a first instruction signal; the first instruction signal is matched with the on-chip accelerator of the on-chip system.

[0035] In the embodiments of this application, the first instruction information is a standardized format defined by the on-chip processor, which may not be directly recognized by accelerators of different architectures and needs to be converted into instruction signals that match the accelerator.

[0036] For example, the on-chip accelerator controller can parse the task instruction and first attribute information of the first instruction information, query a preset mapping table, determine the physical accelerator instance corresponding to the first instruction information, obtain its interface type, and generate a series of specific, timing-correct hardware signals, namely the first instruction signal, according to the interface protocol of the on-chip accelerator.

[0037] Step 104: Send the data to be processed and the first instruction signal to the on-chip accelerator of the system on the chip, so that the on-chip accelerator can execute the data processing task for the data to be processed according to the task instruction.

[0038] In this embodiment, the on-chip acceleration controller can stream data to be processed to the on-chip accelerator through the source operand interface and simultaneously send the first instruction signal; after receiving the data to be processed, the on-chip accelerator can start the acceleration task according to the first instruction signal without needing to care about external logic such as data source and address translation.

[0039] This application embodiment obtains first instruction information sent by the on-chip processor of the on-chip system, and defines the first instruction information as including task instructions and first attribute information. The on-chip processor does not need to know the specific type, interface protocol, and execution logic of the accelerator. It only needs to send the first instruction information in a unified format, without the need for customized adaptation to different accelerators, which reduces the development and maintenance costs of the on-chip processor. Moreover, the first attribute information contains all the core resources (address, size, task identifier, etc.) required for task execution, ensuring the integrity of task information and avoiding execution errors caused by ambiguous task instructions or missing resource parameters. At the same time, the task identifier contained in the first attribute information can distinguish different tasks and schedule them independently when the processor issues multiple tasks at the same time. It can also accurately match the original task when the result is fed back, avoiding multi-task confusion. Subsequently, according to the first attribute information, the data to be processed is obtained from the memory of the on-chip system. The on-chip acceleration controller reads the data through an independent memory access path, i.e., direct memory access, based on the virtual address and data size in the first attribute information. It does not need to occupy the cache or bus resources of the on-chip processor, avoiding resource conflicts between the on-chip processor's data handling and the accelerator's computation, ensuring the parallel working efficiency of both. The on-chip processor only needs to issue instructions, which can improve the utilization of computing power. The first instruction information is then converted into a first instruction signal; the first instruction signal is matched with the on-chip accelerator of the on-chip system; the data to be processed and the first instruction signal are sent to the on-chip accelerator of the on-chip system so that the on-chip accelerator can execute the data processing task for the data to be processed according to the task instruction. This can decouple the on-chip processor and the on-chip accelerator, simplify the task scheduling logic of the on-chip processor, so that the on-chip processor does not need to be aware of the hardware characteristics of the on-chip accelerator (such as interface protocol, data format requirements, etc.), but only needs to generate instructions and send them to the on-chip accelerator controller. The on-chip accelerator controller realizes the data interaction between the on-chip processor and the on-chip accelerator, thereby improving the maintainability and scalability of the on-chip system; at the same time, the on-chip accelerator controller can reduce invalid communication (such as repeated handshakes, retransmission of format errors) between the on-chip processor and the on-chip accelerator through centralized instruction parsing and data acquisition and transmission, and reduce communication and data transmission latency.

[0040] Figure 3 This is a flowchart illustrating the steps of another data processing method for a system-on-a-chip provided in an embodiment of the present invention. Figure 3 As shown, the data processing method of the system-on-chip may include steps 301-307.

[0041] Step 301: Obtain the first instruction information; the first instruction information is sent by the on-chip processor of the on-chip system to the on-chip acceleration controller; the first instruction information includes task instructions and first attribute information.

[0042] In the embodiments of this application, the specific implementation of step 301 can be referred to the relevant description of the specific implementation of step 101 above, and will not be repeated here.

[0043] Step 302: Convert the virtual address of the data to be processed into a physical address; the first attribute information includes the virtual address of the data to be processed.

[0044] Step 303: Obtain the data to be processed from the memory of the on-chip system according to the physical address.

[0045] In this embodiment, regarding steps 302-303, when the on-chip acceleration controller receives the first attribute information, the address information contained in the first attribute information is all virtual address. However, in the memory access channel constructed with the memory controller, physical addresses are required. Therefore, the on-chip acceleration controller needs to have the ability to translate virtual addresses to physical addresses to ensure that it can correctly access memory to obtain the data to be processed from the memory of the on-chip system. After obtaining the virtual address of the data to be processed, the on-chip acceleration controller can use its address translation unit (addr_trans) to translate the virtual address of the data to be processed into a physical address based on the virtual address of the data to be processed and an enable signal. The enable signal can be used to indicate the working state of the address translation unit. The on-chip acceleration controller can use the physical address to read the data to be processed from the memory of the on-chip system through the axi_bridge.

[0046] For example, Figure 4 This is a schematic diagram illustrating the virtual address to physical address conversion process provided in an embodiment of the present invention. Figure 4 As shown, the address translation unit converts a virtual address to a physical address and then feeds the conversion result back to the on-chip acceleration controller. The meanings of the signals during the conversion process are as follows: fetch (1 bit) indicates whether a virtual-to-physical address translation operation needs to be triggered; vaddr (32 bits) represents the virtual address to be converted; index (8 bits) represents the index portion of the physical address; tag (20 bits) represents the tag portion of the physical address; and offset (4 bits) represents the page offset portion of the physical address. For example, at or before the rising edge of the T0 clock, the on-chip acceleration controller can place the virtual address to be converted on the vaddr signal bus and set the fetch signal to a high level. After detecting that the fetch signal is high, the addr_trans module immediately starts the conversion logic to perform virtual-to-physical address mapping on the vaddr signal. After combinational logic delay (or lookup table access), addr_trans completes the conversion within the T0 cycle to obtain the corresponding physical address. The physical address can be decomposed into three fields: tag, index, and offset.

[0047] This embodiment converts the virtual address of the data to be processed into a physical address; based on the physical address, the data to be processed is retrieved from the memory of the on-chip system. Efficient and decoupled address translation can be achieved through explicit signal partitioning and timing control, resolving the incompatibility issue between software logic and hardware addressing rules. Furthermore, the accelerator agent only needs to provide the virtual address and request signal, without needing to concern itself with the translation details, thus reducing address translation latency and improving the real-time performance of address translation.

[0048] Step 304: Extract the key fields of the first instruction information.

[0049] Step 305: Convert key fields into hardware signals based on a preset mapping table.

[0050] Step 306: Convert the hardware signal into the first instruction signal according to the interface protocol of the on-chip accelerator.

[0051] In this embodiment, regarding steps 304-306, after obtaining the first instruction information, the on-chip accelerator controller can filter out fields directly related to the execution of the acceleration task from the first instruction information and filter out redundant auxiliary fields. Each extracted key field is converted into a hardware-recognizable level signal, i.e., the aforementioned hardware signal, through a preset mapping table; the preset mapping table can be understood as a correspondence table between the key fields built into the on-chip accelerator controller and the hardware signals. The hardware signal is a functional description, while the first instruction signal is a series of real electrical signals that strictly conform to the physical interface protocol and timing requirements of the target accelerator. According to the interface protocol of the on-chip accelerator, the aforementioned hardware signals can be assembled into a complete instruction signal according to the format order and level standard.

[0052] For example, the first instruction information may include Opcode: ACCELERATE (execute acceleration task), TaskID: 0x1001 (AI accelerator Gaussian blur task identifier), DataSize: 76800 (total number of bytes in the image to be processed), ResAddr: 0x5000_0000 (result address), and other auxiliary fields, such as check bits. Table 1 is a preset mapping table. The on-chip accelerator interface protocol requires the instruction signal format to be opcode (8 bits) + task identifier (16 bits) + data length (20 bits) + result address (32 bits), and the signal level must match the accelerator's LVCMOS interface standard.

[0053] Table 1

[0054] Then the key fields in the first instruction information can be extracted: Opcode=ACCELERATE, TaskID=0x1001, DataSize=76800, ResAddr=0x5000_0000, and the check digit and redundant description fields in the first instruction information can be filtered out. According to Table 1, Opcode=ACCELERATE is converted into an opcode hardware signal (8 bits, level: 0b00000001); TaskID=0x1001 is converted into a task identifier hardware signal (16 bits, level: 0b0001000000000001); DataSize=76800 is converted into a data length hardware signal (20 bits, level: 0b00010010110000000000); ResAddr=0x5000_0000 is converted into a result address hardware signal (32 bits, level: 0b01010000000000000000000000000). The hardware signals are concatenated into a 76-bit first instruction signal in the order of opcode (8 bits), task identifier (16 bits), data length (20 bits), and result address (32 bits) required by the protocol. At the same time, the level is adjusted to the LVCMOS level supported by the on-chip accelerator, and finally an instruction signal that can be directly recognized by the on-chip accelerator is obtained.

[0055] This embodiment extracts key fields from the first instruction information, identifying core fields strongly correlated with the acceleration task execution. This avoids the on-chip accelerator controller processing redundant information such as check bits and description fields in the first instruction information, reducing the computing power overhead of the on-chip accelerator controller, improving data processing efficiency, and preventing irrelevant fields from interfering with subsequent conversion processes. Converting key fields into hardware signals based on a preset mapping table reduces signal error rates caused by manual or random conversions. It also decouples software and hardware; the CPU sends software-level fields, while the hardware signals represent hardware-level voltage levels. The mapping table acts as a translation layer; changes to software fields only require updating the mapping table, without modifying the hardware circuitry. According to the on-chip accelerator's interface protocol, the hardware signals are converted into first instruction signals, and the signals are assembled according to the accelerator interface protocol. This ensures that the instruction signals can be correctly recognized and received by the accelerator, avoiding acceleration task execution failures due to voltage level mismatches or format errors.

[0056] Step 307: Send a third transaction interface signal to the on-chip accelerator of the system-on-chip; the third transaction interface signal is used to indicate that the data to be processed is in a readable state.

[0057] Step 308: In response to receiving the fourth transaction interface signal sent by the on-chip accelerator, send the data to be processed and the first instruction signal to the on-chip accelerator of the system on the chip, so that the on-chip accelerator can execute the data processing task for the data to be processed according to the task instruction; the fourth transaction interface signal is used to indicate that the on-chip accelerator is in a state where it can receive the data to be processed.

[0058] For example, regarding steps 307-308, Figure 5 This is a schematic diagram of data transmission in a data processing method for a system-on-a-chip provided in an embodiment of this application. For example... Figure 5 As shown, the meanings of each signal are as follows: id represents the communication transaction identifier, i.e., the task identifier mentioned above; res_addr represents the address where the execution result is stored, used for synchronous transmission when the on-chip accelerator sends feedback results to the accelerator agent; rsp_addr represents the address where the response message is stored, used for synchronous transmission when the accelerator sends feedback results to the accelerator agent; src_data_rdy indicates that the source operand (i.e., the data to be processed) is ready to be read by the on-chip accelerator, and src_data_rdy can be understood as the third transaction interface signal mentioned above; src_data represents the source operand, i.e., the data to be processed; src_vaild indicates that the on-chip accelerator is ready to receive data, and src_vaild can be understood as the fourth transaction interface signal; src_done indicates that the batch of data has been processed. The first instruction signal can include the aforementioned id, res_addr, and rsp_addr. Specifically, after the on-chip acceleration controller (i.e., the accelerator agent) sends the src_data_rdy signal, i.e. the third transaction interface signal, to the on-chip accelerator to indicate that the data to be processed is in a readable state, if it receives the src_vaild signal, i.e. the fourth transaction interface signal, sent to the on-chip accelerator, the accelerator agent can send the task identifier, result address, response address, and data to be processed for this task to the on-chip accelerator. When all the data to be processed for this task has been sent to the on-chip accelerator, the on-chip accelerator can send the src_done signal to the accelerator agent to indicate that all the data to be processed for this task has been sent to the on-chip accelerator.

[0059] Based on the above embodiments, for example, Figure 6 This is a schematic diagram of data transmission in another on-chip system data processing method provided in an embodiment of this application. For example... Figure 6As shown, the meanings of each signal are as follows: res_req indicates that the accelerator agent requests the on-chip accelerator to return the computation results; accepted_done indicates that the single batch of results has been stored in memory; id indicates the communication transaction identifier, i.e., the task identifier mentioned above; wr_vaddr indicates the address where the running results are stored, which is returned by the on-chip accelerator to the accelerator agent; rsp_vaddr indicates the address where the response message is stored, which is returned by the on-chip accelerator to the accelerator agent; res_vaild indicates that the results from the on-chip accelerator can be sent; res_data indicates the computation results from the on-chip accelerator; and finished indicates that all results from the on-chip accelerator have been sent. Specifically, when the accelerator agent sends the `res_req` signal to the on-chip accelerator to request feedback on the computation results, the on-chip accelerator can send a `res_vaild` signal to the accelerator agent to indicate that the results from the on-chip accelerator are ready to be sent; it can also send the task identifier, the address where the execution results are stored, the address where the response message is stored, and the computation results from the on-chip accelerator. After the computation results from the on-chip accelerator are sent, it can send a `finished` signal to the accelerator agent to indicate that all computation results for this task have been sent to the accelerator agent. After the computation results for this task are stored in memory, the accelerator agent can also send an `accepted_done` signal to the on-chip accelerator to indicate that the results for a single batch have been stored in memory.

[0060] This embodiment sends a third transaction interface signal to the on-chip accelerator of the system-on-a-chip (SoC). In response to receiving a fourth transaction interface signal from the on-chip accelerator, it sends data to be processed and a first instruction signal to the on-chip accelerator, enabling the on-chip accelerator to execute data processing tasks on the data to be processed according to the task instructions. The third transaction interface signal indicates that the data to be processed is in a readable state; the fourth transaction interface signal indicates that the on-chip accelerator is in a state where it can receive the data to be processed. After the accelerator agent sends the third transaction interface signal, other auxiliary logic (such as verifying data integrity and updating task status) can be processed synchronously without waiting for the accelerator to receive it. After receiving the third transaction interface signal, the accelerator completes preprocessing in parallel. Data or instruction transmission only begins when the accelerator sends the fourth transaction interface signal. The entire process involves no one-way waiting, improving parallel processing efficiency. Simultaneously, it transforms asynchronous interaction into a synchronously controllable process, avoiding transmission errors caused by hardware timing differences (such as the agent's transmission rate being faster than the accelerator's receiving rate), reducing timing conflicts during hardware debugging, and lowering the complexity of the interaction logic between the accelerator agent and the accelerator, thereby improving the stability of the SoC.

[0061] Step 309: In response to receiving the processed data and the second attribute information corresponding to the processed data sent by the on-chip accelerator, send a second instruction signal to the on-chip processor; the second instruction signal is used to indicate that the on-chip accelerator has completed the data processing task for the data to be processed according to the task instruction.

[0062] In this embodiment, the second attribute information may include the task identifier, address information, and data volume corresponding to the processed data. When the on-chip accelerator controller receives the processed data and the corresponding second attribute information from the on-chip accelerator, it can generate a second instruction signal and send it to the on-chip processor to notify the on-chip processor that the task has been completed.

[0063] For example, when the on-chip accelerometer receives the processed data and the corresponding second attribute information sent by the on-chip accelerometer, the on-chip accelerometer triggers a hardware interrupt line connected to the CPU interrupt controller. The CPU, which is executing other tasks, is interrupted by this interrupt, jumps to the corresponding interrupt service routine, reads the second instruction signal, confirms that the task has been successfully completed, and can then call the processed data for further processing (such as display, saving, etc.).

[0064] In this embodiment, in response to receiving the processed data and the corresponding second attribute information sent by the on-chip accelerator, a second instruction signal is sent to the on-chip processor. The CPU only needs to respond once after receiving the second instruction signal, and can focus on other core business for the rest of the time. That is, during the tens of microseconds or milliseconds of the accelerator's operation, the CPU can be completely freed up to execute other software tasks or schedule other accelerators, which greatly improves the overall throughput and resource utilization of the system.

[0065] Step 310: In response to receiving the processed data and the second attribute information corresponding to the processed data sent by the on-chip accelerator, generate the status information corresponding to the processed data.

[0066] In this embodiment, after receiving the processed data and the second attribute information, the on-chip accelerator controller can perform basic verification on the received processed data and the second attribute information. For example, it can verify whether the amount of processed data is consistent with the amount of data to be processed, whether the processed data has been tampered with, and whether there are execution errors inside the on-chip accelerator. After the verification is passed, it can generate status information corresponding to the processed data based on the verification result and the second attribute information. The status information corresponding to the processed data may include a status code, a task identifier corresponding to the processed data, and the amount of processed data, etc., wherein the status code indicates whether the task is successful.

[0067] Step 311: Store the processed data and the corresponding status information of the processed data into the memory of the on-chip system.

[0068] In this embodiment, after generating the status information corresponding to the processed data, the processed data and the status information corresponding to the processed data can be stored in the memory of the on-chip system through the on-chip interconnect bus protocol bridge. For example, the on-chip acceleration controller can write a response instruction at physical address 0x2468_A000, for example, Status is SUCCESS (status code, indicating task success), ID is 0x1001 (corresponding to the original task), and Res_Size is 76800 (confirmation result size).

[0069] In this embodiment, in response to receiving processed data and corresponding second attribute information from the on-chip accelerator, status information corresponding to the processed data is generated. The processed data and its corresponding status information are stored in the on-chip system memory. This allows the on-chip processor to obtain all key information by reading the status information address only once, eliminating the need to query multiple interfaces of the accelerator and memory separately, thus improving access efficiency. Furthermore, since the processed data and status information are stored in on-chip memory, the data is not lost even if the on-chip processor is suspended. The on-chip processor can subsequently read the status information at any time to confirm the task result before accessing the data, reducing the risk of data being overwritten due to delayed reading after the task is completed. Moreover, the storage logic is centralized in the on-chip accelerator controller. When replacing memory, only the memory interface parameters of the on-chip accelerator controller need to be adjusted. When adding an accelerator, only the process of generating status information and associated storage needs to be reused, without modifying the on-chip processor or existing on-chip accelerators, reducing expansion costs.

[0070] Optionally, step 311 above may include sub-steps 3111-3112.

[0071] Sub-step 3111: Send a storage request for the processed data and the corresponding status information to the on-chip interconnect bus protocol bridge, as well as the fifth transaction interface signal corresponding to the second attribute information.

[0072] Sub-step 3112: In response to receiving the sixth transaction interface signal sent by the on-chip interconnect bus protocol bridge, the on-chip interconnect bus protocol bridge stores the processed data and the corresponding status information of the processed data into the memory of the on-chip system according to the fifth transaction interface signal; the sixth transaction interface signal is used to indicate that the on-chip interconnect bus protocol bridge is in a state that can receive storage requests.

[0073] In this embodiment, the on-chip acceleration controller (i.e., the accelerator agent) can send a storage request to the AXI Bridge for the processed data and the corresponding status information. After the AXI Bridge is ready to receive the storage request, it can send a sixth transaction interface signal to the accelerator agent to indicate that the AXI Bridge is ready to receive the storage request. After receiving the sixth transaction interface signal, the accelerator agent can send a fifth transaction interface signal corresponding to the second attribute information, the processed data, and the corresponding status information to the AXI Bridge. The AXI Bridge can store the processed data and the corresponding status information into the memory of the on-chip system according to the fifth transaction interface signal. After storage is completed, the AXI Bridge can send a storage completion signal to the accelerator agent.

[0074] For example, Figure 7 This is a schematic diagram of an on-chip acceleration controller write interface design provided in an embodiment of this application. Figure 7 As shown, the meanings of each interface signal are as follows: wr_req indicates that the accelerator agent sends a write request to the AXI Bridge, which can be understood as a request to store the processed data and the corresponding status information; wr_size indicates the size of the data to be written in this write operation; wr_addr indicates the destination address to be written in this write operation; wr_wstrb indicates the write operation mask, used to identify the valid bytes of the written data; the above wr_size and wr_addr signals can be understood as the fifth transaction interface signal; wr_data indicates the data to be written, i.e., the processed data; wr_rdy indicates whether the AXI Bridge is ready to receive write requests, i.e., the sixth transaction interface signal mentioned above; wr_reqok indicates that the write request has been completed.

[0075] This embodiment sends a storage request for processed data and its corresponding status information, along with a fifth transaction interface signal corresponding to the second attribute information, to the on-chip interconnect bus protocol bridge. In response to receiving a sixth transaction interface signal from the on-chip interconnect bus protocol bridge, the bridge stores the processed data and its corresponding status information into the on-chip system's memory based on the fifth transaction interface signal. The sixth transaction interface signal indicates that the on-chip interconnect bus protocol bridge is in a state where it can receive storage requests. This allows the accelerator agent to interact with the AXI Bridge to complete the accelerator's memory write request. The accelerator agent interacts directly with memory, bypassing the CPU cache. This avoids occupying cache space and replacing CPU cache data, preventing a decrease in accelerator data read / write speed and a decrease in CPU memory hit rate due to cache re-flush. This maintains a high CPU memory hit rate, ensuring that the CPU's own tasks (such as interface rendering and user interaction) are not affected by the accelerator. At the same time, it avoids the limitation of memory access rate on cache capacity bottleneck. The accelerator's data read and write rate can directly match the memory bus bandwidth, reducing memory access latency under large data volume and ensuring the accelerator's continuous computing power output.

[0076] Optionally, the first attribute information includes the first data volume of the data to be processed, and step 303 above may include sub-step 3031.

[0077] Step 3031: Obtain the data to be processed from the memory of the on-chip system according to the second data volume based on the physical address.

[0078] In this embodiment, the first data volume is the total data volume of the data to be processed; the second data volume is the data volume of the data to be processed retrieved from the on-chip system's memory each time. For example, if the data to be processed is a 320×240 pixel grayscale image; the first data volume (total data volume) is 320×240×1 byte = 76800 bytes; the second data volume (data volume per read) is 128 bytes / read; the accelerator agent has obtained the physical address (e.g., 0x1234_5000) and needs to retrieve the image data from the on-chip memory. The accelerator agent does not read all 76800 bytes at once, but rather in 600 reads (76800÷128), that is, 128 bytes are read from the physical address segment of memory each time. After reading, the data is streamed to the on-chip accelerator until all 76800 bytes of data are transmitted.

[0079] In this embodiment, data to be processed is obtained from the memory of the on-chip system according to the physical address and the second data volume. The data is read in blocks according to the second data volume and aligned with the accelerator processing capability. This enables data computation and data transmission to be performed in parallel, thereby reducing end-to-end latency and enhancing the real-time response capability of the on-chip system.

[0080] Optionally, the above method may also include steps 312-313.

[0081] Step 312: Send a request to acquire the data to be processed and the first transaction interface signal corresponding to the first attribute information to the on-chip interconnect bus protocol bridge; Step 313: In response to receiving the second transaction interface signal sent by the on-chip interconnect bus protocol bridge, the on-chip interconnect bus protocol bridge retrieves the data to be processed from the memory of the on-chip system according to the first transaction interface signal; the second transaction interface signal is used to indicate that the on-chip interconnect bus protocol bridge is in a state where it can receive the data to be processed retrieval request.

[0082] In this embodiment, the on-chip acceleration controller (i.e., the accelerator agent) can send a request to the AXI Bridge to acquire data to be processed. After the AXI Bridge is ready to receive the acquisition request, it can send a second transaction interface signal to the accelerator agent to indicate that the AXI Bridge is ready to receive the acquisition request. After receiving the second transaction interface signal, the accelerator agent can send the first transaction interface signal data to be processed corresponding to the first attribute information to the AXI Bridge. The AXI Bridge can acquire the data to be processed from the memory of the on-chip system according to the first transaction interface signal. At the same time, the AXI Bridge can send a validity signal to the accelerator agent to indicate whether the acquired data is valid, and can also send a termination confirmation signal for the read request to the accelerator agent to indicate whether the acquired data is the last byte of this read request.

[0083] For example, Figure 8 This is a schematic diagram of an on-chip acceleration controller read interface design provided in an embodiment of this application. Figure 8 As shown, the meanings of each interface signal are as follows: rd_req represents a read request sent by the accelerator agent to Axi_Bridge, i.e., a request to obtain data to be processed; rd_size represents the size of the data to be read in this read operation; rd_addr represents the target address to be read in this read operation; the above rd_size and rd_addr signals can be understood as the first transaction interface signals; ret_ready represents whether Axi_Bridge is ready to receive read requests, i.e., the above second transaction interface signal; ret_valid represents whether the obtained data is valid; ret_last represents whether the obtained data is the last byte of this read request; ret_data represents the obtained data, i.e., the data to be processed.

[0084] This embodiment sends a request to acquire data to be processed and a first transaction interface signal corresponding to the first attribute information to the on-chip interconnect bus protocol bridge. In response to receiving a second transaction interface signal from the on-chip interconnect bus protocol bridge, the on-chip interconnect bus protocol bridge acquires the data to be processed from the on-chip system memory according to the first transaction interface signal. The second transaction interface signal indicates that the on-chip interconnect bus protocol bridge is in a state where it can receive requests to acquire data to be processed. This allows accelerator agents to interact with the AXI Bridge to complete accelerator-side memory read requests, preventing a decrease in accelerator data read / write speed and a decrease in CPU memory access hit rate due to cache re-flush. A standardized interface protocol is defined, enabling data interoperability between accelerator agents with incompatible interface protocols and memory. Accelerator agents do not need to adapt to different memory bus protocols; they only need to maintain a unified transaction interface with the bridge. There is no need to modify the accelerator agent's hardware interface to adapt to the memory bus. When a new bus protocol or new device is connected, only the bridge needs to be updated, enhancing system compatibility and stability, ensuring interoperability between different hardware, and improving the convenience of integrating and maintaining devices with different protocols. Meanwhile, the handshake logic between the bridge's readiness and the proxy's request ensures that each acquisition request is correctly received by the bridge, thus improving the success rate of data transmission.

[0085] Optionally, the above method further includes steps 314-315.

[0086] Step 314: When the on-chip accelerator executes a data processing task for the data to be processed according to the task instruction, in response to receiving the second instruction information sent by the on-chip processor, the second instruction information is converted into a second instruction signal.

[0087] Step 315: Send a second instruction signal to the on-chip accelerator of the system-on-chip to instruct the on-chip accelerator to suspend the execution of data processing tasks.

[0088] In this embodiment, for steps 314-315, the second command signal is matched with the on-chip accelerator of the system-on-a-chip; the second command signal is used to instruct the on-chip accelerator to suspend the execution of data processing tasks. After receiving the pause command from the user terminal, the on-chip accelerator controller can send a pause signal to the designated on-chip accelerator to stop the internal operation process of the on-chip accelerator and restore it to an idle state. To this end, the on-chip accelerator controller can pull the signal high to instruct the accelerator to pause its current work. At the same time, the connected on-chip accelerator needs to provide dedicated logic processing to ensure that it can correctly identify and respond to the pause signal and maintain the real-time validity of the signal.

[0089] In one optional embodiment, the accelerator agent can periodically check the liveness status of a designated accelerator through a heartbeat detection mechanism. Specifically, the connected accelerator needs to send heartbeat response data to the accelerator agent every n cycles, where n is a preset positive integer. This heartbeat signal requires dedicated processing logic to ensure that the signal accurately reflects the accelerator's operating status and provides timely feedback.

[0090] For example, Figure 9 This is a schematic diagram illustrating the interaction between an on-chip acceleration controller and an on-chip accelerator, provided as an embodiment of this application. Figure 9 As shown, the accelerator agent can send a stop request signal (stop_req) to the accelerator, requesting the accelerator to immediately stop the currently executing acceleration task (e.g., triggered by a task error or a CPU emergency interrupt). Upon receiving the stop_req signal, the accelerator can send a stop completion response signal (stop_done) to the accelerator agent. stop_done can be understood as feedback to stop_req, indicating that the accelerator has completed the stopping operation. The accelerator agent can periodically check the liveness status of a specified accelerator through a heartbeat detection mechanism. For example, the accelerator can periodically send heartbeat message signals (heart_mes) to the accelerator agent to report its own running status.

[0091] In this embodiment, when the on-chip accelerator executes a data processing task for the data to be processed according to the task instructions, in response to receiving a second instruction information sent by the on-chip processor, the second instruction information is converted into a second instruction signal, and then sent to the on-chip accelerator of the on-chip system to instruct the on-chip accelerator to suspend the execution of the data processing task. The second instruction signal is matched with the on-chip accelerator of the on-chip system; the second instruction signal is used to instruct the on-chip accelerator to suspend the execution of the data processing task. This allows for priority response to the processor's urgent or high-priority needs, preventing low-priority tasks (such as Gaussian blur) from occupying accelerator computing power for extended periods, thus avoiding the blocking of high-priority tasks (such as user interaction operations), and improving the real-time interactive experience of the on-chip system. Simultaneously, it prevents the accelerator from wasting computing power on processing invalid or erroneous data, improving the utilization rate of on-chip computing resources.

[0092] This application also provides a system-on-a-chip (SoC) embodiment. Figure 10 This is a schematic diagram of an on-chip system architecture provided in an embodiment of this application. For example... Figure 10 As shown, the system-on-a-chip may include an on-chip accelerator, an on-chip acceleration controller, and an on-chip processor.

[0093] In this embodiment, the on-chip acceleration controller can be understood as an accelerator agent, and the on-chip processor can be understood as a CPU. The on-chip accelerator, accelerator agent, and CPU can be integrated on the same chip. The on-chip acceleration controller includes an address translation unit (addr_trans), which can be used to convert the virtual address of the data to be processed into a physical address. The accelerator agent and the CPU can exchange commands, which can be in the form of instruction messages. The on-chip accelerator and the accelerator agent can exchange data. The accelerator agent and memory can read and write data via an on-chip interconnect bus protocol bridge (AXI Bridge).

[0094] The on-chip processor is used to send first instruction information to the on-chip acceleration controller of the system-on-chip; the first instruction information includes task instructions and first attribute information.

[0095] The on-chip accelerator controller is used to acquire first instruction information; acquire data to be processed from the memory of the on-chip system according to first attribute information; convert the first instruction information into a first instruction signal; match the first instruction signal with the on-chip accelerator of the on-chip system; and send the data to be processed and the first instruction signal to the on-chip accelerator of the on-chip system.

[0096] In this embodiment, the accelerator agent can be understood as an on-chip, enhanced peripheral controller combined with a Direct Memory Access (DMA) controller, but with some differences. Regarding the peripheral controller portion, the accelerator agent differs from the peripheral controller in that: the accelerator agent can interact with multiple accelerators, requires routing, and indicates the accelerator via an ID session identifier; the accelerator agent uses opcodes to describe the computational tasks that need to be executed by the accelerator; the peripheral controller operates the device by reading and writing control / status registers. Regarding the DMA controller portion, the accelerator agent has an additional address translation module (addr_trans) compared to the DMA controller. This address translation can be understood as an external, on-chip memory management unit (MMU) dedicated to the accelerator agent.

[0097] The on-chip accelerator is used to perform data processing tasks on the data to be processed according to the task instructions.

[0098] This application also provides a system-on-a-chip data processing device. Figure 11 This is a structural block diagram of a data processing device for a system-on-a-chip provided in an embodiment of this application. For example... Figure 11 As shown, the data processing device 1100 of the system-on-a-chip may include: an acquisition module 1101, a conversion module 1102, and a transmission module 1103.

[0099] The acquisition module 1101 is used to acquire first instruction information; the first instruction information is sent by the on-chip processor of the on-chip system to the on-chip acceleration controller; the first instruction information includes task instructions and first attribute information. The acquisition module 1101 is also used to acquire the data to be processed from the memory of the on-chip system based on the first attribute information; Conversion module 1102 is used to convert the first instruction information into a first instruction signal; the first instruction signal is matched with the on-chip accelerator of the on-chip system; The sending module 1103 is used to send the data to be processed and the first instruction signal to the on-chip accelerator of the on-chip system, so that the on-chip accelerator can perform data processing tasks on the data to be processed according to the task instructions.

[0100] Optionally, the first attribute information includes the virtual address of the data to be processed; the acquisition module 1101 is specifically used to convert the virtual address of the data to be processed into a physical address; and to acquire the data to be processed from the memory of the on-chip system according to the physical address.

[0101] Optionally, the first attribute information includes a first data volume of the data to be processed; the acquisition module 1101 is specifically used to acquire the data to be processed from the memory of the on-chip system according to the physical address and a second data volume; the first data volume is the total data volume of the data to be processed; the second data volume is the data volume of the data to be processed acquired from the memory of the on-chip system each time.

[0102] Optionally, the acquisition module 1101 is specifically used to send an acquisition request for the data to be processed and a first transaction interface signal corresponding to the first attribute information to the on-chip interconnect bus protocol bridge; in response to receiving a second transaction interface signal sent by the on-chip interconnect bus protocol bridge, the on-chip interconnect bus protocol bridge acquires the data to be processed from the memory of the on-chip system according to the first transaction interface signal; the second transaction interface signal is used to indicate that the on-chip interconnect bus protocol bridge is in a state where it can receive the acquisition request for the data to be processed.

[0103] Optionally, the conversion module 1102 is specifically used to extract key fields of the first instruction information; convert the key fields into hardware signals based on a preset mapping table; and convert the hardware signals into the first instruction signal according to the interface protocol of the on-chip accelerator.

[0104] Optionally, the sending module 1103 is specifically used to send a third transaction interface signal to the on-chip accelerator of the system-on-a-chip; the third transaction interface signal is used to indicate that the data to be processed is in a readable state; in response to receiving the fourth transaction interface signal sent by the on-chip accelerator, the module sends the data to be processed and a first instruction signal to the on-chip accelerator of the system-on-a-chip, so that the on-chip accelerator can execute a data processing task for the data to be processed according to the task instruction; the fourth transaction interface signal is used to indicate that the on-chip accelerator is in a state where it can receive the data to be processed.

[0105] Optionally, the sending module 1103 is further configured to send a second instruction signal to the on-chip processor in response to receiving the processed data and the second attribute information corresponding to the processed data sent by the on-chip accelerator; the second instruction signal is used to indicate that the on-chip accelerator has completed the data processing task for the data to be processed according to the task instruction.

[0106] Optionally, such as Figure 11 As shown, the data processing device 1100 of the system-on-chip may further include: a storage module 1104.

[0107] The storage module 1104 is used to generate status information corresponding to the processed data in response to receiving the processed data and the second attribute information corresponding to the processed data sent by the on-chip accelerator; and to store the processed data and the status information corresponding to the processed data in the memory of the on-chip system.

[0108] Optionally, the storage module 1104 is specifically used to send a storage request for processed data and the status information corresponding to the processed data, as well as a fifth transaction interface signal corresponding to the second attribute information, to the on-chip interconnect bus protocol bridge; in response to receiving a sixth transaction interface signal sent by the on-chip interconnect bus protocol bridge, the on-chip interconnect bus protocol bridge stores the processed data and the status information corresponding to the processed data into the memory of the on-chip system according to the fifth transaction interface signal; the sixth transaction interface signal is used to indicate that the on-chip interconnect bus protocol bridge is in a state that can receive storage requests.

[0109] Optionally, the conversion module 1102 is further configured to, in response to receiving a second instruction information sent by the on-chip processor, convert the second instruction information into a second instruction signal when the on-chip accelerator is executing a data processing task for the data to be processed according to the task instruction; the second instruction signal is matched with the on-chip accelerator of the system on the chip; the second instruction signal is used to instruct the on-chip accelerator to suspend the execution of the data processing task; the sending module 1103 is further configured to send the second instruction signal to the on-chip accelerator of the system on the chip to instruct the on-chip accelerator to suspend the execution of the data processing task.

[0110] This application also provides an electronic device, with reference to... Figure 12 , Figure 12This is a structural block diagram of an electronic device for data processing in a system-on-a-chip, provided in an embodiment of this application. For example... Figure 12 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store executable instructions, which cause the processor to execute the image processing method of the aforementioned embodiment.

[0111] The processor can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0112] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 12 The symbol is represented by only one line, but this does not mean that there is only one bus or one type of bus.

[0113] This application also provides a non-transitory computer-readable storage medium, which, when the instructions in the storage medium are executed by the processor of an electronic device (server or terminal), enables the processor to perform... Figure 1 or Figure 3 The data processing method of the on-chip system is shown.

[0114] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0115] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0116] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0117] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0118] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0119] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0120] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0121] The foregoing has provided a detailed description of a data processing method, apparatus, electronic device, system-on-a-chip, and computer-readable storage medium for a system-on-a-chip. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A data processing method for a system-on-a-chip, characterized in that, The method, applied to the on-chip acceleration controller of the system-on-chip, includes: Obtain first instruction information; the first instruction information is sent by the on-chip processor of the on-chip system to the on-chip acceleration controller; the first instruction information includes task instructions and first attribute information; Based on the first attribute information, the data to be processed is obtained from the memory of the on-chip system; The first instruction information is converted into a first instruction signal; the first instruction signal is matched with the on-chip accelerator of the system-on-chip. The system sends the data to be processed and the first instruction signal to the on-chip accelerator of the system-on-chip, so that the on-chip accelerator can execute a data processing task for the data to be processed according to the task instruction.

2. The method according to claim 1, characterized in that, The first attribute information includes the virtual address of the data to be processed. The step of obtaining the data to be processed from the memory of the on-chip system based on the first attribute information includes: Convert the virtual address of the data to be processed into a physical address; The data to be processed is obtained from the memory of the on-chip system based on the physical address.

3. The method according to claim 2, characterized in that, The first attribute information includes a first data volume of the data to be processed. The step of retrieving the data to be processed from the memory of the on-chip system based on the physical address includes: Based on the physical address, the data to be processed is obtained from the memory of the system-on-chip according to a second data amount; the first data amount is the total data amount of the data to be processed; the second data amount is the data amount of the data to be processed obtained from the memory of the system-on-chip each time.

4. The method according to claim 1, characterized in that, The step of obtaining the data to be processed from the memory of the on-chip system based on the first attribute information includes: Send the request to acquire the data to be processed and the first transaction interface signal corresponding to the first attribute information to the on-chip interconnect bus protocol bridge; In response to receiving a second transaction interface signal sent by the on-chip interconnect bus protocol bridge, the on-chip interconnect bus protocol bridge retrieves the data to be processed from the memory of the on-chip system according to the first transaction interface signal; the second transaction interface signal is used to indicate that the on-chip interconnect bus protocol bridge is in a state where it can receive the request to retrieve the data to be processed.

5. The method according to claim 1, characterized in that, The step of converting the first instruction information into a first instruction signal includes: Extract the key fields from the first instruction information; The key fields are converted into hardware signals based on a preset mapping table; According to the interface protocol of the on-chip accelerator, the hardware signal is converted into the first instruction signal.

6. The method according to claim 1, characterized in that, Sending the data to be processed and the first instruction signal to the on-chip accelerator of the on-chip system, so that the on-chip accelerator can execute a data processing task for the data to be processed according to the task instruction, includes: The third transaction interface signal is sent to the on-chip accelerator of the system-on-chip; the third transaction interface signal is used to indicate that the data to be processed is in a readable state. In response to receiving the fourth transaction interface signal sent by the on-chip accelerator, the system sends the data to be processed and the first instruction signal to the on-chip accelerator, so that the on-chip accelerator can execute a data processing task for the data to be processed according to the task instruction; the fourth transaction interface signal is used to indicate that the on-chip accelerator is in a state where it can receive the data to be processed.

7. The method according to claim 1, characterized in that, The method further includes: In response to receiving processed data and corresponding second attribute information from the on-chip accelerator, a second instruction signal is sent to the on-chip processor; the second instruction signal indicates that the on-chip accelerator has completed the data processing task for the data to be processed according to the task instruction.

8. The method according to claim 1, characterized in that, The method further includes: In response to receiving the processed data and the second attribute information corresponding to the processed data sent by the on-chip accelerator, status information corresponding to the processed data is generated; The processed data and the corresponding status information are stored in the memory of the on-chip system.

9. The method according to claim 8, characterized in that, The step of storing the processed data and the corresponding status information into the memory of the on-chip system includes: Send a storage request for the processed data and the status information corresponding to the processed data, as well as a fifth transaction interface signal corresponding to the second attribute information, to the on-chip interconnect bus protocol bridge. In response to receiving the sixth transaction interface signal sent by the on-chip interconnect bus protocol bridge, the on-chip interconnect bus protocol bridge stores the processed data and the corresponding status information of the processed data into the memory of the on-chip system according to the fifth transaction interface signal; the sixth transaction interface signal is used to indicate that the on-chip interconnect bus protocol bridge is in a state that can receive the storage request.

10. The method according to claim 1, characterized in that, The method further includes: When the on-chip accelerator executes a data processing task for the data to be processed according to the task instruction, in response to receiving a second instruction information sent by the on-chip processor, the second instruction information is converted into a second instruction signal; the second instruction signal is matched with the on-chip accelerator of the system on chip; the second instruction signal is used to instruct the on-chip accelerator to suspend the execution of the data processing task; The second instruction signal is sent to the on-chip accelerator of the system-on-chip to instruct the on-chip accelerator to suspend the execution of the data processing task.

11. A system-on-a-chip, the system-on-a-chip comprising an on-chip accelerator, an on-chip acceleration controller, and an on-chip processor; The on-chip processor is used to send first instruction information to the on-chip acceleration controller of the system-on-chip; the first instruction information includes task instructions and first attribute information. The on-chip acceleration controller is used to acquire first instruction information; acquire the data to be processed from the memory of the on-chip system according to the first attribute information; convert the first instruction information into a first instruction signal; match the first instruction signal with the on-chip accelerator of the on-chip system; and send the data to be processed and the first instruction signal to the on-chip accelerator of the on-chip system. The on-chip accelerator is used to execute data processing tasks for the data to be processed according to the task instructions.

12. A data processing device for a system-on-a-chip, characterized in that, The device includes: An acquisition module is used to acquire first instruction information; the first instruction information is sent by the on-chip processor of the on-chip system to the on-chip acceleration controller; the first instruction information includes task instructions and first attribute information; The acquisition module is further configured to acquire the data to be processed from the memory of the on-chip system based on the first attribute information; A conversion module is used to convert the first instruction information into a first instruction signal; the first instruction signal is matched with the on-chip accelerator of the system-on-chip. The sending module is used to send the data to be processed and the first instruction signal to the on-chip accelerator of the system-on-chip, so that the on-chip accelerator can execute a data processing task for the data to be processed according to the task instruction.

13. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the method as described in any one of claims 1 to 10.

14. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is enabled to perform the method as described in any one of claims 1 to 10.

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