Scale-adaptive logic comprehensive optimization circuit representation learning method

Abstract

The invention discloses a scale-adaptive logic comprehensive optimization circuit representation learning method, and belongs to the technical field of integrated circuit design automation. Comprising the following steps: constructing circuit diagram data, and extracting node features, edge connection relationships and node depth information; a scale adaptive graph encoder is constructed, a double-layer GCN and a multi-scale feature fusion module are adopted, and scale adaptive node representation is generated through multi-hop neighborhood aggregation, circuit perception gating and attention fusion; performing hierarchical pooling based on the node depth to construct a hierarchical graph sequence; carrying out embedded coding on the optimized sequence and injecting position information to obtain sequence representation; establishing bidirectional association between a circuit structure and optimization steps through a dynamic graph-sequence adaptive interaction module, and generating a context sensing target sequence; and a Transform decoder is used for carrying out sequence modeling and predicting a quality result track. According to the method, through scale self-adaption and a dynamic interaction mechanism, the problems of representation learning and optimization dynamic modeling of a heterogeneous scale circuit are solved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design automation technology, and specifically relates to a scale-adaptive logic synthesis optimization circuit representation learning method. Background Technology

[0002] Logic synthesis optimization is a critical step in the Electronic Design Automation (EDA) workflow, improving circuit quality through systematic representation-guided transformations of And-Inverter Graph (AIG) circuits. The effectiveness of logic synthesis optimization fundamentally relies on learning a comprehensive circuit representation capable of capturing structural features crucial to guiding optimization decisions. However, the exponentially expanding search space in logic synthesis makes exhaustive exploration impractical, as heuristic algorithms can generate millions of sequences. Therefore, developing expressive and generalizable circuit representations is key to effectively guiding sequence optimization.

[0003] To meet this need, recent research has leveraged machine learning models to extract AIG structural features through message passing mechanisms. Early works such as OpenABC utilized a combined Graph Convolutional Network (GCN) and Convolutional Neural Network (CNN) architecture. Subsequent efforts, such as LOSTIN, employed Graph Isomorphic Networks (GIN) and Long Short-Term Memory (LSTM) networks for sequence modeling, while GraphSAGE-Transformer explored Transformer-based sequence encoding. The latest LSOformer further improved performance by using a causal Transformer with predictive self-supervised learning to model and optimize trajectories.

[0004] Despite these advances, real-world logic synthesis involves circuits with highly heterogeneous scales and dynamically evolving topologies, which presents two main challenges to previous representation learning methods:

[0005] Challenge 1: Heterogeneous Scale Bottleneck in Circuit Representation

[0006] In practical logic synthesis optimization, circuits exhibit significant scale heterogeneity, with the number of nodes ranging from hundreds to millions. Existing encoders suffer from oversmoothing issues on large-scale circuits and global context loss issues on small-scale circuits. Specifically, this manifests as follows:

[0007] (1) Over-smoothing of large-scale circuits: When a circuit contains tens of thousands or even hundreds of thousands of logic gates, traditional graph neural networks will cause the node features to become homogeneous after multi-layer message passing, making the model unable to distinguish the functional roles of different nodes and losing the ability to finely model local circuit patterns.

[0008] (2) Insufficient global information for small-scale circuits: For small-scale circuits containing only a few hundred nodes, the limited number of message passing hops cannot cover the global propagation path of the entire circuit, causing the model to only capture local neighborhood features and ignore long-range dependencies and global topology patterns across multiple levels.

[0009] Challenge 2: Optimizing the dynamic bottleneck in circuit representation

[0010] In practical logic synthesis optimization workflows, each synthesis step substantially alters the circuit topology and electrical characteristics. This dynamic evolution continuously changes structural properties, but existing methods struggle to model these changes, limiting their ability to capture the bidirectional dependency between circuit states and optimization strategies. Specifically:

[0011] (1) Limitations of static encoding: Existing methods typically encode the graph structure and optimization sequence independently before sequence decoding, employing a late-stage fusion strategy. This approach makes the circuit representation unable to perceive the semantics of the optimization sequence, nor can it dynamically adjust according to the specific requirements of the current optimization step, resulting in insufficient modeling capability for circuit state evolution.

[0012] (2) Lack of step-aware representation: Different optimization operations in logic synthesis have significantly different effects on the circuit. For example, algebraic rewriting mainly affects the local subgraph structure, while balancing optimization reconstructs the depth distribution of the entire circuit. However, existing methods cannot dynamically adjust the focus of the circuit representation according to the semantic characteristics of the current optimization step.

[0013] In summary, there is a need for a circuit representation learning method that can simultaneously address both heterogeneous scale bottlenecks and optimization dynamic bottlenecks, in order to provide consistent and effective optimization guidance across circuits at different scales and optimization stages. Summary of the Invention

[0014] The purpose of this invention is to provide a scale-adaptive circuit representation learning method for logic synthesis optimization, overcoming the shortcomings of existing technologies such as insufficient heterogeneous scale processing capabilities and static encoding limitations. Through multi-scale feature fusion and a dynamic graph-sequence interaction mechanism, it achieves high-precision, adaptive, and highly generalizable circuit quality result prediction, applicable to the logic synthesis optimization stage in digital circuit design. This invention's method is used to learn scale-adaptive circuit representations to predict optimization quality results and can be applied to the logic synthesis optimization stage in digital circuit design.

[0015] The technical solution of this invention:

[0016] A scale-adaptive logic synthesis optimization circuit representation learning method includes the following steps:

[0017] Step (1): Circuit diagram data construction

[0018] The circuit structure and sequence information are extracted from the logic circuit file to be optimized and the optimization sequence to construct a graph data representation G1. First, the input logic circuit C is parsed, and all logic gates are extracted to form a node set V. The type of each logic gate is identified, and an initial node feature matrix X is generated through an embedding layer. Then, the connection relationships between logic gates are extracted to form an edge set E, generating an edge index matrix E_index. Simultaneously, the depth information of each node in the circuit is extracted to form a node depth vector D_node. For the optimization sequence R, the heuristic operations are mapped to an integer index sequence, forming a sequence index matrix R_indices. Finally, the node set V, edge set E, node feature matrix X, edge index matrix E_index, node depth vector D_node, sequence index matrix R_indices, and quality result trajectory Y_trajectory are combined to form the graph data G1, completing the transformation from circuit and sequence to structured data.

[0019] Step (2): Construction of the scale-adaptive graph encoder

[0020] A graph encoder model E_msff with multi-scale feature fusion capability is constructed. This model contains four cascaded functional layers that form a complete feature extraction pipeline through explicit input and output interfaces.

[0021] First, a basic feature extraction layer is constructed, consisting of a two-layer graph convolutional network (GCN). The first layer, GCN1, receives the node feature matrix X (dimension N×D_in) and the edge index matrix E_index as input. It then performs message passing and ReLU activation through the weight matrix W_gcn1, outputting the first-layer embedding (dimension N×d_h). The second layer, GCN2, receives the output from the first layer and further extracts topological features through the weight matrix W_gcn2, outputting the initial node embedding H. (0) (Dimension N×d_h).

[0022] Then, a multi-scale aggregation layer is constructed, containing K parallel jump-specific transformation branches. This layer receives H... (0) Using E_index as input, each branch k aggregates k-hop neighborhood information through k scattering averaging operations to obtain M. (k) Then, after passing through the Transform_k layer (weights W_k and bias b_k), the k-th hop feature F is output. (k) (Dimension N×d_h), K branches output {F in parallel (1) ,F (2) ,...,F (k)}

[0023] Next, a scale-aware modulation layer is constructed, consisting of a circuit-aware gating network and a gating modulation module. The gating network receives a normalized scale feature vector s (containing the number of nodes s_n and the maximum depth s_d), and outputs K-dimensional gating weights g∈[0,1] through two MLP layers (weights W_g1 and W_g2). K The gated modulation module receives {F} (1) ,...,F (k)} and g, for each F (k) Perform element-wise scaling Output gating features .

[0024] Finally, a feature fusion layer is constructed, consisting of an attention network and a projection layer connected in series. The attention network receives... The concatenation is into F_concat (dimension N×Kd_h), and the attention weight α (dimension N×K) is calculated through weight W_att and Softmax. The weighted fusion is then used to obtain F_weighted. The projection layer receives F_weighted and linearly transforms it into H_msf (dimension N×d_h) through weight W_fusion and bias b_fusion.

[0025] The above four layers are connected in series via data flow: This achieves an end-to-end mapping from the original feature X to the scale-adaptive representation H_msf, with H_msf being passed as the encoder output to step (3).

[0026] Step (3): Multi-scale feature fusion and scale-adaptive node representation generation

[0027] The circuit diagram in graph data G1 is input into encoder E_msff, and scale-adaptive node representation H_msf is generated through multi-hop neighborhood aggregation, circuit-aware gating, and attention fusion. First, the node feature matrix X and edge index matrix E_index are input into a two-layer GCN. After ReLU activation in the first layer GCN1 and processing in the second layer GCN2, the initial node embedding H is obtained. (0) Then, the multi-hop neighborhood aggregation process is initiated, setting the current feature H_current equal to H. (0) For each hop k from 1 to K, the neighbor features are aggregated by performing a scattering averaging operation along the edge to obtain M. (k) Then, after passing through a specific transformation layer, the k-th hop feature F is obtained. (k) Simultaneously, circuit scale information is extracted from the node depth vector D_node, and the normalized number of nodes s_n and the normalized maximum depth s_d are calculated to form a scale feature vector s, which is input into the circuit-aware gating network to obtain a K-dimensional gating weight vector g. For each hop feature F (k) Apply the corresponding gating weight g_k to perform element-wise scaling to obtain the gated features. Next, all gated hop features are concatenated along the feature dimension. An attention weight vector α for each node on different hops is obtained through an attention weight calculation layer. Then, the attention weights are weighted and fused with the gated features. Finally, a feature projection layer maps the fused features back to the hidden dimension, yielding the scale-adaptive node representation H_msf. This representation dynamically balances local details and global structure, providing adaptive features for circuits at different scales.

[0028] Step (4): Construction of hierarchical graph sequence

[0029] Based on the scale-adaptive node representation H_msf and the node depth vector D_node, a hierarchical graph sequence representation Z_graph is constructed through hierarchical pooling operations. First, the maximum depth value max_depth of the circuit is obtained from the node depth vector D_node, determining that the circuit has L_g = max_depth + 1 levels. Then, for each level (level from 0 to max_depth), a node mask mask_level is created to identify all nodes with a depth equal to level. If a node exists in a level, the embeddings of all nodes in that level are extracted from H_msf, and the mean pooling feature mean_pool and max pooling feature max_pool are calculated respectively. These two are concatenated along the feature dimension to obtain the embedding vector emb_level for that level. If no node exists in a level, zero vectors are used to fill the space. The embedding vectors of all levels are stacked in hierarchical order to form the hierarchical graph sequence Z_graph, with a dimension of L_g × 2d_h, where d_h is the hidden dimension. This hierarchical graph sequence captures the multi-level topological features of the circuit from the input layer to the output layer.

[0030] Step (5): Sequence Encoding and Position Information Injection

[0031] The optimized sequence is embedded and encoded, and positional information is injected to generate a sequence representation H_recipe containing temporal semantics. First, the sequence index matrix R_indices, with dimensions B×L_r, is extracted from the graph data G1, where B is the batch size and L_r is the sequence length. R_indices is then input into the sequence embedding layer RecipeEmbedding, which contains an embedding matrix that maps the integer indices of each heuristic operation to a 2d_h-dimensional embedding vector, resulting in a sequence embedding matrix with dimensions B×L_r×2d_h. Then, a positional encoding matrix PE is constructed, which encodes the sequence positional information using sine and cosine functions. For position pos and dimension i, the encoded value is sin(pos / 10000). (2i / 2d_h) ) or cos(pos / 10000) (2i / 2d_h)The first L_r rows of the position encoding matrix PE are extracted and added element-wise to the sequence embedding matrix to obtain the sequence representation H_recipe with injected position information. Optionally, a Dropout operation can be applied to H_recipe to prevent overfitting. This representation not only contains the semantic information of each optimization operation but also encodes the relative positional relationships of the operations within the sequence.

[0032] Step (6): Dynamic Graph-Sequence Adaptive Interaction

[0033] A bidirectional association between the optimization sequence and the circuit diagram structure is established through a dynamic interaction mechanism to generate a step-aware dynamic circuit representation H_tgt. First, it is extracted from the sequence representation H_recipe and transposed to L_r×B×2d_h for subsequent processing. It is also extracted from the hierarchical graph sequence Z_graph and expanded along the batch dimension to L_g×B×2d_h. The expanded graph sequence is then input into a graph context aggregation network, which includes a linear transformation layer and a ReLU activation function. After a learnable transformation, the graph sequence is mean-pooled along the hierarchical dimension to obtain a global graph context vector G_global with dimensions 1×B×2d_h. G_global is expanded along the sequence length dimension to L_r×B×2d_h to obtain G_expand. Simultaneously, the transposed sequence representation is input into a step context extraction network, which contains two MLP layers. Through linear transformation, ReLU activation, and a second linear transformation, a compact context representation C_step with dimensions L_r×B×2d_h is extracted for each optimization step. Next, a step-aware modulation network concatenates G_expand and C_step along the feature dimension. After linear transformation and Tanh activation, a modulated graph representation G_mod is generated, which integrates global circuit structure information and the semantic intent of the current optimization step. Further, the sequence representation, modulated graph representation, and step context are concatenated and input into an adaptive gating network. This network calculates the gating weights g_adaptive through linear transformation and Sigmoid activation, and then performs element-wise weighting on G_mod to obtain the gated graph representation G_gated. Finally, a feature fusion layer concatenates the sequence representation and G_gated and performs a linear transformation to obtain the context-aware target sequence H_tgt, with dimensions L_r×B×2d_h. This representation integrates circuit structure knowledge and optimization sequence semantics, realizing a dynamic association between circuit states and optimization strategies.

[0034] Step (7): Transformer Decoding and Quality Result Trajectory Prediction

[0035] Sequence modeling of the dynamic interaction representation is performed using a multi-layer Transformer decoder to predict the quality outcome trajectory Ŷ during the optimization process. First, a causal attention mask M_causal is generated based on the sequence length L_r. This mask is an upper triangular matrix, ensuring that each time step only focuses on the current and previous steps. The context-aware target sequence is obtained from the dynamic interaction representation H_tgt, and the hierarchical representation is obtained from the hierarchical graph sequence Z_graph, with dimensions L_g×2d_h, expanded along the batch dimension (the first dimension) to L_g×B×2d_h, so that the graph sequence can be aligned with each sample in the batch. The decoder's layer 0 state H_dec is initialized. (0) Let H_tgt be the input to the first layer decoder. Initialize the decoder output H_dec to H_tgt. Then perform forward propagation on the L layers of the Transformer decoder layer in sequence: for the ... Layer, firstly for the first The output H_dec of the layer Transformer decoder The LN is applied at the first layer, then processed by the causal self-attention mechanism, SelfAttention, using an M_causal mask to prevent future information leakage, resulting in a self-attention output connected to the residual. Next, the result is applied at the second layer, and then interacted with the hierarchical graph sequence Z_graph through the CrossAttention mechanism to integrate circuit structure information, resulting in a cross-attention output connected to the residual. Finally, the LN is applied again at the third layer, and feature transformation is performed through a feedforward network FFN. This network contains two layers of linear transformation, ReLU activation, and Dropout, resulting in a feedforward output connected to the residual, forming the first... The layer's output H_dec After L layers of decoding, the final decoded output H_final is obtained, with dimensions L_r×B×2d_h. Finally, H_final is input to the quality result prediction head, which is a linear layer that maps the 2d_h-dimensional features to a 1-dimensional scalar, thus obtaining the quality result trajectory prediction. The dimension is B×L_r, which represents the predicted quality result (delay or area) of each circuit in the batch at each step of the sequence.

[0036] Step (8): Loss calculation and model training

[0037] During the training phase, the loss between the predicted trajectory and the true trajectory is calculated, and the model parameters are optimized through backpropagation. From the predicted trajectory... Extract the true quality trajectory Y_trajectory from the graph data G1. Calculate the mean squared error loss MSE_loss, which measures the mean of the element-wise squared differences between the predicted and true trajectories. Calculate the gradient of the loss with respect to all learnable parameters of the model using the backpropagation algorithm, including the GCN parameters in the graph encoder, the multi-scale fusion module parameters, the sequence embedding layer parameters, the dynamic interaction module parameters, the Transformer decoder parameters, and the prediction head parameters. Update the model parameters using the Adam optimizer based on the calculated gradients. The optimizer includes hyperparameters such as learning rate and weight decay. Repeat the above forward propagation, loss calculation, backpropagation, and parameter update process until the model loss converges on the validation set or reaches the preset number of training epochs. After training, save the model parameters and heuristic operation vocabulary for subsequent inference stages.

[0038] Step (9): Reasoning and Quality Result Prediction

[0039] During the inference phase, the trained model is loaded to predict the quality results of new circuit-sequence pairs. First, the saved model parameters and heuristic operation vocabulary are loaded, and a complete model architecture is constructed, including a graph encoder, a multi-scale fusion module, a sequence encoder, a dynamic interaction module, a Transformer decoder, and a prediction head. For the input circuit to be tested and the optimized sequence, graph data G1 is constructed according to step (1), and heuristic operations are mapped to index sequences based on the vocabulary. The graph data is input into the model, and the forward propagation process from step (2) to step (7) is executed sequentially to obtain the predicted quality result trajectory. .from Extract the predicted value from the last step of the sequence as the predicted final quality result for the circuit under a given optimization sequence. Calculate the mean absolute percentage error (MAPE) between the predicted and actual values ​​to evaluate the model's performance on the test set. Optionally, calculate the MAPE for each circuit separately to generate a circuit-level performance analysis report. Further, optionally, visualize the predicted and actual trajectories of some circuits to visually demonstrate the model's ability to model the optimization process. Save the prediction results, performance metrics, and visualizations to the results directory to complete the inference process.

[0040] Furthermore, step (2) specifically includes the following steps:

[0041] 2-1) Construction of a Two-Layer Graph Convolutional Network

[0042] A first-layer graph convolutional network (GCN1) is created, with input dimension D_in and output dimension d_h, where D_in is the initial feature dimension of the nodes and d_h is the hidden layer dimension. GCN1 performs a linear transformation on the node features using a learnable weight matrix W_gcn1 and performs message passing and aggregation along the graph edges to achieve the fusion of neighborhood information. A second-layer graph convolutional network (GCN2) is created, with input dimension d_h and output dimension d_h. GCN2 further extracts graph topological features to enhance the expressive power of the node representations.

[0043] 2-2) Construction of Multi-hop Neighborhood Aggregation Transformation Layer

[0044] Set the maximum number of hops K for multi-scale fusion, preferably K=3. For each hop k from 1 to K, create a hop-specific transformation layer Transform_k, which contains a learnable weight matrix W_k∈ (d_h×d_h) and bias vector b_k∈ d_h The transformation layer is used to extract semantics from the neighborhood aggregation features of the k-th hop, enabling the model to learn differentiated feature representations of neighborhoods at different scales.

[0045] 2-3) Construction of Circuit Sensing Gated Network

[0046] A two-layer multilayer perceptron is constructed as the scale-gated network ScaleGate. The first layer is a linear layer with an input dimension of 2 (corresponding to the normalized number of nodes and the normalized maximum depth) and an output dimension of d_h / 4, using the ReLU activation function. The second layer is also a linear layer with an input dimension of d_h / 4 and an output dimension of K, using the Sigmoid activation function to map the output to the [0,1] interval. The gated network adaptively generates the gating weights for each hop based on the scale characteristics of the circuit, achieving scale-aware feature modulation.

[0047] 2-4) Construction of Attention Fusion Network

[0048] An attention weight calculation layer, AttentionWeights, is created, containing a linear transformation layer. The input dimension is K×d_h (the concatenated multi-hop features), and the output dimension is K. A Softmax activation function is applied to ensure the weight sum is 1. This attention layer assigns importance weights to each node on different hop features, achieving adaptive multi-scale feature integration.

[0049] 2-5) Construction of Feature Projection Layer

[0050] Create a feature fusion projection layer called FusionProjection, which contains a linear transformation layer with an input dimension of K×d_h and an output dimension of d_h. This linear layer contains a learnable weight matrix W_fusion∈ (d_h×K·d_h) and bias vector b_fusion∈ d_h The projection layer maps the multi-hop attention-weighted features back to a unified hidden dimension space, generating the final scale-adaptive node representation.

[0051] 2-6) Output encoder model E_msff

[0052] All the above components are combined to form an encoder model, including a two-layer GCN network, a K-hop specific transform layer, a circuit-aware gating network, an attention fusion network, and a feature projection layer, which together constitute the scale-adaptive graph encoder E_msff.

[0053] Furthermore, step (3) specifically includes the following steps:

[0054] 3-1) Initial Node Embedding Extraction

[0055] The node feature matrix X and edge index matrix E_index are extracted from the graph data G1. X and E_index are input into the first layer GCN1 of the encoder E_msff to perform a linear transformation on the node features and aggregate neighbor information along the edges. The ReLU activation function is then applied to obtain the first layer output. The first layer output and E_index are input into the second layer GCN2 for further message passing and feature extraction to obtain the initial node embedding H. (0) The dimension is N×d_h, where N is the total number of nodes.

[0056] 3-2) Multi-hop neighborhood aggregation

[0057] Initialize the current feature H_current to H (0) Create a list `hop_features` to store the features for each hop. For the k-th hop (k ranges from 1 to K):

[0058] (a) Extract the source node index src and the target node index dst from the edge index matrix E_index;

[0059] (b) Extract the source node feature H_current[src] from H_current based on src;

[0060] (c) By using the scatter_mean operation, the features of the source node are aggregated to the target node according to the dst index, resulting in the neighborhood aggregated feature M of the k-th hop. (k) The dimension is N×d_h;

[0061] (d) M (k) Input is passed to the k-th hop specific transform layer Transform_k, and a linear transform F is performed.(k) =M (k) ·W_k T +b_k, to obtain the transformed k-th hop feature F (k) ;

[0062] (e) Add F (k) to the hop_features list;

[0063] (f) If k < K, update H_current = M (k) , in preparation for the next hop aggregation.

[0064] After K iterations, the hop_features list contains K feature matrices {F (1) , F (2) ,..., F (k)}, which respectively capture the structural information of the 1-hop to K-hop neighborhoods.

[0065] 3-3) Circuit-scale feature extraction and gating weight calculation

[0066] Extract the node depth vector D_node from the graph data G1. Calculate the normalized node number s_n = N / N param , where N is the total number of nodes; N param is the reference value of the normalized node number, making the normalized values reasonably distributed, and can be adjusted according to the specific dataset:

[0067] If the dataset is mainly small-scale circuits (<1000 nodes), s_n = N / 1000;

[0068] If mainly very large-scale circuits (>100,000 nodes), s_n = N / 10000;

[0069] The key is to make the normalized values distributed in a neural network-friendly range (usually 0-10 or 0-20).

[0070] Extract the maximum depth value max_depth from D_node, calculate the normalized maximum depth s_d = max_depth / d param . d param is the reference value of the normalized depth, making the normalized values reasonably distributed. Similar to N param , it can be changed according to the circuit scale. Construct the scale feature vector s = [s_n, s_d] T ∈ ². Input s into the circuit-aware gating network ScaleGate, and after the first layer of linear transformation, ReLU activation, the second layer of linear transformation, and Sigmoid activation, obtain the K-dimensional gating weight vector g = [g_1, g_2,..., g_K]T , where each g_k∈[0,1].

[0071] 3-4) Gated Feature Modulation

[0072] For each hop k from 1 to K, extract the k-th hop feature F from hop_features. (k) Extract the k-th weight g_k from the gated weight vector g. Perform element-wise scaling. The gating features are obtained. The gating mechanism enables large-scale circuits to suppress high-jump features to avoid over-smoothing, while small-scale circuits can enhance high-jump features to capture global patterns. All gated features... Collect them.

[0073] 3-5) Attention-weighted fusion

[0074] Concatenate the K gated features along the feature dimensions to obtain the concatenated feature F_concat∈ (N×Kd_h) Each row contains the gated features of that node across all K hops. The F_concat is input to the attention weight calculation layer AttentionWeights, and through linear transformation and softmax activation, the hop-level attention weight matrix α∈ for each node is obtained. (N×K) Let α_ik be the element in the i-th row and k-th column of α, representing the attention weight of the i-th node for the k-th hop feature, and Σ_kα_ik=1. For each hop k, extract the k-th column α_{:,k} from α and combine it with... Perform element-wise multiplication This yields the k-th hop feature after weighting. All K weighted features are concatenated along the feature dimension to obtain the weighted concatenated feature F_weighted∈ (N×Kd_h) .

[0075] 3-6) Feature Projection and Output

[0076] The weighted concatenated features F_weighted are input into the feature fusion projection layer FusionProjection, and a linear transformation H_msf = F_weighted·W_fusion is performed. T +b_fusion maps the Kd_h-dimensional features back to the d_h-dimensional features, resulting in the scale-adaptive node representation H_msf∈ (N×d_h) The H_msf integrates the structural information of multi-hop neighborhoods and achieves a dynamic balance between local and global features through circuit-aware gating and attention mechanisms.

[0077] Furthermore, step (6) specifically includes the following steps:

[0078] 6-1) Dimensional Adjustment of Sequence and Graph Representations

[0079] The sequence representation after extracting the injection position information from the sequence representation H_recipe has a dimension of B×L_r×2d_h. It is transposed along the 0th and 1st dimensions to obtain the transposed sequence representation with a dimension of L_r×B×2d_h, to adapt to the input format of the subsequent Transformer decoder. It is also extracted from the hierarchical graph sequence Z_graph, with a dimension of L_g×2d_h. Z_graph is expanded along the batch dimension, and B copies are made using a tensor expansion operation to obtain the expanded graph sequence with a dimension of L_g×B×2d_h.

[0080] 6-2) Global Aggregation in Graph Context

[0081] A graph context aggregation network, GraphAggregator, is constructed, containing a linear transformation layer (both input and output dimensions are 2d_h) and a ReLU activation function. The expanded graph sequence is input into GraphAggregator, and linear transformation and activation are performed on each level embedding of each batch to obtain the transformed graph sequence. Mean pooling (torch.mean(dim=0, keepdim=True)) is performed on the transformed graph sequence along the level dimension (0th dimension), aggregating the features of L_g levels into a single global graph context vector G_global, with dimensions 1×B×2d_h. G_global is expanded along the sequence length dimension by copying it L_r times using the expand operation, resulting in the expanded global graph context G_expand, with dimensions L_r×B×2d_h, ensuring that the graph context is aligned with each time step of the sequence.

[0082] 6-3) Semantic Context Extraction

[0083] A step context extraction network, StepEncoder, is constructed, consisting of two multilayer perceptron layers. The first layer is a linear layer with both input and output dimensions of 2d_h, using the ReLU activation function. The second layer is also a linear layer with both input and output dimensions of 2d_h. The transposed sequence representation (dimension L_r×B×2d_h) is input into StepEncoder and sequentially passed through the first linear transformation, ReLU activation, and the second linear transformation to obtain the step context representation C_step, with dimensions L_r×B×2d_h. C_step extracts a compact semantic representation of each optimization step, removing redundant information and focusing on the core intent of the optimization operation.

[0084] 6-4) Step-sensing map modulation

[0085] A step-aware modulation network, GraphModulator, is constructed, comprising a linear layer (input dimension 4d_h, output dimension 2d_h) and a Tanh activation function. The extended global graph context G_expand and the step context C_step are concatenated along the feature dimension (the second dimension) to obtain a concatenated tensor of dimension L_r×B×4d_h. This concatenated tensor is input into GraphModulator, and through linear transformation and Tanh activation, a modulated graph representation G_mod of dimension L_r×B×2d_h is obtained. This modulation process deeply integrates the global structural information of the circuit with the semantic intent of the current optimization step, enabling the graph representation to dynamically adjust its focus according to the different needs of the optimization step.

[0086] 6-5) Adaptive Gating

[0087] An adaptive gating network, AdaptiveGate, is constructed, comprising a linear layer (input dimension 6d_h, output dimension 2d_h) and a sigmoid activation function. The transposed sequence representation, the modulation graph representation G_mod, and the step context C_step are concatenated along the feature dimensions to obtain a gating input tensor of dimension L_r×B×6d_h. This gating input tensor is then input into AdaptiveGate, and through linear transformation and sigmoid activation, adaptive gating weights g_adaptive of dimension L_r×B×2d_h are obtained, where each element takes values ​​in the range [0,1]. Element-wise multiplication G_gated = g_adaptive ⊙ G_mod is performed on the modulation graph representation G_mod and the gating weights g_adaptive to obtain the gated graph representation G_gated of dimension L_r×B×2d_h. This adaptive gating mechanism dynamically adjusts the intensity of graph information flow to the sequence based on the joint information of sequence semantics, graph structure, and step context, achieving refined information fusion control.

[0088] 6-6) Feature Fusion and Output

[0089] A feature fusion layer, FeatureFusion, is constructed, consisting of a linear layer with an input dimension of 4d_h and an output dimension of 2d_h. The transposed sequence representation and the gated graph representation G_gated are concatenated along the feature dimensions to obtain a fused input tensor with dimensions L_r×B×4d_h. This fused input tensor is then input into FeatureFusion, and through a linear transformation, a context-aware target sequence representation H_tgt with dimensions L_r×B×2d_h is obtained. H_tgt integrates the semantic information of the optimized sequence and the dynamic modulation information of the circuit structure, enabling bidirectional interaction between the circuit state and the optimization strategy.

[0090] Furthermore, step (7) specifically includes the following steps:

[0091] 7-1) Causal Attention Mask Generation

[0092] Based on the sequence length L_r, create an L_r×L_r square matrix. Fill the upper triangular portion of the matrix (excluding the diagonal) with negative infinity (-∞), and fill the lower triangular portion and the diagonal with 0, to obtain the causal attention mask M_causal. This mask ensures that in self-attention computation, the query vector at position i can only focus on the key vector at position j≤i, preventing the model from seeing information from future steps when predicting the i-th step, thus conforming to the temporal constraints of causal inference.

[0093] 7-2) Decoder Input Preparation

[0094] Extract the context-aware target sequence from the dynamic interactive representation H_tgt, with dimensions L_r×B×2d_h. Extract it from the hierarchical graph sequence Z_graph and expand it along the batch dimension to L_g×B×2d_h. Initialize the decoder's current state H_dec. (0) For H_tgt.

[0095] 7-3) Transformer decoder layer iteration

[0096] Set the number of decoder layers L_decoder, for each layer From 1 to L_decoder, perform the following operations in sequence:

[0097] (a) Causal self-attention sublayer: for H_dec (l-1) The application layer normalizes LN_sa to obtain a normalized representation. This normalized representation is then input into the multi-head self-attention mechanism SelfAttention, which uses a causal mask M_causal to compute the query, key, and value matrices and performs scaled dot product attention to obtain the self-attention output. This self-attention output is then compared with H_dec. (l-1) Perform residual connections and apply Dropout to obtain the output H_sa of the self-attention layer.

[0098] (b) Cross-Attention Sublayer: Apply layer normalization LN_ca to H_sa to obtain a normalized representation. Use the normalized representation as the query vector and the expanded layered graph sequence Z_graph as the key-value vector, inputting it into the multi-head cross-attention mechanism CrossAttention. Calculate the attention weights and perform weighted aggregation to obtain the cross-attention output. Residually connect the cross-attention output to H_sa and apply Dropout to obtain the output H_ca of the cross-attention layer.

[0099] (c) Feedforward Sublayer: Apply layer normalization LN_ffn to H_ca to obtain a normalized representation. Input the normalized representation into the feedforward network FFN, which includes a first-layer linear transformation (input 2d_h, output d_ff, where d_ff = 4 × 2d_h), ReLU activation, Dropout, a second-layer linear transformation (input d_ff, output 2d_h), and Dropout to obtain the feedforward network output. Residually connect the feedforward output to H_ca to obtain the... The final output of the layer .

[0100] After iteration through the L_decoder layer, the final decoded output H_final = H_dec is obtained. (Ldecoder) The dimension is L_r×B×2d_h.

[0101] 7-4) Prediction of Quality Result Trajectory

[0102] Construct a quality prediction head, QoRHead, containing a linear layer with an input dimension of 2d_h and an output dimension of 1. Input H_final into QoRHead and perform a linear transformation on each sample at each time step to obtain the predicted quality result, which has a dimension of L_r×B×1. Remove the last dimension to obtain an L_r×B tensor. Transpose this tensor along its 0th and 1st dimensions and apply a squeeze operation to remove redundant dimensions, obtaining the predicted quality result trajectory. The dimension is B×L_r. The element in the i-th row and j-th column represents the predicted quality result (delay or area) of the i-th circuit in the batch after the j-th step of the optimization sequence.

[0103] Compared with the prior art, the present invention has the following advantages and effects:

[0104] (1) Strong scale adaptability: Through multi-hop neighborhood aggregation and circuit-aware gating mechanism, this invention can automatically adjust the balance between local details and global structure according to the circuit scale. For large-scale circuits (tens of thousands of nodes), the gating mechanism automatically reduces the weight of high-hop features to prevent over-smoothing and preserve local circuit patterns; for small-scale circuits (hundreds of nodes), the gating mechanism enhances high-hop features to capture global propagation paths. Experiments show that on five benchmark datasets spanning three orders of magnitude (86-114,771 nodes), this invention improves latency prediction by an average of 25.28% and area prediction by an average of 29.49% compared to existing methods, demonstrating its strong adaptability to heterogeneous scale circuits.

[0105] (2) Outstanding Dynamic Modeling Capability: Through a dynamic graph-sequence adaptive interaction mechanism, this invention achieves deep integration of circuit representation and optimization step semantics. Unlike the static encoding and late-stage fusion strategies of existing methods, this invention establishes early interaction between the graph and the sequence before decoding, enabling the circuit representation to be dynamically modulated according to the specific needs of the current optimization step. The step-aware modulation network can identify the differentiated effects of different optimization operations (such as algebraic rewriting, balance optimization, etc.) on the circuit, and the adaptive gating mechanism further finely adjusts the information flow intensity. Experiments show that removing the dynamic interaction module in the ablation experiment leads to a 17.20% decrease in delay prediction performance and a 10.30% decrease in area prediction performance, fully verifying its importance for dynamic optimization modeling. Attached Figure Description

[0106] Figure 1 This is the overall flowchart of the scale-adaptive logic synthesis optimization circuit representation learning method of the present invention.

[0107] Figure 2 This is a detailed flowchart of the scale-adaptive graph encoder construction process.

[0108] Figure 3 This is a detailed flowchart of multi-scale feature fusion and scale-adaptive node representation generation.

[0109] Figure 4 It is a detailed flowchart of dynamic graph-sequence adaptive interaction.

[0110] Figure 5 This is a detailed flowchart of Transformer decoding and quality result trajectory prediction. Detailed Implementation

[0111] The method of the present invention will be described in detail below with reference to the accompanying drawings, technical solutions, and embodiments.

[0112] like Figure 1As shown, the scale-adaptive logic synthesis optimization circuit representation learning method of the present invention proceeds as follows: First, the logic circuit file to be optimized and the optimization sequence are automatically parsed. All logic gates are extracted as a node set through the circuit diagram data construction module. The type of each logic gate is identified and an initial node feature matrix X is generated through the embedding layer. At the same time, the connection relationship between the gates is extracted as an edge set and an edge index matrix E_index. The circuit depth of each node is extracted to form a node depth vector D_node. For the optimization sequence, the heuristic operation is mapped to an integer index sequence R_indices. The above information is used to construct graph data G1. Subsequently, a scale-adaptive graph encoder E_msff is constructed, including a two-layer GCN network for initial feature extraction, a K-hop specific transformation layer for multi-scale semantic extraction, a circuit-aware gating network to generate adaptive weights according to the circuit scale, an attention fusion network to integrate multi-hop features, and a feature projection layer to generate a unified representation. The graph data G1 is input into the encoder E_msff. A scale-adaptive node representation H_msf is generated through multi-hop neighborhood aggregation (iterating K times with scatter averaging and hop-specific transformations), circuit-scale feature extraction (normalizing the number of nodes and depth), gated modulation (element-wise scaling), attention-weighted fusion (Softmax weight allocation), and feature projection. Based on H_msf and D_node, a hierarchical graph sequence Z_graph is constructed through hierarchical pooling operations (performing mean and max pooling on each depth level and concatenating the results). This sequence captures the multi-layered topology of the circuit. The optimized sequence R_indices is embedded and encoded, and sine and cosine position information is injected to generate the sequence representation H_recipe. In the dynamic graph-sequence adaptive interaction stage, the sequence representation is transposed to L_r×B×2d_h, and the hierarchical graph sequence is expanded to L_g×B×2d_h. A graph context aggregation network extracts the global graph vector G_global and expands it to G_expand. A step context extraction network extracts the step semantics C_step from the sequence. A step-aware modulation network fuses G_expand and C_step into a modulation graph G_mod. An adaptive gating network calculates the gating weights and obtains G_gated. Finally, a feature fusion layer integrates the sequence representation and G_gated into a context-aware target sequence H_tgt. Next, a causal attention mask M_causal is generated. H_tgt and the expanded Z_graph are input into a multi-layer Transformer decoder. Each layer sequentially performs causal self-attention (capturing sequence dependencies), cross-attention (integrating circuit structures), and a feedforward network (feature transformation). All sub-layers employ residual connections and layer normalization. After passing through the L_decoder layer, the final decoded output H_final is obtained, which is linearly mapped to the predicted trajectory using a quality result prediction head. During the training phase, calculations are performed. The MSE loss between the model and the true trajectory Y_trajectory is used to update all module parameters through backpropagation and the Adam optimizer, and training is repeated until convergence. During the inference phase, the trained model is loaded and forward propagated to new circuit-sequence pairs to obtain quality predictions. The MAPE is calculated to evaluate performance, and optionally, trajectory comparison visualizations and circuit-level analysis reports are generated, completing the entire automated circuit representation learning and quality prediction process.

[0113] The following section uses the adder circuit from the EPFL benchmark dataset as an example to illustrate the implementation details of each step. The specific process is as follows:

[0114] (1) Circuit diagram data construction

[0115] (1.1) Circuit file parsing

[0116] Select the adder.bench circuit file from the EPFL benchmark dataset. This circuit is an arithmetic adder with 329 main inputs, 188 main outputs, 14852 logic gate nodes, and a circuit depth of 186 layers. Use a Verilog or BENCH format parser to read the circuit file and identify the types (AND, OR, NOT, etc.) and connections of all logic gates.

[0117] (1.2) Node feature initialization

[0118] Iterate through all 14852 logic gates and extract gate type information. This circuit contains multiple gate types, and each gate type is mapped to a unique integer index (e.g., AND=0, OR=1, NOT=2, etc.). Create a node type index vector node_types∈ 14852 The i-th element is the gate type index of node i. The integer indices are mapped to D_in-dimensional initial node feature vectors through the embedding layer Embedding(num_gate_types, D_in), resulting in the node feature matrix X∈ (14852×D_in) In this embodiment, D_in is set to 16.

[0119] (1.3) Construction of edge index matrix

[0120] Extract the connections between all logic gates and construct a set of directed edges. This circuit contains 46,836 directed edges. For each edge, record the source node index and the destination node index, generating an edge index matrix E_index∈ (2×46836) The first row is the source node index, and the second row is the target node index, conforming to the COO format of PyTorchGeometric.

[0121] (1.4) Extraction of node depth information

[0122] The depth of each node in the circuit (the longest path length from the main input to that node) is calculated using a topological sorting algorithm. The main input node has a depth of 0, and the depth of other nodes is the maximum value of the depths of all their predecessor nodes plus 1. A node depth vector D_node∈ is generated. 14852 The node depth of this circuit ranges from 0 to 185, with a maximum depth of 185.

[0123] (1.5) Optimize sequence processing

[0124] Select an optimization sequence containing 20 heuristic operations, such as "resub;resub;rewrite;refactor;balance;...". Map each operation string to an integer index based on a pre-built heuristic operation vocabulary (containing all possible optimization operations and their indices). Generate a sequence index matrix R_indices∈ (1×20) , where 1 is the batch size and 20 is the sequence length.

[0125] (1.6) Acquisition of quality result trajectory

[0126] Read the delay (or area) trajectory of the circuit under the optimized sequence from the dataset. The quality result trajectory Y_trajectory∈ (1×20) The circuit delay value after optimization at each step of the sequence is recorded. In this embodiment, delay prediction is used as an example, where Y_trajectory[0,j] represents the circuit delay after the first j+1 steps of optimization.

[0127] (1.7) Constructing graph data G1

[0128] All the extracted information is used to construct graph data G1, which includes: node feature matrix X (14852×16), edge index matrix E_index (2×46836), node depth vector D_node (14852), sequence index matrix R_indices (1×20), and quality result trajectory Y_trajectory (1×20). At this point, the graph data fully represents the circuit's topology, node attributes, depth information, and the input and output of the optimization task.

[0129] (2) Construction of scale-adaptive graph encoder

[0130] (2.1) Initialization of the two-layer GCN network

[0131] like Figure 3As shown, a first-layer graph convolutional network GCN1 is created with input dimension D_in=16 and output dimension d_h=32. GCN1 contains a learnable weight matrix W_gcn1∈ (32×16) Create a second-layer graph convolutional network GCN2 with input dimension d_h=32 and output dimension d_h=32, containing the weight matrix W_gcn2∈ (32×32) Two layers of GCN jointly extract the initial graph topological features.

[0132] (2.2) Creation of multi-hop transformation layer

[0133] The maximum number of hops is set to K=3 to meet the requirement of capturing multi-scale features. For k=1, 2, 3, hop-specific transformation layers Transform_1, Transform_2, and Transform_3 are created respectively. Each transformation layer contains a weight matrix W_k∈ (32×32) and bias vector b_k∈ 32 These transformation layers will learn how to extract differential features from neighborhood aggregations with different hop counts.

[0134] (2.3) Creation of Circuit-Sensing Gated Network

[0135] A two-layer MLP is created as the ScaleGate. The first linear layer has an input dimension of 2 (normalized number of nodes and normalized maximum depth) and an output dimension of 32 / 4=8, using ReLU activation. The second linear layer has an input dimension of 8 and an output dimension of K=3, using Sigmoid activation. This network will learn how to adaptively adjust the weights of the three hops according to the circuit size.

[0136] (2.4) Attention Fusion Network Creation

[0137] An attention weights calculation layer, AttentionWeights, is created. This layer consists of linear layers with an input dimension of K×d_h = 3×32 = 96 and an output dimension of K = 3, activated using Softmax. This layer learns the importance distribution of each node across three hop features.

[0138] (2.5) Creation of Feature Projection Layer

[0139] Create a FusionProjection linear layer with input dimension K×d_h=96 and output dimension d_h=32. This layer compresses the multi-hop weighted features back to a unified hidden dimension.

[0140] (2.6) Construct the encoder model E_msff

[0141] The scale-adaptive graphical encoder E_msff is constructed by combining a two-layer GCN, three jump transform layers, a gating network, an attention network, and a projection layer. The model has approximately 8K parameters: GCN layer (16×32+32×32≈1.5K), transform layer (3×32×32≈3K), gating network (2×8+8×3≈40), attention layer (96×3≈300), and projection layer (96×32≈3K), achieving efficient parameter utilization.

[0142] (3) Multi-scale feature fusion and scale-adaptive node representation generation

[0143] (3.1) Initial node embedding extraction

[0144] like Figure 4 As shown, the node feature matrix X (14852×16) and the edge index matrix E_index (2×46836) are input into GCN1. GCN1 performs a linear transformation X·W_gcn1 on X. T The process involves message passing and aggregation along the edges (using `scatter_add` or `scatter_mean` operations), followed by ReLU activation to obtain the first layer output (14852×32). The first layer output and `E_index` are then input into GCN2, undergoing similar linear transformations and message passing to obtain the initial node embeddings `H`. (0) ∈ (14852×32) .

[0145] (3.2) First-hop neighborhood aggregation and transformation

[0146] Initialize H_current=H (0) Extract the source node index src (length 46836) and the target node index dst (length 46836) from E_index. Extract the source node feature H_current[src] (46836×32) from H_current based on src. Aggregate along the dst index using scatter_mean(H_current[src],dst,dim=0,dim_size=14852) to obtain the first-hop neighborhood aggregation feature M. (1) ∈ℝ (14852×32) M of each node (1) For all its neighbors in H (0) The characteristic mean in M. (1) Input into Transform_1 and execute F. (1) =M (1) ·W_1 T +b_1, obtain the first-hop feature F (1) ∈ (14852×32) Update H_current=M (1) .

[0147] (3.3) Second and third jump aggregation and transformation

[0148] For k=2, repeat the above process. From H_current (i.e. M) (1) In the process, features are extracted from src and aggregated to dst using scatter_mean to obtain M. (2) (Mean of 2-hop neighbor features for each node). F is obtained through Transform_2. (2) =M (2) ·W_2 T +b_2. Update H_current=M (2) Similarly, for k=3, we obtain M. (3) and F (3) =M (3) ·W_3 T +b_3. At this point, hop_features={F (1) ,F (2) ,F (3) It contains multi-scale neighborhood features ranging from 1 hop to 3 hops.

[0149] (3.4) Circuit-scale feature extraction

[0150] Calculate circuit scale information from D_node. Total number of nodes N = 14852, normalized number of nodes s_n = 14852 / 5000 ≈ 2.97. Maximum depth max_depth = 185, normalized maximum depth s_d = 185 / 20 = 9.25. Construct a scale feature vector s = [2.97, 9.25]. T ∈ 2 .

[0151] (3.5) Calculation of gating weights

[0152] Input s into ScaleGate. First-level linear transformation s·W_g1 T +b_g1 yields an 8-dimensional vector, which is then processed using ReLU to obtain an intermediate representation. A second linear transformation results in a 3-dimensional vector, which is then processed using Sigmoid to obtain the gate weights g = [g_1, g_2, g_3]. T ∈[0,1] 3 In this embodiment, since the adder circuit is large in scale and deep, the gating weights learned by the model may be g≈[0.8,0.5,0.2], that is, a higher weight is given to 1-hop local features and a lower weight is given to 3-hop global features to avoid over-smoothing.

[0153] (3.6) Gated Feature Modulation

[0154] For k=1,2,3, execute . Specifically, , , The gating operation applies scale-aware weighting to the features of different jumps, highlighting local features and suppressing high-jump features that may lead to oversmoothing.

[0155] (3.7) Attention-weighted fusion

[0156] The three gated features are concatenated along the feature dimension. ∈ (14852×96) The input is fed into the AttentionWeights layer, and then subjected to a linear transformation F_concat·W_att. T +b_att yields logits (14852×3), and Softmax is applied to obtain the attention weights α∈ (14852×3) For example, for a key node, the attention weight might be α_i = [0.6, 0.3, 0.1], indicating that the node pays more attention to 1-hop and 2-hop features. For each hop k, calculate... (Element-wise multiplication) yields the weighted features. The three weighted features are then concatenated to form F_weighted∈ (14852×96) .

[0157] (3.8) Feature projection and output

[0158] Input F_weighted into the FusionProjection layer and execute H_msf=F_weighted·W_fusion T +b_fusion, to obtain the scale-adaptive node representation H_msf∈ (14852×32) This representation incorporates multi-hop neighborhood information and achieves a local-global balance for large-scale circuits through gating and attention.

[0159] (4) Construction of hierarchical graph sequences

[0160] (4.1) Hierarchical recognition

[0161] The maximum depth max_depth=185 is obtained from D_node, and it is determined that the circuit has a total of L_g=186 levels (from depth 0 to 185).

[0162] (4.2) Layer-by-layer pooling

[0163] For each level (0 to 185), create a mask `mask_level = (D_node == level)` to identify all nodes with depth equal to `level`. If a node exists at this level (`mask_level.sum() > 0`), extract the node embedding `H_msf[mask_level]` from `H_msf`. Calculate mean pooling `mean_pool = H_msf[mask_level].mean(dim=0)` (32-dimensional) and max pooling `max_pool = H_msf[mask_level].max(dim=0)` (32-dimensional). Concatenate the two to obtain the embedding `emb_level = [mean_pool, max_pool] ∈` for this level. 64 If no node exists at this level, fill it with a zero vector: emb_level=zeros(64).

[0164] (4.3) Stacked layer representation

[0165] The 186 levels of embeddings are stacked sequentially to obtain the hierarchical graph sequence Z_graph∈ (186×64) The first line of this sequence represents the summary information of the input layer, the second line represents the summary information of the output layer, and the middle lines represent the circuit structure features at different depth levels.

[0166] (5) Sequence encoding and position information injection

[0167] (5.1) Sequence embedding

[0168] Extract R_indices (1×20) from G1. Input them into the sequence embedding layer RecipeEmbedding (embedding dimension 64) to obtain the sequence embedding matrix ∈ (1×20×64) This embedding maps each heuristic operation index to a 64-dimensional semantic vector.

[0169] (5.2) Location code generation

[0170] Construct the position encoding matrix PE∈ (5000×64) (Maximum sequence length is set to 5000). For position pos∈[0,19] and dimension i∈[0,63], if i is even, PE[pos,i]=sin(pos / 10000) (i / 64) If i is odd, then PE[pos,i]=cos(pos / 10000). ((i-1) / 64) Extract the first 20 rows PE[:20,:]∈ (20×64) .

[0171] (5.3) Location information injection

[0172] Expand PE[:20,:] to (1×20×64) and add it element-wise to the sequence embedding matrix to obtain H_recipe = sequence embedding + PE[:20,:]. Apply Dropout (probability 0.3) for regularization.

[0173] (6) Dynamic graph-sequence adaptive interaction

[0174] (6.1) Dimensional Adjustment

[0175] like Figure 5 As shown, (1×20×64) is extracted from H_recipe and transposed to (20×1×64). (186×64) is extracted from Z_graph and expanded to (186×1×64).

[0176] (6.2) Graph Context Aggregation

[0177] The expanded graph sequence (186×1×64) is input into the GraphAggregator (linear layer 64→64+ReLU) to obtain the transformed graph sequence. Mean pooling is performed along the hierarchical dimensions to obtain G_global (1×1×64). It is then expanded to G_expand (20×1×64) to align the graph context with each step of the sequence.

[0178] (6.3) Step Context Extraction

[0179] The transposed sequence (20×1×64) is input into StepEncoder (two-layer MLP, 64→64ReLU64→64) to obtain C_step (20×1×64), and the compact semantics of each step are extracted.

[0180] (6.4) Step-aware modulation

[0181] G_expand and C_step are concatenated into (20×1×128), which is then input into GraphModulator (linear 128→64+Tanh) to obtain G_mod (20×1×64). G_mod integrates global circuit information and the semantics of the current step, realizing step-aware graph representation modulation.

[0182] (6.5) Adaptive Gating

[0183] The transposed sequence, G_mod, and C_step are concatenated into (20×1×192), and input into AdaptiveGate (linear 192→64+Sigmoid) to obtain g_adaptive (20×1×64). Then, G_gated = g_adaptive ⊙ G_mod is executed to dynamically adjust the graph information flow intensity.

[0184] (6.6) Feature fusion

[0185] The transposed sequence is concatenated with G_gated to form (20×1×128), which is then input into FeatureFusion (linear 128→64) to obtain H_tgt (20×1×64). H_tgt integrates sequence semantics and circuit structure information of dynamic modulation.

[0186] (7) Transformer Decoding and Quality Result Trajectory Prediction

[0187] (7.1) Causal Mask Generation

[0188] Generate a 20×20 causal mask M_causal, fill the upper triangle (excluding the diagonal) with -∞, and fill the rest with 0.

[0189] (7.2) Decoder initialization

[0190] Extract (20×1×64) from H_tgt, and extract and expand (186×1×64) from Z_graph. Set the number of decoder layers L_decoder=1 (single-layer Transformer decoder).

[0191] (7.3) Forward propagation of the first layer decoder

[0192] Apply layer-normalized LN_sa to H_tgt, input it to a multi-head self-attention network (4 heads, 16 dimensions each), and use an M_causal mask to obtain the self-attention output. Residual connections yield H_sa = H_tgt + Dropout(SelfAttention_output). Apply LN_ca to H_sa, input it to a multi-head cross-attention network (queries from H_sa, keys from Z_graph), and obtain the cross-attention output. Residual connections yield H_ca = H_sa + Dropout(CrossAttention_output). Apply LN_ffn to H_ca, input it to a feedforward network (64→256ReLU256→64), and obtain the FFN output. Residual connections yield H_dec. (1) =H_ca+Dropout(FFN_output).

[0193] (7.4) Prediction of quality results

[0194] H_dec (1) The (20×1×64) tensor is input into QoRHead (linear 64→1) to obtain the prediction tensor (20×1×1). The last dimension is removed and transposed to obtain... (1×20). This trajectory predicts the delay value of the adder circuit at each step of the 20-step optimization sequence.

[0195] (8) Loss calculation and model training

[0196] (8.1) Loss Calculation

[0197] from Extract (1×20), extract Y_trajectory (1×20) from G1. Calculate MSE_loss = ((Ŷ - Y_trajectory) 2 ).mean(). In this embodiment, it is assumed that the predicted trajectory is [185.2,182.3,...,170.5], the actual trajectory is [186.0,183.1,...,171.2], and the MSE is approximately 0.52.

[0198] (8.2) Backpropagation

[0199] Call MSE_loss.backward() to compute the gradients of all model parameters. Update the parameters using the Adam optimizer (learning rate 0.001, weight decay 1e-4).

[0200] (8.3) Training Iteration

[0201] Repeat the above process, iterating through all circuit-sequence pairs in the training set (approximately 82,000 pairs, representing 66% of the sequences). After each epoch, calculate the validation loss on the validation set (approximately 42,000 pairs, representing 34% of the sequences). If the validation loss does not improve for 10 consecutive epochs, stop early. After approximately 50 epochs of training, the validation loss converges to around 0.15. Save the model parameters and vocabulary.

[0202] (9) Reasoning and Quality Result Prediction

[0203] (9.1) Model Loading

[0204] Load the trained model parameters and vocabulary to build a complete graph encoder, sequence encoder, dynamic interaction module, Transformer decoder and prediction head.

[0205] (9.2) Test data preparation

[0206] Select an unseen optimized sequence (different from the sequence during training) of the adder circuit in the validation set, and construct the graph data G1 according to step (1).

[0207] (9.3) Forward propagation

[0208] By sequentially executing the forward process from steps (2) to (7), the predicted trajectory is obtained. (1×20). In this embodiment, the predicted final delay is 170.5, and the actual final delay is 171.2.

[0209] (9.4) Performance Evaluation

[0210] The calculated MAPE is approximately 0.41% (|171.2 - 170.5| / 171.2 × 100%). The average MAPE calculated across the entire EPFL test set is 2.68%, representing a 38.39% improvement compared to the baseline method LSOformer's 4.35%.

[0211] (9.5) Saving Results

[0212] Generate a CSV file containing the predicted trajectory, the actual trajectory, and the MAPE. Plot a trajectory comparison chart to show the high degree of agreement between the predicted and actual curves. Generate a circuit-level MAPE histogram, showing that the adder circuit's prediction error is only 0.41%, lower than the overall average. Save the results to the results directory, completing the inference process.

Claims

1. A scale-adaptive logic synthesis optimization circuit representation learning method, characterized in that, Includes the following steps: Step (1): Circuit diagram data construction The circuit structure and sequence information are extracted from the logic circuit file to be optimized and the optimization sequence to construct a graph data representation G1. First, the input logic circuit C is parsed, and all logic gates are extracted to form a node set V. The type of each logic gate is identified and an initial node feature matrix X is generated through an embedding layer. Then, the connection relationship between the logic gates is extracted to form an edge set E, and an edge index matrix E_index is generated. At the same time, the depth information of each node in the circuit is extracted to form a node depth vector D_node. For the optimization sequence R, the heuristic operations in it are mapped to an integer index sequence to form a sequence index matrix R_indices. Finally, the node set V, the edge set E, the node feature matrix X, the edge index matrix E_index, the node depth vector D_node, the sequence index matrix R_indices, and the quality result trajectory Y_trajectory are combined to form the graph data G1, completing the transformation from circuit and sequence to structured data. Step (2): Construction of the scale-adaptive graph encoder A graph encoder model E_msff with multi-scale feature fusion capability is constructed. This model contains four cascaded functional layers that form a complete feature extraction pipeline through input and output interfaces. First, a basic feature extraction layer is constructed, consisting of a two-layer graph convolutional network (GCN). The first layer, GCN1, receives the node feature matrix X and the edge index matrix E_index as input, performs message passing and ReLU activation through the weight matrix W_gcn1, and outputs the first layer embedding. The second layer, GCN2, receives the output of the first layer, further extracts topological features through the weight matrix W_gcn2, and outputs the initial node embedding H. (0) ; Then, a multi-scale aggregation layer is constructed, containing K parallel skip-specific transformation branches; this layer receives H (0) Using E_index as input, each branch k aggregates k-hop neighborhood information through k scattering averaging operations to obtain M. (k) Then, after passing through the Transform_k layer, the k-th hop feature F is output. (k) K branches output {F} in parallel (1) ,F (2) ,...,F (k) }; Next, a scale-aware modulation layer is constructed, consisting of a circuit-aware gating network and a gating modulation module. The gating network receives a normalized scale feature vector s, containing the number of nodes s_n and the maximum depth s_d, and outputs K-dimensional gating weights g∈[0,1] through two MLP layers (weights W_g1 and W_g2). K The gated modulation module receives {F} (1) ,...,F (k) } and g, for each F (k) Perform element-wise scaling Output gating features ; Finally, a feature fusion layer is constructed, consisting of an attention network and a projection layer connected in series; the attention network receives... The concatenation is F_concat, and the attention weight α is calculated through the weight W_att and Softmax. The weighted fusion is then obtained as F_weighted. The projection layer receives F_weighted and linearly transforms it into H_msf through the weight W_fusion and the bias b_fusion. The above four layers are connected in series via data flow: This achieves an end-to-end mapping from the original feature X to the scale-adaptive representation H_msf, with H_msf being passed as the encoder output to step (3). Step (3): Multi-scale feature fusion and scale-adaptive node representation generation The circuit diagram in graph data G1 is input into encoder E_msff, and scale-adaptive node representation H_msf is generated through multi-hop neighborhood aggregation, circuit-aware gating, and attention fusion. First, the node feature matrix X and edge index matrix E_index are input into a two-layer GCN. After ReLU activation in the first layer GCN1 and processing in the second layer GCN2, the initial node embedding H is obtained. (0) Then, the multi-hop neighborhood aggregation process is initiated, setting the current feature H_current equal to H. (0) For each hop k from 1 to K, the neighbor features are aggregated by performing a scattering averaging operation along the edge to obtain M. (k) Then, after passing through a specific transformation layer, the k-th hop feature F is obtained. (k) Simultaneously, circuit scale information is extracted from the node depth vector D_node, and the normalized number of nodes s_n and the normalized maximum depth s_d are calculated. The scale feature vector s is formed and input into the circuit-sense gated network to obtain the K-dimensional gated weight vector g; for each hop feature F (k) Apply the corresponding gating weight g_k to perform element-wise scaling to obtain the gated features. Next, all gated hop features are concatenated along the feature dimension. The attention weight vector α for each node to different hops is obtained through the attention weight calculation layer. Then, the attention weights are weighted and fused with the gated features. Finally, the fused features are mapped back to the hidden dimension through the feature projection layer to obtain the scale-adaptive node representation H_msf. Step (4): Construction of hierarchical graph sequence Based on the scale-adaptive node representation H_msf and the node depth vector D_node, a hierarchical graph sequence representation Z_graph is constructed through hierarchical pooling operations. First, the maximum depth value max_depth of the circuit is obtained from the node depth vector D_node, determining that the circuit has L_g = max_depth + 1 levels. Then, for each level level from 0 to max_depth, a node mask mask_level is created to identify all nodes with a depth equal to level. If there are nodes in the level, the embeddings of all nodes in the level are extracted from H_msf, and the mean pooling feature mean_pool and the max pooling feature max_pool are calculated respectively. The two are concatenated along the feature dimension to obtain the embedding vector emb_level of the level. If there are no nodes in the level, zero vectors are filled in. The embedding vectors of all levels are stacked in hierarchical order to form the hierarchical graph sequence Z_graph, with a dimension of L_g × 2d_h, where d_h is the hidden dimension. This hierarchical graph sequence captures the multi-level topological structure features of the circuit from the input layer to the output layer. Step (5): Sequence Encoding and Position Information Injection The optimized sequence is embedded and encoded, and positional information is injected to generate a sequence representation H_recipe containing temporal semantics. First, the sequence index matrix R_indices is extracted from the graph data G1, with dimensions B×L_r, where B is the batch size and L_r is the sequence length. R_indices is then input into the sequence embedding layer RecipeEmbedding, which contains an embedding matrix that maps the integer indices of each heuristic operation to a 2d_h-dimensional embedding vector, resulting in a sequence embedding matrix with dimensions B×L_r×2d_h. Then, a positional encoding matrix PE is constructed, which encodes the sequence positional information using sine and cosine functions. For position pos and dimension i, the encoded value is sin(pos / 10000). (2i / 2d_h) ) or cos(pos / 10000) (2i / 2d_h) Extract the first L_r rows of the position encoding matrix PE and add them element-wise to the sequence embedding matrix to obtain the sequence representation H_recipe after injecting position information. Step (6): Dynamic Graph-Sequence Adaptive Interaction A bidirectional association between the optimized sequence and the circuit diagram structure is established through a dynamic interaction mechanism to generate a step-aware dynamic circuit representation H_tgt. First, it is extracted from the sequence representation H_recipe and transposed to L_r×B×2d_h for subsequent processing. Then, it is extracted from the hierarchical graph sequence Z_graph and expanded along the batch dimension to L_g×B×2d_h. The expanded graph sequence is then input into a graph context aggregation network, which includes a linear transformation layer and a ReLU activation function. After a learnable transformation of the graph sequence, mean pooling is performed along the hierarchical dimension to obtain a global graph context vector G_global with dimensions 1×B×2d_h. G_global is then expanded along the sequence length dimension to L_r×B×2d_h to obtain G_expand. Simultaneously, the transposed sequence representation is input into a step context extraction network, which contains two MLP layers and uses linear transformation and ReLU activation functions to perform mean pooling along the batch dimension. The U-activation and subsequent linear transformation extract a compact context representation C_step for each optimization step, with dimensions L_r×B×2d_h. Next, a step-aware modulation network concatenates G_expand and C_step along the feature dimensions, followed by a linear transformation and Tanh activation to generate a modulated graph representation G_mod, which integrates global circuit structure information and the semantic intent of the current optimization step. Further, the sequence representation, modulated graph representation, and step context are concatenated and input into an adaptive gating network. This network calculates the gating weights g_adaptive through a linear transformation and a Sigmoid activation function, and then performs element-wise weighting on G_mod to obtain the gated graph representation G_gated. Finally, a feature fusion layer concatenates the sequence representation with G_gated and performs a linear transformation to obtain the context-aware target sequence H_tgt, with dimensions L_r×B×2d_h. Step (7): Transformer Decoding and Quality Result Trajectory Prediction Sequence modeling of the dynamic interaction representation is performed using a multi-layer Transformer decoder to predict the quality outcome trajectory Ŷ during the optimization process. First, a causal attention mask M_causal is generated based on the sequence length L_r. This mask is an upper triangular matrix, ensuring that each time step only focuses on the current and previous steps. The context-aware target sequence is obtained from the dynamic interaction representation H_tgt, and the hierarchical representation is obtained from the hierarchical graph sequence Z_graph, with dimensions L_g×2d_h, expanded along the batch dimension to L_g×B×2d_h, so that the graph sequence can be aligned with each sample in the batch. The decoder's layer 0 state H_dec is initialized. (0) Let H_tgt be the input to the first layer decoder; initialize the decoder output H_dec to H_tgt; then perform forward propagation on the L layers of the Transformer decoder layer in sequence: for the ... Layer, firstly for the first The output H_dec of the layer Transformer decoder The application layer normalizes the LN, then processes it through a causal self-attention mechanism (SelfAttention), using an M_causal mask to prevent future information leakage, obtaining the self-attention output and connecting it to the residual; finally, the result is applied to the application layer normalize and processed through a cross-attention mechanism. CrossAttention interacts with the hierarchical graph sequence Z_graph, integrating circuit structure information to obtain the cross-attention output, which is then connected to the residual. Next, layer normalization is applied again, followed by feature transformation via a feedforward network FFN. This network contains two layers of linear transformation, ReLU activation, and Dropout, yielding the feedforward output which is then connected to the residual, forming the ... Layer output After L layers of decoding, the final decoded output H_final is obtained, with dimensions L_r×B×2d_h. Finally, H_final is input to the quality result prediction head, which is a linear layer that maps the 2d_h-dimensional features to a 1-dimensional scalar, thus obtaining the quality result trajectory prediction. The dimension is B×L_r, representing the predicted quality result of each circuit in the batch at each step of the sequence, including the delay or area.

2. A scale-adaptive logic synthesis optimization circuit representation learning method according to claim 1, characterized in that, It also includes step (8): loss calculation and model training. During the training phase, the loss between the predicted trajectory and the true trajectory is calculated, and the model parameters are optimized through backpropagation; from the predicted trajectory... Extract the true quality trajectory Y_trajectory from the graph data G1; calculate the mean squared error loss MSE_loss, which measures the mean of the element-wise squared differences between the predicted and true trajectories; calculate the gradient of the loss with respect to all learnable parameters of the model using the backpropagation algorithm, including the GCN parameters in the graph encoder, the multi-scale fusion module parameters, the sequence embedding layer parameters, the dynamic interaction module parameters, the Transformer decoder parameters, and the prediction head parameters; update the model parameters using the Adam optimizer based on the calculated gradients, and the optimizer includes hyperparameters such as learning rate and weight decay; repeat the forward propagation, loss calculation, backpropagation, and parameter update process until the model loss converges on the validation set or reaches the preset number of training epochs; After training is complete, the model parameters and heuristic operation vocabulary are saved for use in the subsequent inference stage.

3. A scale-adaptive logic synthesis optimization circuit representation learning method according to claim 1, characterized in that, It also includes step (9): reasoning and quality outcome prediction During the inference phase, the trained model is loaded to predict the quality results of new circuit-sequence pairs. First, the saved model parameters and heuristic operation vocabulary are loaded to construct a complete model architecture including a graph encoder, a multi-scale fusion module, a sequence encoder, a dynamic interaction module, a Transformer decoder, and a prediction head. For the input circuit to be tested and the optimized sequence, graph data G1 is constructed according to step (1), and the heuristic operations are mapped to index sequences according to the vocabulary. The graph data is input into the model, and the forward propagation process from step (2) to step (7) is executed in sequence to obtain the predicted quality result trajectory. ;from Extract the predicted value of the last step of the sequence as the prediction of the final quality result of the circuit under a given optimized sequence; Calculate the mean absolute percentage error (MAPE) between the predicted and actual values ​​to evaluate the model's performance on the test set; save the prediction results, performance metrics, and visualizations to the results directory to complete the inference process.

4. The scale-adaptive logic synthesis optimization circuit representation learning method according to claim 1, characterized in that, Step (2) specifically includes the following steps: 2-1) Construction of a Two-Layer Graph Convolutional Network A first-layer graph convolutional network (GCN1) is created with an input dimension of D_in and an output dimension of d_h, where D_in is the initial feature dimension of the nodes and d_h is the hidden layer dimension. GCN1 performs linear transformation on the node features using a learnable weight matrix W_gcn1 and performs message passing and aggregation along the graph edges to achieve the fusion of neighborhood information. A second-layer graph convolutional network (GCN2) is created with an input dimension of d_h and an output dimension of d_h. GCN2 further extracts graph topological features to enhance the expressive power of node representations. 2-2) Construction of Multi-hop Neighborhood Aggregation Transformation Layer Set the maximum number of hops K for multi-scale fusion; for each hop k from 1 to K, create a hop-specific transformation layer Transform_k, which contains a learnable weight matrix W_k∈ (d_h×d_h) and bias vector b_k∈ d_h The transformation layer is used to extract semantics from the neighborhood aggregation features of the k-th hop, enabling the model to learn differentiated feature representations of neighborhoods at different scales. 2-3) Construction of Circuit-Sensing Gated Network A two-layer multilayer perceptron is constructed as a scale-gated network, ScaleGate. The first layer is a linear layer with an input dimension of 2, corresponding to the normalized number of nodes and the normalized maximum depth, and an output dimension of d_h / 4, using the ReLU activation function. The second layer is also a linear layer with an input dimension of d_h / 4 and an output dimension of K, using the Sigmoid activation function to map the output to the [0,1] interval. The gated network adaptively generates the gating weights for each hop based on the scale characteristics of the circuit, achieving scale-aware feature modulation. 2-4) Construction of Attention Fusion Network An attention weight calculation layer, AttentionWeights, is created, which includes a linear transformation layer. The input dimension is K×d_h, the output dimension is K, and the Softmax activation function is applied to ensure that the sum of the weights is 1. The attention layer assigns importance weights to each node on different jump features to achieve adaptive multi-scale feature integration. 2-5) Construction of Feature Projection Layer Create a feature fusion projection layer called FusionProjection, which includes a linear transformation layer with an input dimension of K×d_h and an output dimension of d_h; this linear layer contains a learnable weight matrix W_fusion∈ (d_h×K·d_h) and bias vector b_fusion∈ d_h The projection layer maps the multi-hop attention-weighted features back to a unified hidden dimension space, generating the final scale-adaptive node representation. 2-6) Output encoder model E_msff All the above components are combined to form an encoder model, including a two-layer GCN network, a K-hop specific transform layer, a circuit-aware gating network, an attention fusion network, and a feature projection layer, which together constitute the scale-adaptive graph encoder E_msff.

5. The scale-adaptive logic synthesis optimization circuit representation learning method according to claim 1, characterized in that, Step (3) specifically includes the following steps: 3-1) Initial Node Embedding Extraction Extract the node feature matrix X and edge index matrix E_index from the graph data G1; input X and E_index into the first layer GCN1 of the encoder E_msff to perform linear transformation on the node features and aggregate neighbor information along the edges, apply the ReLU activation function to obtain the first layer output; input the first layer output and E_index into the second layer GCN2 for further message passing and feature extraction to obtain the initial node embedding H. (0) The dimension is N×d_h, where N is the total number of nodes; 3-2) Multi-hop neighborhood aggregation Initialize the current feature H_current to H (0) Create a list `hop_features` to store the features for each hop; for the k-th hop: (a) Extract the source node index src and the target node index dst from the edge index matrix E_index; (b) Extract the source node feature H_current[src] from H_current based on src; (c) By using the scatter_mean operation, the features of the source node are aggregated to the target node according to the dst index, resulting in the neighborhood aggregated feature M of the k-th hop. (k) The dimension is N×d_h; (d) M (k) Input is passed to the k-th hop specific transform layer Transform_k, and a linear transform F is performed. (k) =M (k) ·W_k T +b_k, to obtain the k-th hop feature F after transformation. (k) ; (e) F (k) Add to the hop_features list; (f) If k < K, then update H_current = M (k) to prepare for the next-hop aggregation; After K iterations, the hop_features list contains K feature matrices {F (1) ,F (2) ,...,F (k) }, respectively capturing the structural information of the neighborhood from 1 hop to K hops; 3-3) Circuit-scale feature extraction and gating weight calculation Extract the node depth vector D_node from the graph data G1; calculate the normalized number of nodes s_n = N / N param Where N is the total number of nodes; N param This serves as a reference value for the number of nodes in the normalization process, ensuring a reasonable distribution of the normalized values. Extract the maximum depth value max_depth from D_node, and calculate the normalized maximum depth s_d = max_depth / d. param ;d param The reference value for the normalization depth is used to ensure a reasonable distribution of normalized values; a scale feature vector s=[s_n,s_d] is constructed. T ∈ 2 The input s is fed into the circuit-aware gating network ScaleGate. After the first linear transformation, ReLU activation, the second linear transformation, and Sigmoid activation, a K-dimensional gating weight vector g=[g_1,g_2,...,g_K] is obtained. T where each g_k∈[0,1]; 3-4) Gated Feature Modulation For each hop k from 1 to K, extract the k-th hop feature F from hop_features. (k) Extract the k-th weight g_k from the gated weight vector g; perform element-wise scaling operation. The gating features are obtained. ; All gated features Collect them; 3-5) Attention-weighted fusion Concatenate the K gated features along the feature dimensions to obtain the concatenated feature F_concat∈ (N×Kd_h) Each row contains the gated features of that node across all K hops; F_concat is input to the attention weight calculation layer AttentionWeights, and through linear transformation and Softmax activation, the hop-level attention weight matrix α∈ for each node is obtained. (N×K) Where the element α_ik in the i-th row and k-th column of α represents the attention weight of the i-th node to the k-th hop feature, and Σ_kα_ik=1; for each hop k, extract the k-th column α_{:,k} from α, and combine it with... Perform element-wise multiplication We obtain the k-th hop feature after weighting; we concatenate all K weighted features along the feature dimension to obtain the weighted concatenated feature F_weighted∈ (N×Kd_h) ; 3-6) Feature Projection and Output The weighted concatenated features F_weighted are input into the feature fusion projection layer FusionProjection, and a linear transformation H_msf = F_weighted·W_fusion is performed. T +b_fusion maps the Kd_h-dimensional features back to the d_h-dimensional features, resulting in the scale-adaptive node representation H_msf∈ (N×d_h) .

6. The scale-adaptive logic synthesis optimization circuit representation learning method according to claim 1, characterized in that, Step (6) specifically includes the following steps: 6-1) Dimensional Adjustment of Sequence and Graph Representations The sequence representation after extracting the injection position information from the sequence representation H_recipe has a dimension of B×L_r×2d_h; it is then transposed along the 0th and 1st dimensions to obtain the transposed sequence representation with a dimension of L_r×B×2d_h, to adapt to the input format of the subsequent Transformer decoder; it is extracted from the hierarchical graph sequence Z_graph with a dimension of L_g×2d_h; Z_graph is expanded along the batch dimension, and it is copied B times through tensor expansion operations to obtain the expanded graph sequence with a dimension of L_g×B×2d_h; 6-2) Global Aggregation in Graph Context A graph context aggregation network, GraphAggregator, is constructed, consisting of a linear transformation layer with input and output dimensions of 2d_h and a ReLU activation function. The expanded graph sequence is input into GraphAggregator, and linear transformation and activation are performed on each layer embedding of each batch to obtain the transformed graph sequence. Mean pooling (torch.mean(dim=0, keepdim=True)) is performed on the transformed graph sequence along the layer dimension (0th dimension), aggregating the features of L_g layers into a single global graph context vector G_global with dimensions 1×B×2d_h. G_global is then expanded along the sequence length dimension by copying it L_r times using the expand operation to obtain the expanded global graph context G_expand with dimensions L_r×B×2d_h, ensuring that the graph context is aligned with each time step of the sequence. 6-3) Semantic Context Extraction A step context extraction network, StepEncoder, is constructed, consisting of two multilayer perceptron layers. The first layer is a linear layer with both input and output dimensions of 2d_h, using the ReLU activation function. The second layer is also a linear layer with both input and output dimensions of 2d_h. The transposed sequence representation, with dimensions L_r×B×2d_h, is input into StepEncoder and sequentially passes through the first layer linear transformation, ReLU activation, and the second layer linear transformation to obtain the step context representation C_step, with dimensions L_r×B×2d_h. 6-4) Step-sensing map modulation A step-aware modulation network, GraphModulator, is constructed, consisting of linear layers with an input dimension of 4d_h and an output dimension of 2d_h, as well as a Tanh activation function. The extended global graph context G_expand and the step context C_step are concatenated along the feature dimension, i.e., the second dimension, to obtain a concatenated tensor with dimensions L_r×B×4d_h. The concatenated tensor is then input into GraphModulator, and through linear transformation and Tanh activation, the modulated graph representation G_mod with dimensions L_r×B×2d_h is obtained. 6-5) Adaptive Gating An adaptive gating network, AdaptiveGate, is constructed, consisting of linear layers with an input dimension of 6d_h and an output dimension of 2d_h, and a sigmoid activation function. The transposed sequence representation, the modulation graph representation G_mod, and the step context C_step are concatenated along the feature dimension to obtain a gated input tensor with a dimension of L_r×B×6d_h. The gated input tensor is input into AdaptiveGate, and through linear transformation and sigmoid activation, adaptive gate weights g_adaptive with a dimension of L_r×B×2d_h are obtained, where each element takes values ​​in the range [0,1]. Element-wise multiplication G_gated = g_adaptive ⊙ G_mod is performed on the modulation graph representation G_mod and the gate weights g_adaptive to obtain the gated graph representation G_gated with a dimension of L_r×B×2d_h. 6-6) Feature Fusion and Output A feature fusion layer, FeatureFusion, is constructed, consisting of a linear layer with an input dimension of 4d_h and an output dimension of 2d_h. The transposed sequence representation and the gated graph representation G_gated are concatenated along the feature dimensions to obtain a fusion input tensor with dimensions L_r×B×4d_h. The fusion input tensor is then input into FeatureFusion, and through linear transformation, a context-aware target sequence representation H_tgt with dimensions L_r×B×2d_h is obtained.

7. The scale-adaptive logic synthesis optimization circuit representation learning method according to claim 1, characterized in that, Step (7) specifically includes the following steps: 7-1) Causal Attention Mask Generation Based on the sequence length L_r, create an L_r×L_r square matrix; fill the upper triangular part of the square matrix with negative infinity, and fill the lower triangular part and the diagonal with 0 to obtain the causal attention mask M_causal; the mask ensures that in the self-attention calculation, the query vector at position i can only focus on the key vector at position j≤i, preventing the model from seeing information of future steps when predicting the i-th step, which conforms to the temporal constraints of causal inference; 7-2) Decoder Input Preparation Extract the context-aware target sequence from the dynamic interactive representation H_tgt, with dimensions L_r×B×2d_h; extract it from the hierarchical graph sequence Z_graph and expand it along the batch dimension to L_g×B×2d_h; initialize the decoder's current state H_dec. (0) For H_tgt; 7-3) Transformer decoder layer iteration Set the decoder layer number L_decoder. For each layer ℓ from 1 to L_decoder, perform the following operations in sequence: (a) Causal self-attention sublayer: for H_dec (l-1) The application layer normalizes LN_sa to obtain a normalized representation; this normalized representation is then input into the multi-head self-attention mechanism SelfAttention, which uses a causal mask M_causal to compute the query, key, and value matrices and performs scaled dot product attention to obtain the self-attention output; the self-attention output is then compared with H_dec. (l-1) Perform residual connections and apply Dropout to obtain the output H_sa of the self-attention layer; (b) Cross-attention sublayer: Apply layer normalization LN_ca to H_sa to obtain a normalized representation; use the normalized representation as the query vector, and use the expanded layered graph sequence Z_graph as the key and value vector, input it into the multi-head cross-attention mechanism CrossAttention, calculate the attention weights and perform weighted aggregation to obtain the cross-attention output; perform a residual connection between the cross-attention output and H_sa, and apply Dropout to obtain the output H_ca of the cross-attention layer; (c) Feedforward sublayer: Apply layer normalization LN_ffn to H_ca to obtain a normalized representation; input the normalized representation into the feedforward network FFN, which includes a first-layer linear transformation, ReLU activation, Dropout, a second-layer linear transformation, and Dropout, to obtain the feedforward network output; perform a residual connection between the feedforward output and H_ca to obtain the... The final output of the layer ; After iteration through the L_decoder layer, the final decoded output H_final = H_dec is obtained. (Ldecoder) The dimension is L_r×B×2d_h; 7-4) Prediction of Quality Result Trajectory Construct a quality result prediction head, QoRHead, containing a linear layer with an input dimension of 2d_h and an output dimension of 1. Input H_final into QoRHead and perform a linear transformation on each sample at each time step to obtain the predicted quality result with a dimension of L_r×B×1. Remove the last dimension to obtain an L_r×B tensor. Transpose this tensor along the 0th and 1st dimensions and apply a squeeze operation to remove redundant dimensions to obtain the predicted quality result trajectory. The dimension is B×L_r; The element in the i-th row and j-th column represents the predicted quality result of the i-th circuit in the batch after the j-th step of the optimization sequence.

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