Chip verification method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a chip verification method and device, electronic equipment and a storage medium, relates to the technical field of semiconductors, and can effectively improve the chip verification efficiency. The method comprises the steps that a chip simulation model of a to-be-verified chip is acquired, the to-be-verified chip comprises at least two circuit modules which are mutually connected, and the at least two circuit modules comprise a first circuit module and a second circuit module; the chip simulation model comprises a first simulation model, a first interface function, a second simulation model and a second interface function; wherein the first simulation model is a register transfer level simulation model of the first circuit module, and the second simulation model is a transaction level simulation model of the second circuit module; the first interface function is used for being called by the first simulation model to access a target memory; the second interface function is used for being called by a second simulation model to access the target memory; and running the chip simulation model to verify the to-be-verified chip. The method can be applied to chip verification.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a chip verification method, apparatus, electronic device, and storage medium. Background Technology

[0002] In chip design, it is often necessary to build a simulation model for the chip and verify the chip's circuit structure or behavior based on the simulation model to ensure that the chip can achieve the expected function.

[0003] However, while register-transfer level simulation models (such as VCS (Verilog Compiler Simulator)-based simulation models) can accurately simulate the behavior of the logic units of a circuit, the computational load required for verification is increasing and the verification time is getting longer as chip integration density increases and circuit size expands, resulting in low verification efficiency. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention provide a chip verification method, apparatus, electronic device and computer-readable storage medium, which can effectively improve chip verification efficiency.

[0005] In a first aspect, embodiments of the present invention provide a chip verification method, comprising: A chip simulation model of a chip to be verified is obtained. The chip to be verified includes at least two interconnected circuit modules, including a first circuit module and a second circuit module. The chip simulation model includes a first simulation model, a first interface function, a second simulation model, and a second interface function. The first simulation model is a register-transfer level simulation model of the first circuit module, and the second simulation model is a transaction-level simulation model of the second circuit module. The first interface function is used to be called by the first simulation model to access target memory; the second interface function is used to be called by the second simulation model to access the target memory. The chip simulation model is run to verify the chip to be verified. The first simulation model and the second simulation model interact with each other through the first interface function, the second interface function and the target memory according to the clock cycle of the first simulation model.

[0006] In one embodiment, obtaining the chip simulation model of the chip to be verified includes: Obtain a chip to be verified, the chip to be verified including a first circuit module and a second circuit module; A first simulation model is constructed based on the first circuit module, a second simulation model is constructed based on the second circuit module, and the first interface function and the second interface function are constructed based on the interaction signals between the first circuit module and the second circuit module.

[0007] In one implementation, the number of interaction signals is at least one, and the construction of the first interface function and the second interface function based on the interaction signals between the first circuit module and the second circuit module includes: Based on the function and transmission direction of each interaction signal, the interaction signals are grouped to obtain at least one interaction signal group. The interaction signals in the same interaction signal group have the same function and the same transmission direction. The transmission direction includes transmission from the first circuit module to the second circuit module, or transmission from the second circuit module to the first circuit module. A corresponding data structure is generated based on each of the aforementioned interactive signal groups; Based on the transmission direction of the interactive signal in each interactive signal group, construct a first interface function and a second interface function for the data structure corresponding to each interactive signal group; A semaphore generation function is constructed to generate a first semaphore for each of the first interface functions and a second semaphore for each of the second interface functions. Each of the first interface functions is used to write data corresponding to the data structure to the target memory or read data from the target memory according to the indication of the second semaphore. Each of the second interface functions is used to write data corresponding to the data structure to the target memory or read data from the target memory according to the indication of the first semaphore.

[0008] In one implementation, the first interface function includes a first write memory function and / or a first read memory function; the second interface function includes a second write memory function and / or a second read memory function. The step of constructing a first interface function and a second interface function for each data structure corresponding to each interaction signal group based on the transmission direction of the interaction signal in each interaction signal group includes: When the transmission direction of the interaction signal in each interaction signal group is from the first circuit module to the second circuit module, a first write memory function and a second read memory function are constructed for the data structure corresponding to each interaction signal group. or, When the transmission direction of the interaction signal in each interaction signal group is from the second circuit module to the first circuit module, a second write memory function and a first read memory function are constructed for the data structure corresponding to each interaction signal group.

[0009] In one implementation, the first semaphore includes a first read semaphore; the second semaphore includes a second write semaphore. The semaphore generation function is used to: generate a first read semaphore for each of the first read memory functions; and generate a second write semaphore for each of the second write memory functions; or, The first semaphore includes a first write semaphore; the second semaphore includes a second read semaphore. The semaphore generation function is used to: generate the first write semaphore for each of the first write memory functions; and generate the second read semaphore for each of the second read memory functions.

[0010] In one implementation, running the chip simulation model to verify the chip to be verified includes: Obtain the target memory, and grant access permissions to the target memory to the first interface function and the second interface function respectively; In each clock cycle of at least one clock cycle of the first simulation model, the first interface function and the second interface function are executed.

[0011] In one embodiment, before executing the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model, the method further includes: A first semaphore is generated for the first interface function according to a preset semaphore generation function, and a second semaphore is generated for the second interface function. The execution of the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model includes: In each clock cycle of at least one clock cycle of the first simulation model, the first interface function and the second interface function are executed based on the first semaphore and the second semaphore.

[0012] In one implementation, generating a first semaphore for the first interface function and a second semaphore for the second interface function according to a preset semaphore generation function includes: The first semaphore and the second semaphore are generated by using the hash value of the preset process ID as one of the input parameters of the semaphore generation function.

[0013] In one implementation, the first interface function includes a first memory read function; the second interface function includes a second memory write function. The step of generating a first semaphore for the first interface function and a second semaphore for the second interface function according to a preset semaphore generation function includes: A first read semaphore is generated for the first read memory function according to a preset semaphore generation function, and a second write semaphore is generated for the second write memory function. The execution of the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model includes: If the current clock cycle is the first clock cycle of the second simulation model's operation, the second simulation model initializes the target memory; The second simulation model writes data to the target memory through the second write memory function, and sets the second write semaphore to the first value after the write is completed; The first simulation model detects that the second write semaphore is a first value, reads data from the target memory through the first read memory function, and sets the second write semaphore to a second value; After the first simulation model finishes reading data from the target memory, it sets the first read semaphore to a first value to prepare for the next clock cycle.

[0014] In one implementation, after the second simulation model determines whether the triggered current clock cycle is the first clock cycle, the method further includes: If the current clock cycle is not the first clock cycle of the second simulation model, the second simulation model detects whether the first read signal is the first value; In response to detecting that the first read semaphore is a first value, the second simulation model writes data to the target memory through the second write memory function and sets the first read semaphore to a second value; After the second simulation model finishes writing the data, it sets the second write semaphore to the first value; The first simulation model detects that the second write semaphore is a first value, reads data from the target memory through the first read memory function, and sets the second write semaphore to a second value; After the first simulation model finishes reading data from the target memory, it sets the first read semaphore to a first value to prepare for the next clock cycle.

[0015] In one implementation, the first interface function includes a first memory write function; the second interface function includes a second memory read function. The first write memory function has a corresponding first write semaphore; the second read memory function has a corresponding second read semaphore; The execution of the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model includes: In each clock cycle of at least one clock cycle of the first simulation model, the first simulation model detects whether the second read signal is a first value; When the second read semaphore is the first value, the first simulation model writes data to the target memory through the first write memory function and sets the second read semaphore to the second value; After the first simulation model finishes writing data, the first write semaphore is set to the first value; The second simulation model detects that the first write semaphore is a first value, reads data from the target memory through the second read memory function, and sets the first write semaphore to a second value; After the second simulation model finishes reading data from the target memory, it sets the second read semaphore to the first value to prepare for the next cycle.

[0016] In one implementation, acquiring the target memory and granting access permissions to the target memory to the first interface function and the second interface function respectively includes: In response to the startup of one of the first simulation models or the second simulation models, the target memory is requested from the operating system with the hash value of the preset process ID as one of the input parameters of the memory request function, and the access rights of the target memory are granted to one of the interface functions corresponding to the simulation model that has been started in the first interface function and the second interface function, wherein the target memory is labeled with the hash value of the preset process ID; In response to the startup of the first simulation model or another simulation model in the second simulation model, if the target memory labeled with a hash value of a preset process ID is detected to already exist, access rights to the target memory are granted to the other interface function in the first interface function and the second interface function.

[0017] In one implementation, requesting the target memory from the operating system includes: Determine the amount of data exchanged between the first simulation model and the second simulation model within one clock cycle of the first simulation model; Based on the amount of data, request the target memory from the operating system.

[0018] In one embodiment, the at least two circuit modules include at least one first circuit module and at least one second circuit module, wherein one first circuit module is coupled to at least two second circuit modules, and / or, wherein one second circuit module is coupled to at least two first circuit modules; wherein each first circuit module has a corresponding first simulation model, and each second circuit module has a corresponding second simulation model; Each set of the first simulation model and the second simulation model with data interaction relationship is a model combination, which interacts with each other through a set of corresponding first interface functions, second interface functions and target memory; the first interface functions, second interface functions and target memory corresponding to different model combinations are all different from each other.

[0019] Secondly, embodiments of the present invention provide a chip verification apparatus, comprising: A model acquisition unit is used to acquire a chip simulation model of a chip to be verified. The chip to be verified includes at least two interconnected circuit modules, including a first circuit module and a second circuit module. The chip simulation model includes a first simulation model, a first interface function, a second simulation model, and a second interface function. The first simulation model is a register-transfer level simulation model of the first circuit module, and the second simulation model is a transaction-level simulation model of the second circuit module. The first interface function is used to be called by the first simulation model to access target memory; the second interface function is used to be called by the second simulation model to access the target memory. The model running unit is used to run the chip simulation model to verify the chip to be verified. The first simulation model and the second simulation model interact with each other through the first interface function, the second interface function and the target memory according to the clock cycle of the first simulation model.

[0020] In one embodiment, the model acquisition unit includes: An acquisition module is used to acquire a chip to be verified, the chip to be verified including a first circuit module and a second circuit module; A construction module is used to construct a first simulation model based on the first circuit module, construct a second simulation model based on the second circuit module, and construct the first interface function and the second interface function based on the interaction signals between the first circuit module and the second circuit module.

[0021] In one implementation, the building module includes: An interactive signal grouping submodule is used to group the interactive signals according to their functions and transmission directions to obtain at least one interactive signal group. The interactive signals in the same interactive signal group have the same function and the same transmission direction. The transmission direction includes transmission from the first circuit module to the second circuit module, or transmission from the second circuit module to the first circuit module. A data structure generation submodule is used to generate a corresponding data structure based on each group of interaction signals; The first construction submodule is used to construct a first interface function and a second interface function for each data structure corresponding to each interaction signal group according to the transmission direction of the interaction signal in each interaction signal group. The second construction submodule is used to construct a semaphore generation function to generate a first semaphore for each of the first interface functions and a second semaphore for each of the second interface functions. Each of the first interface functions is used to write data corresponding to the data structure into the target memory or read data from the target memory according to the indication of the second semaphore. Each of the second interface functions is used to write data corresponding to the data structure into the target memory or read data from the target memory according to the indication of the first semaphore.

[0022] In one implementation, the first interface function includes a first write memory function and / or a first read memory function; the second interface function includes a second write memory function and / or a second read memory function. The first construction submodule is specifically used for: When the transmission direction of the interaction signal in each interaction signal group is from the first circuit module to the second circuit module, a first write memory function and a second read memory function are constructed for the data structure corresponding to each interaction signal group. or, When the transmission direction of the interaction signal in each interaction signal group is from the second circuit module to the first circuit module, a second write memory function and a first read memory function are constructed for the data structure corresponding to each interaction signal group.

[0023] In one implementation, the first semaphore includes a first read semaphore; the second semaphore includes a second write semaphore. The semaphore generation function is used to: generate a first read semaphore for each of the first read memory functions; and generate a second write semaphore for each of the second write memory functions; or, The first semaphore includes a first write semaphore; the second semaphore includes a second read semaphore. The semaphore generation function is used to: generate the first write semaphore for each of the first write memory functions; and generate the second read semaphore for each of the second read memory functions.

[0024] In one embodiment, the model running unit includes: The memory acquisition module acquires the target memory and assigns access permissions for the target memory to the first interface function and the second interface function, respectively. The function execution module executes the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model.

[0025] In one embodiment, the model running unit further includes: The semaphore generation module is used to generate a first semaphore for the first interface function and a second semaphore for the second interface function according to a preset semaphore generation function before executing the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model. The function execution module is specifically used to execute the first interface function and the second interface function based on the first semaphore and the second semaphore in each clock cycle of at least one clock cycle of the first simulation model.

[0026] In one implementation, the semaphore generation module is specifically used for: The first semaphore and the second semaphore are generated by using the hash value of the preset process ID as one of the input parameters of the semaphore generation function.

[0027] In one implementation, the first interface function includes a first memory read function; the second interface function includes a second memory write function. The semaphore generation module is specifically used to generate a corresponding first read semaphore for the first read memory function and a corresponding second write semaphore for the second write memory function according to a preset semaphore generation function. The function execution module is specifically used for: In the case that the current clock cycle is the first clock cycle of the second simulation model, the target memory is initialized by means of the second simulation model; The second simulation model writes data to the target memory through the second write memory function, and sets the second write semaphore to the first value after the write is completed; The first simulation model detects that the second write semaphore is a first value, reads data from the target memory through the first read memory function, and sets the second write semaphore to a second value; After the first simulation model finishes reading data from the target memory, it sets the first read semaphore to a first value to prepare for the next clock cycle.

[0028] In one implementation, the function execution module is further configured to: If the current clock cycle is not the first clock cycle of the second simulation model, the second simulation model detects whether the first read signal is the first value; In response to detecting that the first read semaphore is a first value, the second simulation model writes data to the target memory through the second write memory function and sets the first read semaphore to a second value; after the second simulation model finishes writing the data, it sets the second write semaphore to the first value. The first simulation model detects that the second write semaphore is a first value, reads data from the target memory through the first read memory function, and sets the second write semaphore to a second value; After the first simulation model finishes reading data from the target memory, it sets the first read semaphore to a first value to prepare for the next clock cycle.

[0029] In one implementation, the first interface function includes a first memory write function; the second interface function includes a second memory read function. The first write memory function has a corresponding first write semaphore; the second read memory function has a corresponding second read semaphore; The function execution module is specifically used for: In each clock cycle of at least one clock cycle of the first simulation model, the first simulation model detects whether the second read signal is a first value; When the second read semaphore is the first value, the first simulation model writes data to the target memory through the first write memory function and sets the second read semaphore to the second value; After the first simulation model finishes writing data, the first write semaphore is set to the first value; The second simulation model detects that the first write semaphore is a first value, reads data from the target memory through the second read memory function, and sets the first write semaphore to a second value; After the second simulation model finishes reading data from the target memory, it sets the second read semaphore to the first value to prepare for the next cycle.

[0030] In one embodiment, the memory acquisition module includes: The memory allocation submodule, in response to the startup of one of the first simulation model or the second simulation model, uses the hash value of the preset process ID as one of the input parameters of the memory allocation function to request the target memory from the operating system, and grants the access rights of the target memory to one of the interface functions corresponding to the simulation model that has been started in the first interface function and the second interface function, wherein the target memory is labeled with the hash value of the preset process ID; Access permissions are granted to the submodule in response to the startup of the first simulation model or another simulation model in the second simulation model. If the target memory labeled with a hash value of a preset process ID is detected, access permissions for the target memory are granted to the other interface function in the first interface function and the second interface function.

[0031] In one implementation, the memory allocation submodule is specifically used for: Determine the amount of data exchanged between the first simulation model and the second simulation model within one clock cycle of the first simulation model; Based on the amount of data, request the target memory from the operating system.

[0032] In one embodiment, the at least two circuit modules include at least one first circuit module and at least one second circuit module, wherein one first circuit module is coupled to at least two second circuit modules, and / or, wherein one second circuit module is coupled to at least two first circuit modules; wherein each first circuit module has a corresponding first simulation model, and each second circuit module has a corresponding second simulation model; Each set of the first simulation model and the second simulation model with data interaction relationship is a model combination, which interacts with each other through a set of corresponding first interface functions, second interface functions and target memory; the first interface functions, second interface functions and target memory corresponding to different model combinations are all different from each other.

[0033] Thirdly, embodiments of the present invention provide an electronic device, including a processor and a memory, wherein the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing any chip verification method provided by embodiments of the present invention.

[0034] Fourthly, embodiments of the present invention provide a computer-readable storage medium having one or more programs that can be executed by one or more processors to implement any of the chip verification methods provided in the embodiments of the present invention.

[0035] This invention provides a chip verification method, apparatus, electronic device, and computer storage medium. It can acquire a chip simulation model of a chip to be verified and run the simulation model to verify the chip. The chip simulation model may include a first simulation model, a first interface function, a second simulation model, and a second interface function. The first simulation model is a register-transfer level simulation model of a first circuit module of the chip to be verified, and the second simulation model is a transaction-level simulation model of a second circuit module of the chip to be verified. During verification, the first simulation model and the second simulation model can interact with each other through the first interface function, the second interface function, and the target memory according to the clock cycle of the first simulation model. In this way, a register-transfer level simulation model can be established for the first circuit module, which is of primary concern at the current stage, and a transaction-level simulation model can be established for the second circuit module, which is not of primary concern at the current stage, based on verification requirements. Since the transaction-level simulation model can interact with the register-transfer-level simulation model to verify the first circuit module, and does not need to simulate circuit operation as precisely as the register-transfer-level simulation model, combining the register-transfer-level simulation model and the transaction-level simulation model can significantly reduce the amount of computation in the simulation and shorten the simulation time while accurately verifying the first circuit module, thereby effectively improving the verification efficiency. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A flowchart of a chip simulation method provided for an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the chip to be verified in an embodiment of the present invention; Figure 3 This is a schematic diagram of a chip simulation model in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the interaction between the first simulation model and the second simulation model in an embodiment of the present invention; Figure 5This is a schematic diagram illustrating the changes in semaphores during the data transmission process from the first simulation model to the second simulation model in an embodiment of the present invention. Figure 6 This is another schematic diagram of the chip simulation model in an embodiment of the present invention; Figure 7 This is a schematic diagram of a chip verification device in an embodiment of the present invention; Figure 8 A schematic diagram of an electronic device provided as an embodiment of the present invention. Detailed Implementation

[0038] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0039] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0040] First, the abbreviations and key terms in this invention are explained as follows: VCS: Verilog Compiler Simulator, is a simulation tool for the Verilog hardware description language. It can compile Verilog code into an executable model and provides simulation and debugging functions for verifying the correctness and performance of hardware designs.

[0041] RTL: Register Transfer Level, is an abstraction level in hardware description languages ​​used to describe the transfer relationships between registers, data paths, and control logic in digital circuits.

[0042] TLM: Transaction Level Modeling, used to describe the interaction and communication behavior in a system without focusing on specific hardware details.

[0043] DPI: Direct Programming Interface, an interface for interacting between hardware description languages ​​(Verilog or SystemVerilog) and other programming languages.

[0044] GEM5: An event-driven computer system simulator. GEM5 is widely used in computer architecture research, processor design, memory design, and operating systems.

[0045] SystemC: A C++-based hardware description language and hardware modeling tool used to describe and model the functionality and behavior of hardware systems.

[0046] As mentioned in the background section, with the increase in chip integration and the expansion of circuit scale, the computational load required for verification is increasing, the verification time is also increasing, and the verification efficiency is low. The inventors found in their research that although there are some transaction-level simulation models with shorter processing times (such as the GEM5 model) in related technologies, the simulation accuracy of transaction-level simulation models is low. Moreover, they can only exchange transaction-level (TLM) information with other systems that support this interface through the SystemC interface, which is difficult to correspond to the behavior of RTL interface. Therefore, it is also difficult to perform synchronous simulation with register transfer level simulation models, making it difficult to improve chip verification efficiency.

[0047] To this end, the inventors discovered a chip verification method that can use register transfer level simulation model and transaction level simulation model to perform chip verification in collaboration, thereby effectively improving chip verification efficiency. The following is a detailed description.

[0048] Firstly, embodiments of the present invention provide a chip verification method that can effectively improve chip verification efficiency.

[0049] like Figure 1 As shown, the chip verification method provided by the embodiments of the present invention may include: Step S100: Obtain the chip simulation model of the chip to be verified. The chip to be verified includes at least two interconnected circuit modules, including a first circuit module and a second circuit module. The chip simulation model includes a first simulation model, a first interface function, a second simulation model, and a second interface function. The first simulation model is a register-transfer level simulation model of the first circuit module, and the second simulation model is a transaction-level simulation model of the second circuit module. The first interface function is used to be called by the first simulation model to access the target memory; the second interface function is used to be called by the second simulation model to access the target memory. In this embodiment, chip verification is the process of verifying the designed chip before it enters the tape-out stage after the chip design is completed, thereby verifying the expected functions and performance of the chip design. Chip verification can be performed on the entire chip or on a partial design, such as verifying a portion of the circuit model within the chip; this embodiment of the invention does not limit this approach. In one example, the chip to be verified may contain two or more circuit modules.

[0050] A chip simulation model is a model established for verifying a chip, and may include the chip itself and the verification environment constructed to verify the chip. In embodiments of the present invention, each circuit module in the chip to be verified may have its own corresponding simulation model, and the chip simulation model may include simulation models of at least two circuit modules.

[0051] Depending on the simulation principle, the simulation model type for each circuit module can also differ. For example, in one example, the simulation model for the first circuit module of the chip to be verified can be a Register Transfer Level (RTL) simulation model, while the simulation model for the second circuit module can be a Transaction Level Modeling (TLM) simulation model. In the embodiments of this invention, different simulation model types result in different representations of the circuit modules within the simulation models. For example, in a Register Transfer Level simulation model, a circuit module can be a Register Transfer Level circuit netlist, while in a Transaction Level Modeling simulation model, a circuit module can be a functional module of the circuit, without involving the specific circuit structure and implementation details of the circuit module.

[0052] Among them, the register-transfer-level simulation model can describe the data transmission and operation between registers and other logic circuits as the clock edge changes, thereby verifying the expected function of registers and other logic circuits; for example, in one example, the register-transfer-level simulation model may include the VCS model, the QEMU (Quick Emulator) model, etc.

[0053] Transaction-level simulation models employ a discrete event-driven mechanism, supporting periodic-level precision modeling and enabling detailed simulation of hardware functional modules in computer systems. Periodic precision modeling achieves high simulation speed while maintaining functional accuracy. For example, a transaction-level simulation model could include a GEM5 model or a Sparta simulation model. Unlike methods that simulate every clock cycle, periodic precision modeling advances the simulation using instruction cycles as the basic unit, thereby reducing the number of events during the simulation process and significantly improving simulation efficiency and shortening simulation time. Compared to other simulation methods, periodic modeling offers advantages such as faster simulation speed and lower computational resource consumption while maintaining high accuracy.

[0054] In embodiments of the present invention, the chip simulation model may include a first simulation model, a second simulation model, a first interface function, and a second interface function, in addition to the first simulation model and the second simulation model. The first interface function can be called by the first simulation model to access the target memory; the second interface function can be called by the second simulation model to access the target memory. That is, both the first and second simulation models can access the same storage space (i.e., the target memory) through their respective interface functions.

[0055] For example, in one instance, the chip to be verified may include a first circuit module and a second circuit module, and the structure of the chip to be verified may be as follows: Figure 2 As shown; the chip simulation model of the chip to be verified may include a first simulation model, a second simulation model, a first interface function, and a second interface function, and the structure of the chip to be verified may be as follows. Figure 3 As shown.

[0056] Step S200: Run the chip simulation model to verify the chip to be verified, wherein the first simulation model and the second simulation model interact with each other through the first interface function, the second interface function and the target memory according to the clock cycle of the first simulation model.

[0057] In this step, the first simulation model is a register-transfer level simulation model of the first circuit module, which can accurately simulate the operation of each logic unit of the first circuit module in each clock cycle. The second simulation model is a transaction-level simulation model of the second circuit module, which can advance the simulation with the instruction cycle as the basic unit. Since an instruction cycle can include one or more clock cycles, in this step, the first simulation model and the second simulation model can interact with each other according to the clock cycle of the first simulation model, thereby realizing synchronous simulation of two different types of simulation models.

[0058] Specifically, data interaction between the first simulation model and the second simulation model can be achieved by calling interface functions in the chip simulation model. Specifically, the first simulation model can call a first interface function to access the target memory, and the second simulation model can call a second interface function to access the target memory.

[0059] The chip simulation model of this invention can acquire a chip simulation model of the chip to be verified and run the chip simulation model to verify the chip to be verified. The chip simulation model may include a first simulation model, a first interface function, a second simulation model, and a second interface function. The first simulation model is a register-transfer level simulation model of a first circuit module of the chip to be verified, and the second simulation model is a transaction-level simulation model of a second circuit module of the chip to be verified. During verification, the first simulation model and the second simulation model can interact with each other through the first interface function, the second interface function, and the target memory according to the clock cycle of the first simulation model. In this way, a register-transfer level simulation model can be established for the first circuit module, which is of primary concern at the current stage, and a transaction-level simulation model can be established for the second circuit module, which is not of primary concern at the current stage, according to the verification requirements. Since the transaction-level simulation model can interact with the register-transfer level simulation model to verify the first circuit module, but does not require the precise simulation of circuit operation as the register-transfer level simulation model, combining the register-transfer level simulation model and the transaction-level simulation model can significantly reduce the computational load and shorten the simulation time while accurately verifying the first circuit module, thereby effectively improving verification efficiency.

[0060] In some embodiments, step S100, obtaining the chip simulation model of the chip to be verified may include: obtaining the chip to be verified, the chip to be verified including a first circuit module and a second circuit module; constructing a first simulation model based on the first circuit module, constructing a second simulation model based on the second circuit module, and constructing the first interface function and the second interface function based on the interaction signals between the first circuit module and the second circuit module.

[0061] In this embodiment, the chip to be verified may include a first circuit module and a second circuit module. The first circuit module can be implemented using register-transfer level design code, which may include specific circuit structure information, such as registers and combinational logic. A register-transfer level simulation model can be constructed based on the first circuit module to obtain a first simulation model. The second circuit module can be implemented using functional description code without specific circuit structure information. A transaction-level simulation model can be constructed based on the second circuit module to obtain a second simulation model. In this embodiment, there may be interaction signals between the first circuit module and the second circuit module. The number of interaction signals is unlimited; there may be one or more. Furthermore, a first interface function and a second interface function can be constructed based on the interaction signals. The first simulation model can call the first interface function to process the interaction signals, and the second simulation model can call the second interface function to process the interaction signals.

[0062] In some embodiments, the number of interaction signals is at least one, and constructing the first interface function and the second interface function based on the interaction signals between the first circuit module and the second circuit module may include: Based on the function and transmission direction of each interaction signal, the interaction signals are grouped to obtain at least one interaction signal group. The interaction signals in the same interaction signal group have the same function and the same transmission direction. The transmission direction includes transmission from the first circuit module to the second circuit module, or transmission from the second circuit module to the first circuit module. A corresponding data structure is generated based on each of the aforementioned interactive signal groups; Based on the transmission direction of the interactive signal in each interactive signal group, construct a first interface function and a second interface function for the data structure corresponding to each interactive signal group; A semaphore generation function is constructed to generate a first semaphore for each of the first interface functions and a second semaphore for each of the second interface functions. Each of the first interface functions is used to write data corresponding to the data structure to the target memory or read data from the target memory according to the indication of the second semaphore. Each of the second interface functions is used to write data corresponding to the data structure to the target memory or read data from the target memory according to the indication of the first semaphore.

[0063] In this embodiment, there are interactive signals between the first circuit module and the second circuit module. The number of interactive signals can be one or more, and the embodiments of the present invention do not limit this. Each interactive signal can have its own function and transmission direction. In one implementation, the interactive signals can be grouped according to their function and transmission direction, and interactive signals with the same function and the same transmission direction can be grouped into the same group to obtain at least one interactive signal group. For example, in one example, D1 and D2 are two data signals with the same function sent in parallel from the first circuit module to the second circuit module, and D1 and D2 can be grouped into one interactive signal group. As another example, in another example, C1 is a control signal sent from the first circuit module to the second circuit module, and C2 is a control signal sent from the second circuit module to the first circuit module. Since C1 and C2 have different transmission directions, C1 and C2 cannot be grouped into the same interactive signal group, but C1 can be grouped into one interactive signal group and C2 into another interactive signal group.

[0064] After obtaining the interaction signal groups, a data structure can be constructed for each interaction signal group. Then, the first simulation model corresponding to the first circuit module and the second simulation model corresponding to the second circuit module can interact with the target memory based on the data structure corresponding to each interaction signal group. For example, the first simulation model can write the data structure into the target memory, and the second simulation model can read the data structure from the target memory.

[0065] In one embodiment of the present invention, a first interface function and a second interface function can be constructed for the data structure corresponding to each group of interactive signals. The first interface function serves as an interaction channel between the first simulation model and the target memory, while the second interface function serves as an interaction channel between the second simulation model and the target memory, thereby enabling data interaction between the first and second simulation models. For example, in one instance, the first simulation model can write data to the target memory through the first interface function, and the second simulation model can read the data written to the target memory through the second interface function, thus realizing the transfer of data from the first simulation model to the second simulation model.

[0066] In embodiments of the present invention, a first interface function is used for data interaction between a first simulation model and target memory, and a second interface function is used for data interaction between a second simulation model and target memory. Here, data interaction with target memory can include writing data to target memory (i.e., performing a write-to-memory operation) or reading data from target memory (i.e., performing a read-to-memory operation). Depending on whether the target memory is read or written, the first interface function may further include a first write-to-memory function and a first read-to-memory function, and the second interface function may further include a second write-to-memory function and a second read-to-memory function.

[0067] Based on this, in one implementation, constructing a first interface function and a second interface function for each data structure corresponding to each interaction signal group, according to the transmission direction of the interaction signals in each interaction signal group, may include: when the transmission direction of the interaction signals in each interaction signal group is from the first circuit module to the second circuit module, constructing a first memory write function and a second memory read function for each data structure corresponding to the interaction signal group. In this way, the first simulation model can write data to the target memory using the first memory write function, and the second simulation model can read the data written to the target memory by the first circuit module using the second memory read function.

[0068] Optionally, in another implementation, constructing a first interface function and a second interface function for each data structure corresponding to each interaction signal group, based on the transmission direction of the interaction signals in each interaction signal group, may include: when the transmission direction of the interaction signals in each interaction signal group is from the second circuit module to the first circuit module, constructing a second memory write function and a first memory read function for each data structure corresponding to each interaction signal group. In this way, the second simulation model can write data to the target memory through the second memory write function, and the first simulation model can read the data written to the target memory by the second simulation model through the first memory read function.

[0069] It should be noted that, in the embodiments of the present invention, the interaction between the first circuit module and the second circuit module can be unidirectional or bidirectional. Accordingly, the interaction signal between the first circuit module and the second circuit module can include the interaction signal transmitted from the first circuit module to the second circuit module, the interaction signal transmitted from the second circuit module to the first circuit module, or both. The embodiments of the present invention do not limit this.

[0070] In addition to generating the first and second interface functions, in one embodiment of the present invention, a semaphore generation function can also be constructed to generate a first semaphore for each of the first interface functions and a second semaphore for each of the second interface functions. The first semaphore can be used to inform the second interface function that its operation on the target memory is complete and that it can then operate on the target memory. The second semaphore can be used to inform the first interface function that its operation on the target memory is complete and that it can then operate on the target memory. In this way, the access to the target memory by the first and second interface functions can be performed in a preset order, thereby ensuring the correctness of memory access operations.

[0071] Depending on the interface function, the semaphores generated for the interface function can also differ. For example, in one embodiment of the present invention, when the first interface function includes a first read memory function and the second interface function includes a second write memory function, the first semaphore may include a first read semaphore, and the second semaphore may include a second write semaphore. Specifically, the semaphore generation function can be used to: generate the first read semaphore for each of the first read memory functions; and generate the second write semaphore for each of the second write memory functions. The first read semaphore can be used to inform the second interface function that the first interface function's read operation on the target memory has been completed, and the second interface function can then perform a write operation on the target memory. The second write semaphore can be used to inform the first interface function that the second interface function's write operation on the target memory has been completed, and the first interface function can then perform a read operation on the target memory.

[0072] In another embodiment of the present invention, when the first interface function includes a first write memory function and the second interface function includes a second read memory function, the first semaphore may include a first write semaphore; the second semaphore may include a second read semaphore; then the semaphore generation function can specifically be used to: generate the first write semaphore for each of the first write memory functions; and generate the second read semaphore for each of the second read memory functions. The first write semaphore can be used to inform the second interface function that the first interface function's read operation on the target memory has been completed, and the second interface function will then perform a write operation on the target memory. The second read semaphore can be used to inform the first interface function that the second interface function's write operation on the target memory has been completed, and the first interface function can then perform a read operation on the target memory.

[0073] In embodiments of the present invention, the number of various interface functions between the first circuit module and the second circuit module can be set and adjusted as needed. For example, in one example, the number of the first read interface function, the first write interface function, the second read interface function, and the second write interface function can all be one or more, and the embodiments of the present invention do not limit this. Regardless of the number of the first read interface functions, the number of the first read semaphore can be 1; regardless of the number of the first write interface functions, the number of the first write semaphore can be 1; similarly, regardless of the number of the second read interface functions, the number of the second read semaphore can be 1; and regardless of the number of the second write interface functions, the number of the second write semaphore can be 1.

[0074] After obtaining the chip simulation model of the chip to be verified in step S100, the chip simulation model can be run in step S200 to verify the chip to be verified. Specifically, in one embodiment of the present invention, running the chip simulation model to verify the chip to be verified may include: obtaining the target memory and granting access permissions of the target memory to the first interface function and the second interface function respectively; executing the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model.

[0075] In this embodiment, during the chip verification process, the chip simulation model can create target memory. The target memory can have a tag (key) and declare that each interface function has access rights to the target memory with the target identifier. In this way, each interface function in the chip simulation model (e.g., each first interface function and each second interface function) can access the target memory according to the target memory tag.

[0076] Specifically, in some embodiments, acquiring the target memory and granting access permissions to the target memory to the first interface function and the second interface function respectively may include: in response to the startup of one of the first simulation model or the second simulation model, requesting the target memory from the operating system with a hash value of a preset process ID as one of the input parameters of the memory request function, and granting access permissions to the target memory to one of the interface functions corresponding to the started simulation model among the first interface function and the second interface function, wherein the target memory is labeled with the hash value of the preset process ID; in response to the startup of the other simulation model among the first simulation model or the second simulation model, detecting that the target memory labeled with the hash value of the preset process ID already exists, and granting access permissions to the target memory to the other interface function among the first interface function and the second interface function.

[0077] In this embodiment, the preset process ID can be any pre-specified process ID, as long as it does not conflict with the process IDs of other processes running on the computer. For example, in one instance, the preset process ID could be the process ID of the process (e.g., a script process) that coordinates the joint operation of the first and second simulation models to complete the chip verification operation. Applying a hash algorithm to this preset process ID yields its hash value. When the simulation model that starts first (e.g., the first simulation model) requests target memory, it can use this hash value as one of the input parameters to obtain the target memory labeled with that hash value and grant access permissions to the corresponding interface function. The simulation model that starts later (e.g., the second simulation model) detects that the target memory labeled with that hash value has already been created, binds the target memory to itself, and grants access permissions to the target memory to the corresponding interface function, thus enabling both simulation models to access the target memory.

[0078] In some embodiments, requesting the target memory from the operating system may include: determining the amount of data that the first simulation model and the second simulation model will interact with within one clock cycle of the first simulation model; and requesting the target memory from the operating system based on the amount of data. In this way, the requested target memory can satisfy the data interaction needs between the first and second simulation models without wasting memory space.

[0079] Furthermore, after granting access permissions to the target memory to the first interface function and the second interface function respectively, the interaction between the first simulation model and the second simulation model can be achieved by executing the first interface function and the second interface function. Specifically, the first simulation model can execute the first interface function in each clock cycle of at least one clock cycle, and the second simulation model can execute the second interface function in each clock cycle of at least one clock cycle, thereby realizing data interaction between the first simulation model and the second simulation model through the execution of the first interface function and the second interface function.

[0080] In one embodiment, before executing the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model, the chip verification method provided by the embodiments of the present invention may further include: generating a corresponding first semaphore for the first interface function and generating a corresponding second semaphore for the second interface function according to a preset semaphore generation function; based on this, executing the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model may specifically include: executing the first interface function and the second interface function based on the first semaphore and the second semaphore in each clock cycle of at least one clock cycle of the first simulation model.

[0081] In this embodiment, before executing the first interface function and the second interface function, a first semaphore can be generated for the first interface function and a second semaphore can be generated for the second interface function based on a preset semaphore generation function. The first semaphore informs the second interface function that its operation on the target memory is complete and that it can now operate on the target memory. Similarly, the second semaphore informs the first interface function that its operation on the target memory is complete and that it can now operate on the target memory. By executing the first and second interface functions according to the first and second semaphores, the target memory can be accessed in a preset order, thus ensuring the correctness of the memory access operation.

[0082] In one embodiment of the present invention, generating a first semaphore for the first interface function and a second semaphore for the second interface function according to a preset semaphore generation function may include: using the hash value of a preset process ID as one of the input parameters of the semaphore generation function to generate the first semaphore and the second semaphore. Here, the preset process ID can be any pre-specified process ID, as long as it does not conflict with the process IDs of other processes running in the computer. For example, in one instance, the preset process ID can be the process ID of the process (e.g., a script process) that coordinates the joint operation of the first simulation model and the second simulation model to complete the chip verification operation.

[0083] By applying a hash algorithm to a preset process ID, a hash value for that process ID can be obtained. This hash value is then used as one of the input parameters to a semaphore generation function, which generates a corresponding semaphore labeled with that hash value. Furthermore, after a semaphore is generated in one simulation model (e.g., the first simulation model), another simulation model (e.g., the second simulation model) can obtain the corresponding semaphore using the same hash value. Optionally, in one implementation, semaphore-related operations can be encapsulated as functions for easier invocation.

[0084] Specifically, in one embodiment of the present invention, the first interface function may include a first read memory function; the second interface function may include a second write memory function; then generating a corresponding first semaphore for the first interface function and a corresponding second semaphore for the second interface function according to a preset semaphore generation function may include: generating a corresponding first read semaphore for the first read memory function and a corresponding second write semaphore for the second write memory function according to a preset semaphore generation function.

[0085] Based on this, in each clock cycle of at least one clock cycle of the first simulation model, executing the first interface function and the second interface function may specifically include: when the current clock cycle is the first clock cycle of the second simulation model, the second simulation model initializes the target memory; the second simulation model writes data to the target memory through the second write memory function, and sets the second write semaphore to a first value after the write is completed; the first simulation model detects that the second write semaphore is the first value, reads data from the target memory through the first read memory function, and sets the second write semaphore to a second value; after the first simulation model finishes reading data from the target memory, the first read semaphore is set to the first value to prepare for the next clock cycle.

[0086] In this embodiment, the data transmission direction is from the second simulation model to the first simulation model; that is, the second simulation model writes data to the target memory, and the first simulation model reads data from the target memory. Correspondingly, the data read and write operations can be controlled by a second write semaphore and a first read semaphore. The value of the second write semaphore can be either a first value or a second value, where the first value indicates that the write operation has been completed, and the second value indicates that the write operation has not yet been completed. The value of the first read semaphore can also be either a first value or a second value, where the first value indicates that the read operation has been completed, and the second value indicates that the read operation has not yet been completed.

[0087] Based on this, the second simulation model can determine whether the current cycle is the first clock cycle of its operation. If it is the first clock cycle, it indicates that the chip simulation model has just started. The second simulation model can initialize the target memory. Initialization can either allocate new target memory or bind an already allocated target memory to the second simulation model. After initializing the target memory, the second simulation model writes data to the target memory by calling the second write memory function. Upon completion of the write operation, the second write semaphore is set to the first value, indicating that the data writing operation has been completed, and the first simulation model can then read the written data. After detecting that the second write semaphore is at the first value, the first simulation model can restore the second write semaphore to the second value and call the first read memory function to read the data from the target memory. Upon completion of the data reading operation, the first read semaphore is set to the first value, indicating that the data reading operation from the target memory has been completed, and the second simulation model can then continue writing data to the target memory in the next clock cycle.

[0088] Furthermore, the method may further include: when the current clock cycle is not the first clock cycle of the second simulation model, the second simulation model detects whether the first read semaphore is a first value; in response to detecting that the first read semaphore is a first value, the second simulation model writes data to the target memory through the second write memory function and sets the first read semaphore to a second value; after the second simulation model finishes writing the data, it sets the second write semaphore to the first value; when the first simulation model detects that the second write semaphore is a first value, it reads data from the target memory through the first read memory function and sets the second write semaphore to the second value; after the first simulation model finishes reading data from the target memory, it sets the first read semaphore to the first value to prepare for the next clock cycle.

[0089] The foregoing embodiments have described in detail the case where the second simulation model performs a write operation on the target memory and the first simulation model performs a read operation on the target memory. However, the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the first simulation model may also perform a write operation on the target memory and the second simulation model may also perform a read operation on the target memory.

[0090] Specifically, in one embodiment of the present invention, the first interface function may include a first write memory function; the second interface function may include a second read memory function; the first write memory function has a corresponding first write semaphore; and the second read memory function has a corresponding second read semaphore.

[0091] In this embodiment, the data transmission direction is from the first simulation model to the second simulation model; that is, the first simulation model writes data to the target memory, and the second simulation model reads data from the target memory. Correspondingly, the data read and write operations can be controlled by a first write semaphore and a second read semaphore. The value of the first write semaphore can be either a first value or a second value, where the first value indicates that the write operation has been completed, and the second value indicates that the write operation has not yet been completed. The value of the second read semaphore can also be either a first value or a second value, where the first value indicates that the read operation has been completed, and the second value indicates that the read operation has not yet been completed.

[0092] Based on this, in each clock cycle of at least one clock cycle of the first simulation model, executing the first interface function and the second interface function may include: in each clock cycle of at least one clock cycle of the first simulation model, the first simulation model detects whether the second read semaphore is a first value; if the second read semaphore is a first value, the first simulation model writes data to the target memory through the first write memory function and sets the second read semaphore to a second value; after the first simulation model finishes writing data, it sets the first write semaphore to a first value; the second simulation model detects that the first write semaphore is a first value, reads data from the target memory through the second read memory function, and sets the first write semaphore to a second value; after the second simulation model finishes reading data from the target memory, it sets the second read semaphore to a first value to prepare for the next cycle.

[0093] For example, in one embodiment of the present invention, the interaction diagram between the first simulation model and the second simulation model can be as follows: Figure 4 As shown, this includes the process of the first simulation model transmitting data to the second simulation model and the process of the second simulation model transmitting data to the first simulation model. In this embodiment, the first simulation model is a VCS model, the second simulation model is a GEM5 model, the second write semaphore is semaphore C, the first read semaphore is semaphore B, the second read semaphore is semaphore A, and the first write semaphore is semaphore D. Figure 4 Sending any semaphore as described herein means setting that semaphore to a first value so that the other party can obtain that first value.

[0094] For example, during the data transmission process from the first simulation model VCS to the second simulation model GEM5, the setting (setting to 1) and resetting (setting to 0) processes of the first write semaphore D and the second read semaphore A can be as follows: Figure 5As shown. The rising edge of the clock of the first simulation model VCS can drive DPI (Direct Programming Interface) activity. The DPI interface is an interface used for interaction between hardware description languages ​​(such as Verilog or SystemVerilog) and other programming languages ​​(such as C / C++). In one implementation, the aforementioned first interface function can be set in the DPI interface.

[0095] Similarly, the setting (setting to 1) and resetting (setting to 0) processes of the second write semaphore C and the first read semaphore B during the data transmission process from the second simulation model GEM5 to the first simulation model VCS can also be obtained, which will not be elaborated here.

[0096] The foregoing embodiments described a scenario where the chip to be verified includes a first circuit module and a second circuit module, but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the number of first circuit modules may be one or more, and similarly, the number of second circuit modules may be one or more.

[0097] For example, see Figure 6 In some embodiments, the at least two circuit modules include at least one first circuit module and at least one second circuit module, wherein one first circuit module is coupled to at least two second circuit modules, and / or, one second circuit module is coupled to at least two first circuit modules; wherein each first circuit module has a corresponding first simulation model, and each second circuit module has a corresponding second simulation model; each set of a first simulation model and a second simulation model with a data interaction relationship constitutes a model combination, which interacts with each other through a set of corresponding first interface functions, second interface functions, and target memory; the first interface functions, second interface functions, and target memory corresponding to different model combinations are all different from each other.

[0098] For example, in one instance, the first simulation model A has data interaction relationships with both the second simulation models B1 and B2. Specifically, A and B1 interact through the first interface function f1, the second interface function f2, and the target memory mem1, while A and B2 interact through the first interface function g1, the second interface function g2, and the target memory mem2.

[0099] Secondly, embodiments of the present invention provide a chip verification device 3, such as... Figure 7 As shown, it includes: The model acquisition unit 31 is used to acquire a chip simulation model of the chip to be verified. The chip to be verified includes at least two interconnected circuit modules, including a first circuit module and a second circuit module. The chip simulation model includes a first simulation model, a first interface function, a second simulation model, and a second interface function. The first simulation model is a register-transfer level simulation model of the first circuit module, and the second simulation model is a transaction-level simulation model of the second circuit module. The first interface function is used to be called by the first simulation model to access target memory; the second interface function is used to be called by the second simulation model to access the target memory. The model running unit 32 is used to run the chip simulation model to verify the chip to be verified. The first simulation model and the second simulation model interact with each other through the first interface function, the second interface function and the target memory according to the clock cycle of the first simulation model.

[0100] The chip verification device in this embodiment of the invention can acquire a chip simulation model of the chip to be verified and run the chip simulation model to verify the chip. The chip simulation model may include a first simulation model, a first interface function, a second simulation model, and a second interface function. The first simulation model is a register-transfer level simulation model of a first circuit module of the chip to be verified, and the second simulation model is a transaction-level simulation model of a second circuit module of the chip to be verified. During verification, the first simulation model and the second simulation model can interact with each other through the first interface function, the second interface function, and the target memory according to the clock cycle of the first simulation model. In this way, a register-transfer level simulation model can be established for the first circuit module, which is currently of primary concern, and a transaction-level simulation model can be established for the second circuit module, which is not currently of primary concern. Since the transaction-level simulation model can interact with the register-transfer level simulation model to verify the first circuit module, but does not require the precise simulation of circuit operation as the register-transfer level simulation model, combining the register-transfer level simulation model and the transaction-level simulation model can significantly reduce the computational load and shorten the simulation time while accurately verifying the first circuit module, thereby effectively improving verification efficiency.

[0101] In one implementation, the model acquisition unit 31 may include: An acquisition module is used to acquire a chip to be verified, the chip to be verified including a first circuit module and a second circuit module; A construction module is used to construct a first simulation model based on the first circuit module, construct a second simulation model based on the second circuit module, and construct the first interface function and the second interface function based on the interaction signals between the first circuit module and the second circuit module.

[0102] In one implementation, the building module may include: An interactive signal grouping submodule is used to group the interactive signals according to their functions and transmission directions to obtain at least one interactive signal group. The interactive signals in the same interactive signal group have the same function and the same transmission direction. The transmission direction includes transmission from the first circuit module to the second circuit module, or transmission from the second circuit module to the first circuit module. A data structure generation submodule is used to generate a corresponding data structure based on each group of interaction signals; The first construction submodule is used to construct a first interface function and a second interface function for each data structure corresponding to each interaction signal group according to the transmission direction of the interaction signal in each interaction signal group. The second construction submodule is used to construct a semaphore generation function to generate a first semaphore for each of the first interface functions and a second semaphore for each of the second interface functions. Each of the first interface functions is used to write data corresponding to the data structure into the target memory or read data from the target memory according to the indication of the second semaphore. Each of the second interface functions is used to write data corresponding to the data structure into the target memory or read data from the target memory according to the indication of the first semaphore.

[0103] In one implementation, the first interface function includes a first write memory function and / or a first read memory function; the second interface function includes a second write memory function and / or a second read memory function. The first construction submodule is specifically used for: When the transmission direction of the interaction signal in each interaction signal group is from the first circuit module to the second circuit module, a first write memory function and a second read memory function are constructed for the data structure corresponding to each interaction signal group. or, When the transmission direction of the interaction signal in each interaction signal group is from the second circuit module to the first circuit module, a second write memory function and a first read memory function are constructed for the data structure corresponding to each interaction signal group.

[0104] In one implementation, the first semaphore includes a first read semaphore; the second semaphore includes a second write semaphore. The semaphore generation function is used to: generate a first read semaphore for each of the first read memory functions; and generate a second write semaphore for each of the second write memory functions; or, The first semaphore includes a first write semaphore; the second semaphore includes a second read semaphore. The semaphore generation function is used to: generate the first write semaphore for each of the first write memory functions; and generate the second read semaphore for each of the second read memory functions.

[0105] In one implementation, the model running unit 32 may include: The memory acquisition module acquires the target memory and assigns access permissions for the target memory to the first interface function and the second interface function, respectively. The function execution module executes the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model.

[0106] In one embodiment, the model running unit 32 may further include: The semaphore generation module is used to generate a first semaphore for the first interface function and a second semaphore for the second interface function according to a preset semaphore generation function before executing the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model. The function execution module is specifically used to execute the first interface function and the second interface function based on the first semaphore and the second semaphore in each clock cycle of at least one clock cycle of the first simulation model.

[0107] In one implementation, the semaphore generation module is specifically used for: The first semaphore and the second semaphore are generated by using the hash value of the preset process ID as one of the input parameters of the semaphore generation function.

[0108] In one implementation, the first interface function includes a first memory read function; the second interface function includes a second memory write function. The semaphore generation module is specifically used to generate a corresponding first read semaphore for the first read memory function and a corresponding second write semaphore for the second write memory function according to a preset semaphore generation function. The function execution module is specifically used for: In the case that the current clock cycle is the first clock cycle of the second simulation model, the target memory is initialized by means of the second simulation model; The second simulation model writes data to the target memory through the second write memory function, and sets the second write semaphore to the first value after the write is completed; The first simulation model detects that the second write semaphore is a first value, reads data from the target memory through the first read memory function, and sets the second write semaphore to a second value; After the first simulation model finishes reading data from the target memory, it sets the first read semaphore to a first value to prepare for the next clock cycle.

[0109] In one implementation, the function execution module is further configured to: If the current clock cycle is not the first clock cycle of the second simulation model, the second simulation model detects whether the first read signal is the first value; In response to detecting that the first read semaphore is a first value, the second simulation model writes data to the target memory through the second write memory function and sets the first read semaphore to a second value; after the second simulation model finishes writing the data, it sets the second write semaphore to the first value. The first simulation model detects that the second write semaphore is a first value, reads data from the target memory through the first read memory function, and sets the second write semaphore to a second value; After the first simulation model finishes reading data from the target memory, it sets the first read semaphore to a first value to prepare for the next clock cycle.

[0110] In one implementation, the first interface function includes a first memory write function; the second interface function includes a second memory read function. The first write memory function has a corresponding first write semaphore; the second read memory function has a corresponding second read semaphore; The function execution module is specifically used for: In each clock cycle of at least one clock cycle of the first simulation model, the first simulation model detects whether the second read signal is a first value; When the second read semaphore is the first value, the first simulation model writes data to the target memory through the first write memory function and sets the second read semaphore to the second value; After the first simulation model finishes writing data, the first write semaphore is set to the first value; The second simulation model detects that the first write semaphore is a first value, reads data from the target memory through the second read memory function, and sets the first write semaphore to a second value; After the second simulation model finishes reading data from the target memory, it sets the second read semaphore to the first value to prepare for the next cycle.

[0111] In one embodiment, the memory acquisition module includes: The memory allocation submodule, in response to the startup of one of the first simulation model or the second simulation model, uses the hash value of the preset process ID as one of the input parameters of the memory allocation function to request the target memory from the operating system, and grants the access rights of the target memory to one of the interface functions corresponding to the simulation model that has been started in the first interface function and the second interface function, wherein the target memory is labeled with the hash value of the preset process ID; Access permissions are granted to the submodule in response to the startup of the first simulation model or another simulation model in the second simulation model. If the target memory labeled with a hash value of a preset process ID is detected, access permissions for the target memory are granted to the other interface function in the first interface function and the second interface function.

[0112] In one implementation, the memory allocation submodule is specifically used for: Determine the amount of data exchanged between the first simulation model and the second simulation model within one clock cycle of the first simulation model; Based on the amount of data, request the target memory from the operating system.

[0113] In one embodiment, the at least two circuit modules include at least one first circuit module and at least one second circuit module, wherein one first circuit module is coupled to at least two second circuit modules, and / or, wherein one second circuit module is coupled to at least two first circuit modules; wherein each first circuit module has a corresponding first simulation model, and each second circuit module has a corresponding second simulation model; Each set of the first simulation model and the second simulation model with data interaction relationship is a model combination, which interacts with each other through a set of corresponding first interface functions, second interface functions and target memory; the first interface functions, second interface functions and target memory corresponding to different model combinations are all different from each other.

[0114] Thirdly, such as Figure 8As shown, an embodiment of the present invention provides an electronic device, including a processor 71 and a memory 72. The memory 72 is used to store executable program code. The processor 71 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 72, for executing the chip verification method described in any of the foregoing embodiments.

[0115] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the chip verification method described in any of the foregoing embodiments.

[0116] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0117] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip verification method, characterized in that, include: A chip simulation model of a chip to be verified is obtained. The chip to be verified includes at least two interconnected circuit modules, including a first circuit module and a second circuit module. The chip simulation model includes a first simulation model, a first interface function, a second simulation model, and a second interface function. The first simulation model is a register-transfer level simulation model of the first circuit module, and the second simulation model is a transaction-level simulation model of the second circuit module. The first interface function is used to be called by the first simulation model to access target memory; the second interface function is used to be called by the second simulation model to access the target memory. The chip simulation model is run to verify the chip to be verified. The first simulation model and the second simulation model interact with each other through the first interface function, the second interface function and the target memory according to the clock cycle of the first simulation model.

2. The method according to claim 1, characterized in that, The chip simulation model for obtaining the chip to be verified includes: Obtain a chip to be verified, the chip to be verified including a first circuit module and a second circuit module; A first simulation model is constructed based on the first circuit module, a second simulation model is constructed based on the second circuit module, and the first interface function and the second interface function are constructed based on the interaction signals between the first circuit module and the second circuit module.

3. The method according to claim 2, characterized in that, The number of interaction signals is at least one, and the construction of the first interface function and the second interface function based on the interaction signals between the first circuit module and the second circuit module includes: Based on the function and transmission direction of each interaction signal, the interaction signals are grouped to obtain at least one interaction signal group. The interaction signals in the same interaction signal group have the same function and the same transmission direction. The transmission direction includes transmission from the first circuit module to the second circuit module, or transmission from the second circuit module to the first circuit module. A corresponding data structure is generated based on each of the aforementioned interactive signal groups; Based on the transmission direction of the interactive signal in each interactive signal group, construct a first interface function and a second interface function for the data structure corresponding to each interactive signal group; A semaphore generation function is constructed to generate a first semaphore for each of the first interface functions and a second semaphore for each of the second interface functions. Each of the first interface functions is used to write data corresponding to the data structure to the target memory or read data from the target memory according to the indication of the second semaphore. Each of the second interface functions is used to write data corresponding to the data structure to the target memory or read data from the target memory according to the indication of the first semaphore.

4. The method according to claim 3, characterized in that, The first interface function includes a first write memory function and / or a first read memory function; the second interface function includes a second write memory function and / or a second read memory function. The step of constructing a first interface function and a second interface function for each data structure corresponding to each interaction signal group based on the transmission direction of the interaction signal in each interaction signal group includes: When the transmission direction of the interaction signal in each interaction signal group is from the first circuit module to the second circuit module, a first write memory function and a second read memory function are constructed for the data structure corresponding to each interaction signal group. or, When the transmission direction of the interaction signal in each interaction signal group is from the second circuit module to the first circuit module, a second write memory function and a first read memory function are constructed for the data structure corresponding to each interaction signal group.

5. The method according to claim 4, characterized in that, The first semaphore includes a first read semaphore; the second semaphore includes a second write semaphore; The semaphore generation function is used to: generate a first read semaphore for each of the first read memory functions; and generate a second write semaphore for each of the second write memory functions; or, The first semaphore includes a first write semaphore; the second semaphore includes a second read semaphore. The semaphore generation function is used to: generate the first write semaphore for each of the first write memory functions; and generate the second read semaphore for each of the second read memory functions.

6. The method according to claim 1, characterized in that, The step of running the chip simulation model to verify the chip to be verified includes: Obtain the target memory, and grant access permissions to the target memory to the first interface function and the second interface function respectively; In each clock cycle of at least one clock cycle of the first simulation model, the first interface function and the second interface function are executed.

7. The method according to claim 6, characterized in that, Before executing the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model, the method further includes: A first semaphore is generated for the first interface function according to a preset semaphore generation function, and a second semaphore is generated for the second interface function. The execution of the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model includes: In each clock cycle of at least one clock cycle of the first simulation model, the first interface function and the second interface function are executed based on the first semaphore and the second semaphore.

8. The method according to claim 7, characterized in that, The step of generating a first semaphore for the first interface function and a second semaphore for the second interface function according to a preset semaphore generation function includes: The first semaphore and the second semaphore are generated by using the hash value of the preset process ID as one of the input parameters of the semaphore generation function.

9. The method according to claim 7, characterized in that, The first interface function includes a first memory read function; the second interface function includes a second memory write function. The step of generating a first semaphore for the first interface function and a second semaphore for the second interface function according to a preset semaphore generation function includes: A first read semaphore is generated for the first read memory function according to a preset semaphore generation function, and a second write semaphore is generated for the second write memory function. The execution of the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model includes: If the current clock cycle is the first clock cycle of the second simulation model's operation, the second simulation model initializes the target memory; The second simulation model writes data to the target memory through the second write memory function, and sets the second write semaphore to the first value after the write is completed; The first simulation model detects that the second write semaphore is a first value, reads data from the target memory through the first read memory function, and sets the second write semaphore to a second value; After the first simulation model finishes reading data from the target memory, it sets the first read semaphore to a first value to prepare for the next clock cycle.

10. The method according to claim 9, characterized in that, The method further includes: If the current clock cycle is not the first clock cycle of the second simulation model, the second simulation model detects whether the first read signal is the first value; In response to detecting that the first read semaphore is a first value, the second simulation model writes data to the target memory through the second write memory function and sets the first read semaphore to a second value; After the second simulation model finishes writing the data, it sets the second write semaphore to the first value; The first simulation model detects that the second write semaphore is a first value, reads data from the target memory through the first read memory function, and sets the second write semaphore to a second value; After the first simulation model finishes reading data from the target memory, it sets the first read semaphore to a first value to prepare for the next clock cycle.

11. The method according to any one of claims 6 to 10, characterized in that, The first interface function includes a first memory write function; the second interface function includes a second memory read function. The first write memory function has a corresponding first write semaphore; The second memory read function has a corresponding second read semaphore; The execution of the first interface function and the second interface function in each clock cycle of at least one clock cycle of the first simulation model includes: In each clock cycle of at least one clock cycle of the first simulation model, the first simulation model detects whether the second read signal is a first value; When the second read semaphore is the first value, the first simulation model writes data to the target memory through the first write memory function and sets the second read semaphore to the second value; After the first simulation model finishes writing data, the first write semaphore is set to the first value; The second simulation model detects that the first write semaphore is a first value, reads data from the target memory through the second read memory function, and sets the first write semaphore to a second value; After the second simulation model finishes reading data from the target memory, it sets the second read semaphore to the first value to prepare for the next cycle.

12. The method according to claim 6, characterized in that, The step of acquiring the target memory and granting access permissions to the target memory to the first interface function and the second interface function respectively includes: In response to the startup of one of the first simulation models or the second simulation models, the target memory is requested from the operating system with the hash value of the preset process ID as one of the input parameters of the memory request function, and the access rights of the target memory are granted to one of the interface functions corresponding to the simulation model that has been started in the first interface function and the second interface function, wherein the target memory is labeled with the hash value of the preset process ID; In response to the startup of the first simulation model or another simulation model in the second simulation model, if the target memory labeled with a hash value of a preset process ID is detected to already exist, access rights to the target memory are granted to the other interface function in the first interface function and the second interface function.

13. The method according to claim 12, characterized in that, The step of requesting the target memory from the operating system includes: Determine the amount of data exchanged between the first simulation model and the second simulation model within one clock cycle of the first simulation model; Based on the amount of data, request the target memory from the operating system.

14. The method according to claim 1, characterized in that, The at least two circuit modules include at least one first circuit module and at least one second circuit module, wherein one first circuit module is coupled to at least two second circuit modules, and / or, one second circuit module is coupled to at least two first circuit modules; wherein each first circuit module has a corresponding first simulation model, and each second circuit module has a corresponding second simulation model; Each set of the first simulation model and the second simulation model with data interaction relationship is a model combination, which interacts with each other through a set of corresponding first interface functions, second interface functions and target memory; the first interface functions, second interface functions and target memory corresponding to different model combinations are all different from each other.

15. A chip verification device, characterized in that, include: A model acquisition unit is used to acquire a chip simulation model of a chip to be verified. The chip to be verified includes at least two interconnected circuit modules, including a first circuit module and a second circuit module. The chip simulation model includes a first simulation model, a first interface function, a second simulation model, and a second interface function. The first simulation model is a register-transfer level simulation model of the first circuit module, and the second simulation model is a transaction-level simulation model of the second circuit module. The first interface function is used to be called by the first simulation model to access target memory; the second interface function is used to be called by the second simulation model to access the target memory. The model running unit is used to run the chip simulation model to verify the chip to be verified. The first simulation model and the second simulation model interact with each other through the first interface function, the second interface function and the target memory according to the clock cycle of the first simulation model.

16. An electronic device, characterized in that, It includes a processor and a memory, wherein the memory is used to store executable program code; the processor runs the program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the chip verification method of any one of claims 1-14.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs that can be executed by one or more processors to implement the chip verification method according to any one of claims 1-14.

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