Signal probability calculation method for reducing correlation error of digital circuit signal
By constructing a directed acyclic graph and using weighted average calculation, the signal correlation error problem caused by the re-converging structure is solved, and the accurate calculation of the signal probability of digital circuits is realized, which is suitable for high-requirement scenarios of complex systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2026-01-28
- Publication Date
- 2026-05-19
AI Technical Summary
The signal correlation error caused by the re-converging structure in the existing technology is relatively large, which affects the accuracy of signal probability calculation in digital circuits, especially in large-scale circuits where the computational complexity increases.
By acquiring the circuit netlist file, parsing the topology information, constructing a directed acyclic graph, dividing the circuit hierarchy, finding fan-out nodes, and combining the signal probability calculation formula and weighted average calculation, statistical and inference rules, the final signal probability result is calculated, reducing signal correlation errors.
It achieves the accuracy of digital circuit signal probability calculation, avoids the cumulative error caused by approximate calculation, provides reliable and accurate quantitative support for complex systems, and ensures system performance and decision reliability.
Smart Images
Figure CN122065744A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of digital circuit design automation, and specifically relates to a signal probability calculation method for reducing signal correlation errors in digital circuits. Background Technology
[0002] As integrated circuit design scale continues to expand and process dimensions continue to shrink, the complexity of digital circuits is growing exponentially. Accurately and efficiently calculating the probability distribution of signals in a circuit (i.e., the probability of a signal being high or low) becomes crucial at every stage of circuit design, verification, and testing.
[0003] In digital circuits, signal probability refers to the probability that the output signal node of a logic unit is at a logic high level (1). It reflects the frequency with which a signal remains in a 1 state over a long period of operation and is one of the important parameters in fields such as digital circuit reliability analysis, power consumption estimation, and test generation. Considering that the time consumption of simulation becomes extremely large as the circuit size and the number of input nodes increase, other calculation methods are needed to replace simulation tools for solving signal probabilities.
[0004] Fan-out reconvergence structures are a significant factor contributing to signal correlation in circuits. They consist of three parts: the fan-out point, the propagation path, and the convergence point. This structure has only one fan-out point, although multiple convergence points may be used or none may be present; however, the propagation path is an indispensable core component. The fan-out point decomposes the original signal into multiple fully correlated sub-signals. These sub-signals maintain varying degrees of correlation as they propagate along the propagation path. The fan-out point is the root cause of signal correlation. When these correlated signals converge at the convergence point, the lack of independence between the signals makes it impossible to calculate the output probability using methods for independent events. This is the core reason why this structure increases the difficulty of calculating circuit signal probabilities, especially in large-scale circuits where fan-out signals exhibit iterative propagation characteristics. A single signal may simultaneously correlate with multiple signals. When these intertwined correlated signals converge, fully clarifying the correlation between each signal requires a significant amount of time, further exacerbating the correlation problem. circuit The complexity of signal probability calculation.
[0005] In the current context, accurately calculating signal probabilities necessitates considering the signal correlation error caused by re-converging structures. In digital circuit design, approximately half of the nodes fan out, leading to re-converging. Considering the impact of fan-out re-converging can improve the accuracy of signal probability calculations.
[0006] Therefore, how to solve the problem of large signal correlation errors caused by the re-converging structure in the existing technology and improve the accuracy of the signal probability calculation results of each unit of the circuit has become an urgent technical problem to be solved. Summary of the Invention
[0007] To address the aforementioned problems in the prior art, this invention provides a signal probability calculation method for reducing signal correlation errors in digital circuits. This invention provides a method for calculating the signal probability to reduce the correlation error of digital circuit signals, comprising the following steps: Obtain the circuit netlist file, parse the circuit netlist file, and extract the circuit topology information; Based on the circuit topology information, a directed acyclic graph of the circuit structure is constructed, and the circuit structure hierarchy is divided into the directed acyclic graph to find the fan-out nodes of the circuit. Using the directed acyclic graph of the circuit structure and the basic formula for signal probability calculation, the initial signal probability result of each node at each level is calculated. Based on the initial signal probability results, the signal probability results of each node are calculated when different signal probabilities are set at the fan-out nodes. The weighted average calculation method is used to calculate the different signal probability results to obtain the weighted signal probability result of each node. The initial corrected signal probability result for each node at each level is calculated by combining the weighted signal probability results and the basic formula for signal probability calculation. For each node, the initial signal probability result, the weighted signal probability result, and the initial corrected signal probability result are statistically analyzed, and the final signal probability result of each node of the circuit is calculated by combining the inference rules and statistical results.
[0008] In one embodiment of the present invention, the circuit netlist file is a gate-level netlist file after logic synthesis.
[0009] In one embodiment of the present invention, the circuit topology information includes: standard cell library cell type, circuit connection relationship, input port, output port, cell name and net name.
[0010] In one embodiment of the present invention, a directed acyclic graph of the circuit structure is constructed based on the circuit topology information, and the directed acyclic graph is hierarchically divided into circuit structures to find the fan-out nodes of the circuit, including: The unit name, the input port, and the output port are used as nodes of the directed acyclic graph, the circuit connection relationship is used as the directed edge of the directed acyclic graph, the wire net name is used as the edge name of the directed acyclic graph, and the standard unit library unit type is stored in the nodes of the directed acyclic graph. The circuit hierarchy is partitioned using the topology sorting algorithm of the directed acyclic graph. The input node is taken as the first level, and the longest node number that the signal passes through from the input node to the current node plus 1 is taken as the level number of the current node. Traverse all nodes of the directed acyclic graph and analyze the node paths to obtain all fan-out nodes, wherein the fan-out nodes are nodes with a fan-out number greater than 1, and the branches of the fan-out nodes reconverge with other nodes within the circuit.
[0011] In one embodiment of the present invention, the basic formula for calculating the signal probability includes: NOT gate: S = 1 - p1; AND gate: S = p1p2p3,…,p n ; NAND gate: S = 1 - p1p2p3, ..., p n ; OR gate: S = 1 - (1 - p1)(1 - p2)(1 - p3), ..., (1 - p n ); NOR gate: S = (1-p1)(1-p2)(1-p3), ..., (1-p n ); XOR gate: 1-p1p2-(1-p1)(1-p2); Where p1, p2, p3, ..., p n This represents the probability of different logic gate input pin signals, where n represents the number of pins.
[0012] In one embodiment of the present invention, the initial signal probability result of each node at each level is calculated using a directed acyclic graph of the circuit structure and the basic formula for signal probability calculation, including: Based on the circuit hierarchy and the unit type of the standard unit library, the initial signal probability result of each node at each level is calculated using the basic formula for signal probability calculation.
[0013] In one embodiment of the present invention, the signal probability results of each node are calculated when different signal probabilities are set at the fan-out node, based on the basic formula for signal probability calculation. A weighted average calculation method is then used to calculate the different signal probability results, yielding a weighted signal probability result for each node, including: The signal probability of each fan-out node is sequentially set to 1.0 and 0.0. Using the basic formula for signal probability calculation, the different signal probability results for each node under different fan-out node signal probabilities are calculated. Then, the different signal probability results are weighted and calculated based on the initial signal probability results to obtain the weighted signal probability result for each node.
[0014] in, This represents the weighted signal probability result calculated at the i-th node. Let represent the initial signal probability of the A-th fan-out node. and These represent the signal probabilities of the i-th node calculated when the signal probability of the A-th fan-out node is set to 1.0 and 0.0, respectively. The number of weighted signal probability results is the same as the number of fan-out nodes.
[0015] In one embodiment of the present invention, the initial corrected signal probability result for each node at each level is calculated by combining the weighted signal probability result and the basic formula for signal probability calculation, including: The weighted signal probability result is used as input to the basic formula for signal probability calculation to calculate the initial corrected signal probability result for each node at each level, wherein the number of the initial corrected signal probability results is the same as the number of the weighted signal probability results.
[0016] In one embodiment of the present invention, statistical analysis of the initial signal probability result, the weighted signal probability result, and the initial corrected signal probability result includes: Each probability group in the weighted signal probability result is compared with the initial signal probability result in turn. If the probability results of the same node are equal, it is marked as the first mark. If the probability results of the same node are not equal, compare each group of probabilities in the weighted signal probability results with the corresponding group of probabilities in the initial corrected signal probability results. If the probabilities of the same node are equal, mark it as the second mark; if the probabilities of the same node are not equal, mark it as the third mark. For each node, count the number of second tags and the number of third tags.
[0017] In one embodiment of the present invention, the final signal probability result of each node of the circuit is calculated by combining inference rules and statistical results, including: When the number of the second marker is 0 and the number of the third marker is 0, the final signal probability result of the target node is: ; When the number of the second marker is not 0 and the number of the third marker is 0, the final signal probability result of the target node is: ; When the number of the second marker is 0 and the number of the third marker is not 0, if the number of the third marker is 1, then the final signal probability result of the target node is: If the number of the third marker is neither 0 nor 1, the final signal probability result of the target node is:
[0018]
[0019] When the number of the second marker is not 0 and the number of the third marker is not 0, the formula for calculating the final signal probability result of the target node is:
[0020]
[0021] in, ND represents the final signal probability result of the target node in the circuit, where ND is the probability calculated by combining the final signal probability result of the node connected to the target node in the previous level with the basic formula for signal probability calculation. This represents the probability result of the weighted signal in the i-th group. This represents the probability result of the initial corrected signal in the i-th group. This indicates several groups corresponding to the third marker. Summation, This represents the target node probability in the initial signal probability result.
[0022] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides a method for obtaining a circuit netlist file, parsing and extracting circuit topology information, constructing a directed acyclic graph (DAG) of the circuit structure, performing hierarchical partitioning of the circuit structure, and identifying and saving fan-out nodes. Using the DAG of the circuit structure, and combining it with basic signal probability calculation formulas, the initial signal probability result is calculated. Based on the fan-out node information, different probabilities are sequentially set for each fan-out node, and a weighted average calculation method is used to calculate the weighted signal probability result for each node. The initial corrected signal probability result is calculated based on the weighted signal probability result. The three probability results are statistically analyzed, and combined with inference rules, the final signal probability result of the circuit is calculated. This method allows direct signal probability calculation on digital circuit gate-level netlist files, effectively addressing the signal correlation error problem caused by circuit re-converging structures. This results in more accurate signal probability calculations, providing precise quantitative support for high-requirement scenarios, ensuring system performance and decision reliability, avoiding cumulative errors caused by approximate calculations, and solving the problem of large signal correlation errors caused by re-converging structures in existing technologies. It provides a reliable foundation for accurate probability calculations in complex systems. Attached Figure Description
[0023] Figure 1 A flowchart illustrating a signal probability calculation method for reducing signal correlation errors in digital circuits, provided in an embodiment of the present invention; Figure 2 A flowchart of another signal probability calculation method for reducing signal correlation error in digital circuits provided in an embodiment of the present invention; Figure 3 This is a comparison chart of the average relative error between the method of this invention and existing calculation methods; Figure 4 This is a comparison chart of the maximum average error between the method of this invention and existing calculation methods. Detailed Implementation
[0024] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0025] Example 1 This invention provides a signal probability calculation method with low digital circuit signal correlation error, which solves the problem of large signal correlation error caused by re-converging structures in the prior art. It realizes the extraction of circuit information from the circuit netlist file and the calculation of accurate signal probability results for each unit of the circuit by combining inference formulas.
[0026] Please see Figure 1 and Figure 2 , Figure 1 This is a flowchart illustrating a signal probability calculation method for reducing signal correlation errors in digital circuits, provided by an embodiment of the present invention. Figure 2 A flowchart of another signal probability calculation method for reducing signal correlation error in digital circuits provided in an embodiment of the present invention.
[0027] The signal probability calculation method for reducing signal correlation errors in digital circuits in this embodiment includes the following steps: S1. Obtain the circuit netlist file, parse the circuit netlist file and extract the circuit topology information.
[0028] Specifically, the circuit netlist file is a gate-level netlist file after logic synthesis. The circuit topology information includes: standard cell library cell types, circuit connections, input ports, output ports, cell names, and net names.
[0029] S2. Construct a directed acyclic graph of the circuit structure based on the circuit topology information, and perform circuit structure hierarchy division on the directed acyclic graph to find the fan-out nodes of the circuit.
[0030] Specifically, firstly, based on the circuit topology information, the cell name, the input port, and the output port are used as nodes of a directed acyclic graph (DAG), the circuit connection relationship is used as a directed edge of the DAG, the net name is used as the edge name of the DAG, and the standard cell library cell type is stored in the nodes of the DAG, thereby constructing a DAG data structure.
[0031] Then, the topology sorting algorithm of the directed acyclic graph data structure is used to divide the circuit into levels. The input node is taken as the first level, and the number of the longest nodes that the signal passes through from the input node to the current node plus 1 is taken as the level number of the current node. After the current level is processed, the subsequent levels are divided in turn.
[0032] Finally, fan-out nodes (i.e. re-converging fan-out nodes) are nodes with a fan-out number greater than 1, and the branches of the fan-out nodes re-converge into other nodes within the circuit. Based on this characteristic, all nodes of the directed acyclic graph are traversed and the node paths are analyzed to obtain and save all fan-out nodes.
[0033] S3. Using the directed acyclic graph of the circuit structure, combined with the basic formula for signal probability calculation, calculate the initial signal probability result for each node at each level.
[0034] Specifically, the basic formula for calculating signal probability is derived directly from the logic gate type. Some logic gate signal probability calculation formulas include: NOT gate: S = 1 - p1; AND gate: S = p1p2p3,…,p n ; NAND gate: S = 1 - p1p2p3, ..., p n ; OR gate: S = 1 - (1 - p1)(1 - p2)(1 - p3), ..., (1 - p n ); NOR gate: S = (1-p1)(1-p2)(1-p3), ..., (1-p n ); XOR gate: 1-p1p2-(1-p1)(1-p2); Where p1, p2, p3, ..., p n This represents the probability of different logic gate input pin signals, where n represents the number of pins.
[0035] Specifically, using the directed graph of the circuit structure, the initial signal probability of each node at each level is calculated based on the circuit hierarchy and the cell types of the standard cell library, combined with the basic formula for signal probability calculation. The initial signal probability calculation does not consider signal correlation errors caused by the re-converging structure. For example, the signal probability of each input pin is set to 0.5 to calculate the initial signal probability of each node.
[0036] The initial signal probability results are in one set, and this set of initial signal probability results is stored in S.
[0037] S4. Based on the initial signal probability results, calculate the signal probability results of each node when different signal probabilities are set at the fan-out node. Use a weighted average calculation method to calculate the different signal probability results to obtain the weighted signal probability results of each node.
[0038] Specifically, the signal probability of each fan-out node is sequentially set to 1.0 and 0.0. Using the basic formula for signal probability calculation, the different signal probability results for each node under different fan-out node signal probabilities are calculated. Then, the different signal probability results are weighted and calculated based on the initial signal probability results to obtain the weighted signal probability result for each node.
[0039] in, This represents the weighted signal probability result calculated at the i-th node. Let represent the initial signal probability of the A-th fan-out node. and These represent the signal probabilities of the i-th node calculated when the signal probability of the A-th fan-out node is set to 1.0 and 0.0, respectively.
[0040] For example, assuming there are n fan-out nodes, firstly, the signal probability of the first fan-out node is set to 1.0. Using the basic formula for signal probability calculation, the probability of each node in the circuit when the signal probability of the first fan-out node is 1.0 is calculated. Then, the signal probability of the first fan-out node is set to 0.0, and the probability of each node in the circuit when the signal probability of the first fan-out node is 0.0 is calculated again. Finally, the two probability results of each node are weighted and calculated together with the initial signal probability of the corresponding node to obtain a set of weighted signal probability results for the circuit nodes, which are stored in a P-tuple. The above steps are repeated, setting the signal probabilities of the second to nth fan-out nodes to 1.0 and 0.0 respectively, and weighting the node probability results under different fan-out node probabilities to obtain the weighted signal probability results for the second to nth sets of circuit nodes, which are also stored in a P-tuple. Therefore, each fan-out node obtains a set of weighted signal probability results through weighted calculation. There are multiple sets of weighted signal probability results, the number of which is the same as the number of fan-out nodes.
[0041] S5. Calculate the initial corrected signal probability result for each node at each level by combining the weighted signal probability result and the basic formula for signal probability calculation.
[0042] Specifically, for each node at each level, the weighted signal probability result of each group is used as input to the basic formula for signal probability calculation. The initial corrected signal probability result for each node at each level is calculated sequentially according to the circuit hierarchy and stored in an E-tuple. There are multiple groups of initial corrected signal probability results, and their number is the same as the number of weighted signal probability results; that is, the number of E-tuples equals the number of P-tuples.
[0043] S6. For each node, calculate the initial signal probability result, the weighted signal probability result, and the initial corrected signal probability result, and combine the inference rules and statistical results to calculate the final signal probability result of each node in the circuit.
[0044] Specifically, for each node, each probability set of the weighted signal probability result (P-tuple) is compared sequentially with the probability result of the corresponding node in the initial signal probability result (S). If the probability results of the same node are equal, it is marked as a first label. If the probability results of the same node are not equal, for each node, each probability set of the weighted signal probability result (P-tuple) is compared with the corresponding probability set of the initial corrected signal probability result (E-tuple). If the probabilities of the same node are equal, it is marked as a second label; if the probabilities of the same node are not equal, it is marked as a third label. For example, the first label is 0, the second label is 1, and the third label is 2.
[0045] For each node in the circuit, count the number of second marker 1 (c1) and the number of third marker 2 (c2).
[0046] Furthermore, the final signal probability result for each node of the circuit is calculated by combining statistical results and inference rules: When the number of the second marker c1 is 0 and the number of the third marker c2 is 0, the final signal probability result of the target node is the target node probability in the initial signal probability result. ,Right now .
[0047] When the number of the second marker c1 is not 0 and the number of the third marker c2 is 0, the final signal probability result of the target node is the probability calculated by combining the final signal probability results of the nodes connected to the target node in the previous level with the basic formula for signal probability calculation. ,Right now .
[0048] When the number of the second marker c1 is 0 and the number of the third marker c2 is not 0, if the number of the third marker c2 is 1, then the weighted signal probability result corresponding to the third marker is... If there is only one set, the target node probability in the weighted signal probability result of that set is taken as the final signal probability result of the target node; if the number of third markers c2 is neither 0 nor 1, then the weighted signal probability result corresponding to the third marker is... and the initial corrected signal probability results There are multiple sets, using the weighted signal probability results corresponding to the third label. and the initial corrected signal probability results Calculate the final signal probability result of the target node:
[0049]
[0050] When the number of the second marker c1 is not 0 and the number of the third marker c2 is not 0, the formula for calculating the final signal probability result of the target node is:
[0051]
[0052] in, ND represents the final signal probability result of the target node in the circuit, where ND is the probability calculated by combining the final signal probability result of the node connected to the target node in the previous level with the basic formula for signal probability calculation. This represents the probability result of the weighted signal in the i-th group. This represents the probability result of the initial corrected signal in the i-th group. This indicates several groups corresponding to the third marker. Summation, This represents the target node probability in the initial signal probability result.
[0053] In summary, the reasoning rules can be expressed as follows:
[0054]
[0055]
[0056]
[0057] ,
[0058]
[0059]
[0060]
[0061]
[0062]
[0063] This embodiment compares the calculation results of the signal probability calculation method for reducing signal correlation errors in digital circuits described above with the calculation results of existing calculation methods (0-Algorithm, WAA, DWAA, IWAA, POA). Please refer to [link to relevant documentation]. Figure 3 and Figure 4 , Figure 3This is a comparison chart of the average relative errors between the method of this invention and existing calculation methods. Figure 4 This is a comparison chart of the maximum average error between the method of this invention and existing calculation methods. Figure 3 , Figure 4 It can be seen that the method of the present invention achieves good accuracy.
[0064] In summary, the method of this invention obtains the circuit netlist file, parses and extracts the circuit topology information, constructs a directed acyclic graph (DAG) of the circuit structure, performs hierarchical partitioning of the circuit structure, finds and saves the fan-out nodes of the circuit; using the DAG of the circuit structure, it calculates the initial signal probability result in combination with the basic formula for signal probability calculation; combining the fan-out node information, it sequentially sets different probabilities for the fan-out nodes and calculates the weighted signal probability result of each node using a weighted average calculation method; it calculates the initial corrected signal probability result in combination with the weighted signal probability result; and it statistically analyzes the above three probability results and, in combination with inference rules, calculates the final signal probability result of the circuit. This method can directly perform signal probability calculation on the gate-level netlist file of digital circuits, effectively handling the signal correlation error problem caused by the circuit re-converging structure, making the signal probability calculation result more accurate, providing precise quantitative support for high-requirement scenarios, ensuring system performance and decision reliability, avoiding cumulative errors caused by approximate calculations, and solving the problem of large signal correlation errors caused by re-converging structures in existing technologies. It provides a reliable foundation for accurate probability calculation in complex systems, has a wide range of applications, low complexity, and higher accuracy compared to existing calculation methods.
[0065] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A method for calculating the signal probability to reduce the correlation error of digital circuit signals, characterized in that, Including the following steps: Obtain the circuit netlist file, parse the circuit netlist file, and extract the circuit topology information; Based on the circuit topology information, a directed acyclic graph of the circuit structure is constructed, and the circuit structure hierarchy is divided into the directed acyclic graph to find the fan-out nodes of the circuit. Using the directed acyclic graph of the circuit structure and the basic formula for signal probability calculation, the initial signal probability result of each node at each level is calculated. Based on the initial signal probability results, the signal probability results of each node are calculated when different signal probabilities are set at the fan-out nodes. The weighted average calculation method is used to calculate the different signal probability results to obtain the weighted signal probability result of each node. The initial corrected signal probability result for each node at each level is calculated by combining the weighted signal probability results and the basic formula for signal probability calculation. For each node, the initial signal probability result, the weighted signal probability result, and the initial corrected signal probability result are statistically analyzed, and the final signal probability result of each node of the circuit is calculated by combining the inference rules and statistical results.
2. The signal probability calculation method for reducing signal correlation error in digital circuits according to claim 1, characterized in that, The circuit netlist file is a gate-level netlist file after logic synthesis.
3. The signal probability calculation method for reducing signal correlation error in digital circuits according to claim 1, characterized in that, The circuit topology information includes: standard cell library cell type, circuit connection relationship, input port, output port, cell name, and net name.
4. The signal probability calculation method for reducing signal correlation error in digital circuits according to claim 3, characterized in that, Based on the circuit topology information, a directed acyclic graph (DAG) of the circuit structure is constructed, and the DAG is hierarchically divided into circuit structures to find the fan-out nodes of the circuit, including: The unit name, the input port, and the output port are used as nodes of the directed acyclic graph, the circuit connection relationship is used as the directed edge of the directed acyclic graph, the wire net name is used as the edge name of the directed acyclic graph, and the standard unit library unit type is stored in the nodes of the directed acyclic graph. The circuit hierarchy is partitioned using the topology sorting algorithm of the directed acyclic graph. The input node is taken as the first level, and the longest node number that the signal passes through from the input node to the current node plus 1 is taken as the level number of the current node. Traverse all nodes of the directed acyclic graph and analyze the node paths to obtain all fan-out nodes, wherein the fan-out nodes are nodes with a fan-out number greater than 1, and the branches of the fan-out nodes reconverge with other nodes within the circuit.
5. The signal probability calculation method for reducing signal correlation error in digital circuits according to claim 1, characterized in that, The basic formula for calculating the signal probability includes: NOT gate: S = 1 - p1; AND gate: S = p1p2p3,…,p n ; NAND gate: S = 1 - p1p2p3, ..., p n ; OR gate: S = 1 - (1 - p1)(1 - p2)(1 - p3), ..., (1 - p n ); NOR gate: S = (1-p1)(1-p2)(1-p3), ..., (1-p n ); XOR gate: 1-p1p2-(1-p1)(1-p2); Where p1, p2, p3, ..., p n This represents the probability of different logic gate input pin signals, where n represents the number of pins.
6. The signal probability calculation method for reducing signal correlation error in digital circuits according to claim 4, characterized in that, Using the directed acyclic graph of the circuit structure and the basic formulas for signal probability calculation, the initial signal probability results for each node at each level are calculated, including: Based on the circuit hierarchy and the unit type of the standard unit library, the initial signal probability result of each node at each level is calculated using the basic formula for signal probability calculation.
7. The signal probability calculation method for reducing signal correlation error in digital circuits according to claim 1, characterized in that, Based on the basic formula for signal probability calculation, the signal probability results for each node are calculated when different signal probabilities are set at the fan-out nodes. A weighted average calculation method is used to calculate the different signal probability results, resulting in the weighted signal probability result for each node, including: The signal probability of each fan-out node is sequentially set to 1.0 and 0.
0. Using the basic formula for signal probability calculation, the different signal probability results for each node under different fan-out node signal probabilities are calculated. Then, the different signal probability results are weighted and calculated based on the initial signal probability results to obtain the weighted signal probability result for each node. in, This represents the weighted signal probability result calculated at the i-th node. Let represent the initial signal probability of the A-th fan-out node. and These represent the signal probabilities of the i-th node calculated when the signal probability of the A-th fan-out node is set to 1.0 and 0.0, respectively. The number of weighted signal probability results is the same as the number of fan-out nodes.
8. The signal probability calculation method for reducing signal correlation error in digital circuits according to claim 1, characterized in that, The initial corrected signal probability result for each node at each level is calculated by combining the weighted signal probability results and the basic formula for signal probability calculation, including: The weighted signal probability result is used as input to the basic formula for signal probability calculation to calculate the initial corrected signal probability result for each node at each level, wherein the number of the initial corrected signal probability results is the same as the number of the weighted signal probability results.
9. The signal probability calculation method for reducing signal correlation error in digital circuits according to claim 1, characterized in that, The statistical analysis of the initial signal probability result, the weighted signal probability result, and the initial corrected signal probability result includes: Each probability group in the weighted signal probability result is compared with the initial signal probability result in turn. If the probability results of the same node are equal, it is marked as the first mark. If the probability results of the same node are not equal, compare each group of probabilities in the weighted signal probability results with the corresponding group of probabilities in the initial corrected signal probability results. If the probabilities of the same node are equal, mark it as the second mark; if the probabilities of the same node are not equal, mark it as the third mark. For each node, count the number of second tags and the number of third tags.
10. The signal probability calculation method for reducing signal correlation error in digital circuits according to claim 9, characterized in that, The final signal probability result for each node of the circuit is calculated by combining inference rules and statistical results, including: When the number of the second marker is 0 and the number of the third marker is 0, the final signal probability result of the target node is: ; When the number of the second marker is not 0 and the number of the third marker is 0, the final signal probability result of the target node is: ; When the number of the second marker is 0 and the number of the third marker is not 0, if the number of the third marker is 1, then the final signal probability result of the target node is: If the number of the third marker is neither 0 nor 1, the final signal probability result of the target node is: When the number of the second marker is not 0 and the number of the third marker is not 0, the formula for calculating the final signal probability result of the target node is: in, ND represents the final signal probability result of the target node in the circuit, where ND is the probability calculated by combining the final signal probability result of the node connected to the target node in the previous level with the basic formula for signal probability calculation. This represents the probability result of the weighted signal in the i-th group. This represents the probability result of the initial corrected signal in the i-th group. This indicates several groups corresponding to the third marker. Summation, This represents the target node probability in the initial signal probability result.