Circuit reduction method and system based on sparse processing
By combining spectrum sparsification with the TICER algorithm, the matrix densification problem caused by the traditional TICER algorithm is solved, achieving matrix sparsification and simulation speed improvement, while ensuring the circuit simplification effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- EMPYREAN TECH CO LTD
- Filing Date
- 2026-02-06
- Publication Date
- 2026-05-19
AI Technical Summary
The traditional TICER algorithm leads to matrix density after circuit reduction, which increases storage requirements and computational complexity. Existing improvement methods cannot fundamentally solve this problem.
Combining spectral sparsification with the TICER algorithm, sparsification is performed after node elimination, redundant non-zero elements are deleted, and a backoff mechanism is introduced to ensure the sparsification effect.
This effectively reduces matrix density, improves simulation speed and computational efficiency, and ensures circuit simplification.
Smart Images
Figure CN122065749A_ABST
Abstract
Description
Technical Field
[0001] This application relates to electronic design automation (EDA) technology for integrated circuits (ICs), and more particularly to a circuit reduction method and system based on sparsity processing. Background Technology
[0002] In the modeling and simulation of analog circuits, circuit reduction techniques are often used to simplify integrated circuit networks in order to reduce computational scale and improve solution efficiency. For example, node elimination methods are often used to reduce the matrix size by eliminating redundant or internal nodes in the integrated circuit, thereby improving circuit simulation efficiency. Among these, the Time Constant Equilibration Reduction (TICER) algorithm is widely used in the reduction of linear and weakly nonlinear circuits due to its advantages such as strong adaptability to circuit topology and fast reduction speed during node elimination.
[0003] However, the traditional TICER algorithm has the following significant drawbacks in practical applications: when eliminating circuit nodes, it generates a large number of new non-zero elements, a phenomenon known as "device filling." This "device filling" phenomenon causes the reduced matrix to transform from an initial sparse matrix into a dense matrix. Although the matrix order may decrease, the storage requirements and computational complexity of the dense matrix increase significantly. For example, for a 1000*1000 matrix, a sparse matrix may have only a few thousand non-zero elements, while a dense matrix may have a much larger number of elements. The time complexity of subsequent matrix operations (such as matrix multiplication and inversion) will then be reduced from [previous value]. or Rise to On the contrary, it will cause a decrease in simulation processing speed and even negate the advantages brought by the node elimination method.
[0004] To address the densification problem caused by the TICER algorithm, existing technologies mainly improve it in two ways: first, by optimizing the node elimination order of the TICER algorithm, prioritizing the elimination of nodes with small fill amounts to reduce the fill amount; second, by employing matrix compression storage techniques to compress the dense matrix and reduce storage overhead. However, both methods have limitations: the former can only reduce the fill amount to a certain extent and cannot fundamentally avoid densification; while the latter only reduces storage requirements without changing the dense nature of the matrix, thus the subsequent computational cost remains unchanged. Therefore, the existing technologies cannot overcome the shortcomings of the traditional TICER algorithm, which easily leads to matrix densification after reduction and results in high computational costs for subsequent simulations.
[0005] Therefore, there is an urgent need to develop a technique that can fundamentally reduce the density of the matrix after TICER reduction while ensuring simulation accuracy. Summary of the Invention
[0006] In view of this, the main objective of this application is to provide a circuit reduction method and system based on sparsification processing. Circuit reduction is achieved by combining spectral sparsification with the TICER algorithm, followed by post-sparse processing to effectively reduce matrix density and significantly improve simulation speed. Furthermore, a backoff mechanism is implemented to ensure the circuit reduction effect.
[0007] To achieve the above objectives, the present invention adopts the following technical solution:
[0008] A circuit reduction method based on sparsity processing includes:
[0009] A. The TICER algorithm, which uses time constant equalization reduction, is used to eliminate nodes in the circuit matrix, resulting in a matrix with fewer nodes but denser due to filling.
[0010] B. Process the matrix using the spectral sparsification algorithm, retain the core characteristics of the matrix, and remove redundant non-zero elements to obtain a sparsified matrix.
[0011] C. Determine the matrix density and sparsification effect of the new sparsified matrix. If the sparsification effect meets expectations, output the new sparsified matrix; otherwise, revert to the initial matrix step.
[0012] Specifically, step A involves using the Time Constant Equalization Reduction (TICER) algorithm to eliminate nodes in the circuit matrix, resulting in a denser matrix due to padding. This includes:
[0013] A13. For the original sparse matrix, let node N be the node to be eliminated. Then, after dividing the original network into blocks, we can obtain:
[0014] (1);
[0015] in: For complex frequencies, and These are the capacitance and conductance matrices of the nodes, respectively. For node voltage vectors, The node current source vector;
[0016] To eliminate node N, we perform Gaussian elimination on equation (1) to obtain:
[0017] (2);
[0018] The newly added term in the first term of equation (2) above is the filler term generated after elimination. ;
[0019] (3);
[0020] If the node to be eliminated is a fast node, that is... We can obtain:
[0021] (4);
[0022] If the node to be eliminated is a slow node, that is... ,but:
[0023] (5).
[0024] Preferably, the method further includes the following steps before step A13:
[0025] A11. Extract the connected graph from the subnet list Nets and traverse its subgraphs;
[0026] A12. Sort the internal nodes of the subgraph and divide it according to the sorting result.
[0027] Wherein: step B includes:
[0028] B1. Calculate the "importance weight" for each edge and convert it into a sampling probability;
[0029] B2. Normalize the above sampling probabilities;
[0030] B3. Sample each edge independently;
[0031] B4. For the retained edges, adjust their weights to compensate for the contribution of the "unsampled edges";
[0032] B5. Update the new matrix after sparsification.
[0033] The process of determining the matrix density of the new sparse matrix in step C is as follows: the matrix density is calculated by determining the relationship between the number of non-zero elements of the matrix and the matrix dimension.
[0034] The process of determining whether the sparsification effect meets the expected standard is as follows: determine whether the matrix density after circuit reduction is small enough.
[0035] Step C, which describes the process of reverting to the initial matrix if the sparsification effect does not meet expectations, includes:
[0036] The circuit is simplified again by using a sparsification algorithm in conjunction with node elimination, in order to offset the side effects of eliminating device filling to the greatest extent possible.
[0037] Step C also includes: if the circuit sparsification is successful, output the sparsified matrix of the circuit.
[0038] A circuit reduction system based on sparsity processing includes a node elimination subsystem of the TICER algorithm for time constant equalization reduction, a sparsity processing subsystem, a matrix density and sparsity effect judgment subsystem, a sparsity backoff subsystem, and a sparsity result output subsystem; wherein:
[0039] The TICER algorithm node elimination subsystem uses the TICER algorithm to eliminate nodes in the circuit matrix, resulting in a matrix with fewer nodes but denser due to filling.
[0040] The sparsity processing subsystem uses the spectral sparsity algorithm to process the matrix, retain the core characteristics of the matrix, and remove redundant non-zero elements to obtain a sparsified matrix.
[0041] The matrix density and sparsity effect judgment subsystem is used to determine whether the circuit sparsification is successful based on the matrix density and sparsification effect of the new sparsified matrix.
[0042] The sparsification rollback subsystem, when it determines that the circuit sparsification effect has not met expectations, rolls back to the initial matrix; and,
[0043] The sparsification result output subsystem outputs the sparsified matrix of the circuit when it is determined that the circuit sparsification is successful.
[0044] An electronic device including the aforementioned circuit reduction system based on sparsity processing, comprising:
[0045] One or more processors;
[0046] Memory, used to store one or more programs;
[0047] When the one or more programs are executed by the one or more processors, the one or more processors are configured to perform the steps of any of the circuit reduction methods described above.
[0048] A computer-readable medium storing a computer program that, when executed by a processor, implements the steps of any of the circuit reduction methods described above.
[0049] The circuit reduction method and system based on sparsity processing of this invention have the following advantages compared with the prior art:
[0050] The circuit reduction method based on sparsity processing of this invention is applicable to the modeling and simulation of large-scale analog circuits, as well as to model reduction and circuit analysis processes in electronic design automation (EDA). Specifically, in the circuit reduction process, a sparsity method is used to post-process the dense matrix formed after node elimination. By introducing sparsity processing technology, some edges can be pruned while maintaining network connectivity and circuit equivalence characteristics, thereby reducing the density of the matrix and the complexity of subsequent calculations.
[0051] The circuit reduction method and system based on sparsity processing of this invention combine node elimination and matrix sparsification, which not only retains the reduction advantages of the TICER algorithm but also solves the problem of circuit density through spectral sparsity processing. This effectively addresses the matrix density issue after TICER reduction, greatly improving the reduction effect and significantly enhancing the computational efficiency of circuit simulation. Furthermore, a backoff mechanism ensures the effectiveness of circuit reduction. Attached Figure Description
[0052] Figure 1 This is a schematic flowchart of the circuit reduction method based on sparsity processing according to an embodiment of the present invention;
[0053] Figure 1a For the present invention Figure 1 The diagram shows the process of node elimination using the TICER algorithm in the circuit reduction method based on sparsity processing.
[0054] Figure 1b For the present invention Figure 1 The diagram shows the process of sparsifying the spectrum in a circuit reduction method based on sparsification.
[0055] Figure 2 This is a functional block diagram of a circuit reduction system based on sparsity processing according to an embodiment of the present invention. Detailed Implementation
[0056] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.
[0057] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0058] The circuit reduction method and system based on sparsity processing provided by this invention are applicable to the modeling, simulation, and optimization calculation of large-scale analog circuits. By combining spectral sparsity with the TICER algorithm for circuit reduction, and then using sparsity techniques to post-process the eliminated circuit, the complexity and computational cost of subsequent calculations can be effectively reduced. Furthermore, by setting a backoff mechanism, the matrix density can be effectively reduced and the simulation speed can be improved, ensuring the reduction effect.
[0059] Figure 1 This is a schematic diagram of the circuit reduction method based on sparsity processing in an embodiment of the present invention.
[0060] like Figure 1 As shown, the circuit reduction method based on sparsity processing includes the following steps:
[0061] Step 11: Use the Time Constant Equilibration Reduction (TICER) algorithm to eliminate nodes in the circuit matrix, resulting in a denser matrix due to filling.
[0062] In the traditional TICER algorithm, to avoid excessive padding leading to poor circuit reduction, the selection criteria for reducible nodes are often quite stringent, requiring checks on potential padding during circuit reduction. However, in this invention, since subsequent sparsification processing is also required, the selection criteria for reducible nodes in the TICER algorithm can be appropriately relaxed, and even padding checks can be discontinued.
[0063] like Figure 1a As shown, in one embodiment of the present invention, the complete implementation process of step 11 includes:
[0064] Step 111: Extract the connected graph from the subnet list (Net) and traverse its subgraphs.
[0065] Here, "Net" refers to a part of a netlist. The netlist describes the logical connections within a circuit and is an indispensable part of integrated circuit (IC) design. Through the netlist, designers can clearly understand how the transistors in the circuit are connected, thereby achieving the expected circuit logic and function during IC chip simulation and manufacturing. Generally, a netlist can be expressed in text or file form. A netlist typically contains the following core components: Instances: Each circuit element, such as a transistor, resistor, capacitor, or logic gate, appears as an "instance" in the netlist. Each "instance" has a unique identifier in the netlist to ensure it can be uniquely identified in the circuit; Pins / Ports: Each element has several pins / ports, which are the "interfaces" of the circuit element. The number and nature of the pins depend on the type of element; Nets: These represent the connections between elements. Nets are composed of the ports of multiple elements and act as "signal paths," enabling signals to be transmitted between elements; Attributes: Some nets also contain attribute information, such as voltage, frequency, and load. These parameters can help designers perform simulations and analyses more accurately. The sub-graph is declared using module instantiation statements to represent sub-modules or functional sub-modules in a hierarchical design. Their internal connections are defined by their own netlist.
[0066] Step 112: Sort the internal nodes of the subgraph and divide it according to the sorting result.
[0067] Step 113: Use the TICER algorithm to eliminate nodes, resulting in a matrix with fewer nodes but a relatively denser matrix.
[0068] In one embodiment of the present invention, the node elimination process using the TICER algorithm is specifically as follows:
[0069] For the original sparse matrix, i.e., the first sparsification matrix, assuming the node to be eliminated is node N, the original circuit network, after being divided into blocks, can be written as:
[0070] (1)
[0071] Where: s is the complex frequency, C is the capacitance of the node, and G is the conductance matrix of the node, G={g ij}, where v is the node voltage vector and J is the node current source vector.
[0072] To eliminate node N, we perform Gaussian elimination on equation (1) to obtain:
[0073] (2)
[0074] Where: s is the complex frequency, C is the node capacitance, G is the node conductance matrix, v is the node voltage vector, and J is the node current source vector.
[0075] The newly added term in the first term of the above formula (2) is the filler term generated after elimination. It can be concluded that:
[0076] (3)
[0077] If the node to be eliminated is a quick node, that is... We can obtain:
[0078] (4)
[0079] If the node to be eliminated is a slow node, that is... ,but:
[0080] (5)
[0081] The above describes the calculation process for node elimination and filling using the TICER algorithm.
[0082] Before using the TICER algorithm for circuit reduction, it is often necessary to check the fill-in status of nodes to select suitable reducible nodes in order to avoid excessive fill.
[0083] In the TICER algorithm described in this embodiment of the invention, since sparsification may be performed again later, the requirements for this check condition are relatively lenient, or the fill-in situation may not be checked, and more nodes can be reduced in subsequent processing.
[0084] Step 12: Use spectral sparsification to preserve the core properties of the matrix and remove redundant non-zero elements to obtain a new sparsified matrix, namely the second sparsified matrix.
[0085] After step 11 above, a relatively dense matrix is obtained, which then needs to be sparsified. (See reference...) Figure 1b The following are the steps for applying the spectrum sparsification process to circuit reduction.
[0086] Here, the idea behind the spectral sparsification process is to randomly sample the "edges" of the network and retain only some "important" elements to reduce the number of non-zero elements in the matrix and lower the matrix density.
[0087] like Figure 1b As shown in the embodiments of the present invention, the process of spectral sparsification refers to post-processing of the matrix generated after processing by the TICER algorithm, which mainly includes the following steps:
[0088] Step 121: Calculate the "importance weight" for each edge and convert it into a sampling probability. In actual calculations, the sampling probability of an edge is proportional to its equivalent resistance.
[0089] Step 122: Normalize the above sampling probabilities.
[0090] Step 123: Sample each edge independently.
[0091] Step 124: For the retained edges, adjust their weights to compensate for the contribution of the "unsampled edges".
[0092] Step 125: Update the new sparse matrix.
[0093] Step 13: Based on the matrix density and sparsification effect of the new sparsified matrix, determine whether the circuit sparsification was successful. If successful, proceed to step 14; otherwise, if the circuit sparsification effect is not as expected, proceed to step 15.
[0094] In one embodiment of the present invention, the method for determining the density of the new matrix is as follows: the matrix density is calculated by judging the relationship between the number of non-zero elements in the matrix and the matrix dimension. The standard for judging whether the sparsity effect has met expectations is: whether the matrix density after circuit reduction is sufficiently small. The matrix density after circuit reduction can be customized. For example, assuming the new matrix density after circuit reduction is less than 5%, the matrix density can be considered sufficiently small.
[0095] Step 14: If the circuit sparsification is successful, output the sparsified matrix of the circuit.
[0096] Step 15: If the circuit sparsification effect does not meet expectations, then fall back to the initial matrix.
[0097] For example, if the sparsification effect of the matrix density is not as expected, the system reverts to the initial matrix, i.e., the revert mechanism is activated. The specific process is as follows:
[0098] The circuit is simplified again using a sparsification algorithm combined with node elimination, with the aim of offsetting the side effects of device filling to the greatest extent. However, for some networks, the dense matrix generated after elimination by the TICER algorithm is difficult to obtain a sufficiently ideal result through sparsification.
[0099] In addition to preprocessing (such as filtering these cases), a backoff condition needs to be added, that is, to check the effect of sparsification and ensure that enough edges are sparsified to obtain a sufficiently sparse matrix. Otherwise, a backoff will occur, meaning that node elimination and sparsification will no longer be performed.
[0100] Based on the same inventive concept, embodiments of the present invention also provide a circuit reduction system based on sparsity processing.
[0101] Figure 2 This is a functional block diagram of a circuit reduction system based on sparsity processing according to an embodiment of the present invention.
[0102] like Figure 2 As shown, this circuit reduction system based on sparsity processing mainly includes a node elimination subsystem for the Time Constant Equalization Reduction (TICER) algorithm, a sparsity processing subsystem, a matrix density and sparsity effect judgment subsystem, a sparsity backoff subsystem, and a sparsity result output subsystem. Among them:
[0103] The Time Constant Equalization Reduction (TICER) algorithm node elimination subsystem uses the TICER algorithm to eliminate nodes in the circuit matrix, resulting in a matrix with fewer nodes but denser due to filling.
[0104] The sparsity processing subsystem uses a spectral sparsity algorithm to process the matrix, retaining the core characteristics of the matrix and removing redundant non-zero elements to obtain a sparsified matrix.
[0105] The matrix density and sparsification effect judgment subsystem is used to determine whether the circuit sparsification is successful based on the matrix density and sparsification effect of the new sparsified matrix.
[0106] The sparsity rollback subsystem, when it determines that the circuit sparsification effect has not met expectations, rolls back to the initial matrix. And,
[0107] The sparsification result output subsystem outputs the sparsified matrix of the circuit when it is determined that the circuit sparsification is successful.
[0108] Based on the same inventive concept, embodiments of the present invention also provide an electronic device. (See reference) Figure 2 The circuit reduction system based on sparsity processing shown is integrated into the electronic device.
[0109] The electronic device includes: one or more processors, a memory, and one or more I / O interfaces. The memory stores one or more programs that, when executed by the one or more processors, cause the one or more processors to implement any of the sparse-processing-based circuit reduction methods described in the above embodiments; the one or more I / O interfaces are connected between the processors and the memory and configured to enable information exchange between the processors and the memory.
[0110] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU), MCU, etc.; the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically such as SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, and can realize information interaction between the processor and the memory, including but not limited to the data bus (Bus), etc.
[0111] In some embodiments, the processor, memory, and I / O interfaces are interconnected via a bus, and thus connected to other components of the computing device.
[0112] In some embodiments, the one or more processors include a field-programmable gate array (FPGA).
[0113] This invention also provides a computer-readable medium. The computer-readable medium stores a computer program, which, when executed by a processor, implements the steps of any of the circuit reduction methods based on sparsity processing described in the above embodiments. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.
[0114] This invention also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is run in the processor of an electronic device, the processor in the electronic device executes the circuit reduction method based on sparsity processing described above.
[0115] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).
[0116] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
[0117] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.
[0118] The computer program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages.
[0119] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK).
[0120] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make other modifications under the guidance of this application without departing from the spirit and scope of protection of the claims, and all such modifications are within the scope of protection claimed by this application.
Claims
1. A circuit reduction method based on sparsity processing, characterized in that, include: A. The TICER algorithm, which uses time constant equalization reduction, is used to eliminate nodes in the circuit matrix, resulting in a matrix with fewer nodes but denser due to filling. B. Process the matrix using the spectral sparsification algorithm, retain the core characteristics of the matrix, and remove redundant non-zero elements to obtain a sparsified matrix. C. Determine the matrix density and sparsification effect of the new sparsified matrix. If the sparsification effect meets expectations, output the new sparsified matrix; otherwise, revert to the initial matrix step.
2. The circuit reduction method based on sparsity processing according to claim 1, characterized in that, Step A involves using the TICER algorithm for time constant equalization reduction to eliminate nodes in the circuit matrix, resulting in a denser matrix due to padding. Specifically, this includes: A13. For the original sparse matrix, let node N be the node to be eliminated. Then, after dividing the original network into blocks, we can obtain: （1）； in: For complex frequencies, and These are the capacitance and conductance matrices of the nodes, respectively. For node voltage vectors, The node current source vector; To eliminate node N, we perform Gaussian elimination on equation (1) to obtain: （2）； The newly added term in the first term of equation (2) above is the filler term generated after elimination. ; （3）； If the node to be eliminated is a fast node, that is... We can obtain: （4）； If the node to be eliminated is a slow node, that is... ,but: （5）。 3. The circuit reduction method based on sparsity processing according to claim 2, characterized in that, The procedure preceding step A13 also includes: A11. Extract the connected graph from the subnet list Nets and traverse its subgraphs; A12. Sort the internal nodes of the subgraph and divide it according to the sorting result.
4. The circuit reduction method based on sparsity processing according to claim 1, characterized in that, Step B includes: B1. Calculate the "importance weight" for each edge and convert it into a sampling probability; B2. Normalize the above sampling probabilities; B3. Sample each edge independently; B4. For the retained edges, adjust their weights to compensate for the contribution of the "unsampled edges"; B5. Update the new matrix after sparsification.
5. The circuit reduction method based on sparsity processing according to claim 1, characterized in that, The process of determining the matrix density of the new sparse matrix in step C is as follows: the matrix density is calculated by determining the relationship between the number of non-zero elements in the matrix and the matrix dimension. The process of determining whether the sparsification effect meets the expected standard is as follows: determine whether the matrix density after circuit reduction is small enough.
6. The circuit reduction method based on sparsity processing according to claim 1, characterized in that, Step C, which describes the process of reverting to the initial matrix if the sparsification effect does not meet expectations, includes: The circuit is simplified again by using a sparsification algorithm in conjunction with node elimination, in order to offset the side effects of eliminating device filling to the greatest extent possible.
7. The circuit reduction method based on sparsity processing according to claim 1, characterized in that, Step C also includes: if the circuit sparsification is successful, output the sparsified matrix of the circuit.
8. A circuit reduction system based on sparsity processing, characterized in that, This includes a node elimination subsystem for the TICER algorithm with time constant equalization reduction, a sparsity processing subsystem, a matrix density and sparsity effect judgment subsystem, a sparsity backoff subsystem, and a sparsity result output subsystem; among which: The TICER algorithm node elimination subsystem uses the TICER algorithm to eliminate nodes in the circuit matrix, resulting in a matrix with fewer nodes but denser due to filling. The sparsity processing subsystem uses the spectral sparsity algorithm to process the matrix, retain the core characteristics of the matrix, and remove redundant non-zero elements to obtain a sparsified matrix. The matrix density and sparsity effect judgment subsystem is used to determine whether the circuit sparsification is successful based on the matrix density and sparsification effect of the new sparsified matrix. The sparsification rollback subsystem, when it determines that the circuit sparsification effect has not met expectations, rolls back to the initial matrix; and, The sparsification result output subsystem outputs the sparsified matrix of the circuit when it is determined that the circuit sparsification is successful.
9. An electronic device comprising the circuit reduction system of claim 8, characterized in that, include: One or more processors; Memory, used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors are configured to perform the steps of the circuit reduction method as described in any one of claims 1 to 7.
10. A computer-readable medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the circuit reduction method as described in any one of claims 1 to 7.