Direct current fault current processing method and system for dr-mmc hybrid cascade system

Abstract

The application relates to the technical field of power system relay protection, and discloses a DR-MMC hybrid cascaded system direct-current fault current processing method and system. In the method, based on fault loop state changes, the direct-current fault process of a DR-MMC hybrid cascaded converter is divided into a plurality of fault stages; the dynamic change characteristics of fault current in each fault stage are analyzed, and a fault current analysis sub-result corresponding to the fault stage is determined; each fault current analysis sub-result is integrated according to the time interval of the corresponding fault stage, and a fault current analysis result covering the direct-current fault process of the DR-MMC hybrid cascaded converter is determined; based on the fault current analysis result, the DR-MMC hybrid cascaded converter is subjected to parameter optimization, and the safe operation boundary of the DR-MMC hybrid cascaded system is determined. The application provides a theoretical basis for DR-MMC hybrid cascaded system fault protection design, equipment selection and safe and stable operation.

Description

Technical Field

[0001] This invention relates to the field of power system relay protection technology, and in particular to a method and system for handling DC fault current in a DR-MMC hybrid cascaded system. Background Technology

[0002] Flexible DC transmission technology based on Modular Multilevel Converters (MMCs) has become one of the core technologies for grid interconnection and renewable energy grid integration due to its advantages such as low harmonic content, high output waveform quality, and independent active / reactive power control. However, when a short-circuit fault occurs on the DC side of the MMC, its internal submodule capacitors discharge rapidly through the fault point, while the AC power supply also continuously feeds current to the fault point through the converter, causing the fault current to rise rapidly and potentially causing serious damage to equipment such as the converter and smoothing reactor. Therefore, accurately analyzing the characteristics of DC fault current is of great significance.

[0003] In recent years, hybrid cascaded converter topologies have gradually become a research hotspot in order to further optimize the economy and operational performance of flexible DC transmission systems. Among them, the DR-MMC hybrid cascaded converter combines the advantages of simple structure and low cost of diode rectifiers (DR) with the flexible control and excellent harmonic performance of MMC, showing promising application prospects in scenarios such as renewable energy transmission and grid interconnection. In the DR-MMC hybrid cascaded converter topology, the DR unit undertakes part of the power transmission task, which can reduce the capacity requirement of the MMC, thereby reducing the number of submodules and significantly reducing system costs. At the same time, the presence of the MMC unit ensures the system's ability to accurately control active and reactive power, balancing economy and flexibility.

[0004] Currently, analytical methods for DC fault current in MMCs are relatively mature, mainly derived by analyzing the capacitor discharge circuits of submodules and the AC-side feed current paths, combined with tools such as the Laplace transform. However, for DR-MMC hybrid cascaded converters, existing research focuses mainly on topology design and steady-state control, and a unified standard for systematic analytical methods for DC fault current has not yet been established, thus failing to provide strong support for subsequent processing of DC fault current. Summary of the Invention

[0005] To fill the technical gap in the analysis of DC fault current characteristics of DR-MMC hybrid cascaded converters, and to provide a theoretical basis for fault protection design, equipment parameter optimization, and safe and stable operation of DR-MMC hybrid cascaded systems, this invention provides a method and system for handling DC fault current in DR-MMC hybrid cascaded systems.

[0006] In a first aspect, embodiments of the present invention provide a method for handling DC fault current in a DR-MMC hybrid cascaded system, applicable to a DR-MMC hybrid cascaded system with a built-in DR-MMC hybrid cascaded converter. The method for handling DC fault current in a DR-MMC hybrid cascaded system includes:

[0007] Based on the changes in the state of the fault circuit, the DC fault process of the DR-MMC hybrid cascade converter is divided into several fault stages.

[0008] Analyze the dynamic change characteristics of the fault current in each fault stage to determine the corresponding fault current analytical sub-results for each fault stage;

[0009] Each fault current analysis sub-result is integrated according to the time interval of the corresponding fault stage to determine the fault current analysis result of the DR-MMC hybrid cascaded converter covering the DC fault process;

[0010] Based on the fault current analysis results, the parameters of the DR-MMC hybrid cascade converter are optimized, and the safe operating boundary of the DR-MMC hybrid cascade system is determined according to the fault current analysis results.

[0011] Preferably, the DC fault process of the DR-MMC hybrid cascaded converter is divided into several fault stages based on the change in the fault circuit state, including:

[0012] Based on the state change of the fault circuit caused by MMC lockout in the DR-MMC hybrid cascade converter, the first fault stage of the DC fault process is determined, wherein the first fault stage is the DC fault process from the occurrence of the fault to the MMC lockout.

[0013] Based on the change in fault circuit state caused by the disconnection of the AC side circuit breakers of MMC and DR in the DR-MMC hybrid cascade converter, the second fault stage of the DC fault process is determined, wherein the second fault stage is the DC fault process from MMC blocking to the disconnection of the AC side circuit breakers of MMC and DR.

[0014] The third fault stage of the DC fault process is determined, wherein the third fault stage is the DC fault process from the disconnection of the AC side circuit breaker of MMC and DR to the decay of the fault current to zero.

[0015] Preferably, the step of analyzing the dynamic change characteristics of the fault current in each fault stage and determining the corresponding fault current analytical sub-result for that fault stage includes:

[0016] In response to the topology operation state of the first fault stage, an equivalent discharge circuit for the first fault stage is constructed based on the AC / DC coupling relationship of DR and the sub-module equivalent characteristics of MMC.

[0017] The equivalent discharge circuit is subjected to a Laplace transform to obtain the first fault discharge operation circuit;

[0018] The first fault discharge operation circuit is subjected to an inverse Laplace transform to obtain several time-domain fault current components, and the fault current sub-result of the first fault stage is obtained by superimposing each of the time-domain fault current components.

[0019] Preferably, the construction of the equivalent discharge circuit for the first fault stage based on the AC / DC coupling relationship of DR and the submodule equivalent characteristics of MMC includes:

[0020] Based on the AC / DC coupling relationship of DR, the DC side of DR is equivalent to a Thevenin circuit formed by a DC voltage source and a first resistor connected in series. The voltage value of the DC voltage source is determined based on the AC side voltage, the leakage reactance of the converter transformer, and the turns ratio of the converter transformer. The resistance value of the first resistor is determined based on the leakage reactance of the converter transformer.

[0021] Based on the submodule equivalent characteristics of MMC, the DC side of MMC is equivalent to an RLC series circuit. The RLC series circuit includes a first capacitor, a first inductor, and a second resistor. The first capacitor is equivalently obtained by first connecting the submodule capacitors in the upper and lower bridge arms of each phase of MMC in series and then connecting them in parallel across three phases. The first inductor is equivalently obtained by first connecting the inductors in the upper and lower bridge arms of each phase of MMC in series and then connecting them in parallel across three phases. The second resistor is equivalently obtained by first connecting the resistors in the upper and lower bridge arms of each phase of MMC in series and then connecting them in parallel across three phases.

[0022] An equivalent discharge loop for the first fault stage is constructed based at least on the integration of the Thevenin circuit and the RLC series circuit.

[0023] Preferably, the step of analyzing the dynamic change characteristics of the fault current in each fault stage and determining the corresponding fault current analytical sub-result for that fault stage further includes:

[0024] In response to the topology operation state of the second fault stage, an equivalent discharge circuit for the second fault stage is constructed based on the AC / DC coupling relationship of DR and the lockout characteristics of MMC.

[0025] The equivalent discharge circuit is subjected to a Laplace transform to obtain the second fault discharge operation circuit;

[0026] The second fault discharge operation circuit is subjected to an inverse Laplace transform to obtain several time-domain fault current components, and the fault current sub-result of the second fault stage is obtained by superimposing each of the time-domain fault current components.

[0027] Preferably, the construction of the equivalent discharge circuit for the second fault stage based on the AC / DC coupling relationship of DR and the post-blocking characteristics of MMC includes:

[0028] Based on the AC / DC coupling relationship of DR, the DC side of DR is equivalent to a Thevenin circuit formed by a DC voltage source and a first resistor connected in series. The voltage value of the DC voltage source is determined based on the AC side voltage, the leakage reactance of the converter transformer, and the turns ratio of the converter transformer. The resistance value of the first resistor is determined based on the leakage reactance of the converter transformer.

[0029] Based on the latch-up characteristics of MMC, the DC side of MMC is equivalent to an RL series circuit. The RL series circuit includes a first inductor and a second resistor. The first inductor is equivalent to the inductors of the upper and lower bridge arms of each phase of MMC connected in series and then in parallel through three phases. The second resistor is equivalent to the resistors of the upper and lower bridge arms of each phase of MMC connected in series and then in parallel through three phases.

[0030] An equivalent discharge loop for the second fault stage is constructed based at least on the integration of the Thevenin circuit and the RL series circuit.

[0031] Preferably, the step of analyzing the dynamic change characteristics of the fault current in each fault stage and determining the corresponding fault current analytical sub-result for that fault stage further includes:

[0032] In response to the topology operation state of the third fault stage, an equivalent discharge circuit for the third fault stage is constructed based on the AC side disconnection characteristics of DR and the AC side disconnection characteristics of MMC.

[0033] The equivalent discharge circuit is subjected to a Laplace transform to obtain the third fault discharge operation circuit;

[0034] The third fault discharge operation circuit is subjected to an inverse Laplace transform to obtain several time-domain fault current components, and the fault current sub-result of the third fault stage is obtained by superimposing each of the time-domain fault current components.

[0035] Preferably, the equivalent discharge circuit for the third fault stage is constructed based on the AC side disconnection characteristics of DR and the AC side disconnection characteristics of MMC, including:

[0036] Based on the AC side disconnection characteristics of the DR, the DC side of the DR is equivalent to a first resistor, wherein the resistance value of the first resistor is determined based on the leakage reactance of the converter transformer.

[0037] Based on the AC side disconnection characteristics of MMC, the DC side of MMC is equivalent to an RL series circuit. The RL series circuit includes a first inductor and a second resistor. The first inductor is equivalent to the inductors of the upper and lower bridge arms of each phase of MMC connected in series and then in parallel by three phases. The second resistor is equivalent to the resistors of the upper and lower bridge arms of each phase of MMC connected in series and then in parallel by three phases.

[0038] An equivalent discharge circuit for the third fault stage is constructed based at least on the integration of the first resistor and the RL series circuit.

[0039] Preferably, after optimizing the parameters of the DR-MMC hybrid cascade converter based on the fault current analysis results, and determining the safe operating boundary of the DR-MMC hybrid cascade system based on the fault current analysis results, the method further includes:

[0040] The fault current target parameters are obtained by feature extraction from the fault current analysis results, and the fault protection strategy pre-configured in the DR-MMC hybrid cascade system is verified based on the fault current target parameters.

[0041] Secondly, embodiments of the present invention provide a DC fault current handling system for a DR-MMC hybrid cascaded system, comprising:

[0042] The fault process division module is used to divide the DC fault process of the DR-MMC hybrid cascaded converter into several fault stages based on the changes in the state of the fault circuit.

[0043] The fault current analysis module is used to analyze the dynamic change characteristics of the fault current in each fault stage and determine the fault current analysis sub-results corresponding to the fault stage.

[0044] The fault current determination module is used to integrate each fault current analysis sub-result according to the time interval of the corresponding fault stage, and determine the fault current analysis result of the DR-MMC hybrid cascaded converter covering the DC fault process.

[0045] The fault current processing module is used to optimize the parameters of the DR-MMC hybrid cascade converter based on the fault current analysis results, and to determine the safe operating boundary of the DR-MMC hybrid cascade system based on the fault current analysis results.

[0046] Compared with existing technologies, the present invention discloses a method and system for handling DC fault current in a DR-MMC hybrid cascaded system. Its advantages lie in the following: By constructing an equivalent discharge circuit in stages based on the changes in the fault circuit state, and combining frequency domain transformation and time domain solution, the analytical sub-results of the fault current at each stage are accurately derived and integrated into a system-level DC fault current analytical result, achieving staged and high-precision calculation of the DC fault current of the DR-MMC hybrid cascaded converter. The system of this invention reveals the generation mechanism and attenuation law of the current at each fault stage, clarifies the influence path of key factors such as the AC / DC coupling characteristics of the DR, the equivalent characteristics of the MMC submodule, and the characteristics after blocking, filling the gap in the systematic calculation method of DC fault current in DR-MMC hybrid cascaded converters; simultaneously, it provides a theoretical basis for the fault protection design, equipment parameter optimization, and safe and stable operation of the DR-MMC hybrid cascaded system. Attached Figure Description

[0047] Figure 1 This is a flowchart illustrating a DC fault current handling method for a DR-MMC hybrid cascaded system according to an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of the DR-MMC hybrid cascade system according to an embodiment of the present invention;

[0049] Figure 3 This is a schematic diagram of the equivalent discharge circuit in the first fault stage of an embodiment of the present invention;

[0050] Figure 4 This is a schematic diagram of the equivalent discharge circuit in the second fault stage of an embodiment of the present invention;

[0051] Figure 5 This is a schematic diagram of the equivalent discharge circuit in the third fault stage of an embodiment of the present invention;

[0052] Figure 6 This is another schematic flowchart of a DC fault current handling method for a DR-MMC hybrid cascaded system according to an embodiment of the present invention;

[0053] Figure 7 This is a schematic diagram of the structure of a DC fault current handling system of a DR-MMC hybrid cascade system according to an embodiment of the present invention;

[0054] Figure label:

[0055] MMC, Modular Multilevel Converter; DR, Diode Rectifier; 01, DR-MMC Hybrid Cascaded Converter; R1, First Resistor; R2, Second Resistor; R3, Line Equivalent Resistance; L1, First Inductor; L2, Line Equivalent Inductance; C1, First Capacitor; U, DC Voltage Source; 02, MMC DC Side Equivalent Circuit; 03, DR DC Side Equivalent Circuit; 1, Fault Process Division Module; 2, Fault Current Analysis Module; 3, Fault Current Determination Module; 4, Fault Current Processing Module. Detailed Implementation

[0056] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0057] In the description of this invention, it should be understood that the terms "first" and "second," etc., are used to distinguish different objects, rather than to describe a specific order.

[0058] In the description of this invention, it should be noted that, unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by those skilled in the art. The terminology used in this specification is for the purpose of describing specific embodiments only and is not intended to limit the invention. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0059] like Figure 1 The diagram shown is a flowchart illustrating a DC fault current handling method for a DR-MMC hybrid cascaded system according to an embodiment of the present invention. This method is applied to a DR-MMC hybrid cascaded system with a built-in DR-MMC hybrid cascaded converter.

[0060] like Figure 2 The diagram shown is a structural schematic of the DR-MMC hybrid cascade system according to an embodiment of the present invention. (Refer to...) Figure 2 The sending-end power grid is connected to the DC system via the DR-MMC hybrid cascaded converter 01. The DR-MMC hybrid cascaded converter is connected to the DC system through positive and negative transmission lines (overhead lines). The thick black line between the MMC and the DC system represents the positive transmission line, and the thick black line between the DR and the DC system represents the negative transmission line. When a DC short-circuit fault occurs on the overhead line, the DR and MMC in the DR-MMC hybrid cascaded converter, as the main energy sources and topology components on the DC side, will release energy to the short-circuit point through their respective circuit paths, forming a fault current. Therefore, analyzing the fault current is crucial for converter topology design, protection strategy formulation, and equipment selection.

[0061] Reference Figure 1 This invention provides a method for handling DC fault current in a DR-MMC hybrid cascaded system, comprising the following steps:

[0062] S1. Based on the changes in the state of the fault circuit, the DC fault process of the DR-MMC hybrid cascade converter is divided into several fault stages;

[0063] The DR-MMC hybrid cascade converter is integrated into the DR-MMC hybrid cascade system. The dynamic process of DC faults in the DR-MMC hybrid cascade converter is divided into three stages based on fault development characteristics. That is, the fault stages include a first fault stage, a second fault stage, and a third fault stage.

[0064] Specifically, step S1 includes:

[0065] 1) Based on the state changes of the fault circuit caused by MMC blocking in the DR-MMC hybrid cascaded converter, the first fault stage of the DC fault process is determined;

[0066] The first fault stage is the DC fault process from the occurrence of the fault to the MMC lockout.

[0067] 2) Based on the state changes of the fault circuit caused by the disconnection of the AC side circuit breakers of MMC and DR in the DR-MMC hybrid cascaded converter, the second fault stage of the DC fault process is determined;

[0068] The second fault stage is the DC fault process from MMC blocking to the opening of the MMC and DR AC side circuit breakers.

[0069] 3) Determine the third fault stage of the DC fault process.

[0070] The third fault stage is the DC fault process from the disconnection of the AC side circuit breaker of MMC and DR until the fault current decays to zero.

[0071] It should be noted that the division into three fault stages is based on the timing of the actions of key equipment in the DR-MMC hybrid cascaded converter. Specifically, the first fault stage is from the occurrence of the fault to the MMC lockout. During this stage, both the DR and MMC respond naturally, and the submodule capacitors participate in the discharge. The second fault stage is from the MMC lockout to the opening of the AC side circuit breakers of the MMC and DR. At this time, the MMC submodule exits, and only the bridge arm inductance and resistance act, while the DR continues to feed current. The third fault stage is after the opening of the AC side circuit breakers of the MMC and DR, the AC power feeding terminates, and the fault current is only attenuated by the remaining inductance of the DR-MMC hybrid cascaded system through the resistor. This division logic closely follows the equipment state switching nodes and better reflects the phased changes in energy source and loop topology during the fault process. It can be understood that the MMC and DR AC side circuit breakers are simplified descriptions in the field of power electronics for multiple devices sharing the same type of component, and by default refer to the AC side circuit breakers of the MMC and DR.

[0072] S2. Analyze the dynamic change characteristics of the fault current in each fault stage and determine the corresponding fault current analytical sub-results for each fault stage.

[0073] Specifically, step S2 includes:

[0074] 211) In response to the topology operation state of the first fault stage, based on the AC / DC coupling relationship of DR and the sub-module equivalent characteristics of MMC, an equivalent discharge circuit for the first fault stage is constructed.

[0075] like Figure 3 The diagram shown is a schematic of the equivalent discharge circuit in the first fault stage of an embodiment of the present invention. The arrows indicate the flow path and direction of the fault current, that is, the specific direction in which the DC fault current flows from high potential to low potential in the equivalent discharge circuit during the first fault stage.

[0076] Reference Figure 3 The construction process of the equivalent discharge circuit in the first fault stage is explained:

[0077] a) Based on the AC / DC coupling relationship of DR, the DC side of DR is equivalent to a Thevenin circuit formed by the DC voltage source U and the first resistor R1 connected in series;

[0078] Specifically, for DR, its AC / DC coupling relationship is shown in the following formula:

[0079]

[0080] in, This indicates the DC output voltage of the DR. This represents the effective value of the AC line voltage at the common grid connection point. In this embodiment, this value is considered a constant. This represents the leakage reactance of the converter transformer referred to the valve side. Indicates the turns ratio of the converter transformer. This indicates the DC side current.

[0081] According to the above formula, in When constant, DR on the DC side can be equivalent to a Thevenin circuit with a DC voltage source connected in series with a first resistor. The voltage value of the DC voltage source is determined based on the AC side voltage, the leakage reactance of the converter transformer, and the turns ratio of the converter transformer; that is, the voltage value of the DC voltage source is the first term on the right-hand side of the above equation. The resistance value of the first resistor is determined based on the leakage reactance of the converter transformer; that is, the resistance value of the first resistor is the second term on the right-hand side of the above equation.

[0082] b) Based on the sub-module equivalent characteristics of MMC, the DC side of MMC is equivalent to an RLC series circuit;

[0083] The RLC series circuit includes a first capacitor C1, a first inductor L1, and a second resistor R2. The first capacitor is equivalently obtained by connecting the submodule capacitors in each phase's upper and lower bridge arms of the MMC in series and then in parallel across the three phases. The first inductor is equivalently obtained by connecting the inductors in each phase's upper and lower bridge arms of the MMC in series and then in parallel across the three phases. The second resistor is equivalently obtained by connecting the resistors in each phase's upper and lower bridge arms of the MMC in series and then in parallel across the three phases.

[0084] Specifically, the MMC continuously invests in the upper and lower arms of each phase. Each submodule has a single-phase equivalent capacitance of [missing information]. ( (This represents the capacitance value of a single MMC submodule). After the equivalent capacitance of the three-phase bridge arms is connected in parallel, since the capacitances of the parallel capacitors are added together, the equivalent first capacitor C1 is... Furthermore, the capacitor initially participates in fault discharge, and its initial DC voltage value is... Smoothing reactor inductance for each phase upper and lower bridge arm First, the inductance of the upper and lower bridge arms is connected in series (the inductance of a single-phase bridge arm becomes...). Then, the three phases are connected in parallel. According to the parallel inductance calculation rule (the parallel inductance value is the single value divided by the number of parallel branches), the first inductance L1 is obtained as follows: The resistance used for equivalent losses in each phase upper and lower bridge arm. Similarly, first connect the upper and lower bridge arms in series (the resistance of a single-phase bridge arm becomes...). ), and then connected in parallel in three phases, according to the logic of parallel resistance calculation, the equivalent second resistance R2 is obtained as This enables the equivalent conversion of MMC to an RLC series circuit based on the characteristics of sub-modules and bridge arm components.

[0085] c) Construct an equivalent discharge loop for the first fault stage, based at least on the integration of the Thevenin circuit and the RLC series circuit.

[0086] Specifically, based on the integration of the Thevenin circuit and the RLC series circuit, combined with the equivalent line inductance L2 (which is equivalent to the line inductance and the smoothing reactor), , Indicates the inductance of the smoothing reactor. (representing the inductance of a DC transmission line), and the equivalent resistance R3 of the line (equivalent to...) , (This represents the resistance of the DC transmission line) and the initial current conditions (the initial current flowing through the inductor is...) This allows for a complete analysis of the current characteristics during the fault stage, thereby obtaining the equivalent discharge circuit for the first fault stage.

[0087] 212) Perform a Laplace transform on the equivalent discharge circuit to obtain the first fault discharge operation circuit;

[0088] Each component in the equivalent discharge circuit is converted into operational impedance according to the Laplace transform rule, and combined with the DC voltage source and the initial current value, it is converted into an operational domain expression to form the first fault discharge operational circuit.

[0089] Specifically, according to Kirchhoff's voltage law, the fault current calculation expression for the first fault discharge operation circuit can be obtained as follows:

[0090]

[0091] in, The Laplace transform expression for fault current, Represents a variable in the complex frequency domain. This indicates the DC side voltage.

[0092] 213) Perform an inverse Laplace transform on the first fault discharge operation circuit to obtain several time-domain fault current components, and perform superposition operation on each time-domain fault current component to obtain the fault current analytic result of the first fault stage.

[0093] Based on the first fault discharge calculation circuit, the inverse Laplace transform is first used to restore the fault current calculation expression in the complex frequency domain to several time-domain fault current components. These components correspond to the transient characteristics of different physical processes such as capacitor discharge and inductor energy storage release. Then, according to the principle of linear superposition of the components in the circuit, the obtained components are superimposed and integrated to obtain the first fault current analytical expression that can completely describe the dynamic process of DC fault in the first fault stage. This analytical expression accurately characterizes the dynamic characteristics of DC fault in the first fault stage.

[0094] Specifically, for Performing an inverse Laplace transform yields several time-domain fault current components, including:

[0095]

[0096]

[0097]

[0098]

[0099] in, It represents the amplitude of the cosine component, which corresponds to the amplitude of the transient component in the fault current that decays in the form of a cosine function. It reflects the intensity of the cosine decay current generated by the circuit resonance characteristics during processes such as capacitor discharge and inductor energy storage. It represents the amplitude of the sinusoidal component, which is the amplitude of the sinusoidal decay component in the fault current. Together with the cosine component, it constitutes the oscillating transient characteristics of the fault current, reflecting the energy exchange intensity under the interaction of inductance, capacitance, and resistance. It represents the decay time constant of the fault current in the first fault stage, characterizing the rate of decay of the transient component of the fault current. It is related to the circuit resistance and inductance parameters. The larger the resistance and the smaller the inductance, the faster the decay. It determines the process of the fault current transitioning from the transient state to the steady state. It represents the transient oscillation angular frequency, describes the rate of change of the fault current oscillation component, and is determined by the energy storage characteristics of the inductor and capacitor and the damping characteristics of the resistor in the circuit. It is a key parameter reflecting the fault current oscillation period.

[0100] Consider that the AC side continuously feeds energy to the DC side through the MMC to maintain the initial current flowing through the inductor. It remains unchanged. Furthermore, the DC-side voltage of the DR remains constant, and the magnitude of the current it generates remains constant. Unchanged can be represented as:

[0101]

[0102] in, This represents the steady-state current injected into the DC side by the DR during the first fault phase.

[0103] Therefore, the analytical expression for the first fault current can be expressed as:

[0104]

[0105] in, This represents the DC fault current of the DR-MMC hybrid cascaded converter during the first fault stage as a function of time. A changing function. It should be noted that the analytical expression for the first fault current is the analytical result of the fault current in the first fault stage.

[0106] Furthermore, step S2 also includes:

[0107] 221) In response to the topology operation state of the second fault stage, based on the AC / DC coupling relationship of DR and the post-blocking characteristics of MMC, an equivalent discharge circuit for the second fault stage is constructed.

[0108] like Figure 4 As shown, this is a schematic diagram of the equivalent discharge circuit in the second fault stage of an embodiment of the present invention. The arrows indicate the flow path and direction of the fault current, that is, the specific direction in which the DC fault current flows from high potential to low potential in the equivalent discharge circuit during the second fault stage.

[0109] Reference Figure 4 The construction process of the equivalent discharge circuit in the second fault stage is explained:

[0110] a) Based on the AC / DC coupling relationship of DR, the DC side of DR is equivalent to a Thevenin circuit formed by the DC voltage source U and the first resistor R1 connected in series;

[0111] Specifically, the voltage value of the DC voltage source is determined based on the AC side voltage, the leakage reactance of the converter transformer, and the turns ratio of the converter transformer, while the resistance value of the first resistor is determined based on the leakage reactance of the converter transformer.

[0112] It should be noted that, in the second fault stage, although the converter topology changes due to actions such as MMC blocking, the AC / DC coupling nature of the DR remains unchanged. When constructing its DC-side Thevenin equivalent circuit based on this characteristic, the basic parameters such as AC-side voltage, converter transformer leakage reactance, and turns ratio are maintained in relation to the first fault stage. The resistance characteristic of the first resistor, determined by the converter transformer leakage reactance, also remains stable. This ensures that the equivalent circuit can accurately reflect the mechanism by which the DR continuously feeds current to the DC side in the second fault stage, which is consistent with the continuity of the DR characteristics in the fault current analysis of this stage.

[0113] b) Based on the latch-up characteristics of MMC, the DC side of MMC is equivalent to an RL series circuit;

[0114] The RL series circuit includes a first inductor L1 and a second resistor R2. The first inductor is obtained by first connecting the inductors of the upper and lower arms of each phase of the MMC in series and then connecting them in parallel across the three phases. The second resistor is obtained by first connecting the resistors of the upper and lower arms of each phase of the MMC in series and then connecting them in parallel across the three phases.

[0115] Specifically, after MMC lockout, the submodule capacitors no longer participate in discharge, and only the inductors and resistors of each phase's upper and lower bridge arms remain functional. The inductors of each phase's upper and lower bridge arms are first connected in series, and their values ​​become... The series inductance of the three-phase bridge arm is then connected in parallel. According to the parallel inductance calculation rules, the equivalent first inductance L1 is obtained as follows: Similarly, the resistors of the upper and lower bridge arms of each phase are first connected in series, and the value becomes... The series resistors of the three-phase bridge arms are connected in parallel, resulting in an equivalent second resistor R2. Thus, an equivalent RL series circuit on the DC side after MMC blocking is constructed for fault current analysis in the second fault stage.

[0116] c) Construct an equivalent discharge loop for the second fault stage, based at least on the integration of the Thevenin circuit and the RL series circuit.

[0117] Specifically, based on the integration of the Thevenin circuit and the RL series circuit, combined with the equivalent line inductance L2 (which is equivalent to the line inductance and the smoothing reactor), , Indicates the inductance of the smoothing reactor. (representing the inductance of a DC transmission line), and the equivalent resistance R3 of the line (equivalent to...) , (This represents the resistance of the DC transmission line) and the initial current conditions (the initial current flowing through the inductor is...) This allows for a complete analysis of the current characteristics during the fault stage, thereby obtaining the equivalent discharge circuit for the second fault stage.

[0118] 222) Perform a Laplace transform on the equivalent discharge circuit to obtain the second fault discharge operation circuit;

[0119] Specifically, according to Kirchhoff's voltage law, the fault current calculation expression for the second fault discharge operation circuit can be obtained as follows:

[0120]

[0121] in, The Laplace transform expression for fault current, Represents a variable in the complex frequency domain. This represents the initial value of the DC fault current during the second fault stage of the DR-MMC hybrid cascaded converter, which is the steady-state value of the fault current at the moment the first fault stage ends.

[0122] 223) Perform an inverse Laplace transform on the second fault discharge operation circuit to obtain several time-domain fault current components, and perform superposition operation on each time-domain fault current component to obtain the fault current analytical result of the second fault stage.

[0123] For the second fault discharge operation circuit, the inverse Laplace transform is first used to convert the fault current operation expression in the complex frequency domain into several time-domain fault current components. These components reflect the current attenuation characteristics under the action of inductors, resistors and other components in the equivalent discharge circuit of the second fault stage. Then, according to the principle of linear superposition of physical quantities in the circuit, the obtained components are superimposed and integrated to obtain the analytical expression of the second fault current. This analytical expression can accurately characterize the DC fault current attenuation law of the second fault stage.

[0124] Specifically, for Performing an inverse Laplace transform yields several time-domain fault current components, including:

[0125]

[0126]

[0127] in, It represents the amplitude of the decaying current component in the fault current of the second fault stage, which is determined by the initial state of the fault. It reflects the intensity characteristics of the fault current at the beginning of the second fault stage and is a key amplitude parameter for constructing a complete analytical expression of the second fault current. It reflects the initial scale of the fault current decay process in this stage. The time constant, which represents the decay of the fault current in the second fault stage, is determined by the parameters of components such as inductance and resistance in the circuit. Its value reflects the rate of decay of the fault current. The larger the time constant, the slower the fault current decays. It is a key parameter for characterizing the decay law of DC fault current in the second fault stage.

[0128] In addition, the AC power supply continuously feeds in the fault current through the DR, and its expression is the same as that in the first fault stage. The same. Therefore, the analytical expression for the second fault current can be expressed as:

[0129]

[0130] in, This represents the DC fault current in the second fault stage of the DR-MMC hybrid cascaded converter as a function of time. A changing function, This indicates the duration of the first fault stage. It should be noted that the second fault current analytical expression is the result of the fault current analytical sub-expression for the second fault stage.

[0131] Furthermore, step S2 also includes:

[0132] 231) In response to the topology operation state of the third fault stage, an equivalent discharge circuit for the third fault stage is constructed based on the AC side disconnection characteristics of DR and the AC side disconnection characteristics of MMC.

[0133] like Figure 5 The diagram shown is a schematic of the equivalent discharge circuit in the third fault stage of an embodiment of the present invention. The arrows indicate the flow path and direction of the fault current, that is, the specific direction in which the DC fault current flows from high potential to low potential in the equivalent discharge circuit during the third fault stage.

[0134] Reference Figure 5The construction process of the equivalent discharge circuit in the third fault stage is explained:

[0135] a) Based on the AC side disconnection characteristics of DR, the DC side of DR is equivalent to the first resistor R1;

[0136] Specifically, the resistance value of the first resistor is determined based on the leakage reactance of the converter transformer.

[0137] It should be noted that in the third fault stage, after the AC side of the DR is disconnected, the AC side power supply channel is cut off, and there is no longer a voltage source continuously supplying power to its DC side. Only the equivalent resistance corresponding to the leakage reactance of the converter transformer remains to participate in the DC side fault circuit. At this time, based on the characteristics of the AC side of the DR being disconnected, its DC side is equivalent to the first resistor R1 whose resistance value is determined by the leakage reactance of the converter transformer. This equivalent resistance becomes the key component for energy dissipation in the discharge circuit of the third fault stage. It works together with other inductors and resistors in the circuit. When constructing the equivalent discharge circuit later, this is used as the basis to integrate the remaining components and line parameters after the MMC blocking, so as to achieve the connection with the fault development of the first two stages and reflect the dynamic changes of the DR characteristics in the evolution of the fault stage.

[0138] b) Based on the AC side disconnection characteristics of MMC, the DC side of MMC is equivalent to an RL series circuit;

[0139] The RL series circuit includes a first inductor L1 and a second resistor R2. The first inductor is obtained by first connecting the inductors of the upper and lower arms of each phase of the MMC in series and then connecting them in parallel across the three phases. The second resistor is obtained by first connecting the resistors of the upper and lower arms of each phase of the MMC in series and then connecting them in parallel across the three phases.

[0140] Specifically, in the third fault stage, after the AC side of the MMC is disconnected, its AC-DC energy interaction path is cut off, and it relies solely on its own bridge arm components to participate in the DC side fault circuit. For each phase upper and lower bridge arm, the bridge arm inductances are first connected in series, and after series connection, the equivalent inductance of each phase bridge arm becomes Then, the equivalent inductance of the three-phase bridge arms is connected in parallel. According to the calculation rules for parallel inductance, the first inductance L1 can be obtained as follows: Similarly, the resistors of the upper and lower bridge arms of each phase are first connected in series, and the single-phase equivalent resistance becomes... The series resistors of the three-phase bridge arms are connected in parallel, resulting in an equivalent second resistor R2. Therefore, an equivalent RL series circuit on the DC side after the AC side of the MMC is disconnected is constructed for the analysis of the fault current decay process in the third fault stage.

[0141] c) Construct an equivalent discharge loop for the third fault stage, based at least on the integration of the first resistor and the RL series circuit.

[0142] Specifically, based on the integration of the first resistor and the RL series circuit, combined with the equivalent line inductance L2 (which is equivalent to the line inductance and the smoothing reactor), , Indicates the inductance of the smoothing reactor. (representing the inductance of a DC transmission line), and the equivalent resistance R3 of the line (equivalent to...) , (This represents the resistance of the DC transmission line) and the initial current conditions (the initial current flowing through the inductor is...) This allows for a complete analysis of the current characteristics during the fault stage, thereby obtaining the equivalent discharge circuit for the third fault stage.

[0143] 232) The equivalent discharge circuit is transformed by Laplace to obtain the third fault discharge operation circuit;

[0144] Specifically, according to Kirchhoff's voltage law, the fault current calculation expression for the third fault discharge operation circuit can be obtained as follows:

[0145]

[0146] in, The Laplace transform expression for fault current, Represents a variable in the complex frequency domain. This represents the initial value of the DC fault current in the third fault stage of the DR-MMC hybrid cascaded converter, which is the steady-state value of the fault current at the moment the second fault stage ends.

[0147] 233) Perform an inverse Laplace transform on the third fault discharge operation circuit to obtain several time-domain fault current components, and perform superposition operation on each time-domain fault current component to obtain the fault current analytic result of the third fault stage.

[0148] For the third fault discharge operation circuit, the inverse Laplace transform is first used to transform the fault current operation expression in the complex frequency domain into several time-domain fault current components. These components reflect the current decay law under the action of the remaining components after the DR AC side is disconnected and the MMC is blocked in the third fault stage. Then, according to the principle of linear superposition of physical quantities in the circuit, the obtained components are superimposed to obtain the analytical expression of the third fault current. This analytical expression can accurately characterize the DC fault current decay characteristics in the third fault stage.

[0149] Specifically, for Performing an inverse Laplace transform yields several time-domain fault current components, including:

[0150]

[0151]

[0152] in, It represents the amplitude of the decaying current component in the fault current of the third fault stage, which is determined by the initial value of the final state current of the second fault stage. It reflects the intensity of the fault current at the beginning of the third fault stage and is the key amplitude parameter for constructing the analytical expression of the third fault current, reflecting the initial scale of the fault current decay process in this stage. The decay time constant of the fault current in the third fault stage is determined by the parameters of components such as inductance and resistance in the circuit. Its value reflects the rate of decay of the fault current. The larger the time constant, the slower the current decays. It is a key parameter for characterizing the decay law of DC fault current in the third fault stage.

[0153] Therefore, the analytical expression for the third fault current can be expressed as:

[0154]

[0155] in, This represents the DC fault current in the third fault stage of the DR-MMC hybrid cascaded converter as a function of time. A changing function, This indicates the duration of the second fault stage. It should be noted that the third fault current analytical expression is the result of the fault current analytical expression for the third fault stage.

[0156] S3. Integrate each fault current analysis sub-result according to the time interval of the corresponding fault stage to determine the fault current analysis result of the DR-MMC hybrid cascaded converter covering the DC fault process.

[0157] The analytical expressions for the first, second, and third fault currents are integrated based on the duration of each fault stage to obtain the analytical expression for the DC fault current of the DR-MMC hybrid cascaded converter. It should be noted that the analytical expression for the DC fault current is the same as the result of the fault current analysis.

[0158] Specifically, the duration range of each fault stage is first defined: the duration of the first fault stage is... The second stage of failure is The third stage of failure is Then, within the corresponding time interval, the first fault current analytical expression, the second fault current analytical expression, and the third fault current analytical expression are substituted into the equations respectively. Finally, according to the division of the time interval, the analytical expressions of each stage are integrated into a piecewise function form, thereby obtaining a DC fault current analytical expression that can completely describe the current change characteristics of the DR-MMC hybrid cascade converter during the entire DC fault process, realizing the full-time characterization of the fault current from the initial fault to each stage of evolution until it tends to stabilize.

[0159] S4. Optimize the parameters of the DR-MMC hybrid cascade converter based on the fault current analysis results, and determine the safe operating boundary of the DR-MMC hybrid cascade system based on the fault current analysis results.

[0160] Specifically, from the fault current analysis results of the DR-MMC hybrid cascaded converter, time-domain characteristic parameters of the entire fault process are extracted, including the peak fault current, current rise rate, decay time constant, and steady-state residual current value at each stage. This determines the current withstand requirements of the core components of the converter (MMC arm inductors, submodule capacitors, DR equivalent impedance, and smoothing reactors) under fault conditions. The extracted key fault current parameters are compared with the rated withstand indicators of the components. If the peak fault current exceeds the withstand limit of the components, the MMC arm inductor parameters are adjusted to suppress the current rise rate, or the submodule capacitor capacity is optimized to balance the discharge impact and steady-state energy storage requirements. At the same time, the influence of the DR equivalent resistance / equivalent inductance on the fault current decay characteristics is verified to ensure that the optimized parameters meet the current suppression requirements under fault conditions without affecting the power transmission efficiency and harmonic control performance of the converter during steady-state operation.

[0161] Furthermore, based on the fault current analysis results, multiple fault conditions (such as faults under different DC-side short-circuit locations, different initial operating power, and different AC grid voltage levels) are simulated to extract the maximum peak value, allowable duration, and critical attenuation threshold of the fault current under each scenario. Combining the withstand limits of the core equipment (converter, DC line, AC circuit breaker) of the DR-MMC hybrid cascade system with the response capabilities of protection devices (such as DC circuit breaker breaking time and overcurrent protection action delay), the safe operating boundaries of the system under different fault scenarios are defined. For example, under what fault intensity and duration can the DR-MMC hybrid cascade system achieve safe isolation through protection measures, preventing the fault from escalating to cascading tripping.

[0162] like Figure 6 The diagram shown is another flowchart illustrating a DC fault current handling method for a DR-MMC hybrid cascaded system according to an embodiment of the present invention. (Refer to...) Figure 6 According to an embodiment of the present invention, a method for handling DC fault current in a DR-MMC hybrid cascaded system, after step S4, further includes the following step:

[0163] S5. Extract the features from the fault current analysis results to obtain the fault current target parameters, and verify the fault protection strategy pre-configured in the DR-MMC hybrid cascade system based on the fault current target parameters.

[0164] Specifically, from the fault current analysis results of the DR-MMC hybrid cascaded converter, the target parameters of the fault current that are directly related to the verification of the fault protection strategy are extracted, including but not limited to the peak current of each fault stage, the fault current rise rate, the current decay time constant, and the critical time from the occurrence of the fault to the current reaching the equipment tolerance limit.

[0165] Furthermore, based on the extracted fault current target parameters, a multi-dimensional verification is performed on the fault protection strategy pre-configured in the DR-MMC hybrid cascade system:

[0166] First, verify the rationality of the protection action threshold;

[0167] The extracted fault current peak value and steady-state residual current value are compared with the preset overcurrent protection threshold and zero-sequence current protection threshold to determine whether the threshold can both prevent failure to operate during a fault and prevent false operation during normal fluctuations.

[0168] Second, verify the matching of protection response delay;

[0169] By combining the fault current rise rate and critical time, we analyze whether the preset protection device action delay (such as MMC blocking command response time and AC side circuit breaker breaking time) can be triggered before the fault current reaches the equipment damage risk value.

[0170] Third, verify the consistency of the protection logic.

[0171] Based on the current evolution pattern of each fault stage (such as the current decay characteristics after MMC blocking and the residual current characteristics after the circuit breaker is opened), verify whether the timing logic in the protection strategy matches the current change pattern to avoid inadequate protection due to timing errors.

[0172] Ultimately, if the verification results show that the protection strategy matches the target parameters of the fault current, it is confirmed that the protection strategy is suitable for the current system. If there are threshold deviations, time delay mismatches, or logic gaps, the problem direction fed back by the target parameters will provide a quantitative basis for the optimization of the protection strategy, ensuring that the final configured protection strategy can accurately deal with DC faults in the DR-MMC hybrid cascaded system.

[0173] It should be noted that steps S4 to S5 together constitute the subsequent processing of DC fault current. However, the DC fault current processing method of the DR-MMC hybrid cascade system of this invention is not limited to the above processing process. Other suitable processing processes can be derived based on the fault current analysis results according to the actual application scenario of the DR-MMC hybrid cascade system.

[0174] This invention discloses a method for analyzing DC fault current in a DR-MMC hybrid cascaded system. By constructing an equivalent discharge circuit in stages based on the changes in the fault circuit state, and combining frequency domain transformation and time domain solution, the method accurately derives the sub-results of fault current analysis at each stage and integrates them into a system-level DC fault current analysis result. This achieves staged, high-precision calculation of DC fault current in DR-MMC hybrid cascaded converters. The invention systematically reveals the generation mechanism and attenuation law of current in each fault stage, clarifies the influence path of key factors such as DR AC / DC coupling characteristics, MMC submodule equivalent characteristics, and post-blocking characteristics, filling the gap in systematic calculation methods for DC fault current in DR-MMC hybrid cascaded converters. Simultaneously, it provides a theoretical basis for fault protection design, equipment parameter optimization, and safe and stable operation of DR-MMC hybrid cascaded systems.

[0175] like Figure 7 The diagram shown is a structural schematic of a DC fault current handling system for a DR-MMC hybrid cascade system according to an embodiment of the present invention. (Refer to...) Figure 7 An embodiment of the present invention provides a DC fault current handling system for a DR-MMC hybrid cascaded system, comprising:

[0176] Fault process division module 1 is used to divide the DC fault process of the DR-MMC hybrid cascaded converter into several fault stages based on the changes in the state of the fault circuit;

[0177] Fault current analysis module 2 is used to analyze the dynamic change characteristics of fault current in each fault stage and determine the fault current analysis sub-results for the corresponding fault stage.

[0178] The fault current determination module 3 is used to integrate each fault current analysis sub-result according to the time interval of the corresponding fault stage to determine the fault current analysis result of the DR-MMC hybrid cascaded converter covering the DC fault process.

[0179] The fault current processing module 4 is used to optimize the parameters of the DR-MMC hybrid cascade converter based on the fault current analysis results, and to determine the safe operating boundary of the DR-MMC hybrid cascade system based on the fault current analysis results.

[0180] It should be noted that each module in the aforementioned DR-MMC hybrid cascaded system for handling DC fault current can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the computer device's memory as software, so that the processor can call and execute the corresponding operations of each module. For specific limitations regarding the DR-MMC hybrid cascaded system for handling DC fault current, please refer to the limitations of the DR-MMC hybrid cascaded system DC fault current handling method described above; both have the same function and role, and will not be repeated here.

[0181] In summary, this invention provides a method and system for handling DC fault current in a DR-MMC hybrid cascaded system. By constructing an equivalent discharge circuit in stages based on the changes in the fault circuit state, and combining frequency domain transformation and time domain solution, the analytical sub-results of the fault current at each stage are accurately derived and integrated into a system-level DC fault current analytical result. This achieves staged, high-precision calculation of the DC fault current of the DR-MMC hybrid cascaded converter. The system reveals the generation mechanism and attenuation law of the current at each fault stage, clarifies the influence path of key factors such as the AC / DC coupling characteristics of the DR, the equivalent characteristics of the MMC submodules, and the characteristics after blocking, filling the gap in systematic calculation methods for DC fault current in DR-MMC hybrid cascaded converters. Simultaneously, it provides a theoretical basis for fault protection design, equipment parameter optimization, and safe and stable operation of DR-MMC hybrid cascaded systems.

[0182] The various embodiments in this specification are described in a progressive manner. For directly identical or similar parts of the embodiments, refer to each other. Each embodiment focuses on its differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. It should be noted that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0183] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A method for handling DC fault current in a DR-MMC hybrid cascaded system, characterized in that, A method for handling DC fault current in a DR-MMC hybrid cascaded system with a built-in DR-MMC hybrid cascaded converter, applicable to such systems, includes: Based on the changes in the state of the fault circuit, the DC fault process of the DR-MMC hybrid cascade converter is divided into several fault stages. Analyze the dynamic change characteristics of the fault current in each fault stage to determine the corresponding fault current analytical sub-results for each fault stage; Each fault current analysis sub-result is integrated according to the time interval of the corresponding fault stage to determine the fault current analysis result of the DR-MMC hybrid cascaded converter covering the DC fault process; Based on the fault current analysis results, the parameters of the DR-MMC hybrid cascade converter are optimized, and the safe operating boundary of the DR-MMC hybrid cascade system is determined according to the fault current analysis results. Based on the changes in the fault circuit state, the DC fault process of the DR-MMC hybrid cascaded converter is divided into several fault stages, including: Based on the state change of the fault circuit caused by MMC lockout in the DR-MMC hybrid cascade converter, the first fault stage of the DC fault process is determined, wherein the first fault stage is the DC fault process from the occurrence of the fault to the MMC lockout. Based on the change in fault circuit state caused by the disconnection of the AC side circuit breakers of MMC and DR in the DR-MMC hybrid cascade converter, the second fault stage of the DC fault process is determined, wherein the second fault stage is the DC fault process from MMC blocking to the disconnection of the AC side circuit breakers of MMC and DR. The third fault stage of the DC fault process is defined as the DC fault process from the disconnection of the AC side circuit breaker of MMC and DR to the decay of the fault current to zero.

2. The method for handling DC fault current in a DR-MMC hybrid cascaded system according to claim 1, characterized in that, The analysis of the dynamic change characteristics of the fault current in each fault stage, and the determination of the corresponding fault current analytical sub-results for each fault stage, includes: In response to the topology operation state of the first fault stage, an equivalent discharge circuit for the first fault stage is constructed based on the AC / DC coupling relationship of DR and the sub-module equivalent characteristics of MMC. The equivalent discharge circuit is subjected to a Laplace transform to obtain the first fault discharge operation circuit; The first fault discharge operation circuit is subjected to an inverse Laplace transform to obtain several time-domain fault current components, and the fault current sub-result of the first fault stage is obtained by superimposing each of the time-domain fault current components.

3. The method for handling DC fault current in a DR-MMC hybrid cascaded system according to claim 2, characterized in that, The equivalent discharge circuit for the first fault stage is constructed based on the AC / DC coupling relationship of DR and the submodule equivalent characteristics of MMC, including: Based on the AC / DC coupling relationship of DR, the DC side of DR is equivalent to a Thevenin circuit formed by a DC voltage source and a first resistor connected in series. The voltage value of the DC voltage source is determined based on the AC side voltage, the leakage reactance of the converter transformer, and the turns ratio of the converter transformer. The resistance value of the first resistor is determined based on the leakage reactance of the converter transformer. Based on the submodule equivalent characteristics of MMC, the DC side of MMC is equivalent to an RLC series circuit. The RLC series circuit includes a first capacitor, a first inductor, and a second resistor. The first capacitor is equivalently obtained by first connecting the submodule capacitors in the upper and lower bridge arms of each phase of MMC in series and then connecting them in parallel across three phases. The first inductor is equivalently obtained by first connecting the inductors in the upper and lower bridge arms of each phase of MMC in series and then connecting them in parallel across three phases. The second resistor is equivalently obtained by first connecting the resistors in the upper and lower bridge arms of each phase of MMC in series and then connecting them in parallel across three phases. An equivalent discharge loop for the first fault stage is constructed based at least on the integration of the Thevenin circuit and the RLC series circuit.

4. The method for handling DC fault current in a DR-MMC hybrid cascaded system according to claim 1, characterized in that, The step of analyzing the dynamic change characteristics of the fault current in each fault stage and determining the corresponding fault current analytical sub-result for that fault stage also includes: In response to the topology operation state of the second fault stage, an equivalent discharge circuit for the second fault stage is constructed based on the AC / DC coupling relationship of DR and the lockout characteristics of MMC. The equivalent discharge circuit is subjected to a Laplace transform to obtain the second fault discharge operation circuit; The second fault discharge operation circuit is subjected to an inverse Laplace transform to obtain several time-domain fault current components, and the fault current sub-result of the second fault stage is obtained by superimposing each of the time-domain fault current components.

5. The method for handling DC fault current in a DR-MMC hybrid cascaded system according to claim 4, characterized in that, The equivalent discharge circuit for the second fault stage is constructed based on the AC / DC coupling relationship of DR and the post-blocking characteristics of MMC, including: Based on the AC / DC coupling relationship of DR, the DC side of DR is equivalent to a Thevenin circuit formed by a DC voltage source and a first resistor connected in series. The voltage value of the DC voltage source is determined based on the AC side voltage, the leakage reactance of the converter transformer, and the turns ratio of the converter transformer. The resistance value of the first resistor is determined based on the leakage reactance of the converter transformer. Based on the latch-up characteristics of MMC, the DC side of MMC is equivalent to an RL series circuit. The RL series circuit includes a first inductor and a second resistor. The first inductor is equivalent to the inductors of the upper and lower bridge arms of each phase of MMC connected in series and then in parallel through three phases. The second resistor is equivalent to the resistors of the upper and lower bridge arms of each phase of MMC connected in series and then in parallel through three phases. An equivalent discharge loop for the second fault stage is constructed based at least on the integration of the Thevenin circuit and the RL series circuit.

6. The method for handling DC fault current in a DR-MMC hybrid cascaded system according to claim 1, characterized in that, The step of analyzing the dynamic change characteristics of the fault current in each fault stage and determining the corresponding fault current analytical sub-result for that fault stage also includes: In response to the topology operation state of the third fault stage, an equivalent discharge circuit for the third fault stage is constructed based on the AC side disconnection characteristics of DR and the AC side disconnection characteristics of MMC. The equivalent discharge circuit is subjected to a Laplace transform to obtain the third fault discharge operation circuit; The third fault discharge operation circuit is subjected to an inverse Laplace transform to obtain several time-domain fault current components, and the fault current sub-result of the third fault stage is obtained by superimposing each of the time-domain fault current components.

7. The method for handling DC fault current in a DR-MMC hybrid cascaded system according to claim 6, characterized in that, The equivalent discharge circuit for the third fault stage is constructed based on the AC side disconnection characteristics of DR and the AC side disconnection characteristics of MMC, including: Based on the AC side disconnection characteristics of the DR, the DC side of the DR is equivalent to a first resistor, wherein the resistance value of the first resistor is determined based on the leakage reactance of the converter transformer. Based on the AC side disconnection characteristics of MMC, the DC side of MMC is equivalent to an RL series circuit. The RL series circuit includes a first inductor and a second resistor. The first inductor is equivalent to the inductors of the upper and lower bridge arms of each phase of MMC connected in series and then in parallel by three phases. The second resistor is equivalent to the resistors of the upper and lower bridge arms of each phase of MMC connected in series and then in parallel by three phases. An equivalent discharge circuit for the third fault stage is constructed based at least on the integration of the first resistor and the RL series circuit.

8. The method for handling DC fault current in a DR-MMC hybrid cascaded system according to claim 1, characterized in that, After optimizing the parameters of the DR-MMC hybrid cascade converter based on the fault current analysis results, and determining the safe operating boundary of the DR-MMC hybrid cascade system based on the fault current analysis results, the method further includes: Feature extraction is performed on the fault current analysis results to obtain the fault current target parameters, and the fault protection strategy pre-configured in the DR-MMC hybrid cascade system is verified based on the fault current target parameters.

9. A DC fault current handling system for a DR-MMC hybrid cascaded system, characterized in that, include: The fault process division module is used to divide the DC fault process of the DR-MMC hybrid cascaded converter into several fault stages based on the changes in the state of the fault circuit. The fault current analysis module is used to analyze the dynamic change characteristics of the fault current in each fault stage and determine the fault current analysis sub-results corresponding to the fault stage. The fault current determination module is used to integrate each fault current analysis sub-result according to the time interval of the corresponding fault stage, and determine the fault current analysis result of the DR-MMC hybrid cascaded converter covering the DC fault process. The fault current processing module is used to optimize the parameters of the DR-MMC hybrid cascade converter based on the fault current analysis results, and to determine the safe operating boundary of the DR-MMC hybrid cascade system based on the fault current analysis results. Based on the changes in the fault circuit state, the DC fault process of the DR-MMC hybrid cascaded converter is divided into several fault stages, including: Based on the state change of the fault circuit caused by MMC lockout in the DR-MMC hybrid cascade converter, the first fault stage of the DC fault process is determined, wherein the first fault stage is the DC fault process from the occurrence of the fault to the MMC lockout. Based on the change in fault circuit state caused by the disconnection of the AC side circuit breakers of MMC and DR in the DR-MMC hybrid cascade converter, the second fault stage of the DC fault process is determined, wherein the second fault stage is the DC fault process from MMC blocking to the disconnection of the AC side circuit breakers of MMC and DR. The third fault stage of the DC fault process is defined as the DC fault process from the disconnection of the AC side circuit breaker of MMC and DR to the decay of the fault current to zero.

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