Method for manufacturing read-only memory code and semiconductor structure

Abstract

The invention provides a method for manufacturing a read-only memory code and a semiconductor structure. The method comprises the following steps: providing a substrate and forming top metal with a buffer distance in a sealing ring area; depositing a passivation layer and coating a photosensitive layer; forming differentiated side wall covering contours at positions corresponding to different logic codes by utilizing the sensitivity difference of a photosensitive layer to exposure parameters; etching the passivation layer to selectively expose the top metal side wall; metal wet etching is executed, the top layer metal is removed to define a first logic state according to the characteristic that the etching liquid erodes and exposes the side wall, and the rest of the top layer metal is reserved to define a second logic state. According to the method, the original process failure mechanism is converted into a programming means, an additional photomask is not needed, and flexible code definition is realized while the cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for manufacturing read-only memory code and a semiconductor structure. Background Technology

[0002] In the manufacturing process of semiconductor integrated circuits, read-only memory (ROM) is widely used to store fixed configuration information, version numbers, or feature identifiers and other code data. Traditional methods for creating ROM code usually require additional photomasks or specific process steps, which not only increases production costs but also extends the process cycle.

[0003] In the peripheral structure of semiconductor chips, a sealing ring is typically designed to prevent moisture and impurity ions from penetrating the active area. A scribe line is also provided on the outside of the sealing ring for dicing. The sealing ring is usually composed of multiple layers of metal and through-holes. In existing manufacturing processes, especially those involving wafer-level chip-scale packaging (CSP), passivation layer etching and wet metal etching are commonly performed.

[0004] In actual production, an anomaly was observed: when the photoresist of the capping layer is affected by parameter fluctuations during exposure, the area between the top metal of the sealing ring and its adjacent scribe line exhibits high sensitivity to exposure energy. If the exposure energy deviates from the preset range, or if the geometric redundancy in this area is insufficient, the photoresist's coverage on the sidewalls of the top metal decreases, potentially causing the sidewalls of the top metal to be accidentally etched open during subsequent passivation layer etching. In the subsequent wet etching step for packaging, the etching solution can penetrate along the sidewall gaps, resulting in the complete etching away of the top metal in the sealing ring area.

[0005] How to effectively solve the stability problem caused by process fluctuations is a technical challenge currently faced by those skilled in the art. Summary of the Invention

[0006] The present invention aims to solve the technical problem that defining read-only memory code in the prior art usually requires additional photomasks or specific process steps, which leads to increased chip production costs and increased manufacturing process complexity.

[0007] The read-only memory (ROM) code semiconductor structure includes:

[0008] The substrate defines a scribe groove region and a sealing ring region;

[0009] A sealing ring is disposed within the sealing ring area. The sealing ring includes a top layer metal, and there is a buffer distance between the top layer metal and the boundary of the scribing groove area.

[0010] The sealing ring area is divided into a first area and a second area according to the logical design of the read-only memory code. The top metal in the first area is missing to present an open circuit corresponding to the first logical state, while the top metal in the second area is retained to present a path corresponding to the second logical state.

[0011] The sidewalls of the top metal in the through-path state are covered by a passivation layer, and the passivation layer has an opening at the location corresponding to the first region that exposes the sidewalls of the top metal.

[0012] Preferably, the passivation layer is selected from at least one or a combination of the following materials: undoped silicon glass, fluorine-doped silicon glass, phosphosilicate glass, borosilicate glass, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, polyimide, and polybenzobisoxazole.

[0013] Preferably, the buffer distance between the top metal and the boundary of the dicing groove area is 0.8 μm to 1.2 μm.

[0014] Preferably, the width of the top layer metal is 3.5 μm to 4.5 μm, and / or the width of the dicing groove area is 55 μm to 65 μm.

[0015] Preferably, the total thickness of the passivation layer is 1.0 μm to 1.5 μm, and / or the thickness of the top metal layer is 8.0 μm to 10.5 μm.

[0016] The method for creating read-only memory code includes the following steps:

[0017] Step 1: Provide a substrate, which defines a scribe groove region and a sealing ring region. Form a top layer metal in the sealing ring region and set a buffer distance between the top layer metal and the boundary of the scribe groove region.

[0018] Step 2: Form a passivation layer covering the sidewalls of the top metal on the upper surface of the top metal and the substrate, and coat a photosensitive layer on the upper surface of the passivation layer;

[0019] Step 3: According to the design requirements of the read-only memory code, the photosensitive layer is exposed and developed. For the positions corresponding to different logic states, the sensitivity difference of the photosensitive layer to the exposure parameters is used to make the photosensitive layer form different coverage states on the side wall of the top metal near the scribe groove area.

[0020] Step 4: Use the patterned photosensitive layer as a mask to etch the passivation layer, so that the top metal sidewalls corresponding to different logic states are either exposed or covered.

[0021] Step 5: Perform a metal etching process to remove the top layer metal with exposed sidewalls to define the first logic state, and retain the top layer metal with covered sidewalls to define the second logic state, thereby forming the read-only memory code.

[0022] Preferably, in step two, the passivation layer is selected from at least one or a combination of the following materials: undoped silicon glass, fluorine-doped silicon glass, phosphosilicate glass, borosilicate glass, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, polyimide, and polybenzobisoxazole.

[0023] Preferably, in step one, the buffer distance between the top metal and the boundary of the dicing groove area is 0.8 μm to 1.2 μm.

[0024] Preferably, in step one, the width of the top layer metal is 3.5 μm to 4.5 μm, and / or the width of the dicing groove area is 55 μm to 65 μm.

[0025] Preferably, in step two, the total thickness of the passivation layer is 1.0 μm to 1.5 μm, and / or the thickness of the top metal layer is 8.0 μm to 10.5 μm.

[0026] Preferably, in step two, the photosensitive layer is a photoresist, and the thickness of the photoresist is 3.2 μm to 3.8 μm.

[0027] Preferably, in step three, the development profile of the photosensitive layer at the top metal sidewall is controlled by adjusting the exposure energy.

[0028] Preferably, in step five, the metal etching process is a wet etching process for the metallization layer under the bump, and the wet etching process is performed in wafer-level chip-scale packaging.

[0029] As described above, the method for fabricating read-only memory code and the semiconductor structure of the present invention have the following beneficial effects:

[0030] This invention leverages the high sensitivity of the top metal layer to photolithography exposure parameters at specific geometric intervals, transforming a failure mechanism that is inherently process-sensitive into a precise and controllable code programming method. By adjusting the exposure dose to differentially control the coverage effectiveness of the passivation layer mask on the sidewalls of the top metal layer, and combining this with the wet etching step in the subsequent packaging process, selective removal of the metal layer is achieved. This approach not only eliminates the dependence on additional photomasks or physical programming steps, significantly reducing manufacturing costs and simplifying the process flow, but also makes full use of the sealing ring space around the chip. Attached Figure Description

[0031] Figure 1 The diagram shows a flowchart of the method for creating a read-only memory code according to the present invention.

[0032] Figure 2 This diagram illustrates the state in which the top metal sidewall is covered during the method for manufacturing read-only memory code according to the present invention.

[0033] Figure 3 This diagram illustrates the open state of the top metal sidewall in the method for creating read-only memory code according to the present invention.

[0034] Figure 4 The diagram shown is an exposure schematic of the first logic code in the method for creating read-only memory code of the present invention;

[0035] Figure 5 The diagram shown is an exposure schematic of the second logic code in the method for creating read-only memory code of the present invention;

[0036] Figure 6 The diagram shown is an exposure diagram of the third logic code in the method for creating read-only memory code of the present invention. Detailed Implementation

[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] The read-only memory (ROM) code semiconductor structure includes a substrate, which defines a scribe groove region and a sealing ring region.

[0039] In some embodiments, the substrate is a material with semiconductor properties, such as a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a silicon-germanium substrate. In some embodiments, the substrate is selected from at least one or a combination of the following materials: single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, silicon carbide, or compound semiconductor materials such as gallium arsenide, indium phosphide, and indium antimonide. The substrate is used to form well regions via ion implantation, and active devices and metal interconnect layers are formed on its surface using typical complementary metal-oxide-semiconductor (CMOS) processes.

[0040] A sealing ring is disposed within the sealing ring region. The sealing ring includes a top layer metal, and a buffer distance exists between the top layer metal and the boundary of the dicing groove region. The sealing ring body is formed by stacking multiple metallization processes in the dielectric layer above the substrate. (Reference) Figure 2 The top layer of metal on the sealing ring is prepared by physical vapor deposition or electroplating.

[0041] Substrates can be defined by various semiconductor processing techniques to define different functional zones. For example, well regions or isolation doped regions can be formed within the substrate using a photomask combined with ion implantation, or shallow trench isolation structures can be formed by dry etching using a mask and filling them with insulating materials such as silicon oxide. This physically and electrically defines the active region for circuit layout, as well as the surrounding sealing ring region and dicing groove region. This scheme, defined by a deep structure, ensures that the sealing ring has better substrate anchoring force when subjected to cutting stress.

[0042] The process of forming the top metal in the sealing ring region typically involves a multi-layer metallization stacking process. In some embodiments, multiple intermetallic dielectric layers can be alternately formed on the substrate using plasma-enhanced chemical vapor deposition (PECVD) or atmospheric pressure chemical vapor deposition (APCVD). The dielectric material can be selected from undoped silicon glass, fluorine-doped silicon glass, or low-k dielectric materials. In each dielectric layer, metal lines and vias made of copper or aluminum-copper alloys are formed using a dual-damascene or single-damascene process. Before forming the top metal layer, a diffusion barrier layer containing titanium, titanium nitride, tantalum, tantalum nitride, or titanium-tungsten alloy is typically formed by physical vapor deposition (PVD). Next, a thick metal host layer is formed by high-current electroplating, chemical vapor deposition, or sputtering processes; the material is typically aluminum or an aluminum-copper alloy.

[0043] The method for establishing a buffer distance between the top metal layer and the boundary of the scribe line region primarily relies on a high-resolution photolithography system. A thick layer of photosensitive emulsion is coated onto the surface of the top metal layer, and exposure is performed using a stepper lithography machine, allowing the photosensitive emulsion to form a precisely defined mask pattern after development. Subsequently, anisotropic dry etching techniques such as reactive ion etching are used to remove the exposed metal, causing the edge of the top metal layer to precisely recede to the side of the scribe line region boundary. In some embodiments, the buffer distance is precisely set to the diffraction-sensitive area during optical system exposure. Specific photoresist viscosity and spin coating parameters are used to create a negatively correlated function between the thickness attenuation of the photoresist at the edge of the top metal step and this buffer distance. This provides a refined physical basis for selectively exposing the sidewalls by adjusting the exposure dose in subsequent steps.

[0044] In some embodiments, the buffer distance between the top metal and the boundary of the scribe groove region is 0.8 μm to 1.2 μm. By precisely controlling the physical span from the edge of the top metal to the boundary of the scribe groove sidewall, a controllable optical interference effect can be generated in the photolithography process, thereby affecting the photosensitive deformation of the subsequent photoresist.

[0045] The sealing ring region is divided into a first region and a second region according to the logical design of the read-only memory code. The top metal in the first region is missing to represent an open circuit corresponding to the first logical state, while the top metal in the second region is retained to represent a closed circuit corresponding to the second logical state. The sidewalls of the top metal in the closed circuit state are covered by a passivation layer, which has openings at the locations corresponding to the first region that expose the sidewalls of the top metal. This physical arrangement of open and closed circuits simulates high and low voltage levels through different metal retention states, thereby permanently writing binary information into the topology of the sealing ring.

[0046] In some embodiments, the passivation layer is selected from at least one or a combination of the following materials: undoped silicon glass, fluorine-doped silicon glass, phosphosilicate glass, borosilicate glass, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, polyimide, and polybenzobisoxazole.

[0047] In some embodiments, the passivation layer consists of a silicon oxide layer with a thickness of 4500 Å to 5500 Å and a silicon nitride layer with a thickness of 8200 Å to 9200 Å, sequentially stacked using a plasma-enhanced chemical vapor deposition process. For example, in a specific application, the silicon oxide layer has a thickness of 5000 Å and the silicon nitride layer has a thickness of 8700 Å. This dual-layer passivation structure effectively mitigates thermal stress during the packaging process and utilizes the high density of the silicon nitride layer to prevent moisture penetration.

[0048] In some embodiments, the width of the top layer metal is 3.5 μm to 4.5 μm, and / or the width of the dicing groove region is 55 μm to 65 μm. Reference Figure 2 The typical width of the dicing groove region is set to 60 μm, and the typical width of the top layer metal is set to 4 μm. The optimized width ratio ensures resistance to crack propagation during wafer dicing while also providing sufficient lateral etching windows for defining the logic states of the top layer metal.

[0049] In some embodiments, the total thickness of the passivation layer is 1.0 μm to 1.5 μm, and / or the thickness of the top layer metal is 8.0 μm to 10.5 μm. The thicker top layer metal, combined with the passivation layer of a specific thickness, enables the formation of a deeper and steeper opening profile at the code opening location in the first region. This steepness facilitates the wetting and lateral erosion of the wet etching solution at that specific site.

[0050] refer to Figure 1 The method for creating read-only memory code includes the following steps:

[0051] Step 1: Provide a substrate, which defines a dicing groove region and a sealing ring region. Form a top layer metal in the sealing ring region and set a buffer distance between the top layer metal and the boundary of the dicing groove region.

[0052] In step one, the substrate can be defined by various semiconductor processing techniques to define different functional zones. For example, a well region or isolation doped region can be formed within the substrate using a photomask combined with ion implantation, or a shallow trench isolation structure can be formed by dry etching using a mask and filling it with insulating materials such as silicon oxide. This physically and electrically defines the active region for circuit layout, as well as the surrounding sealing ring region and dicing groove region. This scheme, defined by a deep structure, ensures that the sealing ring has better substrate anchoring force when subjected to cutting stress.

[0053] The process of forming the top metal in the sealing ring region typically involves a multi-layer metallization stacking process. In some embodiments, multiple intermetallic dielectric layers can be alternately formed on the substrate using plasma-enhanced chemical vapor deposition (PECVD) or atmospheric pressure chemical vapor deposition (APCVD). The dielectric material can be selected from undoped silicon glass, fluorine-doped silicon glass, or low-k dielectric materials. In each dielectric layer, metal lines and vias made of copper or aluminum-copper alloys are formed using a dual-damascene or single-damascene process. Before forming the top metal layer, a diffusion barrier layer containing titanium, titanium nitride, tantalum, tantalum nitride, or titanium-tungsten alloy is typically formed by physical vapor deposition (PVD). Next, a metal host layer is formed by high-current electroplating, chemical vapor deposition, or sputtering processes; the material is typically aluminum or an aluminum-copper alloy.

[0054] The method for establishing a buffer distance between the top metal layer and the boundary of the scribe line region primarily relies on a high-resolution photolithography system. A thick layer of photosensitive emulsion is coated onto the surface of the top metal layer, and exposure is performed using a stepper lithography machine, allowing the photosensitive emulsion to form a precisely defined mask pattern after development. Subsequently, anisotropic dry etching techniques such as reactive ion etching are used to remove the exposed metal, causing the edge of the top metal layer to precisely recede to the side of the scribe line region boundary. In some embodiments, the buffer distance is precisely set to the diffraction-sensitive area during optical system exposure. Specific photoresist viscosity and spin coating parameters are used to create a negatively correlated function between the thickness attenuation of the photoresist at the edge of the top metal step and this buffer distance. This provides a refined physical basis for selectively exposing the sidewalls by adjusting the exposure dose in subsequent steps.

[0055] In some embodiments, in step one, the buffer distance between the top metal and the boundary of the dicing groove region is 0.8 μm to 1.2 μm. For example, the buffer distance of the top metal perpendicularly projected to the boundary of the dicing groove region is 1 μm.

[0056] In some embodiments, in step one, the width of the top layer metal is 3.5 μm to 4.5 μm, and / or the width of the dicing groove region is 55 μm to 65 μm.

[0057] Step 2: A passivation layer covering the sidewalls of the top metal is formed on the upper surface of the top metal and the substrate, and a photosensitive layer is coated on the upper surface of the passivation layer. In Step 2, the passivation layer is deposited on the top and sidewall surfaces of the top metal by vapor deposition, thereby forming a conformal coating. The photosensitive layer is then coated on the substrate surface.

[0058] In some embodiments, in step two, the passivation layer is selected from at least one or a combination of the following materials: undoped silicon glass, fluorine-doped silicon glass, phosphosilicate glass, borosilicate glass, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, polyimide, and polybenzobisoxazole.

[0059] In some embodiments, in step two, the photosensitive layer is a photoresist with a thickness of 3.2 μm to 3.8 μm, and in step two, the total thickness of the passivation layer is 1.0 μm to 1.5 μm, and the thickness of the top metal layer is 8.0 μm to 10.5 μm. Figure 2 In the cross-sectional structure shown, the photoresist thickness is preferably 3.5 μm.

[0060] Step 3: According to the design requirements of the read-only memory code, the photosensitive layer undergoes exposure and development processes. For positions corresponding to different logic states, the sensitivity of the photosensitive layer to exposure parameters is utilized to create different coverage states on the sidewall of the top metal layer near the scribe line area. In Step 3, by controlling the energy distribution of the stepper in different areas, the photosensitive layer exhibits differentiated etching resistance properties. (Reference) Figure 3 Under specific exposure parameters, the photoresist will shrink or open at the edge of the sealing ring, which determines whether the subsequent passivation layer will be removed.

[0061] In some embodiments, in step three, the development profile of the photosensitive layer at the top metal sidewall is controlled by adjusting the exposure energy. (See reference) Figure 4 , Figure 5 and Figure 6 For different code designs on the same batch or the same wafer, lithography energies 1, 2, and 3 are used for exposure, respectively. By modulating the retention profile of the photosensitive layer at specific locations, the exposure energies of different intensities can selectively determine the effectiveness of the passivation layer's coverage of the top metal sidewall, thereby achieving code programming functionality that does not depend on changes to the physical photomask.

[0062] Step 4: Using the patterned photosensitive layer as a mask, etch the passivation layer, exposing or covering the top metal sidewalls corresponding to different logic states. Step 4 employs reactive ion etching to remove the passivation layer material not protected by the photosensitive layer. For overexposed areas, the passivation layer is completely removed from the buffer region, thus exposing the sidewall interfaces of the top metal.

[0063] Step 5: Perform a metal etching process to remove the top metal with exposed sidewalls to define the first logic state, and retain the top metal with covered sidewalls to define the second logic state, thereby forming the read-only memory code. In Step 5, the etching solution enters through the opening area of ​​the top metal sidewall and isotropically etches the metal layer in the first region.

[0064] In some embodiments, in step five, the metal etching process is a wet etching process for the under-bump metallization layer, and the wet etching process is performed in wafer-level chip-scale packaging. The wet etching solution used during the packaging process to remove excess under-bump metallization layer simultaneously penetrates the top metal sites of the exposed sidewalls while removing residual metal layers. This process reuse not only eliminates the need for additional dedicated etching steps but also utilizes the sidewall etching characteristics, which are originally an abnormal mechanism, to transform them into a controlled code programming technique, significantly improving the security of semiconductor devices in wafer-level packaging (WLCSP).

[0065] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0066] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A read-only memory code semiconductor structure, characterized in that, include: The substrate defines a scribe groove region and a sealing ring region; A sealing ring is disposed within the sealing ring area. The sealing ring includes a top layer metal, and there is a buffer distance between the top layer metal and the boundary of the scribing groove area. The sealing ring area is divided into a first area and a second area according to the logical design of the read-only memory code. The top metal in the first area is missing to present an open circuit corresponding to the first logical state, while the top metal in the second area is retained to present a path corresponding to the second logical state. The sidewalls of the top metal in the through-path state are covered by a passivation layer, and the passivation layer has an opening at the location corresponding to the first region that exposes the sidewalls of the top metal.

2. The read-only memory code semiconductor structure according to claim 1, characterized in that: The passivation layer is selected from at least one or a combination of the following materials: undoped silicon glass, fluorine-doped silicon glass, phosphosilicate glass, borosilicate glass, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, polyimide, and polybenzobisoxazole.

3. The read-only memory code semiconductor structure according to claim 1, characterized in that: The buffer distance between the top metal and the boundary of the dicing groove area is 0.8 μm to 1.2 μm.

4. The read-only memory code semiconductor structure according to claim 1, characterized in that: The width of the top metal layer is 3.5 μm to 4.5 μm, and / or the width of the dicing groove area is 55 μm to 65 μm.

5. The read-only memory code semiconductor structure according to claim 1, characterized in that: The total thickness of the passivation layer is 1.0 μm to 1.5 μm, and / or the thickness of the top metal layer is 8.0 μm to 10.5 μm.

6. A method for generating read-only memory code, characterized in that, include: Step 1: Provide a substrate, which defines a scribe groove region and a sealing ring region. Form a top layer metal in the sealing ring region and set a buffer distance between the top layer metal and the boundary of the scribe groove region. Step 2: Form a passivation layer covering the sidewalls of the top metal on the upper surface of the top metal and the substrate, and coat a photosensitive layer on the upper surface of the passivation layer; Step 3: According to the design requirements of the read-only memory code, the photosensitive layer is exposed and developed. For the positions corresponding to different logic states, the sensitivity difference of the photosensitive layer to the exposure parameters is used to make the photosensitive layer form different coverage states on the side wall of the top metal near the scribe groove area. Step 4: Use the patterned photosensitive layer as a mask to etch the passivation layer, so that the top metal sidewalls corresponding to different logic states are either exposed or covered. Step 5: Perform a metal etching process to remove the top layer metal with exposed sidewalls to define the first logic state, and retain the top layer metal with covered sidewalls to define the second logic state, thereby forming the read-only memory code.

7. The method for generating read-only memory code according to claim 6, characterized in that: In step two, the passivation layer is selected from at least one or a combination of the following materials: undoped silicon glass, fluorine-doped silicon glass, phosphosilicate glass, borosilicate glass, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, polyimide, and polybenzobisoxazole.

8. The method for generating read-only memory code according to claim 6, characterized in that: In step one, the buffer distance between the top metal and the boundary of the dicing groove area is 0.8 μm to 1.2 μm.

9. The method for generating read-only memory code according to claim 6, characterized in that: In step one, the width of the top layer metal is 3.5 μm to 4.5 μm, and / or the width of the dicing groove area is 55 μm to 65 μm.

10. The method for generating read-only memory code according to claim 6, characterized in that: In step two, the total thickness of the passivation layer is 1.0 μm to 1.5 μm, and / or the thickness of the top metal layer is 8.0 μm to 10.5 μm.

11. The method for generating read-only memory code according to claim 6, characterized in that: In step two, the photosensitive layer is photoresist, and the thickness of the photoresist is 3.2 μm to 3.8 μm.

12. The method for generating read-only memory code according to claim 6, characterized in that: In step three, the development profile of the photosensitive layer at the top metal sidewall is controlled by adjusting the exposure energy.

13. The method for generating read-only memory code according to claim 6, characterized in that: In step five, the metal etching process is a wet etching process for the metallization layer under the bump, and the wet etching process is performed in wafer-level chip-scale packaging.

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