Semiconductor structure and preparation method thereof, memory and memory system

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method of the semiconductor structure, a memory and a memory system, the semiconductor structure comprises a semiconductor-on-insulator structure, and the semiconductor-on-insulator structure comprises an insulating layer, a first semiconductor layer and a second semiconductor layer; the first semiconductor layer is located on one side of the insulating layer along the first direction; the second semiconductor layer is located on one side of the insulating layer in the first direction and located on at least one side of the first semiconductor layer in the direction intersecting with the first direction; wherein in the first direction, the size of the first semiconductor layer is larger than that of the second semiconductor layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods for fabricating semiconductor structures, memories, and memory systems. Background Technology

[0002] Memory is one of the most important components in electronic systems. Memory can include Random Access Memory (RAM), Read Only Memory (ROM), and Cache. Random Access Memory can include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Memory also includes Flash memory. Summary of the Invention

[0003] This application provides semiconductor structures, methods for fabricating semiconductor structures, memories, and storage systems that can at least partially solve the problems described above or other problems in the art.

[0004] This application provides a semiconductor structure, including a semiconductor-on-insulator structure, which includes an insulating layer, a first semiconductor layer, and a second semiconductor layer; the first semiconductor layer is located on one side of the insulating layer along a first direction; the second semiconductor layer is located on one side of the insulating layer along the first direction and on at least one side of the first semiconductor layer along a direction intersecting the first direction; wherein, in the first direction, the size of the first semiconductor layer is larger than the size of the second semiconductor layer.

[0005] In some implementations, in the first direction, the size of the first semiconductor layer is 1.5 to 3 times the size of the second semiconductor layer.

[0006] In some embodiments, the semiconductor structure further includes a first gate structure and a second gate structure; the first gate structure is located on the side of the first semiconductor layer away from the insulating layer; and the second gate structure is located on the side of the second semiconductor layer away from the insulating layer.

[0007] In some embodiments, the insulating layer includes a first insulating portion located on the side of the second semiconductor layer opposite to the first direction and a second insulating portion located on the side of the first semiconductor layer opposite to the first direction; wherein, in the first direction, the size of the first insulating portion is larger than the size of the second insulating portion.

[0008] In some embodiments, the height of the surface of the first semiconductor layer facing away from the insulating layer in the first direction is the same as the height of the surface of the second semiconductor layer facing away from the insulating layer in the first direction, relative to the side of the insulating layer facing away from the first direction.

[0009] In some embodiments, the height of the surface of the second semiconductor layer facing away from the insulating layer in the first direction is less than the height of the surface of the first semiconductor layer facing away from the insulating layer in the first direction, relative to the side of the insulating layer facing away from the first direction.

[0010] In some embodiments, in a first direction, the size of the portion of the insulating layer located on the side of the first semiconductor layer is equal to the size of the portion of the insulating layer located on the side of the second semiconductor layer.

[0011] In some embodiments, the semiconductor structure further includes a first isolation structure and a second isolation structure; the first isolation structure is located on both sides of the first semiconductor layer along a second direction and is connected to an insulating layer; the second isolation structure is located on both sides of the second semiconductor layer along a second direction and is connected to an insulating layer; wherein the second direction intersects the first direction.

[0012] In some implementations, in the second direction, the size of the first semiconductor layer between adjacent first isolation structures is larger than the size of the second semiconductor layer between adjacent second isolation structures.

[0013] In some embodiments, the semiconductor structure further includes a third isolation structure and a fourth isolation structure. The third isolation structure is located on both sides of the first semiconductor layer along a third direction and is connected to the insulating layer and the first isolation structure. The fourth isolation structure is located on both sides of the second semiconductor layer along a third direction and is connected to the insulating layer and the second isolation structure. The third direction intersects the second direction and the first direction.

[0014] In some implementations, in the third direction, the size of the first semiconductor layer between adjacent third isolation structures is larger than the size of the second semiconductor layer between adjacent fourth isolation structures.

[0015] In some embodiments, the first gate structure includes a first gate dielectric layer and a first gate electrode layer, wherein the first gate dielectric layer is located on the side of the first semiconductor layer away from the insulating layer, and the first gate electrode layer is located on the side of the first gate dielectric layer away from the first semiconductor layer; wherein the second gate structure includes a second gate dielectric layer and a second gate electrode layer, wherein the second gate dielectric layer is located on the side of the second semiconductor layer away from the insulating layer, and the second gate electrode layer is located on the side of the second gate dielectric layer away from the second semiconductor layer; wherein, along a first direction, the size of the first gate dielectric layer is larger than the size of the second gate dielectric layer.

[0016] This application also provides a method for fabricating a semiconductor structure, the semiconductor structure including a semiconductor-on-insulator structure, the fabrication method including: forming an insulating layer and an initial semiconductor layer, the initial semiconductor layer being located on one side of the insulating layer in a first direction; etching the initial semiconductor layer to form a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is located on at least one side of the first semiconductor layer along a direction intersecting the first direction, and in the first direction, the size of the first semiconductor layer is larger than the size of the second semiconductor layer.

[0017] In some embodiments, forming an insulating layer and an initial semiconductor layer includes: forming a third semiconductor layer, an insulating layer, and an initial semiconductor layer stacked along a first direction, the insulating layer being located between the third semiconductor layer and the initial semiconductor layer, the initial semiconductor layer including a first portion and a second portion, the second portion being located on at least one side of the first portion along a direction intersecting the first direction; wherein etching the initial semiconductor layer to form the first semiconductor layer and the second semiconductor layer includes: etching the first portion to form a plurality of first isolation trenches spaced along a second direction, wherein portions of the first portion located between adjacent first isolation trenches form the first semiconductor layer; and etching the second portion to form a plurality of second isolation trenches spaced along the second direction, wherein portions of the second portion located between adjacent second isolation trenches form the second semiconductor layer; wherein the second direction intersects the first direction.

[0018] In some embodiments, before etching the first portion and before etching the second portion, in a first direction, the size of the second portion is smaller than the size of the first portion, and the size of the portion of the insulating layer located on the side of the second portion opposite to the first direction is larger than the size of the portion of the insulating layer located on the side of the first portion opposite to the first direction.

[0019] In some embodiments, the preparation method further includes: thinning the second portion from the side of the second portion away from the insulating layer before etching the second portion, wherein the dimension of the second portion in the first direction is smaller than the dimension of the first portion in the first direction.

[0020] In some embodiments, forming a third semiconductor layer, an insulating layer, and an initial semiconductor layer stacked along a first direction includes: forming a third semiconductor layer, a first insulating layer, and a semiconductor material layer stacked along the first direction; and forming a second insulating layer connected to a portion of the first insulating layer in a portion of the semiconductor material layer, the second insulating layer having a dimension along the first direction smaller than the semiconductor material layer having a dimension along the first direction, wherein the remaining semiconductor material layer forms the initial semiconductor layer; wherein the first insulating layer and the second insulating layer constitute an insulating layer.

[0021] In some embodiments, forming a second insulating layer connected to a portion of the first insulating layer in a certain region of the semiconductor material layer includes: forming an ion-doped region in a certain region of the semiconductor material layer; and annealing the ion-doped region, wherein the ion-doped region forms the second insulating layer.

[0022] In some embodiments, the preparation method further includes: forming a first isolation structure in a first isolation trench; and forming a second isolation structure in a second isolation trench.

[0023] In some embodiments, etching the first portion further forms a plurality of third isolation trenches spaced apart along a third direction, the third isolation trenches communicating with the first isolation trench; etching the second portion further forms a plurality of fourth isolation trenches spaced apart along a third direction, the fourth isolation trenches communicating with the second isolation trench; wherein, the portion of the first portion located between adjacent first isolation trenches and adjacent third isolation trenches forms a first semiconductor layer, and the portion of the second portion located between adjacent second isolation trenches and adjacent fourth isolation trenches forms a second semiconductor layer; wherein, the third direction intersects with the first direction and intersects with the second direction.

[0024] In some embodiments, the preparation method further includes: forming a third isolation structure in a third isolation trench; and forming a fourth isolation structure in a fourth isolation trench.

[0025] In some embodiments, the fabrication method further includes: forming a first gate structure located on the side of the first semiconductor layer away from the insulating layer; and forming a second gate structure located on the side of the second semiconductor layer away from the insulating layer; wherein forming the first gate structure includes: forming a first gate dielectric layer on the side of the first semiconductor layer away from the insulating layer; and forming a first gate electrode layer on the side of the first gate dielectric layer away from the first semiconductor layer; wherein forming the second gate structure includes: forming a second gate dielectric layer on the side of the second semiconductor layer away from the insulating layer; and forming a second gate electrode layer on the side of the second gate dielectric layer away from the second semiconductor layer; wherein, along a first direction, the size of the first gate dielectric layer is larger than the size of the second gate dielectric layer.

[0026] This application also provides a memory, including: a memory cell array; peripheral circuitry, including and including the semiconductor structure mentioned in any of the embodiments above, the peripheral circuitry being coupled to the memory cell array.

[0027] In another aspect, this application provides a storage system including a controller and a memory as mentioned in any of the embodiments above, the controller being coupled to the memory and used to control the memory to store data. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0029] Figure 1 A schematic diagram of a semiconductor structure;

[0030] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of this application;

[0031] Figure 3 This is a schematic diagram of a semiconductor structure according to another embodiment of this application;

[0032] Figure 4 This is a schematic diagram of a semiconductor structure according to yet another embodiment of this application;

[0033] Figure 5 A flowchart illustrating a method for fabricating a semiconductor structure according to one embodiment;

[0034] Figures 6 to 14 This is a structural diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this application;

[0035] Figures 15 to 26 This is a structural diagram illustrating the fabrication process of a semiconductor structure according to another embodiment of this application;

[0036] Figures 27 to 32 A structural diagram illustrating the fabrication process of a semiconductor structure according to another embodiment of this application;

[0037] Figure 33 A schematic diagram of a memory according to another embodiment;

[0038] Figure 34 A block diagram of a system having a storage system according to an exemplary embodiment of this application;

[0039] Figure 35 A schematic diagram of a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0040] A semiconductor structure, reference Figure 1 It includes: a semiconductor substrate layer 10; a first well region 11; a second well region 12; a first active region 21 located in the first well region 11, a portion of the first active region 21 being a first source region and another portion of the first active region 21 being a first drain region; a first lead-out region 31 located in the first well region 11; a second active region 22 located in the second well region 12, a portion of the second active region 22 being a second source region and another portion of the second active region 22 being a second drain region; and a second lead-out region 32 located in the second well region 11.

[0041] A first transistor is formed on the first well region 11, the first transistor including a first gate structure, a first source region, and a first drain region. A second transistor is formed on the second well region 12, the second transistor including a second gate structure, a second source region, and a second drain region. The operating voltage of the first transistor is greater than the operating voltage of the second transistor. The first lead-out region 31 and the first source region are shorted together to reduce the substrate bias effect of the first transistor. The second lead-out region 32 and the second source region are shorted together to reduce the substrate bias effect of the second transistor.

[0042] Since a certain area is required to set up the first lead-out region 31 and the second lead-out region 32, the layout area of ​​the semiconductor structure is relatively large.

[0043] To control costs, the integration level of semiconductor structures needs to be increased, and smaller semiconductor structures are more conducive to reducing costs.

[0044] Based on this, the embodiments of this application provide a semiconductor structure, a method for fabricating a semiconductor structure, a memory, and a memory system, which improve the integration of the semiconductor structure and reduce the cost of the semiconductor structure.

[0045] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0047] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0048] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0049] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0050] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0051] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0052] This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0053] Figure 2 This is a schematic diagram of a semiconductor structure provided in one embodiment of this application.

[0054] refer to Figure 2 The semiconductor structure 10000 includes a semiconductor-on-insulator structure 10, which includes an insulating layer 104, a first semiconductor layer 1021, and a second semiconductor layer 1022. The first semiconductor layer 1021 is located on one side of the insulating layer 104 along a first direction Z; the second semiconductor layer 1022 is located on one side of the insulating layer 104 along the first direction Z, and on at least one side of the first semiconductor layer 1021 along a direction intersecting the first direction Z; wherein, in the first direction Z, the size of the first semiconductor layer 1021 is larger than the size of the second semiconductor layer 1022.

[0055] The semiconductor structure 10000 can be a peripheral circuit, or it can include a structure combining a memory cell array and peripheral circuitry. The peripheral circuitry is electrically connected to the memory cell array, and it drives the memory cell array to perform erasing, writing, and reading operations. The memory cell array can be a two-dimensional or three-dimensional memory array, or even a portion of a two-dimensional or three-dimensional memory array. Alternatively, the three-dimensional memory array can include at least one of a three-dimensional NAND memory array and a three-dimensional NOR memory array.

[0056] As the number of stacked layers in a memory cell array increases, the number of transistors required in the peripheral circuitry also increases accordingly. In this case, to control costs, the size of the peripheral circuitry needs to be controlled; the smaller the size of the peripheral circuitry, the better for cost reduction.

[0057] In at least one embodiment of this application, the semiconductor structure 10000 includes a semiconductor-on-insulator (SBI) structure 10, which includes an insulating layer 104, a first semiconductor layer 1021, and a second semiconductor layer 1022. The first semiconductor layer 1021 is used to form a first transistor, and the second semiconductor layer 1022 is used to form a second transistor. The operating voltage of the first transistor is greater than that of the second transistor. The dimension of the first semiconductor layer 1021 in the first direction Z is greater than that of the second semiconductor layer 1022 in the first direction Z. The relatively large dimension of the first semiconductor layer 1021 in the first direction Z results in a larger depletion region volume for the first transistor during operation, enabling the first transistor to withstand higher voltages. The relatively small dimension of the second semiconductor layer 1022 in the first direction Z results in a smaller depletion region volume for the second transistor during operation compared to that of the first transistor, enabling the second transistor to withstand lower voltages. Furthermore, the first transistor exhibits a high degree of channel depletion during operation; for example, the channel of the first transistor is fully depleted, eliminating the substrate bias effect of the first transistor. The second transistor has a high degree of channel depletion during operation; for example, the channel of the second transistor is fully depleted, thus eliminating the substrate bias effect of the second transistor.

[0058] Since the semiconductor structure 10000 of the present application embodiment does not need to provide lead-out areas in the first semiconductor layer 1021 and the second semiconductor layer 1022, the layout area of ​​the semiconductor structure 10000 can be reduced and the integration density of the semiconductor structure 10000 can be improved.

[0059] In some embodiments, the material of the first semiconductor layer 1021 is, for example, silicon, germanium, a group II-V compound semiconductor material, or a group II-VI compound semiconductor material. The material of the second semiconductor layer 1022 is, for example, silicon, germanium, a group II-V compound semiconductor material, or a group II-VI compound semiconductor material.

[0060] In some embodiments, the material of the insulating layer 104 includes an insulating dielectric material, such as silicon oxide.

[0061] In some embodiments, the second semiconductor layer 1022 is located on at least one side of the first semiconductor layer 1021 along the second direction X. In other embodiments, the second semiconductor layer is located on at least one side of the first semiconductor layer along a third direction. In other embodiments, a portion of the second semiconductor layers are located on at least one side of the first semiconductor layer along the second direction, and another portion of the second semiconductor layers are located on at least one side of the first semiconductor layer along a third direction.

[0062] In some implementations, the first direction Z intersects the second direction X and the third direction pairwise. For example, the first direction Z is perpendicular to the second direction X, the first direction Z is perpendicular to the third direction, and the second direction X is perpendicular to the third direction.

[0063] In some embodiments, in the first direction Z, the size of the first semiconductor layer 1021 is 1.5 to 3 times the size of the second semiconductor layer 1022, for example, 1.5, 2, 2.5, or 3 times. The size of the first semiconductor layer 1021 in the first direction Z is greater than or equal to 1.5 times the size of the second semiconductor layer 1022 in the first direction Z, ensuring that the size of the second semiconductor layer 1022 in the first direction Z is not excessively large, thus allowing the size of the second semiconductor layer 1022 in the first direction Z to better match the operating voltage of the second transistor. Alternatively, the size of the first semiconductor layer 1021 in the first direction Z is less than or equal to 3 times the size of the second semiconductor layer 1022 in the first direction Z, ensuring that the size of the first semiconductor layer 1021 in the first direction Z is not excessively large, thus allowing the size of the first semiconductor layer 1021 in the first direction Z to better match the operating voltage of the first transistor.

[0064] In some embodiments, in the first direction Z, the size of the first semiconductor layer 1021 is 280nm to 350nm, and the size of the second semiconductor layer 1022 is 150nm to 200nm.

[0065] In some embodiments, the insulating layer 104 includes a first insulating portion located on the side of the second semiconductor layer 1022 opposite to the first direction Z and a second insulating portion located on the side of the first semiconductor layer 1021 opposite to the first direction Z; wherein, in the first direction Z, the size of the first insulating portion is larger than the size of the second insulating portion.

[0066] In some embodiments, the height of the surface of the first semiconductor layer 1021 facing away from the insulating layer 104 in the first direction Z is the same as the height of the surface of the second semiconductor layer 1022 facing away from the insulating layer 104 in the first direction Z, relative to the side of the insulating layer 104 facing away from the first direction Z. It should be noted that a certain margin of error is permissible. For example, the ratio of the height of the surface of the first semiconductor layer 1021 facing away from the insulating layer 104 in the first direction Z to the height of the surface of the second semiconductor layer 1022 facing away from the insulating layer 104 in the first direction Z is 0.85 to 1.15.

[0067] In some implementations, reference Figure 2 The semiconductor structure 10000 further includes a first isolation structure F1 and a second isolation structure F2. The first isolation structure F1 is located on both sides of the first semiconductor layer 1021 along the second direction X and is connected to the insulating layer 104. The second isolation structure F2 is located on both sides of the second semiconductor layer 1022 along the second direction X and is connected to the insulating layer 104. The first isolation structure F1 penetrates the first semiconductor layer 1021 along the first direction Z, and the second isolation structure F2 penetrates the second semiconductor layer 1022 along the first direction Z.

[0068] In some embodiments, a plurality of first isolation structures F1 are arranged at intervals along a second direction X, and the first isolation structures F1 extend along a third direction Y. A plurality of second isolation structures F2 are arranged at intervals along the second direction X, and the second isolation structures F2 extend along a third direction Y.

[0069] In some implementations, reference Figure 2 The semiconductor structure 10000 further includes a third isolation structure F3 and a fourth isolation structure F4. The third isolation structure F3 is located on both sides of the first semiconductor layer 1021 along a third direction Y and is connected to the insulating layer 104 and the first isolation structure F1. The fourth isolation structure F4 is located on both sides of the second semiconductor layer 1022 along a third direction Y and is connected to the insulating layer 104 and the second isolation structure F2. The third isolation structure F3 penetrates the first semiconductor layer 1021 along a first direction Z, and the fourth isolation structure F4 penetrates the second semiconductor layer 1022 along the first direction Z.

[0070] In some embodiments, a plurality of third isolation structures F3 are arranged at intervals along a third direction Y, and the third isolation structures F3 extend along a second direction X. A plurality of fourth isolation structures F4 are arranged at intervals along a third direction Y, and the fourth isolation structures F4 extend along a second direction X.

[0071] In some embodiments, the material of the first isolation structure F1 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the second isolation structure F2 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the third isolation structure F3 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the fourth isolation structure F4 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0072] In some embodiments, in the second direction X, the size of the first semiconductor layer 1021 between adjacent first isolation structures F1 is larger than the size of the second semiconductor layer 1022 between adjacent second isolation structures F2.

[0073] In some implementations, in the third direction Y, the size of the first semiconductor layer 1021 between adjacent third isolation structures F3 is larger than the size of the second semiconductor layer 1022 between adjacent fourth isolation structures F4.

[0074] Since the first semiconductor layers 1021 adjacent to each other in the second direction X are completely isolated by the first isolation structure F1, the adjacent first semiconductor layers 1021 in the second direction X will not connect together, and the depletion regions in the adjacent first semiconductor layers 1021 in the second direction X will not connect together. Therefore, the size of the first isolation structure F1 in the second direction X can be set to be smaller. Since the second semiconductor layers 1022 adjacent to each other in the second direction X are completely isolated by the second isolation structure F2, the adjacent second semiconductor layers 1022 in the second direction X will not connect together, and the depletion regions in the adjacent second semiconductor layers 1022 in the second direction X will not connect together. Therefore, the size of the second isolation structure F2 in the second direction X can be set to be smaller.

[0075] Because the first semiconductor layer 1021 adjacent to the third semiconductor layer 1021 in the third direction Y is completely isolated by the third isolation structure F3, the first semiconductor layers 1021 adjacent to the third semiconductor layer 1021 in the third direction Y will not be connected together, and the depletion regions in the first semiconductor layers 1021 adjacent to the third semiconductor layer 1021 in the third direction Y will not be connected together. Therefore, the size of the third isolation structure F3 in the third direction Y can be set to be smaller. Because the second semiconductor layer 1022 adjacent to the third semiconductor layer 1022 in the third direction Y is completely isolated by the fourth isolation structure F4, the second semiconductor layers 1022 adjacent to the third semiconductor layer 1022 in the third direction Y will not be connected together, and the depletion regions in the second semiconductor layer 1022 adjacent to the third semiconductor layer 1022 in the third direction Y will not be connected together. Therefore, the size of the fourth isolation structure F4 in the third direction Y can be set to be smaller.

[0076] In some embodiments, the first isolation structure F1 has a size of 70nm to 100nm in the second direction X; the second isolation structure F2 has a size of 70nm to 100nm in the second direction X, for example, 70nm, 80nm, 90nm or 100nm.

[0077] In some implementations, the third isolation structure has a dimension of 70 nm to 100 nm in the third-direction Y. The fourth isolation structure F4 has a dimension of 70 nm to 100 nm in the third-direction Y, for example, 70 nm, 80 nm, 90 nm or 100 nm.

[0078] In some implementations, reference Figure 2 The semiconductor structure 10000 also includes a first gate structure 201 and a second gate structure 206. The first gate structure 201 is located on the side of the first semiconductor layer 1021 away from the insulating layer 104, and the second gate structure 206 is located on the side of the second semiconductor layer 1022 away from the insulating layer 104.

[0079] The first gate structure 201 corresponds to the first transistor, and the second gate structure 206 corresponds to the second transistor.

[0080] In some implementations, reference Figure 2 The first gate structure 201 includes a first gate dielectric layer 202 and a first gate electrode layer 203. The first gate dielectric layer 203 is located on the side of the first semiconductor layer 1021 away from the insulating layer 104, and the first gate electrode layer 203 is located on the side of the first gate dielectric layer 203 away from the first semiconductor layer 1021.

[0081] In some implementations, reference Figure 2 The second gate structure 206 includes a second gate dielectric layer 204 and a second gate electrode layer 205. The second gate dielectric layer 204 is located on the side of the second semiconductor layer 1022 opposite to the insulating layer 104, and the second gate electrode layer 205 is located on the side of the second gate dielectric layer 204 opposite to the second semiconductor layer 1022. Along the first direction Z, the size of the first gate dielectric layer 203 is larger than the size of the second gate dielectric layer 205. The larger size of the first gate dielectric layer 203 along the first direction Z is beneficial for improving the breakdown voltage of the first transistor.

[0082] In some embodiments, the first gate dielectric layer 202 is made of silicon oxide or a high dielectric constant (k) dielectric material, and the second gate dielectric layer 204 is made of silicon oxide or a high-k dielectric material. For example, k is greater than 3.9.

[0083] In some embodiments, the first gate electrode layer 203 includes any one of a metal gate material and a polycrystalline silicon gate material. The material of the first gate electrode layer 203 may be, for example, any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride, doped crystalline silicon, or silicides. For example, the material of the first gate electrode layer 203 may be a combination of tungsten and titanium nitride.

[0084] In some embodiments, the second gate electrode layer 205 comprises any one of a metal gate material and a polycrystalline silicon gate material. The material of the second gate electrode layer 205 may be, for example, any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride, doped crystalline silicon, or silicides. For example, the material of the second gate electrode layer 205 may be a combination of tungsten and titanium nitride.

[0085] In some implementations, reference Figure 2 The semiconductor structure 10000 also includes a first source region 2071 and a first drain region 2072. The first source region 2071 is located in the first semiconductor layer 1021 on one side of the first gate structure 201, and the first drain region 2072 is located in the first semiconductor layer 1021 on the other side of the first gate structure 201.

[0086] In some implementations, reference Figure 2 The semiconductor structure 10000 also includes a second source region 2081 and a second drain region 2082. The second source region 2081 is located in the second semiconductor layer 1022 on one side of the second gate structure 206, and the second drain region 2082 is located in the second semiconductor layer 1022 on the other side of the second gate structure 206.

[0087] In some implementations, reference Figure 2 The semiconductor-on-insulator structure 10 further includes a third semiconductor layer 100, which is located on the side of the insulating layer 104 opposite to the first semiconductor layer 1021 and the second semiconductor layer 1022. In some embodiments, the material of the third semiconductor layer 100 is, for example, silicon, germanium, a group II-V compound semiconductor material, or a group II-VI compound semiconductor material.

[0088] Another embodiment of this application also provides a semiconductor structure, see reference. Figure 3The semiconductor structure 10000 includes a semiconductor-on-insulator structure 10, which includes an insulating layer 104, a first semiconductor layer 1021, and a second semiconductor layer 1022. The first semiconductor layer 1021 is located on one side of the insulating layer 104 along a first direction Z; the second semiconductor layer 1022 is located on one side of the insulating layer 104 along the first direction Z, and on at least one side of the first semiconductor layer 1021 along a direction intersecting the first direction Z; wherein, in the first direction Z, the size of the first semiconductor layer 1021 is larger than the size of the second semiconductor layer 1022.

[0089] The materials of the first semiconductor layer 1021, the second semiconductor layer 1022, and the insulating layer 104 are as described in the foregoing embodiments. The relative positional relationship between the second semiconductor layer 1022 and the first semiconductor layer 1021 is as described in the foregoing embodiments. The relationship between the dimensions of the first semiconductor layer 1021 and the second semiconductor layer 1022 in the first direction Z is as described in the foregoing embodiments. The semiconductor structure, including the dimensions of the first semiconductor layer 1021 and the second semiconductor layer 1022 in the first direction Z, is as described in the foregoing embodiments.

[0090] In some implementations, reference Figure 3 The semiconductor structure 10000 further includes a first isolation structure F1, a second isolation structure F2, a third isolation structure F3, and a fourth isolation structure F4. The positions and materials of the first isolation structure F1, the second isolation structure F2, the third isolation structure F3, and the fourth isolation structure F4 are as described in the foregoing embodiments.

[0091] In some embodiments, in the second direction X, the size of the first semiconductor layer 1021 between adjacent first isolation structures F1 is larger than the size of the second semiconductor layer 1022 between adjacent second isolation structures F2.

[0092] In some implementations, in the third direction Y, the size of the first semiconductor layer 1021 between adjacent third isolation structures F3 is larger than the size of the second semiconductor layer 1022 between adjacent fourth isolation structures F4.

[0093] In some embodiments, the first isolation structure F1 has a size of 70 nm to 100 nm in the second direction X; the second isolation structure F2 has a size of 70 nm to 100 nm in the second direction X.

[0094] In some embodiments, the third isolation structure F3 has a dimension of 70 nm to 100 nm in the third-direction Y. The fourth isolation structure F4 has a dimension of 70 nm to 100 nm in the third-direction Y.

[0095] In some implementations, reference Figure 3 The semiconductor structure 10000 also includes a first gate structure 201 and a second gate structure 206. The structures of the first gate structure 201 and the second gate structure 206 are as described in the foregoing embodiments.

[0096] In some implementations, reference Figure 3 The semiconductor structure 10000 further includes a first source region 2071, a first drain region 2072, a second source region 2081, and a second drain region 2082. The positions of the first source region 2071, the first drain region 2072, the second source region 2081, and the second drain region 2082 are as described in the foregoing embodiments.

[0097] In some implementations, reference Figure 3 The semiconductor-on-insulator structure 10 further includes a third semiconductor layer 100. The location and material of the third semiconductor layer 100 are as described in the foregoing embodiments.

[0098] The difference between the semiconductor structure 10000 in this embodiment and the semiconductor structure 10000 in the previous embodiment is that, relative to the side surface of the insulating layer 104 in the direction opposite to the first direction Z, the height of the surface of the second semiconductor layer 1022 facing away from the insulating layer 104 in the first direction Z is less than the height of the surface of the first semiconductor layer 1021 facing away from the insulating layer 104 in the first direction Z.

[0099] In one implementation, reference Figure 3 In the first direction Z, the size of the portion of the insulating layer 104 located on the side of the first semiconductor layer 1021 is equal to the size of the portion of the insulating layer 104 located on the side of the second semiconductor layer 1022.

[0100] Another embodiment of this application also provides a semiconductor structure, see reference. Figure 4 The semiconductor structure 10000 includes a semiconductor-on-insulator (SBI) structure 10, which includes an insulating layer 104, a first semiconductor layer 1021, and a second semiconductor layer 1022. The first semiconductor layer 1021 is located on one side of the insulating layer 104 along a first direction Z. The second semiconductor layer 1022 is located on one side of the insulating layer 104 along the first direction Z and on at least one side of the first semiconductor layer 1021 along a direction intersecting the first direction Z. In the second direction X, the size of the first semiconductor layer 1021 is significantly larger than the size of the second semiconductor layer 1022.

[0101] In this embodiment, the semiconductor structure 10000 increases the size of the first semiconductor layer 1021 in the second direction X, so that the first semiconductor layer 1021 has a larger depletion region, thereby enabling the first transistor to withstand a higher voltage.

[0102] The second direction X intersects the first direction Z. For example, the second direction X is perpendicular to the first direction Z.

[0103] The materials of the first semiconductor layer 1021, the second semiconductor layer 1022, and the insulating layer 104 are as described in the foregoing embodiments. The relative positional relationship between the second semiconductor layer 1022 and the first semiconductor layer 1021 is as described in the foregoing embodiments.

[0104] In one implementation, reference Figure 4 The semiconductor structure 10000 further includes a first isolation structure F1, a second isolation structure F2, a third isolation structure F3, and a fourth isolation structure F4. The positions and materials of the first isolation structure F1, the second isolation structure F2, the third isolation structure F3, and the fourth isolation structure F4 are as described in the foregoing embodiments.

[0105] The dimensions of the first isolation structure F1 in the second direction X, the second isolation structure F2 in the second direction X, the third isolation structure F3 in the third direction Y, and the fourth isolation structure F4 in the third direction Y are as described in the foregoing embodiments.

[0106] In one implementation, reference Figure 4 The semiconductor structure 10000 also includes a first gate structure 201 and a second gate structure 206. The structures of the first gate structure 201 and the second gate structure 206 are as described in the foregoing embodiments.

[0107] In some implementations, reference Figure 4 The semiconductor structure 10000 further includes a first source region 2071, a first drain region 2072, a second source region 2081, and a second drain region 2082. The positions of the first source region 2071, the first drain region 2072, the second source region 2081, and the second drain region 2082 are as described in the foregoing embodiments.

[0108] In some implementations, reference Figure 4 The semiconductor-on-insulator structure 10 further includes a third semiconductor layer 100. The location and material of the third semiconductor layer 100 are as described in the foregoing embodiments.

[0109] In one embodiment, in the second direction X, the size of the first semiconductor layer 1021 between adjacent first isolation structures F1 is much larger than the size of the second semiconductor layer 1022 between adjacent second isolation structures F2, meaning that in the second direction X, the size of the first semiconductor layer 1021 between adjacent first isolation structures F1 is greater than or equal to 10 times the size of the second semiconductor layer 1022 between adjacent second isolation structures F2, for example, 10 times, 12 times or 15 times.

[0110] In one embodiment, in the first direction Z, the size of the first semiconductor layer 1021 is equal to the size of the second semiconductor layer 1022.

[0111] In one embodiment, in the third direction Y, the size of the first semiconductor layer 1021 between adjacent third isolation structures F3 is larger than the size of the second semiconductor layer 1022 between adjacent fourth isolation structures F4.

[0112] One embodiment of this application provides a method for fabricating a semiconductor structure, the semiconductor structure including a semiconductor-on-insulator structure, as shown in the reference. Figure 5 The preparation methods include:

[0113] Step S1: Form an insulating layer and an initial semiconductor layer, wherein the initial semiconductor layer is located on one side of the insulating layer in a first direction;

[0114] Step S2: Etch the initial semiconductor layer to form a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is located on at least one side of the first semiconductor layer along a direction intersecting with a first direction, and in the first direction, the size of the first semiconductor layer is larger than the size of the second semiconductor layer.

[0115] The following is for reference. Figures 6 to 14 This article details a process for fabricating semiconductor structures.

[0116] refer to Figures 6 to 9 The formation of the insulating layer 104 and the initial semiconductor layer 102a includes: forming a third semiconductor layer 100, an insulating layer 104 and an initial semiconductor layer 102a stacked along a first direction Z, wherein the insulating layer 104 is located between the third semiconductor layer 100 and the initial semiconductor layer 102a, and the initial semiconductor layer 102a includes a first portion A and a second portion B, wherein the second portion B is located on at least one side of the first portion A along a direction intersecting the first direction Z.

[0117] refer to Figures 6 to 9 The method comprises forming a third semiconductor layer 100, an insulating layer 104, and an initial semiconductor layer 102a stacked along a first direction Z, including: forming a third semiconductor layer 100, a first insulating layer 101, and a semiconductor material layer 102 stacked along the first direction Z; and forming a second insulating layer 103 connected to a portion of the first insulating layer 101 in a portion region of the semiconductor material layer 102, wherein the size of the second insulating layer 103 along the first direction Z is smaller than the size of the semiconductor material layer 102 along the first direction Z, wherein the remaining semiconductor material layer 102 forms the initial semiconductor layer 102a; wherein the first insulating layer 101 and the second insulating layer 103 constitute the insulating layer 104.

[0118] refer to Figure 6A third semiconductor layer 100, a first insulating layer 101, and a semiconductor material layer 102 are formed by stacking along the first direction Z.

[0119] In some embodiments, forming a third semiconductor layer 100, a first insulating layer 101, and a semiconductor material layer 102 stacked along the first direction Z includes: forming the first insulating layer 101 in a semiconductor substrate using an ion implantation process; forming the semiconductor material layer 102 in a portion of the semiconductor substrate located on one side of the first insulating layer 101 along the first direction Z; and forming the third semiconductor layer 100 in a portion of the semiconductor substrate located on the other side of the first insulating layer 101 along the first direction Z.

[0120] In some embodiments, the material of the third semiconductor layer 100 is, for example, silicon, germanium, a group II-V compound semiconductor material, or a group II-VI compound semiconductor material. The material of the semiconductor material layer 102 is, for example, silicon, germanium, a group II-V compound semiconductor material, or a group II-VI compound semiconductor material.

[0121] In some embodiments, the material of the first insulating layer 101 includes an insulating dielectric material, such as silicon oxide.

[0122] refer to Figures 7 to 8 In semiconductor material layer 102 (reference) Figure 6 A second insulating layer 103 is formed in a portion of the region of the first insulating layer 101 (see reference). Figure 8 The second insulating layer 103 has a dimension along the first direction Z smaller than the dimension of the semiconductor material layer 102 along the first direction Z, wherein the remaining semiconductor material layer 102 forms the initial semiconductor layer 102a; wherein the first insulating layer 101 and the second insulating layer 103 constitute the insulating layer 104 (see reference). Figure 9 ).

[0123] refer to Figure 7 A second insulating layer 103 connected to a portion of the first insulating layer 101 is formed in a portion of the semiconductor material layer 102, including: forming an ion-doped region 103a in a portion of the semiconductor material layer 102.

[0124] In some embodiments, the process for forming the ion-doped region 103a includes an ion implantation process.

[0125] In some embodiments, the ions implanted in the ion-doped region 103a include oxygen ions. In other embodiments, the ions implanted in the ion-doped region 103a may also include other ions.

[0126] refer to Figure 8The method further includes forming a second insulating layer 103 connected to a portion of the first insulating layer 101 in a certain region of the semiconductor material layer 102, and annealing the ion-doped region 103a, wherein the ion-doped region 103a forms the second insulating layer 103.

[0127] In some embodiments, the semiconductor material layer 102 is made of silicon, the ions implanted in the ion-doped region 103a are oxygen ions, and correspondingly, the second insulating layer 103 is made of silicon oxide.

[0128] It should be noted that the material of the semiconductor material layer 102 is not limited to the materials described above, and the material of the second insulating layer 103 is not limited to the materials described above.

[0129] refer to Figure 9 The third semiconductor layer 100, the insulating layer 104 and the initial semiconductor layer 102a are stacked along the first direction Z. The insulating layer 104 is located between the third semiconductor layer 100 and the initial semiconductor layer 102a. The initial semiconductor layer 102a includes a first part A and a second part B. The second part B is located on at least one side of the first part A along the direction intersecting the first direction Z.

[0130] For example, the second portion B is located on at least one side of the first portion A along the second direction X. In other embodiments, the second portion is located on at least one side of the first portion along a third direction. In other embodiments, a portion of the second portions are located on at least one side of the first portion along the second direction X, and another portion of the second portions are located on at least one side of the first portion along a third direction.

[0131] In some implementations, the first direction Z intersects the second direction X and the third direction pairwise. For example, the first direction Z is perpendicular to the second direction X, the first direction Z is perpendicular to the third direction, and the second direction X is perpendicular to the third direction.

[0132] refer to Figure 9 In the first direction Z, the size of the second part B is smaller than the size of the first part A, and the size of the portion of the insulating layer 104 located on the side of the second part B opposite to the first direction Z is larger than the size of the portion of the insulating layer 104 located on the side of the first part A opposite to the first direction Z.

[0133] refer to Figure 10 and Figure 11 , Figure 10 In order to be in Figure 9 A basic diagram. Figure 11 for Figure 10The top view shows that etching the initial semiconductor layer 102a to form the first semiconductor layer 1021 and the second semiconductor layer 1022 includes: etching a first portion A to form a plurality of first isolation trenches G1 spaced along a second direction X, wherein the portion of the first portion A located between adjacent first isolation trenches G1 forms the first semiconductor layer 1021; and etching a second portion B to form a plurality of second isolation trenches G2 spaced along a second direction X, wherein the portion of the second portion B located between adjacent second isolation trenches G2 forms the second semiconductor layer 1022.

[0134] The first isolation groove G1 extends along the third direction Y, and the second isolation groove G2 extends along the third direction Y.

[0135] In some embodiments, the process of etching the initial semiconductor layer 102a to form the first semiconductor layer 1021 and the second semiconductor layer 1022 includes one or a combination of wet etching and dry etching processes.

[0136] In some embodiments, etching the first portion A further forms a plurality of third isolation trenches G3 spaced along a third direction Y, the third isolation trenches G3 being connected to the first isolation trench G1; etching the second portion B further forms a plurality of fourth isolation trenches G4 spaced along a third direction Y, the fourth isolation trenches G4 being connected to the second isolation trench G2. The portion of the first portion A located between adjacent first isolation trenches G1 and adjacent third isolation trenches G3 forms a first semiconductor layer 1021, and the portion of the second portion B located between adjacent second isolation trenches G2 and adjacent fourth isolation trenches G4 forms a second semiconductor layer 1022.

[0137] The third isolation groove G3 extends along the second direction X, and the fourth isolation groove G4 extends along the second direction X.

[0138] refer to Figure 12 and Figure 13 , Figure 12 In order to be in Figure 10 A basic diagram. Figure 13 In order to be in Figure 11 A basic diagram. Figure 13 for Figure 12 The top view shows that a first isolation structure F1 is formed in the first isolation groove G1; and a second isolation structure F2 is formed in the second isolation groove G2.

[0139] In some embodiments, the process for forming the first isolation structure F1 in the first isolation tank G1 is a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The process for forming the second isolation structure F2 in the second isolation tank G2 is also a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0140] In some embodiments, a plurality of first isolation structures F1 are arranged at intervals along a second direction X, and the first isolation structures F1 extend along a third direction Y. A plurality of second isolation structures F2 are arranged at intervals along the second direction X, and the second isolation structures F2 extend along a third direction Y.

[0141] In some implementations, reference Figure 13 The method for fabricating the semiconductor structure further includes: forming a third isolation structure F3 in a third isolation trench G3; and forming a fourth isolation structure F4 in a fourth isolation trench G4. The third isolation structure F3 is connected to the first isolation structure F1, and the fourth isolation structure F4 is connected to the second isolation structure F2.

[0142] In some embodiments, the process for forming the third isolation structure F3 in the third isolation tank G3 is a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof thin film deposition process. The process for forming the fourth isolation structure F4 in the fourth isolation tank G4 is a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof thin film deposition process.

[0143] In some embodiments, a plurality of third isolation structures F3 are arranged at intervals along a third direction Y, and the third isolation structures F3 extend along a second direction X. A plurality of fourth isolation structures F4 are arranged at intervals along a third direction Y, and the fourth isolation structures F4 extend along a second direction X.

[0144] In some embodiments, the third isolation structure F3 is formed during the formation of the first isolation structure F1, and the fourth isolation structure F4 is formed during the formation of the second isolation structure F2, simplifying the process. In other embodiments, the first isolation structure F1, the second isolation structure F2, the third isolation structure F3, and the fourth isolation structure F4 can be formed independently in different processes.

[0145] In some embodiments, the material of the first isolation structure F1 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the second isolation structure F2 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the third isolation structure F3 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the fourth isolation structure F4 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0146] In some embodiments, in the second direction X, the size of the first semiconductor layer 1021 between adjacent first isolation structures F1 is larger than the size of the second semiconductor layer 1022 between adjacent second isolation structures F2.

[0147] In some implementations, in the third direction Y, the size of the first semiconductor layer 1021 between adjacent third isolation structures F3 is larger than the size of the second semiconductor layer 1022 between adjacent fourth isolation structures F4.

[0148] In some embodiments, the first isolation structure F1 is in contact with the insulating layer 104, the second isolation structure F2 is in contact with the insulating layer 104, the third isolation structure F3 is in contact with the insulating layer 104, and the fourth isolation structure F4 is in contact with the insulating layer 104.

[0149] refer to Figure 14 , Figure 14 In order to be in Figure 12 Based on the schematic diagram, a first gate structure 201 is formed, which is located on the side of the first semiconductor layer 1021 away from the insulating layer 104; a second gate structure 206 is formed, which is located on the side of the second semiconductor layer 1022 away from the insulating layer 104.

[0150] In some implementations, reference Figure 14 The formation of the first gate structure 201 includes: forming a first gate dielectric layer 202 on the side of the first semiconductor layer 1021 away from the insulating layer 104; and forming a first gate electrode layer 203 on the side of the first gate dielectric layer 202 away from the first semiconductor layer 1021.

[0151] In some implementations, reference Figure 14 The formation of the second gate structure 206 includes: forming a second gate dielectric layer 204 on the side of the second semiconductor layer 1022 away from the insulating layer 104; and forming a second gate electrode layer 205 on the side of the second gate dielectric layer 204 away from the second semiconductor layer 1022.

[0152] In some embodiments, the second gate structure 206 is formed during the formation of the first gate structure 201. Correspondingly, the second gate dielectric layer 204 is formed during the formation of the first gate dielectric layer 202, and the second gate electrode layer 205 is formed during the formation of the first gate electrode layer 203, simplifying the process. In other embodiments, the second gate structure 206 is formed after the formation of the first gate structure 201, or the first gate structure 201 is formed after the formation of the second gate structure 206.

[0153] The first gate structure 201 corresponds to the first transistor, and the second gate structure 206 corresponds to the second transistor.

[0154] In this configuration, the size of the first gate dielectric layer 203 is larger than the size of the second gate dielectric layer 205 along the first direction Z. The larger size of the first gate dielectric layer 203 along the first direction Z is beneficial for improving the breakdown voltage of the first transistor.

[0155] In some embodiments, the first gate dielectric layer 202 is made of silicon oxide or a high dielectric constant (k) dielectric material, and the second gate dielectric layer 204 is made of silicon oxide or a high-k dielectric material. For example, k is greater than 3.9.

[0156] In some embodiments, the first gate electrode layer 203 includes any one of a metal gate material and a polycrystalline silicon gate material. The material of the first gate electrode layer 203 may be, for example, any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride, doped crystalline silicon, or silicides. For example, the material of the first gate electrode layer 203 may be a combination of tungsten and titanium nitride.

[0157] In some embodiments, the second gate electrode layer 205 comprises any one of a metal gate material and a polycrystalline silicon gate material. The material of the second gate electrode layer 205 may be, for example, any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride, doped crystalline silicon, or silicides. For example, the material of the second gate electrode layer 205 may be a combination of tungsten and titanium nitride.

[0158] In some implementations, reference Figure 14 The method for fabricating the semiconductor structure further includes: forming a first source region 2071 in a first semiconductor layer 1021 on one side of the first gate structure 201, and forming a first drain region 2072 in a first semiconductor layer 1021 on the other side of the first gate structure 201; forming a second source region 2081 in a second semiconductor layer 1022 on one side of the second gate structure 206, and forming a second drain region 2082 in a second semiconductor layer 1022 on the other side of the second gate structure 206.

[0159] The first transistor includes a first gate structure 201, a first source region 2071, and a first drain region 2072. The second transistor includes a second gate structure 206, a second source region 2081, and a second drain region 2082.

[0160] In some embodiments, the process of forming the first source region 2071 and the first drain region 2072 includes an ion implantation process. The process of forming the second source region 2081 and the second drain region 2082 includes an ion implantation process.

[0161] In some embodiments, the first source region 2071 and the first drain region 2072 are located on opposite sides of the first gate structure 201 along the second direction X. In other embodiments, the first source region and the first drain region are located on opposite sides of the first gate structure 201 along the third direction Y. In other embodiments, the first source region 2071 and the first drain region 2072 in a portion of the first transistors are located on opposite sides of the first gate structure 201 along the second direction X, while the first source region and the first drain region in another portion of the first transistors are located on opposite sides of the first gate structure 201 along the third direction Y.

[0162] In some embodiments, the second source region 2081 and the second drain region 2082 are located on opposite sides of the second gate structure 206 along the second direction X. In other embodiments, the second source region and the second drain region are located on opposite sides of the second gate structure along a third direction. In other embodiments, the second source region and the second drain region in a portion of the second transistors are located on opposite sides of the second gate structure along the second direction, while the second source region and the second drain region in another portion of the second transistors are located on opposite sides of the second gate structure along a third direction.

[0163] In some implementations, the operating voltage of the first transistor is higher than that of the second transistor, and the breakdown voltage of the first transistor is greater than that of the second transistor.

[0164] Figures 15 to 26 This is a structural diagram illustrating the fabrication process of a semiconductor structure according to another embodiment of this application.

[0165] refer to Figure 15 An insulating layer 104 and an initial semiconductor layer 102a are formed, wherein the initial semiconductor layer 102a is located on one side of the insulating layer 104 in the first direction Z.

[0166] In some embodiments, forming an insulating layer 104 and an initial semiconductor layer 102a includes forming a third semiconductor layer 100, an insulating layer 104, and an initial semiconductor layer 102a stacked along a first direction Z, wherein the insulating layer 104 is located between the third semiconductor layer 100 and the initial semiconductor layer 102a, and the initial semiconductor layer 102a includes a first portion A and a second portion B, wherein the second portion B is located on at least one side of the first portion A along a direction intersecting the first direction Z.

[0167] For example, the second portion B is located on at least one side of the first portion A along the second direction X. In other embodiments, the second portion is located on at least one side of the first portion along a third direction. In other embodiments, a portion of the second portions are located on at least one side of the first portion along the second direction X, and another portion of the second portions are located on at least one side of the first portion along a third direction.

[0168] In some implementations, the first direction Z intersects the second direction X and the third direction pairwise. For example, the first direction Z is perpendicular to the second direction X, the first direction Z is perpendicular to the third direction, and the second direction X is perpendicular to the third direction.

[0169] In some embodiments, forming a third semiconductor layer 100, an insulating layer 104, and an initial semiconductor layer 102a stacked along a first direction Z includes: forming an insulating layer 104 in a semiconductor substrate using an ion implantation process; forming an initial semiconductor layer 102a on a portion of the semiconductor substrate located on one side of the insulating layer 104 along the first direction Z; and forming a third semiconductor layer 100 on a portion of the semiconductor substrate located on the other side of the insulating layer 104 along the first direction Z.

[0170] In some embodiments, the material of the third semiconductor layer 100 is, for example, silicon, germanium, a group II-V compound semiconductor material, or a group II-VI compound semiconductor material. The material of the initial semiconductor layer 102a is, for example, silicon, germanium, a group II-V compound semiconductor material, or a group II-VI compound semiconductor material. The material of the insulating layer 104 includes an insulating dielectric material, such as silicon oxide.

[0171] refer to Figures 16 to 23 The initial semiconductor layer 102a is etched to form a first semiconductor layer 1021 and a second semiconductor layer 1022, wherein the second semiconductor layer 1022 is located on at least one side of the first semiconductor layer 1021 along a direction intersecting with a first direction Z, and in the first direction Z, the size of the first semiconductor layer 1021 is larger than the size of the second semiconductor layer 1022.

[0172] refer to Figure 16 and Figure 17 , Figure 16 In order to be in Figure 15 A basic diagram. Figure 17 for Figure 16 A top view shows that the first portion A is etched to form a plurality of first isolation trenches G1 spaced along the second direction X, wherein the portion of the first portion A located between adjacent first isolation trenches G1 forms a first semiconductor layer 1021.

[0173] The etching process for Part A includes one or a combination of wet etching and dry etching processes.

[0174] The first isolation groove G1 extends along the third direction Y.

[0175] In some implementations, reference Figure 17 The first portion A is etched, and multiple third isolation trenches G3 spaced along a third direction Y are formed. The third isolation trenches G3 are connected to the first isolation trenches G1. The third isolation trenches G3 extend along a second direction X. The portion of the first portion A located between adjacent first isolation trenches G1 and adjacent third isolation trenches G3 forms a first semiconductor layer 1021.

[0176] In some implementations, reference Figure 16 The method for fabricating the semiconductor structure further includes: forming a first mask layer 300, the first mask layer 300 being located on the side of the second portion B opposite to the insulating layer 104, the first mask layer 300 exposing the first portion A. Etching the first portion A includes: etching the first portion A using the first mask layer 300 as a mask. The material of the first mask layer 300 includes photoresist.

[0177] It should be noted that, for ease of illustration, Figure 17 The first mask layer 300 is omitted.

[0178] refer to Figure 18 and Figure 19 , Figure 18 In order to be in Figure 16 A basic diagram. Figure 19 In order to be in Figure 17 A basic diagram. Figure 19 for Figure 18 The top view shows that a first isolation structure F1 is formed in the first isolation groove G1; a third isolation structure F3 is formed in the third isolation groove G3, and the third isolation structure F3 is connected to the first isolation structure F1.

[0179] In some embodiments, the process for forming the first isolation structure F1 in the first isolation tank G1 is a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The process for forming the third isolation structure F3 in the third isolation tank G3 is a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0180] In some embodiments, a plurality of first isolation structures F1 are arranged at intervals along a second direction X, and the first isolation structures F1 extend along a third direction Y. A plurality of third isolation structures F3 are arranged at intervals along a third direction Y, and the third isolation structures F3 extend along the second direction X.

[0181] In some embodiments, the third isolation structure F3 is formed during the formation of the first isolation structure F1, simplifying the process. In other embodiments, the first isolation structure F1 and the third isolation structure F3 can be formed independently in different processes.

[0182] The materials of the first isolation structure F1 and the third isolation structure F3 are as described in the foregoing embodiments.

[0183] In some embodiments, the first isolation structure F1 is in contact with the insulating layer 104, and the third isolation structure F3 is in contact with the insulating layer 104.

[0184] refer to Figure 20 , Figure 20 In order to be in Figure 18 Based on the schematic diagram, the first mask layer 300 is removed; a second mask layer 400 is formed. The second mask layer 400 is located on the side of the first semiconductor layer 1021 and the first isolation structure F1 away from the insulating layer 104, and the second mask layer 400 exposes the second portion B.

[0185] The material of the second mask layer 400 includes photoresist.

[0186] refer to Figure 21 The second part B is thinned from the side opposite to the insulating layer 104, and the dimension of the second part B in the first direction Z is smaller than the dimension of the first part A in the first direction Z.

[0187] For example, using the second mask layer 400 as a mask, the second portion B is thinned from the side of the second portion B opposite to the insulating layer 104.

[0188] In some embodiments, the process of thinning the second portion B from the side opposite to the insulating layer 104 includes an etching process.

[0189] refer to Figure 22 and Figure 23 , Figure 22 In order to be in Figure 21 A basic diagram. Figure 23 for Figure 22 A top view shows that the second portion B is etched to form a plurality of second isolation trenches G2 spaced apart along the second direction X. The portion of the second portion B located between adjacent second isolation trenches G2 forms a second semiconductor layer 1022. The second isolation trenches G2 extend along the third direction Y.

[0190] It should be noted that, for ease of illustration, Figure 23 The second mask layer 400 is omitted.

[0191] In some embodiments, after the second portion B is thinned from the side opposite to the insulating layer 104, the second portion B is etched to form a plurality of second isolation trenches G2 spaced along the second direction X.

[0192] In some embodiments, the etching process for the second part B includes one or a combination of wet etching and dry etching processes.

[0193] In some implementations, reference Figure 23 The second portion B is etched, and a plurality of fourth isolation trenches G4 spaced apart along the third direction Y are formed. The fourth isolation trenches G4 are connected to the second isolation trenches G2. The portion of the second portion B located between adjacent second isolation trenches G2 and adjacent fourth isolation trenches G4 forms a second semiconductor layer 1022. The fourth isolation trenches G4 extend along the second direction X.

[0194] In some embodiments, in the second direction X, the size of the first semiconductor layer 1021 between adjacent first isolation structures F1 is larger than the size of the second semiconductor layer 1022 between adjacent second isolation structures F2.

[0195] In some implementations, in the third direction Y, the size of the first semiconductor layer 1021 between adjacent third isolation structures F3 is larger than the size of the second semiconductor layer 1022 between adjacent fourth isolation structures F4.

[0196] refer to Figure 24 and Figure 25 , Figure 24 In order to be in Figure 22 A basic diagram. Figure 25 In order to be in Figure 23 A basic diagram. Figure 25 for Figure 24 The top view shows that a second isolation structure F2 is formed in the second isolation groove G2; a fourth isolation structure F4 is formed in the fourth isolation groove G4, and the fourth isolation structure F4 is connected to the second isolation structure F2.

[0197] In some embodiments, the process for forming the second isolation structure F2 in the second isolation tank G2 is a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The process for forming the fourth isolation structure F4 in the fourth isolation tank G4 is a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0198] In some embodiments, the fourth isolation structure F4 is formed during the formation of the second isolation structure F2, simplifying the process. In other embodiments, the second isolation structure F2 and the fourth isolation structure F4 can be formed independently in different processes.

[0199] In some embodiments, a plurality of second isolation structures F2 are arranged at intervals along a second direction X, and the second isolation structures F2 extend along a third direction Y. A plurality of fourth isolation structures F4 are arranged at intervals along a third direction Y, and the fourth isolation structures F4 extend along the second direction X.

[0200] In some embodiments, the second isolation structure F2 is in contact with the insulating layer 104, and the fourth isolation structure F4 is in contact with the insulating layer 104.

[0201] The materials for the second isolation structure F2 and the fourth isolation structure F4 are the same as those described in the aforementioned embodiments.

[0202] refer to Figure 26 , Figure 26 In order to be in Figure 24 Based on the schematic diagram, a first gate structure 201 is formed, which is located on the side of the first semiconductor layer 1021 away from the insulating layer 104; a second gate structure 206 is formed, which is located on the side of the second semiconductor layer 1022 away from the insulating layer 104.

[0203] In some implementations, reference Figure 26 The formation of the first gate structure 201 includes: forming a first gate dielectric layer 202 on the side of the first semiconductor layer 1021 away from the insulating layer 104; and forming a first gate electrode layer 203 on the side of the first gate dielectric layer 202 away from the first semiconductor layer 1021.

[0204] In some implementations, reference Figure 26 The formation of the second gate structure 206 includes: forming a second gate dielectric layer 204 on the side of the second semiconductor layer 1022 away from the insulating layer 104; and forming a second gate electrode layer 205 on the side of the second gate dielectric layer 204 away from the second semiconductor layer 1022.

[0205] In some embodiments, the second gate structure 206 is formed during the formation of the first gate structure 201. Correspondingly, the second gate dielectric layer 204 is formed during the formation of the first gate dielectric layer 202, and the second gate electrode layer 205 is formed during the formation of the first gate electrode layer 203, simplifying the process. In other embodiments, the second gate structure 206 is formed after the formation of the first gate structure 201, or the first gate structure 201 is formed after the formation of the second gate structure 206.

[0206] The first gate structure 201 corresponds to the first transistor, and the second gate structure 206 corresponds to the second transistor.

[0207] In this configuration, the size of the first gate dielectric layer 203 is larger than the size of the second gate dielectric layer 205 along the first direction Z. The larger size of the first gate dielectric layer 203 along the first direction Z is beneficial for improving the breakdown voltage of the first transistor.

[0208] In some embodiments, the materials of the first gate dielectric layer 202, the second gate dielectric layer 204, the first gate electrode layer 203, and the second gate electrode layer 205 are the same as those described in the preceding embodiments.

[0209] In some implementations, reference Figure 26 The method for fabricating the semiconductor structure further includes: forming a first source region 2071 in a first semiconductor layer 1021 on one side of the first gate structure 201, forming a first drain region 2072 in a first semiconductor layer 1021 on one side of the first gate structure 201; forming a second source region 2081 in a second semiconductor layer 1022 on one side of the second gate structure 206, and forming a second drain region 2082 in a second semiconductor layer 1022 on the other side of the second gate structure 206.

[0210] The first transistor includes a first gate structure 201, a first source region 2071, and a first drain region 2072. The second transistor includes a second gate structure 206, a second source region 2081, and a second drain region 2082.

[0211] In some embodiments, the process of forming the first source region 2071 and the first drain region 2072 includes an ion implantation process. The process of forming the second source region 2081 and the second drain region 2082 includes an ion implantation process.

[0212] In some embodiments, the positions of the first source region 2071 and the first drain region 2072, and the positions of the second source region 2081 and the second drain region 2082 are the same as those described in the previous embodiments.

[0213] In some implementations, the operating voltage of the first transistor is higher than that of the second transistor, and the breakdown voltage of the first transistor is greater than that of the second transistor.

[0214] Another embodiment of this application also provides a method for fabricating a semiconductor structure, comprising: forming an insulating layer and an initial semiconductor layer, the initial semiconductor layer being located on one side of the insulating layer in a first direction; etching the initial semiconductor layer to form a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is located on at least one side of the first semiconductor layer along a direction intersecting the first direction, and in a second direction, the size of the first semiconductor layer is much larger than the size of the second semiconductor layer; wherein the second direction intersects the first direction.

[0215] Figures 27 to 32 This is a structural diagram illustrating the fabrication process of a semiconductor structure according to another embodiment of this application.

[0216] refer to Figure 27 An insulating layer 104 and an initial semiconductor layer 102a are formed, wherein the initial semiconductor layer 102a is located on one side of the insulating layer 104 in the first direction Z.

[0217] In some embodiments, forming the insulating layer 104 and the initial semiconductor layer 102a includes forming a third semiconductor layer 100, the insulating layer 104 and the initial semiconductor layer 102a stacked along a first direction Z, wherein the insulating layer 104 is located between the third semiconductor layer 100 and the initial semiconductor layer 102a.

[0218] In some embodiments, forming a third semiconductor layer 100, an insulating layer 104, and an initial semiconductor layer 102a stacked along a first direction Z includes: forming an insulating layer 104 in a semiconductor substrate using an ion implantation process; forming an initial semiconductor layer 102a on a portion of the semiconductor substrate located on one side of the insulating layer 104 along the first direction Z; and forming a third semiconductor layer 100 on a portion of the semiconductor substrate located on the other side of the insulating layer 104 along the first direction Z.

[0219] The materials of the third semiconductor layer 100, the initial semiconductor layer 102a, and the insulating layer 104 are as described in the foregoing embodiments.

[0220] refer to Figure 28 and Figure 29 , Figure 28 In order to be in Figure 27 A basic diagram. Figure 29 for Figure 28 The top view shows that etching the initial semiconductor layer 102a to form a first semiconductor layer 1021 and a second semiconductor layer 1022 includes: etching the initial semiconductor layer 102a to form a plurality of first isolation trenches G1 spaced along a second direction X and a plurality of second isolation trenches G2 spaced along a second direction X, wherein the portion of the initial semiconductor layer 102a located between adjacent first isolation trenches G1 forms the first semiconductor layer 1021, and the portion of the initial semiconductor layer 102a located between adjacent second isolation trenches G2 forms the second semiconductor layer 1022.

[0221] In some embodiments, the process of etching the initial semiconductor layer 102a to form the first semiconductor layer 1021 and the second semiconductor layer 1022 includes one or a combination of wet etching and dry etching processes.

[0222] The first isolation groove G1 extends along the third direction Y, and the second isolation groove G2 extends along the third direction Y.

[0223] In some implementations, reference Figure 29 The initial semiconductor layer 102a is etched, and a plurality of third isolation trenches G3 and a plurality of fourth isolation trenches G4 spaced along the third direction Y are formed. The third isolation trenches G3 are connected to the first isolation trenches G1, and the fourth isolation trenches G4 are connected to the second isolation trenches G2. The portion of the initial semiconductor layer 102a located between adjacent first isolation trenches G1 and adjacent third isolation trenches G3 forms the first semiconductor layer 1021, and the portion of the initial semiconductor layer 102a located between adjacent second isolation trenches G2 and adjacent fourth isolation trenches G4 forms the second semiconductor layer 1022.

[0224] The third isolation groove G3 extends along the second direction X, and the fourth isolation groove G4 extends along the second direction X.

[0225] refer to Figure 30 and Figure 31 , Figure 30 In order to be in Figure 28 A basic diagram. Figure 31 In order to be in Figure 29 A basic diagram. Figure 31 for Figure 30 The top view shows that a first isolation structure F1 is formed in the first isolation groove G1; a second isolation structure F2 is formed in the second isolation groove G2; a third isolation structure F3 is formed in the third isolation groove G3; and a fourth isolation structure F4 is formed in the fourth isolation groove G4. The third isolation structure F3 is connected to the first isolation structure F1, and the fourth isolation structure F4 is connected to the second isolation structure F2.

[0226] In some embodiments, the processes for forming the first isolation structure F1 in the first isolation tank G1, the process for forming the second isolation structure F2 in the second isolation tank G2, the process for forming the third isolation structure F3 in the third isolation tank G3, and the process for forming the fourth isolation structure F4 in the fourth isolation tank G4 can each be deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof thin film deposition processes.

[0227] In some embodiments, a plurality of first isolation structures F1 are arranged at intervals along a second direction X, and the first isolation structures F1 extend along a third direction Y. A plurality of second isolation structures F2 are arranged at intervals along the second direction X, and the second isolation structures F2 extend along a third direction Y.

[0228] In some embodiments, a plurality of third isolation structures F3 are arranged at intervals along a third direction Y, and the third isolation structures F3 extend along a second direction X. A plurality of fourth isolation structures F4 are arranged at intervals along a third direction Y, and the fourth isolation structures F4 extend along a second direction X.

[0229] In some embodiments, the third isolation structure F3 is formed during the formation of the first isolation structure F1, and the fourth isolation structure F4 is formed during the formation of the second isolation structure F2, simplifying the process. In other embodiments, the first isolation structure F1, the second isolation structure F2, the third isolation structure F3, and the fourth isolation structure F4 can be formed independently in different processes.

[0230] The materials of the first isolation structure F1, the second isolation structure F2, the third isolation structure F3, and the fourth isolation structure F4 are as described in the foregoing embodiments.

[0231] In some embodiments, the first isolation structure F1 is in contact with the insulating layer 104, the second isolation structure F2 is in contact with the insulating layer 104, the third isolation structure F3 is in contact with the insulating layer 104, and the fourth isolation structure F4 is in contact with the insulating layer 104.

[0232] In some implementations, in the first direction Z, the size of the first semiconductor layer 1021 is equal to the size of the second semiconductor layer 1022.

[0233] In some implementations, in the third direction Y, the size of the first semiconductor layer 1021 between adjacent third isolation structures F3 is larger than the size of the second semiconductor layer 1022 between adjacent fourth isolation structures F4.

[0234] In some embodiments, a first isolation structure F1 is located on both sides of the first semiconductor layer 1021 along the second direction X and is connected to the insulating layer 104. A second isolation structure F2 is located on both sides of the second semiconductor layer 1022 along the second direction X and is connected to the insulating layer 104. A third isolation structure F3 is located on both sides of the first semiconductor layer 1021 along the third direction Y and is connected to the insulating layer 104 and the first isolation structure F1. A fourth isolation structure F4 is located on both sides of the second semiconductor layer 1022 along the third direction Y and is connected to the insulating layer 104 and the second isolation structure F2.

[0235] Wherein, the third direction Y intersects the second direction X and the first direction Z. For example, the first direction Z is perpendicular to the second direction X, the first direction Z is perpendicular to the third direction Y, and the second direction X is perpendicular to the third direction Y.

[0236] refer to Figure 32 , Figure 32 In order to be in Figure 30 Based on the schematic diagram, a first gate structure 201 is formed, which is located on the side of the first semiconductor layer 1021 away from the insulating layer 104; a second gate structure 206 is formed, which is located on the side of the second semiconductor layer 1022 away from the insulating layer 104.

[0237] The method for forming the first gate structure is the same as described in the aforementioned embodiments, and the method for forming the second gate structure is the same as described in the aforementioned embodiments.

[0238] In one implementation, reference Figure 32 The method for fabricating the semiconductor structure further includes: forming a first source region 2071 in a first semiconductor layer 1021 on one side of the first gate structure 201, forming a first drain region 2072 in a first semiconductor layer 1021 on one side of the first gate structure 201; forming a second source region 2081 in a second semiconductor layer 1022 on one side of the second gate structure 206, and forming a second drain region 2082 in a second semiconductor layer 1022 on the other side of the second gate structure 206.

[0239] The process for forming the first source region 2071, the first drain region 2072, the second source region 2081, and the second drain region 2082 is described in the foregoing embodiment. The positions of the first source region 2071, the first drain region 2072, the second source region 2081, and the second drain region 2082 are described in the foregoing embodiment.

[0240] Another embodiment of this application also provides a memory, referenced... Figure 33 It includes a memory cell array C1 and peripheral circuitry C2, with peripheral circuitry C2 coupled to the memory cell array C1. Peripheral circuitry C2 includes the semiconductor structure provided in the above embodiments of this application.

[0241] The memory cell array C1 can be a 3D NAND flash memory cell array. The memory cell array C1 can also be a DRAM cell array.

[0242] The semiconductor structure may be the same as the semiconductor structure described in any of the embodiments above, and will not be described again in the embodiments of this application.

[0243] In some implementations, the peripheral circuitry C2 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array C1. For example, the peripheral circuitry C2 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0244] Another embodiment of this application also provides a system 30000 having a storage system 32000. (See reference...) Figure 34 , Figure 34This is a block diagram of a system 30000 having a storage system 32000 according to one embodiment of this application. Figure 35 This is a schematic diagram of a storage system according to one embodiment of this application.

[0245] like Figure 34 As shown, system 30000 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 32000 located therein). Figure 34 As shown, system 30000 may include host 31000 and storage system 32000, storage system 32000 having one or more memories 32100 and controller 32200. Host 31000 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 31000 may be configured to send or receive data to and from memory 32100.

[0246] Memory 32100 may include the memory described in any embodiment of this application. According to some embodiments, controller 32200 is coupled to memory 32100 and host 31000 and is configured to control memory 32100. Controller 32200 can manage data stored in memory 32100 and communicate with host 31000. In some embodiments, controller 32200 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 32200 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device such as a smartphone, tablet, laptop, etc. The controller 32200 can be configured to control the operation of the memory 32100, such as read, erase, and program operations. The controller 32200 can also be configured to manage various functions related to data stored in or to be stored in the memory 32100, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the controller 32200 is further configured to process error correction codes (ECCs) related to data read from or written to the memory 32100. The controller 32200 can also perform any other appropriate functions, such as formatting the memory 32100. The controller 32200 can communicate with external devices (e.g., host 31000) according to a specific communication protocol. For example, the controller 32200 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-express, PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0247] The controller 32200 and one or more memories 32100 can be integrated into various types of storage systems, such as Universal Flash Memory (UFS) packaged products or eMMC packaged products, where the controller 32200 and one or more memories 32100 can be included in the same packaged product (such as a Universal Flash Memory (UFS) packaged product or an eMMC packaged product). Figure 35 In one example shown in (a), the controller 32200 and a single memory 32100 may be integrated into a memory card 33100. The memory card 33100 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 33100 may further include a connection between the memory card 33100 and a host (e.g., Figure 34 The host 31000 in the memory card connector 32300 is coupled to the host 31000. In such a... Figure 35 In another example shown in (b), the controller 32200 and multiple memories 32100 may be integrated into the solid-state drive 33200. The solid-state drive 33200 may further include a connection between the solid-state drive 33200 and a host (e.g., Figure 34 The solid-state drive connector 32400 is coupled to the host 3100. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 33200 is higher than that of the memory card 33100.

[0248] Although exemplary fabrication methods and structures of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor structure. Furthermore, the materials of the exemplified layers are merely exemplary.

[0249] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure comprising a semiconductor-on-insulator structure, the semiconductor-on-insulator structure comprising: Insulating layer; The first semiconductor layer is located on one side of the insulating layer along the first direction; as well as The second semiconductor layer is located on one side of the insulating layer along the first direction and on at least one side of the first semiconductor layer along a direction intersecting the first direction; wherein, in the first direction, the size of the first semiconductor layer is larger than the size of the second semiconductor layer.

2. The semiconductor structure according to claim 1, wherein, In the first direction, the size of the first semiconductor layer is 1.5 to 3 times the size of the second semiconductor layer.

3. The semiconductor structure according to claim 1, further comprising: The first gate structure is located on the side of the first semiconductor layer away from the insulating layer; as well as The second gate structure is located on the side of the second semiconductor layer away from the insulating layer.

4. The semiconductor structure according to claim 1, wherein, The insulating layer includes a first insulating portion located on the side of the second semiconductor layer opposite to the first direction and a second insulating portion located on the side of the first semiconductor layer opposite to the first direction; In the first direction, the size of the first insulating portion is larger than the size of the second insulating portion.

5. The semiconductor structure according to claim 4, wherein, Relative to the side surface of the insulating layer facing the opposite direction to the first direction, the height of the surface of the first semiconductor layer facing away from the insulating layer in the first direction is the same as the height of the surface of the second semiconductor layer facing away from the insulating layer in the first direction.

6. The semiconductor structure according to claim 1, wherein, Relative to the side surface of the insulating layer facing the opposite direction to the first direction, the height of the surface of the second semiconductor layer facing away from the insulating layer in the first direction is less than the height of the surface of the first semiconductor layer facing away from the insulating layer in the first direction.

7. The semiconductor structure according to claim 6, wherein, In the first direction, the size of the portion of the insulating layer located on the side of the first semiconductor layer is equal to the size of the portion of the insulating layer located on the side of the second semiconductor layer.

8. The semiconductor structure according to any one of claims 1 to 7, wherein, The semiconductor structure also includes: A first isolation structure is located on both sides of the first semiconductor layer along a second direction and connected to the insulating layer; and The second isolation structure is located on both sides of the second semiconductor layer along the second direction and is connected to the insulating layer; The second direction intersects with the first direction.

9. The semiconductor structure according to claim 8, wherein, In the second direction, the size of the first semiconductor layer between adjacent first isolation structures is larger than the size of the second semiconductor layer between adjacent second isolation structures.

10. The semiconductor structure according to claim 8, wherein, The semiconductor structure also includes: A third isolation structure is located on both sides of the first semiconductor layer along a third direction and is connected to the insulating layer and the first isolation structure; and The fourth isolation structure is located on both sides of the second semiconductor layer along the third direction and is connected to the insulating layer and the second isolation structure; Wherein, the third direction intersects with the second direction and also intersects with the first direction.

11. The semiconductor structure according to claim 10, wherein, In the third direction, the size of the first semiconductor layer between adjacent third isolation structures is larger than the size of the second semiconductor layer between adjacent fourth isolation structures.

12. The semiconductor structure according to claim 3, wherein, The first gate structure includes a first gate dielectric layer and a first gate electrode layer, wherein the first gate dielectric layer is located on the side of the first semiconductor layer away from the insulating layer, and the first gate electrode layer is located on the side of the first gate dielectric layer away from the first semiconductor layer; The second gate structure includes a second gate dielectric layer and a second gate electrode layer. The second gate dielectric layer is located on the side of the second semiconductor layer away from the insulating layer, and the second gate electrode layer is located on the side of the second gate dielectric layer away from the second semiconductor layer. Wherein, along the first direction, the size of the first gate dielectric layer is larger than the size of the second gate dielectric layer.

13. A method for fabricating a semiconductor structure, said semiconductor structure comprising a semiconductor-on-insulator structure, the fabrication method comprising: An insulating layer and an initial semiconductor layer are formed, wherein the initial semiconductor layer is located on one side of the insulating layer in a first direction; The initial semiconductor layer is etched to form a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is located on at least one side of the first semiconductor layer along a direction intersecting the first direction, and in the first direction, the size of the first semiconductor layer is larger than the size of the second semiconductor layer.

14. The preparation method according to claim 13, wherein, Forming the insulating layer and the initial semiconductor layer includes: A third semiconductor layer, the insulating layer, and the initial semiconductor layer are formed and stacked along the first direction. The insulating layer is located between the third semiconductor layer and the initial semiconductor layer. The initial semiconductor layer includes a first portion and a second portion, and the second portion is located on at least one side of the first portion along a direction intersecting the first direction. The etching of the initial semiconductor layer to form the first semiconductor layer and the second semiconductor layer includes: The first portion is etched to form a plurality of first isolation trenches spaced apart along a second direction, wherein the portions of the first portion located between adjacent first isolation trenches form the first semiconductor layer; and The second portion is etched to form a plurality of second isolation trenches spaced apart along the second direction, and the portion of the second portion located between adjacent second isolation trenches forms the second semiconductor layer; The second direction intersects with the first direction.

15. The preparation method according to claim 14, wherein, Before etching the first portion and before etching the second portion, in the first direction, the size of the second portion is smaller than the size of the first portion, and the size of the portion of the insulating layer located on the side of the second portion opposite to the first direction is larger than the size of the portion of the insulating layer located on the side of the first portion opposite to the first direction.

16. The preparation method according to claim 14, wherein, The preparation method further includes: Before etching the second portion, the second portion is thinned from the side of the second portion away from the insulating layer, and the size of the second portion in the first direction is smaller than the size of the first portion in the first direction.

17. The preparation method according to claim 15, wherein, Forming a third semiconductor layer, the insulating layer, and the initial semiconductor layer stacked along the first direction includes: Forming a third semiconductor layer, a first insulating layer, and a semiconductor material layer stacked along the first direction; and A second insulating layer is formed in a portion of the semiconductor material layer and is connected to a portion of the first insulating layer. The dimension of the second insulating layer along the first direction is smaller than the dimension of the semiconductor material layer along the first direction. The remaining semiconductor material layer forms the initial semiconductor layer. The first insulating layer and the second insulating layer constitute the insulating layer.

18. The preparation method according to claim 17, wherein, A second insulating layer, connected to a portion of the first insulating layer, is formed in a certain region of the semiconductor material layer, including: An ion-doped region is formed in a portion of the semiconductor material layer; and The ion-doped region is annealed, wherein the ion-doped region forms the second insulating layer.

19. The preparation method according to claim 14, wherein, The preparation method further includes: A first isolation structure is formed in the first isolation groove; and A second isolation structure is formed in the second isolation groove.

20. The preparation method according to claim 14, wherein, Etching the first portion also forms a plurality of third isolation grooves spaced apart along a third direction, the third isolation grooves being connected to the first isolation groove; Etching the second portion also forms a plurality of fourth isolation trenches spaced apart along the third direction, the fourth isolation trenches being in communication with the second isolation trench; The first part, located between adjacent first isolation trenches and adjacent third isolation trenches, forms the first semiconductor layer; the second part, located between adjacent second isolation trenches and adjacent fourth isolation trenches, forms the second semiconductor layer. Wherein, the third direction intersects with the first direction and also intersects with the second direction.

21. The preparation method according to claim 20, wherein, The preparation method further includes: A third isolation structure is formed in the third isolation groove; and A fourth isolation structure is formed in the fourth isolation groove.

22. The preparation method according to claim 13, wherein, The preparation method further includes: A first gate structure is formed, the first gate structure being located on the side of the first semiconductor layer opposite to the insulating layer; and A second gate structure is formed, wherein the second gate structure is located on the side of the second semiconductor layer opposite to the insulating layer; The formation of the first gate structure includes: A first gate dielectric layer is formed on the side of the first semiconductor layer opposite to the insulating layer; and A first gate electrode layer is formed on the side of the first gate dielectric layer that is opposite to the first semiconductor layer; The formation of the second gate structure includes: A second gate dielectric layer is formed on the side of the second semiconductor layer opposite to the insulating layer; and A second gate electrode layer is formed on the side of the second gate dielectric layer that is opposite to the second semiconductor layer; Wherein, along the first direction, the size of the first gate dielectric layer is larger than the size of the second gate dielectric layer.

23. A memory comprising: Memory cell array; The peripheral circuitry includes a semiconductor structure as described in any one of claims 1 to 12, the peripheral circuitry being coupled to the memory cell array.

24. A storage system, comprising: The memory as described in claim 23; as well as A controller, coupled to the memory, is used to control the memory to store data.

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