Semiconductor device

Abstract

A semiconductor device includes: a rear interlayer insulating film; a plurality of first channel patterns on the rear interlayer insulating film and spaced apart from each other in a vertical direction; a plurality of second channel patterns on the rear interlayer insulating film and spaced apart from each other in the vertical direction; a source / drain pattern between the plurality of first channel patterns and the plurality of second channel patterns; and a source / drain contact connected to the source / drain pattern, in which the source / drain pattern includes: a first layer in contact with the plurality of first channel patterns and the plurality of second channel patterns; a second layer on or below the first layer; and a third layer on or above the second layer, in which a width of the first layer in the vertical direction decreases and then increases in a direction from the plurality of first channel patterns to the plurality of second channel patterns.

Description

Technical Field

[0001] One or more example embodiments of this disclosure relate to semiconductor devices, and more specifically, to a device including an MBCFET. TM Semiconductor devices (multi-bridge channel field-effect transistors). Background Technology

[0002] As one of the scaling techniques for increasing the density of integrated circuit devices, multi-gate transistors have been proposed, in which a silicon host in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the silicon host.

[0003] Because such multi-gate transistors utilize a three-dimensional channel, scaling is easily implemented. Furthermore, current control capability can be improved even without increasing the gate length of the multi-gate transistor. Additionally, the short-channel effect (SCE), where the channel region potential is affected by the drain voltage, can be effectively suppressed. However, a technique is needed to reduce the contact resistance between the source / drain contacts and the source / drain patterns. Summary of the Invention

[0004] One or more exemplary embodiments of this disclosure provide a semiconductor device in which the contact resistance between the source / drain contact and the source / drain pattern is reduced.

[0005] According to one aspect of an exemplary embodiment of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a back interlayer insulating film; a plurality of first channel patterns located on the back interlayer insulating film and spaced apart from each other in a vertical direction; a plurality of second channel patterns located on the back interlayer insulating film, spaced apart from each other in the vertical direction and spaced apart from the plurality of first channel patterns in a first horizontal direction; a source / drain pattern located between the plurality of first channel patterns and the plurality of second channel patterns; and a source / drain contact connected to the source / drain pattern, wherein the source / drain pattern comprises: a first layer contacting the plurality of first channel patterns and the plurality of second channel patterns; a second layer located on or above the first layer; and a third layer located on or above the second layer, wherein the width of the first layer in the vertical direction decreases and then increases along a direction from the plurality of first channel patterns to the plurality of second channel patterns.

[0006] According to one aspect of an exemplary embodiment of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a back interlayer insulating film; a plurality of first channel patterns located on the back interlayer insulating film and spaced apart from each other in a vertical direction; a plurality of second channel patterns located on the back interlayer insulating film, spaced apart from each other in the vertical direction, and spaced apart from the plurality of first channel patterns in a first horizontal direction; a source / drain pattern located between the plurality of first channel patterns and the plurality of second channel patterns; and a source / drain contact connected to the source / drain pattern, wherein the source / drain pattern comprises: a first layer in contact with the plurality of first channel patterns and the plurality of second channel patterns; a second layer located on or below the first layer; and a third layer located on or above the first layer and comprising the same material as the second layer.

[0007] According to one aspect of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a first lower channel pattern and a second lower channel pattern, the first lower channel pattern and the second lower channel pattern being spaced apart from each other in a first horizontal direction; a first upper channel pattern, the first upper channel pattern being spaced apart from the first lower channel pattern in a vertical direction; a second upper channel pattern, the second upper channel pattern being spaced apart from the second lower channel pattern in the vertical direction; a lower source / drain pattern, the lower source / drain pattern being in contact with the first lower channel pattern and the second lower channel pattern; and an upper source / drain pattern, the upper source / drain pattern being in contact with the first lower channel pattern and the second lower channel pattern; and an upper source / drain pattern, the upper source / drain pattern being in contact with the first lower channel pattern and the second lower channel pattern. The source / drain pattern is in contact with the first upper channel pattern and the second upper channel pattern, wherein the lower source / drain pattern includes a first lower layer in contact with the first lower channel pattern and the second lower channel pattern, a second lower layer located above or below the first lower layer, and a third lower layer located above or above the first lower layer, and wherein the upper source / drain pattern includes a first upper layer in contact with the first upper channel pattern and the second upper channel pattern, a second upper layer located above or below the first upper layer, and a third upper layer located above or above the first upper layer.

[0008] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become clearer to those skilled in the art upon reference to the following detailed description of the disclosure. Attached Figure Description

[0009] The above and other aspects and features of this disclosure will become clearer from the detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 This is an example layout diagram used to illustrate a semiconductor device according to one or more embodiments; Figure 2 and Figure 5 It is along Figure 1 Example cross-sectional view taken from A-A' in the diagram; Figure 3 It is along Figure 1 Example cross-sectional view taken from B-B' in the diagram; Figure 4 It is along Figure 1 Example cross-sectional view taken from C-C' in the image; Figures 6 to 18 It is a diagram used to illustrate a semiconductor device according to one or more embodiments; Figures 19 to 43 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to one or more embodiments. Detailed Implementation

[0010] In the following description, exemplary embodiments are illustrated with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions are omitted.

[0011] It will be understood that although the terms first, second, third, fourth, etc., may be used herein to describe various elements, components, regions, layers, and / or portions (collectively, “elements”), these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, a first element described in this descriptive section may be referred to as a second element in the claims section, or vice versa.

[0012] It will be understood that when a component or layer is referred to as being "above," "on top of," "on," "below," "under," "beneath," "connected to," or "coupled to" another component or layer, it can be directly above, on, on, below, under, or beneath another component or layer, connected to, or coupled to another component or layer, or intermediate components or layers may exist. In contrast, when a component is referred to as being "directly above," "directly on," "directly on," "directly above," "directly on," "directly below," "directly under," "directly connected to," or "directly coupled to" another component or layer, no intermediate components or layers exist.

[0013] As used in this article, the expression "at least one" preceding a list of elements modifies the entire list of elements, not individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0014] In this paper, the direction on the plane defined by the X and Y axes can be referred to as the horizontal direction, while the direction along the Z axis can be referred to as the vertical direction. A component positioned relative to other components in the +Z axis direction can be referred to as being above other components, while a component positioned relative to other components in the -Z axis direction can be referred to as being below other components.

[0015] Figure 1 This is an example layout diagram used to illustrate a semiconductor device according to one or more embodiments. Figure 2 and Figure 5 It is along Figure 1 Example cross-sectional view taken from A-A' in the diagram. Figure 3 It is along Figure 1 Example cross-sectional view taken from B-B' in the figure. Figure 4 It is along Figure 1 Example cross-sectional view taken from C-C' in the image.

[0016] refer to Figures 1 to 5 A semiconductor device according to one or more embodiments may include a first active pattern AP1, a second active pattern AP2, a plurality of gate electrodes 120, a source / drain pattern 160, a back source / drain contact 195, and a back interlayer insulating film 180.

[0017] The back interlayer insulating film 180 may include at least one of, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low dielectric constant material. The low dielectric constant material may have a dielectric constant smaller than the 3.9 of silicon oxide. Although the back interlayer insulating film 180 is shown as a single film, this is for illustrative purposes only, and the embodiments are not limited thereto.

[0018] The back interlayer insulating film 180 may extend in the first horizontal direction DR1. The back interlayer insulating film 180 may include an upper surface and a bottom surface opposite each other in the vertical direction DR3.

[0019] The field insulating film 105 may be disposed on the sidewall of the back interlayer insulating film 180. The field insulating film 105 may cover the sidewall of the back interlayer insulating film 180. The field insulating film 105 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low dielectric constant materials. Although the field insulating film 105 is shown as a single film, this is only for illustrative purposes, and the embodiments are not limited thereto.

[0020] When both the back interlayer insulating film 180 and the field insulating film 105 are single films and comprise the same insulating material, the boundary between the back interlayer insulating film 180 and the field insulating film 105 may not be distinguishable.

[0021] The first active pattern AP1 and the second active pattern AP2 can be disposed on the upper surface of the back interlayer insulating film 180. The first active pattern AP1 and the second active pattern AP2 can be spaced apart from each other in the first horizontal direction DR1. The first active pattern AP1 and the second active pattern AP2 can be adjacent to each other in the first horizontal direction DR1.

[0022] Each of the first active pattern AP1 and the second active pattern AP2 may be a multi-channel active pattern. In some embodiments, the first active pattern AP1 may include a plurality of first channel patterns NS1, and the second active pattern AP2 may include a plurality of second channel patterns NS2. In some embodiments, each of the first active pattern AP1 and the second active pattern AP2 may be an active pattern comprising nanosheets or nanowires.

[0023] Multiple first channel patterns NS1 can be disposed on the upper surface of the back interlayer insulating film 180. The multiple first channel patterns NS1 can be spaced apart from each other in the vertical direction DR3.

[0024] Multiple second channel patterns NS2 can be disposed on the upper surface of the back interlayer insulating film 180. The multiple second channel patterns NS2 can be spaced apart from the multiple first channel patterns NS1 along a first horizontal direction DR1 on the upper surface of the back interlayer insulating film 180. The multiple second channel patterns NS2 can be adjacent to the multiple first channel patterns NS1 in the first horizontal direction DR1. The multiple second channel patterns NS2 can be spaced apart from each other in the vertical direction DR3.

[0025] Although the three first channel patterns NS1 and the three second channel patterns NS2 are shown as being arranged on the vertical direction DR3, this is only for illustrative purposes and the embodiments are not limited thereto.

[0026] The first channel pattern NS1 and the second channel pattern NS2 may both include, for example, but not limited to, silicon or germanium as elemental semiconductor materials. Additionally, both the first channel pattern NS1 and the second channel pattern NS2 may include compound semiconductors, and may include, for example, group IV-IV compound semiconductors or group III-V compound semiconductors.

[0027] Group IV-IV compound semiconductors can be, for example, but not limited to, binary or ternary compounds comprising at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds obtained by doping any of these elements with a group IV element.

[0028] III-V compound semiconductors can be, for example, but not limited to, binary, ternary, or quaternary compounds formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), and antimony (Sb), which are group V elements.

[0029] The width of the first channel pattern NS1 is shown to be the same, but the embodiment is not limited thereto. The width of each first channel pattern NS1 may be increased or decreased proportionally to the width of the back interlayer insulating film 180 in the second direction DR2. The description of the width of the second channel pattern NS2 may be substantially the same as the description of the width of the first channel pattern NS1.

[0030] Multiple gate structures GS can be disposed on the field insulating film 105 and the back interlayer insulating film 180. Multiple gate structures GS can be disposed on the upper surface of the back interlayer insulating film 180.

[0031] Each gate structure GS may extend on the second horizontal direction DR2. The gate structures GS may be spaced apart from each other on the first horizontal direction DR1. The gate structures GS may be adjacent to each other on the first horizontal direction DR1. The gate structures GS may intersect with the back interlayer insulating film 180.

[0032] The gate structure GS can surround a corresponding first channel pattern NS1. The gate structure GS can surround a corresponding second channel pattern NS2.

[0033] The gate structure GS may include, for example, a gate insulating film 110 and a gate electrode 120.

[0034] The gate structure GS may include multiple inner gate structures IGS, which are disposed between first channel patterns NS1 adjacent to each other along the vertical direction DR3, between the back interlayer insulating film 180 and the first channel pattern NS1 adjacent to each other along the vertical direction DR3, between second channel patterns NS2 adjacent to each other along the vertical direction DR3, and between the back interlayer insulating film 180 and the second channel pattern NS2 adjacent to each other along the vertical direction DR3. The inner gate structure IGS may include a gate insulating film 110 and a gate electrode 120.

[0035] The inner gate structure IGS can contact the upper surface and the lower surface of one of the first channel patterns NS1. The inner gate structure IGS can contact the upper surface and the lower surface of one of the second channel patterns NS2.

[0036] The bottom surface of one of the internal gate structure IGS can contact the upper surface of the back interlayer insulating film 180. The side surface of the internal gate structure IGS can contact the source / drain pattern 160.

[0037] The gate electrode 120 may be disposed on the back interlayer insulating film 180. The gate electrode 120 may intersect with the back interlayer insulating film 180. The gate electrode 120 may surround the first channel pattern NS1 and the second channel pattern NS2.

[0038] The upper surface of the gate electrode 120 is shown as a concave, curved surface, but is not limited thereto. It should be understood that the upper surface of the gate electrode 120 may have any other form, such as a flat surface.

[0039] The gate electrode 120 may include at least one of the following: metal, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, and conductive metal oxynitride. For example, the gate electrode 120 may include, but is not limited to, titanium nitride (TiN), titanium carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and titanium carbonitride (TiC). At least one of the following: TaCN, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (NiPt), niobium (Nb), niobium nitride (NbN), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and any combination thereof. Conductive metal oxides and conductive metal nitrides may be, but are not limited to, the oxidation forms of the aforementioned materials.

[0040] The gate insulating film 110 may extend along the upper surface of the field insulating film 105 and the upper surface of the back interlayer insulating film 180. The gate insulating film 110 may surround a plurality of first channel patterns NS1. The gate insulating film 110 may surround a plurality of second channel patterns NS2. The gate insulating film 110 may be disposed along the periphery of the first channel patterns NS1 and the periphery of the second channel patterns NS2. The gate electrode 120 may be disposed on the gate insulating film 110.

[0041] The gate insulating film 110 can be disposed between the gate electrode 120 and the first channel pattern NS1, and between the gate electrode 120 and the second channel pattern NS2. For example, the gate insulating film 110 can contact the back interlayer insulating film 180. The gate insulating film 110 included in the inner gate structure IGS can contact the source / drain pattern 160.

[0042] The gate insulating film 110 may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material with a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, but not limited to, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0043] Although the gate insulating film 110 is shown as a single film, this is for illustrative purposes only, and the embodiments are not limited thereto. The gate insulating film 110 may include multiple films. The gate insulating film 110 may also include an interface layer and a high-dielectric-constant insulating film disposed between the first channel pattern NS1 and the gate electrode 120 and between the second channel pattern NS2 and the gate electrode 120. For example, the interface layer may not be formed along the contour of the upper surface of the field insulating film 105.

[0044] The semiconductor device according to some other embodiments may include an NC (negative capacitance) FET that uses negative capacitance. For example, each gate insulating film 110 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0045] Ferroelectric films can have negative capacitance, while paraelectric films can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance can be reduced from the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative capacitance, the total capacitance can be greater than the absolute value of the capacitance of each individual capacitor while also having a positive value.

[0046] When a ferroelectric film with negative capacitance and a paraelectric film with positive capacitance are connected in series, the total capacitance of the two films increases. By using this increased total capacitance, transistors incorporating ferroelectric films can achieve a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0047] Ferroelectric material films can possess ferroelectric properties. For example, ferroelectric material films can include, but are not limited to, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide can be a material formed by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide can be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0048] Ferroelectric material films may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (CA), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film can vary depending on the type of ferroelectric material included.

[0049] When the ferroelectric material film includes hafnium oxide, the dopants included in the ferroelectric material film may include, for example, but not limited to, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and yttrium (Y).

[0050] When the dopant is aluminum (Al), the ferroelectric film may include 3 at% (atomic%) to 8 at% aluminum. Here, the dopant ratio can be the ratio of aluminum to the sum of hafnium and aluminum.

[0051] When the dopant is silicon (Si), the ferroelectric film may comprise 2 at% to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric film may comprise 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric film may comprise 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric film may comprise 50 at% to 80 at% zirconium.

[0052] The paraelectric material film may possess paraelectric properties. The paraelectric material film may include, for example, but not limited to, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, but not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0053] Ferroelectric and paraelectric material films can comprise the same material. Ferroelectric material films possess ferroelectric properties, but paraelectric material films may not. For example, when both ferroelectric and paraelectric material films include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film differs from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0054] Ferroelectric material films can have a thickness that exhibits ferroelectric properties. The thickness of a ferroelectric material film can be, for example, but not limited to, 0.5 nm to 10 nm. Since the critical thickness exhibiting ferroelectric properties can vary for each ferroelectric material, the thickness of a ferroelectric material film can vary depending on the ferroelectric material included in the film.

[0055] As an example, the gate insulating film 110 may include a ferroelectric material film. As another example, the gate insulating film 110 may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film 110 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0056] Gate spacer 130 may be disposed on the sidewall of gate electrode 120. Gate spacer 130 may not be disposed between the back interlayer insulating film 180 and the first channel pattern NS1, or between the first channel patterns NS1 that are adjacent to each other along the vertical direction DR3. Gate spacer 130 may not be disposed between the back interlayer insulating film 180 and the second channel pattern NS2, or between the second channel patterns NS2 that are adjacent to each other along the vertical direction DR3.

[0057] The gate spacer 130 may include, for example, but not limited to, at least one and any combination thereof, of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), and silicon carbonitride (SiOC). Although the gate spacer 130 is shown as a single film, this is for illustrative purposes only, and the embodiments are not limited thereto.

[0058] A gate cover pattern 145 may be disposed on the gate electrode 120. The upper surface of the gate cover pattern 145 may be disposed on the same plane as the upper surface of the front interlayer insulating film 175. Unlike the example shown, the gate cover pattern 145 may be disposed between the gate spacers 130.

[0059] The gate cover pattern 145 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and any combination thereof. The gate cover pattern 145 may include a material that has etch selectivity relative to the front interlayer insulating film 175.

[0060] Source / drain pattern 160 may be disposed on the back interlayer insulating film 180. Source / drain pattern 160 may be disposed on at least one side surface of gate electrode 120. Source / drain pattern 160 may be disposed between gate electrodes 120 adjacent to each other along the first horizontal direction DR1.

[0061] The source / drain pattern 160 can be disposed between the first channel pattern NS1 and the second channel pattern NS2. The source / drain pattern 160 can contact the first channel pattern NS1 and the second channel pattern NS2. The source / drain pattern 160 can be connected to the ends of the first channel pattern NS1 and the ends of the second channel pattern NS2 that are opposite to each other.

[0062] Although not shown, the source / drain pattern 160 may be disposed on both sides of the first channel pattern NS1 and both sides of the second channel pattern NS2.

[0063] Although the external shape of the source / drain pattern 160 is shown in the accompanying drawings as having a hexagonal shape, the embodiment is not limited to this. Unlike the example shown, the external shape of the source / drain pattern 160 may be a pentagonal or rectangular shape.

[0064] In some embodiments, the source / drain pattern 160 may include a first layer 161, a second layer 162, a third layer 163, a fourth layer 164, and a fifth layer 165.

[0065] The first layer 161 may contact the first channel pattern NS1 and the second channel pattern NS2. The first layer 161 may contact the gate insulating film 110. The thickness of the first layer 161 in the vertical direction DR3 may decrease and then increase along the direction from the first channel pattern NS1 to the second channel pattern NS2. The distance between the second layer 162 and the third layer 163 in the vertical direction DR3 may decrease and then increase along the direction from the first channel pattern NS1 to the second channel pattern NS2.

[0066] The second layer 162 can be disposed on or below the first layer 161. The third layer 163 can be disposed on or above the first layer 161. The second layer 162 and the third layer 163 can contain the same material as each other.

[0067] In some embodiments, the second layer 162 and the third layer 163 may be separated from each other without contacting each other. The first layer 161 may fill the gap between the second layer 162 and the third layer 163. The width of the second layer 162 in the vertical direction DR3 may increase and then decrease along the direction from the first channel pattern NS1 to the second channel pattern NS2. The width of the third layer 163 in the vertical direction DR3 may increase and then decrease along the direction from the first channel pattern NS1 to the second channel pattern NS2.

[0068] The fourth layer 164 can be disposed on or below the second layer 162. The fourth layer 164 can be disposed at the bottom of the source / drain pattern 160. The fifth layer 165 can be disposed above the third layer 163. The fifth layer 165 can be disposed at the top of the source / drain pattern 160. The fifth layer 165 can include the same material as the fourth layer 164.

[0069] In some embodiments, the source / drain pattern 160 may include a first layer 161, a second layer 162, a third layer 163, and a fifth layer 165. That is, unlike the example shown, the fourth layer 164 may be omitted.

[0070] The source / drain pattern 160 may include a semiconductor material. The source / drain pattern 160 may include, for example, but not limited to, silicon or germanium as elemental semiconductor materials. The source / drain pattern 160 may also include, for example, but not limited to, binary or ternary compounds comprising at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds formed by doping any of these elements with a group IV element.

[0071] The source / drain pattern 160 may include dopants incorporated into the semiconductor material. As an example, the first channel pattern NS1 and the second channel pattern NS2 may be used as the channel region of a p-type transistor, and the source / drain pattern 160 may be included in the source / drain of the p-type transistor, and the source / drain pattern 160 may include a p-type dopant. The p-type dopant may include, but is not limited to, at least one of boron (B) and gallium (Ga). As another example, the first channel pattern NS1 and the second channel pattern NS2 may be used as the channel region of an n-type transistor, and the source / drain pattern 160 may be included in the source / drain of the n-type transistor, and the source / drain pattern 160 may include an n-type dopant. The n-type dopant may include, but is not limited to, at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0072] In some embodiments, the first layer 161 may comprise boron (B)-doped silicon (Si) and / or boron (B)-doped silicon carbide (SiC). The second layer 162 and the third layer 163 may comprise boron (B)-doped silicon germanium (SiGe), boron (B)-doped silicon germanium carbon (SiGeC), boron (B)-doped silicon (Si) and / or boron (B)-doped silicon carbide (SiC).

[0073] The concentration of doped material in each of the second layer 162 and the third layer 163 may be equal to or greater than the concentration of doped material in the first layer 161. Here, the concentration of doped material may refer to atomic percentage. For example, each of the second layer 162 and the third layer 163 may include the same material as the first layer 161. For example, each of the first layer 161, the second layer 162, and the third layer 163 may include silicon (Si) doped with boron (B). In this case, the concentration of boron (B) contained in each of the second layer 162 and the third layer 163 may be equal to or greater than the concentration of boron (B) contained in the first layer 161. In some other embodiments, each of the second layer 162 and the third layer 163 may include a different material than the first layer 161.

[0074] The fourth layer 164 and the fifth layer 165 may both include silicon (Si) and / or silicon germanium (SiGe).

[0075] The front interlayer insulating film 175 can be disposed on the rear interlayer insulating film 180 and the field insulating film 105. The front interlayer insulating film 175 can be disposed on the source / drain pattern 160. The front interlayer insulating film 175 may not cover the upper surface of the gate cover pattern 145. For example, the upper surface of the front interlayer insulating film 175 may be disposed on the same plane as the upper surface of the gate cover pattern 145.

[0076] The front interlayer insulating film 175 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and low dielectric constant materials.

[0077] The source / drain etch stop film 170 may extend along the contour of the source / drain pattern 160. The source / drain etch stop film 170 may be disposed between the source / drain pattern 160 and the front interlayer insulating film 175.

[0078] The source / drain etch stop film 170 may include, but is not limited to, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and any combination thereof.

[0079] A front spacer 140 may be disposed on the sidewall of the gate spacer 130. The front spacer 140 may be disposed between the source / drain etch stop film 170 and the gate spacer 130. The front spacer 140 may include an insulating material. The front spacer 140 may include a material different from the source / drain etch stop film 170. For example, the front spacer 140 may include silicon nitride (SiN), while the source / drain etch stop film 170 may include a material different from silicon nitride (SiN).

[0080] In some embodiments, the rear source / drain contact 195 may extend elongatedly in the vertical direction DR3. The rear source / drain contact 195 may be electrically connected to the source / drain pattern 160. The rear source / drain contact 195 may be electrically connected to a rear wiring line disposed on the bottom surface of the rear interlayer insulating film 180. The rear wiring line may be a power line supplying power to the semiconductor device or a signal line supplying operating signals to the semiconductor device. Here, the rear source / drain contact 195 may be referred to as a source / drain contact.

[0081] The rear source / drain contact 195 may be disposed within the rear interlayer insulating film 180. The rear source / drain contact 195 may extend from the bottom surface to the top surface of the rear interlayer insulating film 180. The rear source / drain contact 195 may penetrate the rear interlayer insulating film 180.

[0082] The rear source / drain contact 195 can be disposed within the source / drain pattern 160. The rear source / drain contact 195 can enter the source / drain pattern 160. The rear source / drain contact 195 can penetrate a portion of the source / drain pattern 160. The upper surface of the rear source / drain contact 195 can be disposed within the source / drain pattern 160. The upper surface of the rear source / drain contact 195 can have a convex shape facing the source / drain pattern 160.

[0083] In some embodiments, the post-source / drain contact 195 may extend into the second layer 162. The upper surface of the post-source / drain contact 195 may be disposed within the second layer 162. The post-source / drain contact 195 may penetrate the fourth layer 164 and a portion of the second layer 162.

[0084] The post-source / drain contact 195 may include a conductive material. The post-source / drain contact 195 may include, for example, but not limited to, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal oxide oxynitride, a conductive metal silicon nitride, a conductive metal carbonitride, and a two-dimensional material. Although the post-source / drain contact 195 is shown as a single film, this is for illustrative purposes only, and the embodiments are not limited thereto. Unlike the example shown, the first post-source / drain contact 195 may have a multi-conductive film structure. The post-source / drain contact 195 may include, for example, a post-contact barrier film and a post-contact fill film.

[0085] A post-contact silicide film 190 may be disposed between the post-source / drain contact 195 and the source / drain pattern 160. The post-contact silicide film 190 may contact the post-source / drain contact 195 and the source / drain pattern 160. The post-contact silicide film 190 may contact the post-source / drain contact 195 and the second layer 162. The post-contact silicide film 190 may include a metal silicide material.

[0086] In a semiconductor device according to some embodiments, since the back contact silicide film 190 contacts the second layer 162 of the source / drain pattern 160, and the concentration of doped material in the second layer 162 is higher than that in the first layer 161, the contact resistance between the back source / drain contact 195 and the source / drain pattern 160 can be reduced. Therefore, the performance and reliability of the semiconductor device according to some embodiments can be improved.

[0087] In some embodiments, a rear spacer 185 may be disposed on the sidewall of the rear source / drain contact 195. The rear spacer 185 may extend along the sidewall of the rear source / drain contact 195. The rear spacer 185 may be disposed between the rear interlayer insulating film 180 and the rear source / drain contact 195. The rear spacer 185 may include an insulating material. The rear spacer 185 may include, for example, but not limited to, silicon nitride (SiN).

[0088] refer to Figure 2 In some embodiments, the substrate pattern 100 may be disposed between the back interlayer insulating film 180 and the back spacer 185 and between the back interlayer insulating film 180 and the source / drain pattern 160.

[0089] The substrate pattern 100 may be bulk silicon, silicon-on-insulator (SOI), silicon, or may include other materials, such as, but not limited to, silicon germanium, silicon-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0090] refer to Figure 5 The semiconductor device according to one or more embodiments may not include Figure 2 The substrate pattern 100.

[0091] Figures 6 to 18 This is a diagram used to illustrate a semiconductor device according to one or more embodiments. For ease of explanation, the main focus will be on the description and use of... Figures 1 to 5 The differences described are those of the semiconductor devices. For reference, Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 It is along Figure 1 Example cross-sectional view taken from A-A' in the figure. Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 and Figure 17 It is along Figure 1 Example cross-sectional view taken from B-B' in the figure, and Figure 18 It is along Figure 1 Example cross-sectional view taken from C-C' in the image.

[0092] refer to Figure 6 and Figure 7 In a semiconductor device according to some embodiments, a back interlayer insulating film 180 may be disposed on the sidewall of the back source / drain contact 195. Back spacers (e.g., Figure 2 The source / drain contact 195 may not be positioned between the source / drain contact 195 and the back interlayer insulating film 180. The back source / drain contact 195 may be in contact with the back interlayer insulating film 180.

[0093] In some embodiments, substrate pattern 100 may be disposed between the rear source / drain contact 195 and the rear interlayer insulating film 180. In contrast, in some alternative embodiments, substrate pattern 100 may be omitted.

[0094] refer to Figure 8 and Figure 9 According to some embodiments, the semiconductor device may further include a front contact silicide film 290 and a front source / drain contact 295. That is, the source / drain pattern 160 can be electrically connected to the front source / drain contact 295 and the rear source / drain contact 195. Here, the front source / drain contact 295 may be referred to as the source / drain contact.

[0095] The front source / drain contact 295 may extend elongatedly in the vertical direction DR3. The front source / drain contact 295 may be electrically connected to the source / drain pattern 160. The front source / drain contact 295 may be electrically connected to the front wiring line disposed on the upper surface of the front interlayer insulating film 175.

[0096] A source / drain etch stop film 170 may be disposed between the front source / drain contact 295 and the front spacer 140. The front source / drain contact 295 may be disposed within the front interlayer insulating film 175. The front source / drain contact 295 may extend from the upper surface to the lower surface of the front interlayer insulating film 175. The front source / drain contact 295 may penetrate the front interlayer insulating film 175.

[0097] A front source / drain contact 295 may be disposed within the source / drain pattern 160. The front source / drain contact 295 may enter the source / drain pattern 160. The front source / drain contact 295 may penetrate a portion of the source / drain pattern 160. The bottom surface of the front source / drain contact 295 may be disposed within the source / drain pattern 160. The bottom surface of the front source / drain contact 295 may have a convex shape facing the source / drain pattern 160.

[0098] In some embodiments, the front source / drain contact 295 may extend into the third layer 163. The bottom surface of the front source / drain contact 295 may be disposed within the third layer 163.

[0099] The source / drain contact 295 may include, for example, but not limited to, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material.

[0100] A front contact silicide film 290 may be disposed between the front source / drain contact 295 and the source / drain pattern 160. The front contact silicide film 290 may contact the front source / drain contact 295 and the source / drain pattern 160. The front contact silicide film 290 may contact the front source / drain contact 295 and the third layer 163. The front contact silicide film 290 may include, for example, but not limited to, a metal silicide material.

[0101] In a semiconductor device according to some embodiments, since the front source / drain contact 295 contacts the third layer 163 of the source / drain pattern 160, and the concentration of doped material in the third layer 163 is higher than that in the first layer 161, the contact resistance between the front source / drain contact 295 and the source / drain pattern 160 can be reduced. Therefore, the performance and reliability of the semiconductor device according to some embodiments can be improved.

[0102] In some embodiments, the substrate pattern 100 may be omitted. In some embodiments, the back spacer 185 may be omitted.

[0103] refer to Figure 10 and Figure 11 According to some embodiments, a semiconductor device may include a front contact silicide film 290, a front source / drain contact 295, a sacrificial pattern 150, a sacrificial spacer 151, and a sacrificial filler film 152.

[0104] The source / drain pattern 160 can be electrically connected to the front source / drain contact 295. The front source / drain contact 295 and the front contact silicide film 290 can be used with... Figure 8 and Figure 9 The described front source / drain contact 295 and front contact silicide film 290 are essentially the same.

[0105] The sacrificial pattern 150 can be disposed within the back interlayer insulating film 180. The sacrificial pattern 150 can contact the back interlayer insulating film 180.

[0106] The sacrificial pattern 150 can be placed on or below the source / drain pattern 160. The sacrificial pattern 150 can overlap with the source / drain pattern 160 in the vertical direction DR3.

[0107] In some embodiments, the sacrificial pattern 150 may include a dielectric material.

[0108] In some embodiments, the sacrificial pattern 150 may include a semiconductor material. For example, the sacrificial pattern 150 may include silicon germanium (SiGe). The concentration of germanium (Ge) included in the sacrificial pattern 150 may differ from the concentration of germanium (Ge) included in the second layer 162 and the third layer 163. The concentration of germanium (Ge) included in the sacrificial pattern 150 may be lower than the concentration of germanium (Ge) included in the second layer 162 and the third layer 163.

[0109] Sacrificial spacer 151 and sacrificial filler 152 may be disposed on or below source / drain pattern 160. Sacrificial spacer 151 and sacrificial filler 152 may be disposed between source / drain pattern 160 and sacrificial pattern 150. Sacrificial spacer 151 may define a trench between source / drain pattern 160 and sacrificial pattern 150, and sacrificial filler 152 may fill the trench between source / drain pattern 160 and sacrificial pattern 150. Sacrificial spacer 151 and sacrificial filler 152 may contact source / drain pattern 160 and sacrificial pattern 150. Sacrificial spacer 151 may extend along the sidewalls and bottom surface of sacrificial filler 152. The upper surfaces of sacrificial spacer 151 and sacrificial filler 152 may contact the fourth layer 164 of source / drain pattern 160.

[0110] Both the sacrificial spacer 151 and the sacrificial filler 152 may comprise insulating materials. For example, the sacrificial spacer 151 may comprise silicon nitride (SiN), while the sacrificial filler 152 may comprise Tonen silazane (TOSZ).

[0111] In some embodiments, the substrate pattern 100 may be omitted.

[0112] refer to Figure 12 and Figure 13 In a semiconductor device according to some embodiments, a rear source / drain contact 195 may extend into a first layer 161. The upper surface of the rear source / drain contact 195 may be disposed within the first layer 161. The rear source / drain contact 195 may penetrate a fourth layer 164, a second layer 162, and a portion of the first layer 161.

[0113] In some embodiments, the substrate pattern 100 may be omitted. In some embodiments, the back spacer 185 may be omitted.

[0114] refer to Figure 14 and Figure 15In a semiconductor device according to some embodiments, the first layers 161_1, 161_2, 161_3, and 161_4 of the source / drain pattern 160 may include a first portion 161_1, a second portion 161_2, a third portion 161_3, and a fourth portion 161_4. The first portion 161_1 may contact a first channel pattern NS1. The second portion 161_2 may contact a second channel pattern NS2. The third portion 161_3 and the fourth portion 161_4 may be disposed between the second layer 162 and the third layer 163 and the front interlayer insulating film 175. The third portion 161_3 and the fourth portion 161_4 may be opposite to each other in a second horizontal direction DR2. From a top view including the first horizontal direction DR1 and the second horizontal direction DR2, the first portion 161_1, the second portion 161_2, the third portion 161_3, and the fourth portion 161_4 may have a shape surrounding the second layer 162 and the third layer 163.

[0115] The width of the first part 161_1 in the vertical direction DR3 can decrease along the direction away from the first channel pattern NS1. The width of the second part 161_2 in the vertical direction DR3 can decrease along the direction away from the second channel pattern NS2. The width of the third part 161_3 in the vertical direction DR3 can increase and then decrease along the direction approaching the fourth part 161_4. The width of the fourth part 161_4 in the vertical direction DR3 can increase and then decrease along the direction approaching the third part 161_3. Figure 14 In the cross-section shown, the first part 161_1 and the second part 161_2 can be spaced apart from each other. Figure 14 In the cross-section shown, the first part 161_1 and the second part 161_2 may not be connected to each other. Figure 15 In the cross-section shown, the third part 161_3 and the fourth part 161_4 can be spaced apart from each other. Figure 15 In the cross section shown, the third part 161_3 and the fourth part 161_4 may not be connected to each other.

[0116] The second layer 162 and the third layer 163 can be connected to each other. The second layer 162 and the third layer 163 can fill the space between the first part 161_1, the second part 161_2, the third part 161_3 and the fourth part 161_4.

[0117] Although the accompanying drawings show a sidewall of a first portion 161_1 opposite to a second portion 161_2 pointing towards a second portion 161_2, a sidewall of a second portion 161_2 opposite to a first portion 161_1 pointing towards a first portion 161_1, a sidewall of a third portion 161_3 opposite to a fourth portion 161_4 pointing towards a fourth portion 161_4, and a sidewall of a fourth portion 161_4 opposite to a third portion 161_3 pointing towards a third portion 161_3, the embodiments are not limited thereto. Unlike the example shown, at least one of the sidewalls of the first portion 161_1 opposite to a second portion 161_2, the second portion 161_2 opposite to a first portion 161_1, the third portion 161_3 opposite to a fourth portion 161_4, and the fourth portion 161_4 opposite to a third portion 161_3 may include a flat portion. For example, the width of the first part 161_1 in the first horizontal direction DR1 and the width of the second part 161_2 in the first horizontal direction DR1 can increase, remain constant and then decrease along the direction from the fourth layer 164 to the fifth layer 165.

[0118] In some embodiments, the source / drain pattern 160 may include, for example, using Figures 1 to 5 The p-type dopant is described.

[0119] In some embodiments, the source / drain pattern 160 may include an n-type dopant. The first layers 161_1, 161_2, 161_3, and 161_4 may include silicon (Si) doped with an n-type dopant. The second layer 162 and the third layer 163 may both include silicon (Si). The fourth layer 164 and the fifth layer 165 may both include silicon (Si) and / or silicon-germanium (SiGe).

[0120] In some embodiments, the substrate pattern 100 may be omitted. In some embodiments, the back spacer 185 may be omitted.

[0121] refer to Figure 1 and Figures 16 to 18 In a semiconductor device according to some embodiments, a first active pattern AP1 may include a first lower channel pattern BNS1 and a first upper channel pattern UNS1, and a second active pattern AP2 may include a second lower channel pattern BNS2 and a second upper channel pattern UNS2.

[0122] At least one or more first lower channel patterns BNS1 may be disposed on the back interlayer insulating film 180. When multiple first lower channel patterns BNS1 are disposed on the back interlayer insulating film 180, each first lower channel pattern BNS1 may be spaced apart from the back interlayer insulating film 180 in the vertical direction DR3. Each first lower channel pattern BNS1 may be spaced apart from each other in the vertical direction DR3. Although two first lower channel patterns BNS1 are shown as disposed on the upper surface of the back interlayer insulating film 180, the embodiment is not limited thereto. Unlike the example shown, one or three or more first lower channel patterns BNS1 may be disposed on the upper surface of the back interlayer insulating film 180.

[0123] At least one or more first upper channel patterns UNS1 may be disposed on the upper surface of the back interlayer insulating film 180. The first upper channel pattern UNS1 may be disposed on the first lower channel pattern BNS1. The first lower channel pattern BNS1 may be disposed between the back interlayer insulating film 180 and the first upper channel pattern UNS1.

[0124] The first upper channel pattern UNS1 may be spaced apart from the first lower channel pattern BNS1 in the vertical direction DR3. When each first upper channel pattern UNS1 is disposed on the upper surface of the first rear interlayer insulating film 180, multiple first upper channel patterns UNS1 may be spaced apart from each other in the vertical direction DR3. Although two first upper channel patterns UNS1 are shown as disposed on the upper surface of the rear interlayer insulating film 180, the embodiment is not limited thereto. Unlike the illustrated example, one or three or more first upper channel patterns UNS1 may be disposed on the upper surface of the rear interlayer insulating film 180. Although the number of first upper channel patterns UNS1 is shown to be the same as the number of first lower channel patterns BNS1, this is for illustrative purposes only, and the embodiment is not limited thereto.

[0125] At least one or more second lower channel patterns BNS2 may be disposed on the back interlayer insulating film 180. When multiple second lower channel patterns BNS2 are disposed on the back interlayer insulating film 180, each second lower channel pattern BNS2 may be spaced apart from the back interlayer insulating film 180 in the vertical direction DR3. Each second lower channel pattern BNS2 may be spaced apart from each other in the vertical direction DR3. Although two second lower channel patterns BNS2 are shown as disposed on the upper surface of the back interlayer insulating film 180, the embodiment is not limited thereto. Unlike the example shown, one or three or more second lower channel patterns BNS2 may be disposed on the upper surface of the back interlayer insulating film 180.

[0126] At least one or more second upper channel patterns UNS2 may be disposed on the upper surface of the back interlayer insulating film 180. The second upper channel pattern UNS2 may be disposed on the second lower channel pattern BNS2. The second lower channel pattern BNS2 may be disposed between the back interlayer insulating film 180 and the second upper channel pattern UNS2.

[0127] The second upper channel pattern UNS2 may be spaced apart from the second lower channel pattern BNS2 in the vertical direction DR3. When each second upper channel pattern UNS2 is disposed on the upper surface of the first rear interlayer insulating film 180, multiple second upper channel patterns UNS2 may be spaced apart from each other in the vertical direction DR3. Although two second upper channel patterns UNS2 are shown as disposed on the upper surface of the rear interlayer insulating film 180, the embodiment is not limited thereto. Unlike the illustrated example, one or three or more second upper channel patterns UNS2 may be disposed on the upper surface of the rear interlayer insulating film 180. Although the number of second upper channel patterns UNS2 is shown to be the same as the number of second lower channel patterns BNS2, this is for illustrative purposes only, and the embodiment is not limited thereto.

[0128] The channel separation pattern 115 can be disposed between the first lower channel pattern BNS1 and the first upper channel pattern UNS1. The channel separation pattern 115 can be disposed between the second lower channel pattern BNS2 and the second upper channel pattern UNS2. The channel separation pattern 115 can be spaced apart from the first lower channel pattern BNS1 and the second lower channel pattern BNS2 in the vertical direction DR3. The channel separation pattern 115 can be spaced apart from the first upper channel pattern UNS1 and the second upper channel pattern UNS2 in the vertical direction DR3.

[0129] The channel separation pattern 115 may include an insulating material. For example, the channel separation pattern 115 may include at least one of silicon nitride, silicon carbonitride, silicon boron carbonitride, silicon carbonitride, silicon oxide, silicon oxynitride, and any combination thereof.

[0130] The gate structure GS may surround the first lower channel pattern BNS1 and the first upper channel pattern UNS1. For example, in a cross-sectional view taken along the second horizontal direction DR2 and the vertical direction DR3, the gate structure GS may surround the periphery of the first lower channel pattern BNS1 and the periphery of the first upper channel pattern UNS1. The gate structure GS may surround the channel separation pattern 115. The gate structure GS may surround the second lower channel pattern BNS2 and the second upper channel pattern UNS2. For example, in a cross-sectional view taken along the second horizontal direction DR2 and the vertical direction DR3, the gate structure GS may surround the periphery of the second lower channel pattern BNS2 and the periphery of the second upper channel pattern UNS2.

[0131] The gate electrode 120 may surround the first lower channel pattern BNS1, the first upper channel pattern UNS1, the channel separator pattern 115, the second lower channel pattern BNS2, and the second upper channel pattern UNS2. In other words, the first lower channel pattern BNS1, the first upper channel pattern UNS1, the channel separator pattern 115, the second lower channel pattern BNS2, and the second upper channel pattern UNS2 may penetrate the gate electrode 120.

[0132] The gate structure GS may include an inner gate structure IGS, which is disposed between first lower channel patterns BNS1 adjacent to each other along the vertical direction DR3, between first upper channel patterns UNS1 adjacent to each other along the vertical direction DR3, between the back interlayer insulating film 180 and the first lower channel pattern NS1 adjacent to each other along the vertical direction DR3, between second lower channel patterns BNS2 adjacent to each other along the vertical direction DR3, between second upper channel patterns UNS2 adjacent to each other along the vertical direction DR3, and between the back interlayer insulating film 180 and the second lower pattern NS2 adjacent to each other along the vertical direction DR3.

[0133] The gate insulating film 110 can be disposed between the first lower channel pattern BNS1 and the gate electrode 120, between the first upper channel pattern UNS1 and the gate electrode 120, between the channel separator pattern 115 and the gate electrode 120, between the second lower channel pattern BNS2 and the gate electrode 120, and between the second upper channel pattern UNS2 and the gate electrode 120. The gate insulating film 110 can be disposed along the periphery of the first lower channel pattern BNS1, the periphery of the first upper channel pattern UNS1, the periphery of the channel separator pattern 115, the periphery of the second lower channel pattern BNS2, and the periphery of the second upper channel pattern UNS2.

[0134] Gate spacer 130 may not be disposed between the back interlayer insulating film 180 and the first lower channel pattern BNS1, between the first lower channel patterns BNS1 adjacent to DR3 in the vertical direction, between the back interlayer insulating film 180 and the second lower channel pattern BNS2, or between the second lower channel patterns BNS2 adjacent to DR3 in the vertical direction. Gate spacer 130 may not be disposed between the channel separator pattern 115 and the first upper channel pattern UNS1, between the first upper channel patterns UNS1 adjacent to DR3 in the vertical direction, between the channel separator pattern 115 and the second upper channel pattern UNS2, or between the second upper channel patterns UNS1 adjacent to DR3 in the vertical direction. Gate spacer 130 may not be disposed between the channel separator pattern 115 and the first lower channel pattern BNS1, or between the channel separator pattern 115 and the second lower channel pattern BNS2.

[0135] The lower source / drain pattern 160B can be disposed on the back interlayer insulating film 180. The lower source / drain pattern 160B can be disposed on at least one side surface of the gate electrode 120. The lower source / drain pattern 160B can be disposed between adjacent gate electrodes 120 along the first horizontal direction DR1.

[0136] The lower source / drain pattern 160B can be disposed between the first lower channel pattern BNS1 and the second lower channel pattern BNS2. The lower source / drain pattern 160B can contact the first lower channel pattern BNS1 and the second lower channel pattern BNS2. The lower source / drain pattern 160B can be connected to the ends of the first lower channel pattern BNS1 and the ends of the second lower channel pattern BNS2 that are opposite to each other.

[0137] The upper source / drain pattern 160U can be set on the lower source / drain pattern 160B. The upper source / drain pattern 160U can be spaced apart from the lower source / drain pattern 160B in the vertical direction DR3.

[0138] The upper source / drain pattern 160U can be disposed on at least one side surface of the gate electrode 120. The upper source / drain pattern 160U can be disposed between adjacent gate electrodes 120 along the first horizontal direction DR1.

[0139] The upper source / drain pattern 160U can be disposed between the first upper channel pattern UNS1 and the second upper channel pattern UNS2. The upper source / drain pattern 160U can contact the first upper channel pattern UNS1 and the second upper channel pattern UNS2. The upper source / drain pattern 160U can be connected to the ends of the first upper channel pattern UNS1 and the ends of the second upper channel pattern UNS2 that are opposite to each other.

[0140] The first lower channel pattern BNS1 and the first upper channel pattern UNS1 can be included in transistors of the same conductivity type.

[0141] The lower source / drain pattern 160B may include a first lower layer 161B, a second lower layer 162B, a third lower layer 163B, a fourth lower layer 164B, and a fifth lower layer 165B. The descriptions of the first lower layer 161B, the second lower layer 162B, the third lower layer 163B, the fourth lower layer 164B, and the fifth lower layer 165B can be compared with those using... Figures 1 to 4The descriptions of the first layer 161, second layer 162, third layer 163, fourth layer 164, and fifth layer 165 are essentially the same. The upper source / drain pattern 160U may include the first upper layers 161U_1, 161U_2, 161U_3, and 161U_4, the second upper layer 162U, the third upper layer 163U, the fourth upper layer 164U, and the fifth upper layer 165U. The descriptions of the first upper layers 161U_1, 161U_2, 161U_3, and 161U_4, the second upper layer 162U, the third upper layer 163U, the fourth upper layer 164U, and the fifth upper layer 165U can be the same as those used separately. Figure 14 and Figure 15 The descriptions of the first layer 161_1, 161_2, 161_3 and 161_4, the second layer 162, the third layer 163, the fourth layer 164 and the fifth layer 165 are basically the same.

[0142] In some embodiments, the first lower channel pattern BNS1 and the second lower channel pattern BNS2 can be used as the channel region of a p-type transistor, the lower source / drain pattern 160B can be included in the source / drain of the p-type transistor, and the lower source / drain pattern 160B can include a p-type dopant. The first upper channel pattern UNS1 and the second upper channel pattern UNS2 can be used as the channel region of an n-type transistor, the upper source / drain pattern 160U can be included in the source / drain of the n-type transistor, and the upper source / drain pattern 160U can include an n-type dopant.

[0143] In some other embodiments, the first lower channel pattern BNS1 and the second lower channel pattern BNS2 can be used as the channel region of an n-type transistor, the lower source / drain pattern 160B can be included in the source / drain of the n-type transistor, and the lower source / drain pattern 160B can include an n-type dopant. The first upper channel pattern UNS1 and the second upper channel pattern UNS2 can be used as the channel region of a p-type transistor, the upper source / drain pattern 160U can be included in the source / drain of the p-type transistor, and the upper source / drain pattern 160U can include a p-type dopant.

[0144] The lower front interlayer insulating film 175B can be disposed on the upper surface of the rear interlayer insulating film 180. The lower front interlayer insulating film 175B can cover the lower source / drain pattern 160B.

[0145] The upper source / drain pattern 160U can be disposed on the lower front interlayer insulating film 175B. The lower front interlayer insulating film 175B can be disposed between the lower source / drain pattern 160B and the upper source / drain pattern 160U.

[0146] The lower source / drain etch stop film 170B can extend along the contour of the lower source / drain pattern 160B. The lower source / drain etch stop film 170B can be disposed between the lower source / drain pattern 160B and the lower front interlayer insulating film 175B. The lower source / drain etch stop film 170B can extend along the contour of the upper surface of the rear interlayer insulating film 180.

[0147] Unlike the example shown, the lower source / drain etch stop film 170B may not be placed between the lower source / drain pattern 160B and the lower front interlayer insulating film 175B.

[0148] The lower front spacer 140B can be disposed on the sidewall of the gate spacer 130. The lower front spacer 140B can be disposed between the lower source / drain etch stop film 170B and the channel separation pattern 115.

[0149] The upper front interlayer insulating film 175U can be disposed on the lower front interlayer insulating film 175B. The upper front interlayer insulating film 175U can cover the upper source / drain pattern 160U.

[0150] The upper source / drain etch stop film 170U may be disposed between the upper front interlayer insulating film 175U and the upper source / drain pattern 160U. The upper source / drain etch stop film 170U may extend along at least a portion of the outline of the upper source / drain pattern 160U.

[0151] Unlike the example shown, the upper front interlayer insulating film 175U and the lower front interlayer insulating film 175B may not be separated by the upper source / drain etch stop film 170U.

[0152] The lower front interlayer insulating film 175B and the upper front interlayer insulating film 175U may each comprise at least one of, for example, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, and low dielectric constant materials. The lower source / drain etch stop film 170B and the upper source / drain etch stop film 170U may each comprise at least one of, for example, but not limited to, silicon nitride, silicon oxynitride, silicon carbonitride, silicon boron nitride, silicon boron oxynitride, silicon carbonitride, silicon carbonitride, and any combination thereof.

[0153] The rear contact silicide film 190 can be disposed between the rear source / drain contact 195 and the lower source / drain pattern 160B. The front source / drain contact 295 can be disposed in the upper front interlayer insulating film 175U. The front source / drain contact 295 can be electrically connected to the upper source / drain pattern 160U. The front contact silicide film 290 can be disposed between the front source / drain contact 295 and the upper source / drain pattern 160U.

[0154] Figures 19 to 43 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to one or more embodiments.

[0155] refer to Figure 19 and Figure 20 The lower pattern BP, the field insulating film 105, and the upper pattern structure UP can be formed on the substrate 10.

[0156] The substrate 10 may be bulk silicon or silicon-on-insulator (SOI). In contrast, the substrate 10 may be a silicon substrate, or may include other materials, such as, but not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0157] The lower pattern BP can be disposed on the substrate 10. The lower pattern BP can protrude from the upper surface of the substrate 10 in the vertical direction DR3. The lower patterns BP can be spaced apart in the first horizontal direction DR1.

[0158] A field insulating film 105 can be disposed between the lower patterns BP. The field insulating film 105 can contact the sidewalls of the lower patterns BP and the upper surface of the substrate 10.

[0159] The upper pattern structure UP can be set on the lower pattern BP. The upper pattern structure UP may include multiple sacrificial films SC and multiple active patterns ACT alternately stacked on the lower pattern BP.

[0160] For example, the sacrificial film SC may include a silicon-germanium film, while the active pattern ACT may include a silicon film.

[0161] Next, a dummy gate insulating film 110p, a dummy gate electrode 120p, and a dummy gate capping film 120_HM can be formed on the upper patterned structure UP. The dummy gate insulating film 110p may include, for example, but not limited to, silicon oxide. The dummy gate electrode 120p may include, for example, but not limited to, polysilicon. The dummy gate capping film 120_HM may include, for example, but not limited to, silicon nitride.

[0162] refer to Figure 21 and Figure 22 A pre-gate spacer 130p can be formed on the sidewall of the dummy gate electrode 120p.

[0163] Using a dummy gate electrode 120p as a mask, patterned structures (e.g., ...) can be patterned on top of the structure. Figure 19 and Figure 20 The first hole H1 is formed in the UP. The first hole H1 can be formed in the following pattern (e.g., UP). Figure 19 and Figure 20 In the BP). The pattern below (e.g., Figure 19 and Figure 20 The BP can be separated by a first aperture H1 to form a first lower pattern BP1 and a second lower pattern BP2. Active patterns (e.g., Figure 19 and Figure 20 The ACT can be separated by a first hole H1 to form a first channel pattern NS1 and a second channel pattern NS2.

[0164] Next, a front spacer 140 can be formed on the sidewall of the pre-gate spacer 130p. The front spacer 140 can expose the side surface of the first channel pattern NS1, the side surface of the second channel pattern NS2, and the side surface of the sacrificial film SC.

[0165] Next, a sacrificial pattern 150 can be formed to fill a portion of the first hole H1. The upper surface of the sacrificial pattern 150 can be positioned below the bottom surface of the lowest sacrificial film SC.

[0166] In some embodiments, an epitaxial growth method may be used to form the sacrificial pattern 150. For example, the sacrificial pattern 150 may be grown from the substrate 10 in a bottom-up manner.

[0167] In some embodiments, the sacrificial pattern 150 may include a dielectric material.

[0168] refer to Figure 23 and Figure 24 A pre-sacrificial spacer 151p and a pre-sacrificial filler film 152p can be formed on the sacrificial pattern 150. The pre-sacrificial spacer 151p can extend along the first hole H1 on the sacrificial pattern 150. The pre-sacrificial spacer 151p can extend along the upper surface of the sacrificial pattern 150, the side surface of the first hole H1, and the side surface of the front spacer 140. The pre-sacrificial spacer 151p can extend along the upper surface of the field insulating film 105. The pre-sacrificial filler film 152p can fill the first hole H1 on the pre-sacrificial spacer 151p. The pre-sacrificial filler film 152p can cover the field insulating film 105 on the pre-sacrificial spacer 151p.

[0169] The pre-sacrificial spacer 151p may be made of a material different from that of the front spacer 140. The pre-sacrificial spacer 151p and the front spacer 140 may be made of materials different from each other, such as SiN, SiCN, SiOCN, SiBCN, and SiBN.

[0170] refer to Figure 25 and Figure 26 A portion of the pre-sacrificial spacer 151p and a portion of the pre-sacrificial filler film 152p can be removed to form sacrificial spacer 151 and sacrificial filler film 152. Sacrificial spacer 151 and sacrificial filler film 152 can expose the side surfaces of the first channel pattern NS1, the second channel pattern NS2, and the sacrificial film SC. First aperture (e.g., Figure 23 and Figure 24The area retained on the upper surface of the sacrificial spacer 151 and the upper surface of the sacrificial filling film 152 within H1 can be defined as the second hole H2.

[0171] refer to Figure 27 and Figure 28 Source / drain patterns 160 can be formed on the sacrificial spacer 151 and the sacrificial filler film 152. Source / drain patterns 160 that fill a portion of the second hole H2 can be formed.

[0172] The first layer 161 can be formed by epitaxial growth from the sidewalls of the first channel pattern NS1 and the second channel pattern NS2 in the first horizontal direction DR1. The first layer 161 can be grown in the horizontal direction (e.g., the first horizontal direction DR1 and / or the second horizontal direction DR2). The first layer 161 can be in contact with the first channel pattern NS1 and the second channel pattern NS2. The thickness of the first end of the first layer 161 in contact with the sidewall of the first channel pattern NS1 in the vertical direction DR3, and the thickness of the second end of the first layer 161 in contact with the sidewall of the second channel pattern NS2 in the vertical direction DR3, can be thicker than the thickness of the central portion of the first layer 161 in the vertical direction DR3.

[0173] In some embodiments, the portion grown horizontally from the sidewall of the first channel pattern NS1 and the second portion 161_2 may be combined with the portion grown horizontally from the sidewall of the second channel pattern NS2. The first layer 161 grown horizontally from the first channel pattern NS1 and the second channel pattern NS2 may include a material that provides compressive stress to each of the first channel pattern NS1 and the second channel pattern NS2. For example, when the first channel pattern NS1 and the second channel pattern NS2 are silicon patterns, the first layer 161 may include a material having a smaller lattice constant than silicon (Si) (e.g., silicon carbide (SiC)). The first layer 161 grown horizontally from the first channel pattern NS1 and the second channel pattern NS2 may provide compressive stress to each of the first channel pattern NS1 and the second channel pattern NS2 and may improve carrier mobility in the channel region.

[0174] In some other embodiments, such as in Figure 14 and Figure 15Similarly, the first portion 161_1 can be grown horizontally from the sidewall of the first channel pattern NS1, and the second portion 161_2 can be grown horizontally from the sidewall of the second channel pattern NS2. The first portion 161_1 pattern NS1 grown horizontally from the first channel pattern NS1 can include a material that provides tensile stress to the first channel pattern NS1. For example, when the first channel pattern NS1 and the second channel pattern NS2 are silicon patterns, the first layer 161 can include a material with a larger lattice constant than silicon (Si) (e.g., silicon-germanium (SiGe)). The first portion 161_1 can provide tensile stress to the first channel pattern NS1, and the second portion 161_2 grown horizontally from the second channel pattern NS2 can provide tensile stress to the second channel pattern NS2, thereby improving the carrier mobility in the channel region.

[0175] The second layer 162 can be formed on or below the first layer 161. The third layer 163 can be formed on or above the first layer 161. For example, the second layer 162 and the third layer 163 can be formed by epitaxial growth from the first layer 161. The second layer 162 and the third layer 163 can be in contact with the first layer 161.

[0176] The positions of the topmost part of the second layer 162 and the bottommost part of the third layer 163 are not limited to the positions shown and can vary.

[0177] The fourth layer 164 can be formed on or below the second layer 162. The fifth layer 165 can be formed on or above the third layer 163. For example, the fourth layer 164 can be formed by epitaxial growth from the second layer 162, and the fifth layer 165 can be formed by epitaxial growth from the third layer 163. The fourth layer 164 can be in contact with the sacrificial spacer 151 and the sacrificial filler film 152. The fourth layer 164 can be formed between the sacrificial spacer 151, the sacrificial filler film 152, and the second layer 162.

[0178] Although the upper surface of the fifth layer 165 is shown above the lower surface of the front spacer 140 in the accompanying drawings, the embodiment is not limited thereto. The upper surface of the fifth layer 165 may be disposed on a plane substantially the same as the lower surface of the front spacer 140.

[0179] In a semiconductor device according to some embodiments, the source / drain pattern 160 can be grown horizontally from a first channel pattern NS1 and a second channel pattern NS2. Since the source / drain pattern 160 is not grown from a sacrificial pattern 150, the sacrificial pattern 150 is not limited to semiconductor materials (e.g., silicon-germanium (SiGe)) and can be formed from various materials such as dielectric materials. Therefore, the design freedom (shape, material, etc.) of the sacrificial pattern 150 can be improved. Furthermore, the material of the first layer 161 of the source / drain pattern 160 can be adjusted to apply stress to the first channel pattern NS1 and the second channel pattern NS2.

[0180] refer to Figure 29 and Figure 30 Source / drain etch stop film 170 and front interlayer insulating film 175 can be sequentially formed on source / drain pattern 160.

[0181] refer to Figures 29 to 31 A portion of the front interlayer insulating film 175, a portion of the source / drain etch stop film 170, and the dummy gate cover film 120_HM can be removed to expose the upper surface of the dummy gate electrode 120p. When the upper surface of the dummy gate electrode 120p is exposed, a gate spacer 130 can be formed.

[0182] The dummy gate insulating film 110p and dummy gate electrode 120p can be removed to expose the sacrificial film SC between the gate spacer 130 and the first channel pattern NS1 and the second channel pattern NS2.

[0183] Next, the sacrificial film SC can be removed, and the gate insulating film 110 and the gate electrode 120 can be formed in the space where the sacrificial film SC has been removed. As a result, the gate structure GS and the inner gate structure IGS can be formed. In addition, the gate cover pattern 145 can be formed.

[0184] refer to Figures 31 to 33 The substrate 10, the first lower pattern BP1, and the second lower pattern BP2 can be removed. Therefore, the field insulating film 105 and the sacrificial pattern 150 can be exposed.

[0185] In some embodiments, during the process of removing the substrate 10, the first lower pattern BP1, and the second lower pattern BP2, a portion of the first lower pattern BP1 and / or a portion of the second lower pattern BP2 may be retained. The remaining portions of the first lower pattern BP1 and / or the remaining portions of the second lower pattern BP2 may be converted into the substrate pattern 100.

[0186] In some embodiments, the substrate 10, the first lower pattern BP1, and the second lower pattern BP2 can all be removed. In this case, the substrate pattern 100 may not be formed.

[0187] refer to Figures 32 to 35 A pre-interlayer insulating film 180p can be formed to fill the space from which the substrate 10, the first lower pattern BP1, and the second lower pattern BP2 have been removed. The pre-interlayer insulating film 180p can cover the sacrificial pattern 150, the sacrificial spacer 151, the substrate pattern 100, the field insulating film 105, and the bottommost surface of the inner gate structure IGS.

[0188] refer to Figures 34 to 37 A portion of the post-interlayer insulating film 180p can be etched to expose the sacrificial pattern 150, thereby forming the post-interlayer insulating film 180. For example, a planarization process can be performed on the post-interlayer insulating film 180p until the sacrificial pattern 150 is exposed.

[0189] Next, the sacrificial pattern 150 can be removed to form the third hole H3. The third hole H3 can be defined by the back interlayer insulating film 180 and the sacrificial spacer 151. The sacrificial pattern 150 can be removed only at the location where the back source / drain contact 195 is later formed. That is, the sacrificial pattern 150 at the location where the back source / drain contact 195 is not formed can be retained and not removed.

[0190] refer to Figures 36 to 39 The sacrificial spacer 151 and sacrificial filler 152 can be removed through the third hole H3 to form the fourth hole H4. The fourth hole H4 can be defined by the back interlayer insulating film 180 and the source / drain pattern 160. The source / drain pattern 160 can be exposed through the fourth hole H4. A wet cleaning process can be performed during the process of removing the sacrificial spacer 151 and sacrificial filler 152.

[0191] refer to Figure 40 and Figure 41 A pre-spacer 185p can be formed along the fourth hole H4 and the back interlayer insulating film 180. The pre-spacer 185p can be formed along the contour of the fourth hole H4 and the contour of the lower surface of the back interlayer insulating film 180.

[0192] refer to Figures 40 to 43 A fifth hole H5 can be formed that penetrates a portion of the source / drain pattern 160. The fifth hole H5 can penetrate a portion of the fourth layer 164 and the second layer 162 of the source / drain pattern 160. The fifth hole H5 can expose the source / drain pattern 160.

[0193] The pre-spacer 185p on the lower surface of the back interlayer insulating film 180 and the lower surface of the source / drain pattern 160 can be removed. Therefore, the post-spacer 185 can be formed.

[0194] Next, refer to Figure 42 , Figure 43 , Figure 2 and Figure 3 A post-contact silicide film 190 and a post-source / drain contact 195 can be formed in the fifth hole H5.

[0195] refer to Figure 6 and Figure 7 In some embodiments, it is possible to execute Figure 38 and Figure 29 Immediately after the manufacturing process, vias for exposing the source / drain pattern 160 are formed. The processes for forming the pre-spacer 185p and post-spacer 185 can be omitted. Next, a post-contact silicide film 190 and a post-source / drain contact 195 can be formed in the vias.

[0196] Although exemplary embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be made in various different forms. Those skilled in the art will understand that the present disclosure can be embodied in other specific forms without altering the technical spirit or essential features of the present disclosure. Therefore, the above embodiments should be understood in all respects as illustrative rather than restrictive.

Claims

1. A semiconductor device, the semiconductor device comprising: Back interlayer insulating film; A plurality of first trench patterns are located on the back interlayer insulating film and are spaced apart from each other in the vertical direction; A plurality of second channel patterns are located on the back interlayer insulating film and are spaced apart from each other in the vertical direction, and the plurality of second channel patterns are spaced apart from the plurality of first channel patterns in the first horizontal direction; Source / drain pattern, wherein the source / drain pattern is located between the plurality of first channel patterns and the plurality of second channel patterns; as well as Source / drain contacts connected to the source / drain pattern. The source / drain pattern includes: The first layer that is in contact with the plurality of first channel patterns and the plurality of second channel patterns; The second layer located above or below the first layer; and The third layer located on or above the second layer. The width of the first layer in the vertical direction decreases and then increases along the direction from the plurality of first channel patterns to the plurality of second channel patterns.

2. The semiconductor device according to claim 1, further comprising: A front interlayer insulating film, wherein the front interlayer insulating film is located on the plurality of first channel patterns and the plurality of second channel patterns. The source / drain contact penetrates the front interlayer insulating film and contacts the third layer of the source / drain pattern.

3. The semiconductor device according to claim 2, further comprising: A sacrificial pattern located in the back interlayer insulating film beneath the source / drain pattern.

4. The semiconductor device according to claim 3, further comprising: A sacrificial spacer and a sacrificial filler film, the sacrificial spacer defining a trench between the source / drain pattern and the sacrificial pattern, the sacrificial filler film filling the trench between the source / drain pattern and the sacrificial pattern.

5. The semiconductor device according to claim 3, wherein, The sacrificial pattern includes a dielectric pattern or a semiconductor material.

6. The semiconductor device according to claim 2, further comprising: A front spacer, the front spacer being located between the front interlayer insulating film and the source / drain contacts.

7. The semiconductor device according to claim 1, wherein, The source / drain contact penetrates the back interlayer insulating film and contacts the second layer of the source / drain pattern.

8. The semiconductor device according to claim 7, further comprising: A back spacer, the back spacer being located between the back interlayer insulating film and the source / drain contacts.

9. The semiconductor device according to claim 7, further comprising: A substrate pattern located between the back interlayer insulating film and the source / drain contacts.

10. The semiconductor device according to claim 1, further comprising: A front interlayer insulating film, wherein the front interlayer insulating film is located on the plurality of first channel patterns and the plurality of second channel patterns. The source / drain contact includes a rear source / drain contact and a front source / drain contact. The rear source / drain contact penetrates the rear interlayer insulating film and contacts the second layer of the source / drain pattern. The front source / drain contact penetrates the front interlayer insulating film and contacts the third layer of the source / drain pattern.

11. A semiconductor device, the semiconductor device comprising: Back interlayer insulating film; A plurality of first trench patterns are located on the back interlayer insulating film and are spaced apart from each other in the vertical direction; A plurality of second channel patterns are located on the back interlayer insulating film and are spaced apart from each other in the vertical direction, and the plurality of second channel patterns are spaced apart from the plurality of first channel patterns in the first horizontal direction; Source / drain pattern, wherein the source / drain pattern is located between the plurality of first channel patterns and the plurality of second channel patterns; as well as Source / drain contacts connected to the source / drain pattern. The source / drain pattern includes: The first layer that is in contact with the plurality of first channel patterns and the plurality of second channel patterns; The second layer located above or below the first layer; and A third layer located on or above the first layer, and the third layer comprising the same material as the second layer.

12. The semiconductor device according to claim 11, wherein, Each of the first layer, the second layer, and the third layer includes a dopant, and Wherein, the first concentration of the dopant in the first layer is less than the second concentration of the dopant in the second layer and less than the third concentration of the dopant in the third layer.

13. The semiconductor device according to claim 11, wherein, The first layer includes a first portion that contacts the plurality of first channel patterns and a second portion that contacts the plurality of second channel patterns. The first part and the second part are spaced apart from each other, and The second layer and the third layer are connected to each other.

14. The semiconductor device according to claim 13, wherein, The first layer comprises a material with a lattice constant greater than that of silicon.

15. The semiconductor device according to claim 11, wherein, The second layer is separated from the third layer by the first layer.

16. The semiconductor device according to claim 11, wherein, The first layer comprises a material whose lattice constant is less than that of silicon.

17. The semiconductor device according to claim 11, wherein, The source / drain contact is in contact with the second or third layer of the source / drain pattern.

18. A semiconductor device, the semiconductor device comprising: The first lower channel pattern and the second lower channel pattern are spaced apart from each other in the first horizontal direction. The first upper groove pattern is spaced apart from the first lower groove pattern in the vertical direction; The second upper groove pattern is spaced apart from the second lower groove pattern in the vertical direction; Lower source / drain pattern, wherein the lower source / drain pattern is in contact with the first lower channel pattern and the second lower channel pattern; as well as The upper source / drain pattern is in contact with the first upper channel pattern and the second upper channel pattern. The lower source / drain pattern includes a first lower layer in contact with the first lower channel pattern and the second lower channel pattern, a second lower layer located above or below the first lower layer, and a third lower layer located above or above the first lower layer. The source / drain pattern includes a first upper layer that contacts the first upper channel pattern and the second upper channel pattern, a second upper layer located on or below the first upper layer, and a third upper layer located on or above the first upper layer.

19. The semiconductor device according to claim 18, wherein, The second lower layer and the third lower layer are separated from each other by the first lower layer. The first upper layer includes a first portion that contacts the first upper layer channel pattern and a second portion that contacts the second upper layer channel pattern. The first part and the second part are spaced apart from each other, and The second upper layer and the third upper layer are connected to each other.

20. The semiconductor device of claim 18, further comprising: The rear source / drain contact is in contact with the second lower layer of the lower source / drain pattern; as well as A front source / drain contact, wherein the front source / drain contact is in contact with the third upper layer of the upper source / drain pattern.

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