Wide bandgap semiconductor device and preparation method thereof
By designing an electrical connection structure between a conductive ring and a shielding layer in a wide bandgap semiconductor device, the electric field distribution is optimized, solving the problems of low electric field utilization efficiency and insufficient withstand voltage in existing devices, and achieving efficient electric field utilization and improved withstand voltage performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUBEI JIUFENGSHAN LAB
- Filing Date
- 2026-02-12
- Publication Date
- 2026-05-19
AI Technical Summary
The existing wide bandgap semiconductor device termination structure cannot be adapted to the three-layer superjunction cell, resulting in low electric field utilization efficiency, easy device breakdown, and poor reverse blocking characteristics.
The structure includes a first epitaxial layer, a second epitaxial layer, a superjunction ring pillar, a first shielding layer, a conductive ring, and a first source region. The conductive ring and the shielding layer are electrically connected to form a junction terminal extension structure or a field limiting ring structure, which optimizes the electric field distribution and improves the withstand voltage performance of the terminal region.
This improves the electric field utilization efficiency and voltage withstand performance of the device, solves the problems of insufficient voltage withstand and poor reverse blocking characteristics of traditional terminal structures, and fully leverages the high voltage advantages of wide bandgap semiconductor materials.
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Figure CN122069764A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a wide bandgap semiconductor device and its fabrication method. Background Technology
[0002] In recent years, wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN) have been widely used in the new energy field because they have advantages over silicon (Si) in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. Power devices made from these materials have superior electrical characteristics.
[0003] Currently, superjunction structures are being introduced into the development of wide-bandgap semiconductor power devices as a crucial structural design to break through the one-dimensional performance limits of power devices. The three-layer superjunction cell, consisting of a lower superjunction voltage-bearing layer, a middle shielding layer, and a top switching control structure fabrication layer, has become an important structural form for wide-bandgap semiconductor devices. However, the termination structures of existing wide-bandgap semiconductor devices are mostly based on traditional silicon-based device designs, which cannot be adapted to three-layer superjunction cells. Effective charge balance and electric field control are difficult to achieve in the termination region, easily leading to a significant decrease in the reverse blocking characteristics of the device. This restricts the voltage-bearing performance of three-layer superjunction wide-bandgap semiconductor devices, making them prone to localized breakdown and resulting in low electric field utilization efficiency.
[0004] Therefore, improving the electric field utilization efficiency of wide bandgap semiconductor devices with superjunction structures has become a problem that needs to be solved. Summary of the Invention
[0005] To address the aforementioned issues, this application provides a wide bandgap semiconductor device and its fabrication method, which can improve the breakdown voltage characteristics of the termination region of a wide bandgap semiconductor device with a superjunction structure.
[0006] The embodiments of this application disclose the following technical solutions:
[0007] On the one hand, this application provides a wide bandgap semiconductor device, which includes a cell region and a terminal region;
[0008] The terminal region includes a first epitaxial layer, a second epitaxial layer, a superjunction ring pillar, a first shielding layer, a conductive ring, and a first source region;
[0009] The first epitaxial layer and the second epitaxial layer are stacked along the first direction;
[0010] The superjunction pillar, the first shielding layer, and the conductive ring are arranged along the first direction;
[0011] The superstructure pillars are arranged along a second direction in the first epitaxial layer, and the first direction is perpendicular to the second direction;
[0012] The first shielding layer is disposed on the contact side between the first epitaxial layer and the second epitaxial layer, and connects multiple superjunction pillars;
[0013] The conductive ring is disposed in the second epitaxial layer;
[0014] The first shielding layer is electrically connected to the first source region that penetrates the second epitaxial layer;
[0015] The first epitaxial layer and the second epitaxial layer are configured as the first conductivity type, and the first shielding layer, the superjunction pillar, the conductive ring and the first source region are configured as the second conductivity type.
[0016] In some embodiments, the conductive ring and the first shielding layer are electrically connected.
[0017] In some embodiments, the device further includes a trench formed in a second epitaxial layer, the bottom surface of which contacts a conductive ring.
[0018] In some embodiments, the device further includes a well region located on the side of the second epitaxial layer away from the first epitaxial layer, the well region connecting the first source region and a plurality of conductive rings, and the well region being of a second conductivity type.
[0019] In some embodiments, the length of a single conductive ring along the second direction is greater than the length of the bottom surface of the trench along the second direction.
[0020] In some embodiments, the conductive ring and the superjunction pillar are staggered in a first direction.
[0021] In some embodiments, a single conductive ring is electrically connected to a first source region.
[0022] In some embodiments, the superstructure columns are arranged discontinuously in a third direction; the third direction is perpendicular to the first direction and the second direction.
[0023] In some embodiments, the first shielding layers are arranged discontinuously in a third-direction upward direction, and multiple first shielding layers are interconnected.
[0024] On the other hand, this application also provides a method for fabricating a wide bandgap semiconductor device, the method comprising:
[0025] A first epitaxial layer of a first conductivity type is epitaxially grown on the surface of the initial structure; the initial structure and the first epitaxial layer are stacked along a first direction;
[0026] Multiple superjunction pillars are formed embedded in the first epitaxial layer, and the multiple superjunction pillars are distributed at intervals along the second direction within the first epitaxial layer; the superjunction pillars are of the second conductivity type; the second direction is perpendicular to the first direction;
[0027] A first shielding layer is formed embedded in the first epitaxial layer, and the first shielding layer is located on the side of the superstructure pillar away from the surface of the initial structure.
[0028] A second epitaxial layer of the first conductivity type is epitaxially grown on the side of the first epitaxial layer away from the initial structure;
[0029] A first source region is formed that penetrates the second epitaxial layer. The first source region is of the second conductivity type and is electrically connected to the first shielding layer.
[0030] A conductive ring is formed along the second epitaxial layer, and the conductive ring is of the second conductivity type.
[0031] This application provides a wide bandgap semiconductor device, which includes a cell region and a terminal region. The terminal region includes a first epitaxial layer, a second epitaxial layer, a superjunction pillar, a first shielding layer, a conductive ring, and a first source region. The first and second epitaxial layers are stacked along a first direction. The superjunction pillar, the first shielding layer, and the conductive ring are arranged along the first direction. The superjunction pillars are arranged in the first epitaxial layer along a second direction, with the first direction perpendicular to the second direction. The first shielding layer is disposed on the contact side between the first and second epitaxial layers and connects multiple superjunction pillars. The conductive ring is disposed in the second epitaxial layer. The first shielding layer is electrically connected to the first source region. The first and second epitaxial layers are configured with a first conductivity type, and the first shielding layer, the superjunction pillar, the conductive ring, and the first source region are configured with a second conductivity type.
[0032] Therefore, when the conductive ring is in contact with the first shielding layer, a junction termination extension structure can be formed. Under reverse bias, a potential distribution that gradually decreases from the termination region to the cell region is formed in the termination region. This gradient distribution, in conjunction with the potential of the epitaxial layer, allows the electric field to spread uniformly, effectively improving the breakdown voltage performance of the device's termination region and enhancing the device's electric field utilization efficiency. When the conductive ring is not in contact with the first shielding layer, a field limiting ring structure can be formed, optimizing the electric field distribution on the surface of the termination region. Combined with the superjunction structure, this significantly improves the overall breakdown voltage of the termination region, fully leveraging the high voltage advantage of wide bandgap semiconductor materials. This solves the technical problems of insufficient breakdown voltage and poor reverse blocking characteristics in traditional termination structures, and improves the device's electric field utilization efficiency. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 A side cross-sectional view of a wide bandgap semiconductor device provided in an embodiment of this application;
[0035] Figure 2A side cross-sectional view of another wide bandgap semiconductor device provided in an embodiment of this application;
[0036] Figure 3 A side cross-sectional view of another wide bandgap semiconductor device provided in an embodiment of this application;
[0037] Figure 4 A side cross-sectional view of another wide bandgap semiconductor device provided in an embodiment of this application;
[0038] Figure 5 A side cross-sectional view of another wide bandgap semiconductor device provided in an embodiment of this application;
[0039] Figure 6 A side cross-sectional view of another wide bandgap semiconductor device provided in an embodiment of this application;
[0040] Figure 7 A side cross-sectional view of another wide bandgap semiconductor device provided in an embodiment of this application;
[0041] Figure 8 A side cross-sectional view of another wide bandgap semiconductor device provided in an embodiment of this application;
[0042] Figure 9 A top perspective view of a wide bandgap semiconductor device provided for an embodiment of this application;
[0043] Figure 10 Another wide bandgap semiconductor device provided in the embodiments of this application;
[0044] Figure 11 A flowchart illustrating a method for fabricating a wide bandgap semiconductor device is provided in this application embodiment;
[0045] Figures 12-21 This is a schematic diagram of the structure corresponding to a wide bandgap semiconductor device fabrication process provided in an embodiment of this application.
[0046] Figure reference numerals: 11-cell region; 12-terminal region; 100-substrate; 101-first epitaxial layer; 102-second epitaxial layer; 103-superjunction pillar; 104-first shielding layer; 105-conductive ring; 106-first source region; 107-well region; 108-second source region; 109-gate structure; 1091-gate dielectric layer; 1092-polysilicon layer; 110-second shielding layer; 111-back electrode; T1-gate trench; T2-trench; 10-wide bandgap semiconductor device. Detailed Implementation
[0047] The wide bandgap semiconductor device and its fabrication method provided in this application can be used in the semiconductor field. The above are merely examples and do not limit the application field of the wide bandgap semiconductor device and its fabrication method provided in this application.
[0048] The terms "first," "second," "third," and "fourth," etc., used in this application specification, claims, and drawings are used to distinguish different objects, not to limit a specific order.
[0049] In the embodiments of this application, the terms "as an example" or "for example" are used to indicate that they are examples, illustrations, or explanations. Any embodiment or design that is described as "as an example" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of terms such as "as an example" or "for example" is intended to present the relevant concepts in a specific manner.
[0050] The terminology used in the implementation section of this application is for the purpose of explaining specific embodiments of this application only, and is not intended to limit this application.
[0051] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0052] This application provides a wide bandgap semiconductor device, such as... Figure 1 As shown, Figure 1 This is a side cross-sectional view of a wide bandgap semiconductor device 10 provided in an embodiment of this application.
[0053] like Figure 1 As shown, the device includes a cell region 11 and a terminal region 12; the terminal region 12 includes a first epitaxial layer 101, a second epitaxial layer 102, a superjunction pillar 103, a first shielding layer 104, a conductive ring 105, and a first source region 106.
[0054] In this embodiment, the first epitaxial layer 101 and the second epitaxial layer 102 are configured with a first conductivity type, and the first shielding layer 104, superjunction pillar 103, conductive ring 105, and first source region 106 are configured with a second conductivity type. In the following embodiments of this application, the first conductivity type is N-type and the second conductivity type is P-type, as an example.
[0055] Specifically, cell region 11 is the core switching and conductive functional region of the device, and terminal region 12 is the voltage withstand protection functional region of the device. The two work together to enable the wide bandgap semiconductor device 10 to operate stably in high-power, high-voltage, and high-frequency scenarios. This device can be fabricated based on wide bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN).
[0056] The first epitaxial layer 101 and the second epitaxial layer 102 are stacked along the first direction Y.
[0057] Specifically, the N-type first epitaxial layer 101 and the N-type second epitaxial layer 102 are stacked sequentially along the first direction Y. The thickness of the epitaxial layer can be adapted to the voltage withstand requirements of the device.
[0058] The superstructure pillar 103, the first shielding layer 104, and the conductive ring 105 are arranged along the first direction Y.
[0059] For example, the P-type superjunction pillar 103, the P-type first shielding layer 104, and the P-type conductive ring 105 are arranged sequentially along the first direction Y. The P-type superjunction pillar 103 and the N-type first epitaxial layer 101, the P-type first shielding layer 104 and the N-type first epitaxial layer 101, and the P-type conductive ring 105 and the N-type second epitaxial layer 102 form a PN junction composite structure of the terminal region 12 along the first direction Y, which can ensure the conduction of electrical signals along the first direction Y and the continuous modulation of the electric field.
[0060] The superstructure pillars 103 are arranged along the second direction X in the first epitaxial layer 101, and the first direction Y is perpendicular to the second direction X.
[0061] For example, the superjunction pillar 103 is disposed inside the first epitaxial layer 101. In this embodiment, the superjunction pillar 103 is P-type and the first epitaxial layer 101 is N-type. The superjunction pillar 103 is arranged along the second direction X in the first epitaxial layer 101, which is equivalent to the periodic distribution of N-type pillars and P-type pillars to form a superjunction structure. This can promote the terminal region 12 to maintain the same charge balance as the cell region 11, reduce the risk of premature device breakdown due to uneven charge distribution, and at the same time ensure the uniformity of the electric field distribution in the terminal region 12.
[0062] The first shielding layer 104 is disposed on the contact side between the first epitaxial layer 101 and the second epitaxial layer 102, and connects multiple superstructure pillars 103.
[0063] For example, the first shielding layer 104 is disposed at the contact interface between the first epitaxial layer 101 and the second epitaxial layer 102. The first shielding layer 104 connects multiple superjunction pillars 103, which can integrate the discrete superjunction pillars 103 into a whole conductive structure, realize the potential synchronization between each superjunction pillar 103, and avoid the local electric field concentration caused by the large potential difference of a single superjunction pillar 103.
[0064] The conductive ring 105 is disposed in the second epitaxial layer 102.
[0065] For example, the conductive ring 105 is embedded inside the second epitaxial layer 102. The number of conductive rings 105 can be one or more. Multiple conductive rings 105 can be periodically arranged in the second epitaxial layer 102 along the second direction X. The conductive rings 105 can be electrically connected to the first shielding layer 104, or can be spaced apart from the first shielding layer 104 in the first direction Y.
[0066] The first shielding layer 104 is electrically connected to the first source region 106 that penetrates the second epitaxial layer 102.
[0067] For example, the external electrical signal of the first source region 106 can be transmitted to all superjunction pillars 103 through the first shielding layer 104, thereby achieving unified control of the potential of the superjunction pillars 103 in the terminal region 12, and then modulating the electric field of the terminal region 12 through potential adjustment.
[0068] refer to Figure 1 Taking the conductive ring 105 and the first shielding layer 104 as an example, the conductive ring 105 and the first shielding layer 104 being spaced apart in the first direction Y can form a field limiting ring structure.
[0069] The PN junction formed by the adjacent conductive rings 105 and the second epitaxial layer 102 will successively share the reverse bias voltage of the terminal region 12, so that the electric field peak is gradually dispersed and reduced from the terminal edge to the cell region 11, eliminating local electric field spikes, ensuring that the electric field strength at any position of the terminal region 12 does not exceed the breakdown field strength of the wide bandgap semiconductor material, and fundamentally avoiding premature breakdown of the device.
[0070] This embodiment of the application forms a field-limiting ring structure by setting a conductive ring 105 in the second epitaxial layer 102. This combines the charge balance characteristics of the superjunction structure with the electric field modulation characteristics of the field-limiting ring. That is, the periodic arrangement of the superjunction pillars 103 in the first epitaxial layer 101 maintains the charge balance in the terminal region 12, while the field-limiting ring optimizes the electric field distribution on the surface of the terminal region 12. The two work together to significantly improve the overall withstand voltage of the terminal region 12, giving full play to the high voltage advantage of the wide bandgap semiconductor material. This solves the technical problems of insufficient withstand voltage and poor reverse blocking characteristics of traditional terminal structures, improves the electric field utilization efficiency of the device, and achieves high terminal efficiency.
[0071] refer to Figure 2 Taking the electrical connection between the conductive ring 105 and the first shielding layer 104 as an example, when the conductive ring 105, the first shielding layer 104, and the superjunction pillar 103 are electrically connected, they form an integrated P-type conductive network. The first shielding layer 104, due to its inherent thin-film resistance, acts as a voltage divider in this network. Since this network is connected to the first source region 106 in cell region 11, and the voltage of the first source region 106 is zero, under reverse bias, when current flows from the high-voltage side to the first source region 106, a voltage drop is generated on the first shielding layer 104. This causes the conductive ring 105 and the superjunction pillar 103 connected to it at different positions in the second direction X of the terminal region 12 to obtain different ground potentials; that is, those farther from the first source region 106 have higher potentials, and those closer to the first source region 106 have lower potentials. This results in a potential distribution in the terminal region 12 that gradually decreases from the terminal region 12 to the cell region 11. The gradient distribution, combined with the potential of the N-type epitaxial layer, allows the electric field to be spread uniformly, effectively improving the withstand voltage performance of the device terminal region 12 and enhancing the electric field utilization efficiency of the device.
[0072] In some embodiments, such as Figure 1 As shown, the wide bandgap semiconductor device 10 further includes: a well region 107, a second source region 108, a gate trench T1, a gate structure 109, and a second shielding layer 110 located within the device cell region 11.
[0073] The second source region 108 is disposed on the side of the second epitaxial layer 102 away from the first epitaxial layer 101. The second source region 108 is configured with a first conductivity type, and the well region 107 is configured with a second conductivity type. The well region 107 is disposed on the side of the second source region 108 close to the first epitaxial layer 101.
[0074] The gate trench T1 is embedded in the second epitaxial layer 102 and extends through the second source region 108 and the well region 107.
[0075] The gate structure 109 is located in the gate trench T1. The gate structure 109 includes a gate dielectric layer formed on the surface of the gate trench T1 and a polysilicon layer formed in the gate dielectric layer.
[0076] The second shielding layer 110 is located on the side of the gate trench T1 near the first epitaxial layer 101.
[0077] In some embodiments, such as Figure 2 As shown, the conductive ring 105 and the first shielding layer 104 are electrically connected.
[0078] For details, please refer to Figure 2When the conductive ring 105, the first shielding layer 104, and the superjunction pillar 103 are electrically connected, the P-type first shielding layer 104, the P-type conductive ring 105, and the N-type second epitaxial layer 102 located between the P-type conductive rings 105 together constitute a junction termination extension (JTE) structure. The first shielding layer 104, due to its inherent thin-film resistance, acts as a voltage divider in this structure. Since this structure connects the cell region 11 to the first source region 106, and the voltage of the first source region 106 is zero, under reverse bias, when current flows from the high-voltage side to the first source region 106, a voltage drop will occur on the first shielding layer 104. This results in different ground potentials for the conductive rings 105 and the superjunction pillars 103 located at different positions in the second direction X of the terminal region 12. Specifically, the potential is higher for the rings farther from the first source region 106 and lower for the rings closer to the first source region 106, thus naturally forming a gradually decreasing potential distribution from the outside to the inside in the terminal region 12. This gradient distribution, combined with the potential of the N-type epitaxial layer, allows the electric field to spread uniformly, effectively improving the breakdown voltage performance of the device terminal region 12 and enhancing the electric field utilization efficiency of the device.
[0079] In some embodiments, such as Figure 5 As shown, the terminal region 12 of the device also includes a well region 107. The well region 107 is located on the side of the second epitaxial layer 102 away from the first epitaxial layer 101. The well region 107 connects the first source region 106 and multiple conductive rings 105. The well region 107 is of the second conductivity type.
[0080] For details, please refer to Figure 5 The P-type well region 107 and the first shielding layer 104 have lateral resistance, i.e., resistance along the second direction X. Under reverse bias, the connection points in the well region 107 at different distances from the first source region 106 correspond to different voltage drops, forming a potential gradient. This causes the P-type conductive rings 105 at different lateral positions in the terminal region 12 to generate ground potentials that gradually decrease from the terminal region 12 to the cell region 11, thereby optimizing the terminal electric field, reducing the probability of premature breakdown at the device edge, and improving the device's withstand voltage performance. In some embodiments, such as Figure 8 As shown, a conductive ring 105 is provided in the terminal region 12, and the conductive ring 105 is electrically connected to the first source region 106.
[0081] The length of a single conductive ring 105 along the second direction X is not less than the length of the first shielding layer 104 along the second direction X. The single P-type ring 105, the N-type second epitaxial layer 102, and the P-type first shielding layer 104 together constitute a double resurf JTE structure, which can optimize the electric field distribution of the terminal region 12 and improve its breakdown voltage.
[0082] In some embodiments, such as Figure 3As shown, the device also includes a trench T2, which is formed in the second epitaxial layer 102 within the terminal region 12, and the bottom surface of the trench T2 is in contact with the conductive ring 105.
[0083] like Figure 3 As shown, the P-type conductive ring 105 and the N-type second epitaxial layer 102 constitute a field-limiting ring structure. By forming a trench T2 in the second epitaxial layer 102 and placing the conductive ring 105 at the bottom of the trench T2, the insulating sidewalls of the trench T2 cause the electric field lines, originally concentrated on the surface of the second epitaxial layer 102, to bend and extend towards the bottom and sidewalls of the trench T2, increasing the effective path length of the electric field lines. This effectively reduces the peak surface electric field in the field-limiting ring structure, making the breakdown voltage of the terminal region 12 closer to the theoretical breakdown value of the bulk material, directly improving the reverse blocking characteristics of the device. As an example, the trench T2 can be filled with an insulating dielectric.
[0084] In another case, such as Figure 4 As shown, after the P-type first shielding layer 104, the P-type conductive ring 105, and the N-type second epitaxial layer 102 located between the P-type conductive rings 105 together constitute the JTE structure, a trench T2 can be further formed in the second epitaxial layer 102. The insulating sidewalls of the trench T2 will form a new potential boundary, causing the electric field lines originally concentrated on the surface of the JTE structure to bend and stretch towards the bottom and sidewalls of the trench T2, dispersing the single electric field peak to the edge of the trench T2, making the electric field distribution on the surface of the terminal region 12 smoother, further reducing the electric field strength at the edge of the JTE structure junction, and significantly improving the device's withstand voltage limit. As an example, the trench T2 can be filled with an insulating dielectric.
[0085] In some embodiments, such as Figure 6 As shown, the length of a single conductive ring 105 along the second direction X is greater than the length of the bottom surface of the trench T2 along the second direction X.
[0086] Compared to forming multiple discrete conductive rings 105 whose width and spacing require precise control, the ion implantation process required to fabricate a continuous conductive ring 105 along the second direction X is simpler, reducing process difficulty and improving device manufacturing yield. Simultaneously, the length of a single conductive ring 105 along the second direction X is greater than the length of the bottom surface of the trench T2 along the second direction X, effectively increasing the depletion region extension and further reducing the electric field strength of the terminal region 12.
[0087] In another case, such as Figure 7 As shown, the length of a single conductive ring 105 along the second direction X is less than the length of the bottom surface of the trench T2 along the second direction X. When the edge space of the device is small, this structural design ensures the most efficient electric field control within a minimal lateral extension range, achieving the highest area efficiency.
[0088] In some embodiments, such as Figure 4 As shown, multiple conductive rings 105 and multiple superjunction pillars 103 are staggered in the first direction Y.
[0089] It is understandable that during the process of ion implantation to form the conductive ring 105 and the superstructure pillar 103, there may be process deviations such as ion implantation metering deviation or ion diffusion inhomogeneity. This structural design allows for a large alignment error without significantly affecting the terminal withstand voltage, thus improving the manufacturing yield.
[0090] In some embodiments, such as Figure 9 As shown, the superstructure columns 103 are intermittently arranged in the third direction Z, which is perpendicular to the first direction Y and the second direction X.
[0091] Specifically, the discontinuous arrangement of the superjunction pillars 103 helps improve the heat distribution in the terminal region 12, avoids local overheating, and improves the reliability of the device at high temperatures. At the same time, the cross-sectional shape of the superjunction pillars 103 in the first direction Y can be varied, such as rectangular, circular, or hexagonal, which can be flexibly selected according to the process capability, enhancing design flexibility.
[0092] In some embodiments, such as Figure 10 As shown, the first shielding layer 104 is intermittently arranged in the third direction Z, and multiple first shielding layers 104 are interconnected.
[0093] Specifically, the superjunction pillars 103 are periodically and discretely arranged. The continuous whole layer of the first type shielding layer 104 will cause excessive P-type doping in the terminal region 12, which may result in the P-type charge density in the terminal region 12 being higher than the charge density of the N-type epitaxial layer, thus disrupting the charge balance of the superjunction. The first shielding layer 104 is intermittently arranged in the third direction Z, forming a ring structure along the second direction X, which can reduce the probability of local breakdown caused by charge imbalance.
[0094] Furthermore, the continuous first shielding layer 104 requires large-area, highly uniform ion implantation, while large-area, high-concentration P-type implantation of wide-bandgap semiconductors is prone to doping unevenness. The annularly connected first shielding layer 104 divides the implantation region into multiple annular small regions, resulting in a smaller implantation area and easier control of uniformity.
[0095] This application also provides a method for fabricating a wide-bandgap semiconductor device, such as... Figure 11 As shown, Figure 11 This is a flowchart illustrating a method for fabricating a wide bandgap semiconductor device, as provided in an embodiment of this application. Figures 12-21 This is a schematic diagram of the structure corresponding to a wide bandgap semiconductor device fabrication process provided in an embodiment of this application.
[0096] like Figure 11As shown, the preparation method includes the following steps S10 to S60:
[0097] Step S10: As Figure 12 As shown, a first epitaxial layer 101 of a first conductivity type is epitaxially grown on the surface of the initial structure; the initial structure and the first epitaxial layer 101 are stacked along the first direction Y.
[0098] For example, refer to Figure 12 The initial structure includes at least one substrate 100, which can be a single-crystal semiconductor material of a first conductivity type, such as silicon (Si), silicon carbide (SiC), or gallium arsenide (GaAs).
[0099] An epitaxial layer 101 is grown on the surface of a substrate 100 along a first direction Y using an epitaxial growth process, such as chemical vapor deposition (CVD). The first epitaxial layer 101 has a first conductivity type, such as N-type, and the thickness and doping concentration of the first epitaxial layer 101 can be designed and controlled according to the target blocking voltage.
[0100] Step S20: As Figure 12 As shown, a plurality of superjunction pillars 103 are formed embedded in the first epitaxial layer 101, and the plurality of superjunction pillars 103 are distributed at intervals along the second direction X within the first epitaxial layer 101; the superjunction pillars 103 are of the second conductivity type; the second direction X is perpendicular to the first direction Y.
[0101] For example, refer to Figure 12 A groove structure with a specific pattern can be formed on the surface of the first epitaxial layer 101 through photolithography and etching processes. The groove structure is arranged along the second direction X, that is, the transverse direction of the device, at a preset spacing and width interval. The second direction X is perpendicular to the aforementioned first direction Y. Then, a second conductivity type, such as a P-type semiconductor material, can be used for epitaxial filling to form a P-type superjunction pillar 103.
[0102] Alternatively, a P-type superjunction pillar 103 can be formed by photolithography to create a mask, define the ion implantation region, and perform P+ ion implantation.
[0103] Step S30: As Figure 13 As shown, a first shielding layer 104 is formed embedded in the first epitaxial layer 101. The first shielding layer 104 is located on the side of the superjunction pillar 103 away from the surface of the substrate 100, and the first shielding layer 104 and the superjunction pillar 103 are electrically connected.
[0104] For example, refer to Figure 13 A mask is formed by photolithography, an ion implantation region is defined, and P+ ion implantation is performed to form a first shielding layer 104 embedded in the first epitaxial layer 101. The first shielding layer 104 and the superjunction pillar 103 are electrically connected.
[0105] Step S40: As Figure 14 As shown, a second epitaxial layer 102 of a first conductivity type is epitaxially grown on the side of the first epitaxial layer 101 away from the substrate 100.
[0106] For example, refer to Figure 14 The second epitaxial layer 102 can be epitaxially grown on the side of the first epitaxial layer 101 away from the substrate 100 using processes such as chemical vapor deposition or molecular beam epitaxy. Both the second epitaxial layer 102 and the first epitaxial layer 101 are N-type, and the doping concentration and thickness of the second epitaxial layer 102 can be independently designed according to the device function.
[0107] Step S50: As Figure 15 As shown, a first source region 106 is formed that penetrates the second epitaxial layer 102. The first source region 106 is of the second conductivity type and is electrically connected to the first shielding layer 104.
[0108] For example, refer to Figure 15 A mask is formed by photolithography, an ion implantation region is defined, and P+ ion implantation is performed to form a first source region 106 in the second epitaxial layer 102. The first source region 106 is electrically connected to the first shielding layer 104.
[0109] Step S60: As Figure 1 As shown, a conductive ring 105 is formed within the second epitaxial layer 102, and the conductive ring 105 is of the second conductivity type.
[0110] For example, refer to Figure 1 A photolithography process is used to form a mask, define ion implantation regions, and perform P+ ion implantation to form conductive rings 105 spaced apart along the second direction X within the second epitaxial layer 102. The conductive rings 105 and the first shielding layer 104 are spaced apart along the first direction Y.
[0111] In another case, refer to Figure 2 A photolithography process is used to form a mask, define ion implantation regions, and perform P+ ion implantation to form conductive rings 105 spaced at intervals along the second direction X within the second epitaxial layer 102. The conductive rings 105 are electrically connected to the first shielding layer 104.
[0112] In some embodiments, the preparation method after step S50 and before step S60 further includes steps S51 to S56:
[0113] Step S51: As Figure 15 As shown, a mask can be formed by photolithography, an ion implantation region can be defined, and N+ ion implantation can be performed to form a second source region 108. The second source region 108 is disposed on the side of the second epitaxial layer 102 away from the first epitaxial layer 101.
[0114] After removing the mask, a new mask is formed using photolithography, and the ion implantation region is defined. P+ ion implantation forms the well region 107, which is located on the side of the second source region 108 near the first epitaxial layer 101. (Refer to...) Figure 17 .
[0115] Step S52: As Figure 16 As shown, a gate trench T1 is formed within the second epitaxial layer 102, and the gate trench T1 penetrates the second source region 108 and the well region 107.
[0116] Step S53: As Figure 17 As shown, a P-type second shielding layer 110 is formed at the bottom of the gate trench T1 by ion implantation. The second shielding layer 110 is located on the side of the gate trench T1 near the first epitaxial layer 101.
[0117] Step S54: As Figure 18 As shown, trench T2 is formed through an etching process.
[0118] It should be noted that the reference Figure 19 A semiconductor device with a trench T2 structure can form a P-type conductive ring 105 at the bottom of the trench T2 by ion implantation after the trench T2 is formed.
[0119] Step S55: As Figure 20 As shown, a gate structure 109 is formed within a gate trench T1. The gate structure 109 includes a gate dielectric layer 1091 formed on the surface of the gate trench T1 and a polysilicon layer 1092 formed within the gate dielectric layer 1091.
[0120] Step S56: Reference Figure 20 A dielectric layer is filled into the trench T2.
[0121] In some embodiments, the preparation method further includes the following after step S60:
[0122] Step S61: Reference Figure 21 A back electrode 111 is deposited on the side of the substrate 100 away from the first epitaxial layer 101.
[0123] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the structural embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the structural embodiments. The method embodiments described above are merely illustrative, and some or all of the steps can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement them without creative effort.
[0124] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A wide bandgap semiconductor device, characterized in that, The device includes a cell region and a terminal region; The terminal region includes a first epitaxial layer, a second epitaxial layer, a superjunction pillar, a first shielding layer, a conductive ring, and a first source region; The first epitaxial layer and the second epitaxial layer are stacked along a first direction; The superjunction pillar, the first shielding layer, and the conductive ring are arranged along the first direction; The superstructure pillars are arranged in the first epitaxial layer along a second direction, wherein the first direction is perpendicular to the second direction; The first shielding layer is disposed on the contact side between the first epitaxial layer and the second epitaxial layer, and connects the plurality of superjunction pillars; The conductive ring is disposed in the second epitaxial layer; The first shielding layer is electrically connected to the first source region that penetrates the second epitaxial layer; Wherein, the first epitaxial layer and the second epitaxial layer are configured as a first conductivity type, and the first shielding layer, the superjunction pillar, the conductive ring and the first source region are configured as a second conductivity type.
2. The device according to claim 1, characterized in that, The conductive ring is electrically connected to the first shielding layer.
3. The device according to claim 2, characterized in that, The device further includes a well region located on the side of the second epitaxial layer away from the first epitaxial layer. The well region connects the first source region and the plurality of conductive rings, and the well region is of a second conductivity type.
4. The device according to claim 1, characterized in that, The conductive ring and the superjunction pillar are staggered in the first direction.
5. The device according to claim 2, characterized in that, Each of the conductive rings is electrically connected to the first source region.
6. The device according to claim 1, characterized in that, The device further includes a trench formed in the second epitaxial layer, the bottom surface of which contacts the conductive ring.
7. The device according to claim 6, characterized in that, The length of a single conductive ring along the second direction is greater than the length of the bottom surface of the trench along the second direction.
8. The device according to claim 1, characterized in that, The superstructure columns are intermittently arranged in a third direction; the third direction is perpendicular to the first direction and the second direction.
9. The device according to claim 1, characterized in that, The first shielding layers are arranged intermittently in a third direction, and multiple first shielding layers are interconnected.
10. A method for fabricating a wide bandgap semiconductor device, characterized in that, The method includes: A first epitaxial layer of a first conductivity type is epitaxially grown on the surface of an initial structure; the initial structure and the first epitaxial layer are stacked along a first direction; Multiple superjunction pillars are formed embedded in the first epitaxial layer, and the multiple superjunction pillars are spaced apart in the first epitaxial layer along a second direction; the superjunction pillars are of a second conductivity type; the second direction is perpendicular to the first direction; A first shielding layer is formed embedded in the first epitaxial layer, and the first shielding layer is located on the side of the superstructure pillar away from the surface of the initial structure. A second epitaxial layer of a first conductivity type is epitaxially grown on the side of the first epitaxial layer opposite to the initial structure; A first source region is formed that penetrates the second epitaxial layer. The first source region is of the second conductivity type and is electrically connected to the first shielding layer. A conductive ring is formed within the second epitaxial layer, the conductive ring being of a second conductivity type.