Radio frequency device three-dimensional integrated packaging structure and preparation method thereof
By using back-to-back chip bonding and a metal interconnect layer design, the problems of complex integration processes and large package sizes in existing RF modules are solved, enabling low-cost, high-efficiency three-dimensional integrated packaging of RF devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU KEYANG SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2026-04-23
- Publication Date
- 2026-05-19
AI Technical Summary
The integration process of existing RF modules is complex, requiring the fabrication of conductive vias and buried trenches on the substrate, resulting in large package size, high cost, and severe heat accumulation in the chip.
The chip is directly back-to-back bonded, and the chip is stacked and integrated through a fence support layer and a metal interconnect layer, avoiding the design of conductive vias and buried trenches on the substrate. The metal interconnect vias are formed using conventional photolithography processes.
The packaging size and thickness have been reduced, which has lowered the difficulty and cost of the process, reduced the accumulation of heat in the chip, and improved the processing efficiency.
Smart Images
Figure CN122069773A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip packaging technology, and more specifically, to a three-dimensional integrated packaging structure for radio frequency devices and its fabrication method. Background Technology
[0002] Currently, the integration of RF modules mainly relies on surface mount technology (SMT), which integrates active and passive components that make up the RF front-end module on organic substrates or low-temperature co-fired ceramic substrates. This typically requires the fabrication of buried trenches on the substrate to accommodate the chip, and additional conductive vias. However, the substrate fabrication process for chip embedding is complex, requiring separate fabrication of conductive vias and buried trenches, resulting in complex processes and high costs. Furthermore, the introduction of a substrate and the design of buried trenches on it contributes to the overall large package size. Summary of the Invention
[0003] The purpose of this invention is to provide a three-dimensional integrated packaging structure for radio frequency devices and its fabrication method. It eliminates the need for a substrate, enables direct back-to-back chip bonding, reduces packaging size, and eliminates the need for separate design of conductive vias and buried grooves on the substrate, thereby reducing process difficulty and cost, and shrinking packaging size.
[0004] The embodiments of the present invention are implemented through the following technical solutions: In a first aspect, the present invention provides a three-dimensional integrated packaging structure for radio frequency devices, comprising: The first and second chips are spaced apart; A first fence support layer covering the first chip and the second chip, wherein the back sides of the first chip and the second chip are located on the same plane and are both exposed outside the first fence support layer; A first coating layer disposed on the first fence support layer; A first metal interconnect layer is disposed in the first coating layer, and the first metal interconnect layer is electrically connected to the first chip and the second chip; A third chip and a fourth chip are spaced apart, wherein the back side of the third chip is bonded to the back side of the first chip, and the back side of the fourth chip is bonded to the back side of the second chip; A second fence support layer covering the third chip and the fourth chip; A second coating layer is disposed on the side of the second fence support layer away from the first fence support layer; A second metal interconnect layer is disposed in the second coating layer, and the second metal interconnect layer is electrically connected to the third chip and the fourth chip; The first fence support layer is provided with a first interconnecting hole, and the first metal interconnecting layer extends to the first interconnecting hole. The second fence support layer is provided with a corresponding second interconnecting hole, and the second metal interconnecting layer extends to the second interconnecting hole. The first interconnecting hole and the second interconnecting hole are connected to each other so that the first metal interconnecting layer and the second metal interconnecting layer are electrically connected.
[0005] In an optional embodiment, the front side of the first chip is provided with a first electrode and a first functional area, the first electrode is located around the first functional area, the first fence support layer covers the front side of the first chip and avoids the first electrode and the first functional area, and a first cavity is formed between the first coating layer and the first functional area, and the first metal interconnect layer is electrically connected to the first electrode. And / or, the front side of the second chip is provided with a second electrode and a second functional area, the second electrode is located around the second functional area, the first fence support layer covers the front side of the second chip and avoids the second electrode and the second functional area, and a second cavity is formed between the first coating layer and the second functional area, and the first metal interconnect layer is electrically connected to the second electrode.
[0006] In an optional embodiment, the front side of the third chip is provided with a third electrode and a third functional area. The third electrode is located around the third functional area. The second fence support layer covers the front side of the third chip and avoids the third electrode and the third functional area. A third cavity is formed between the second coating layer and the third functional area. The second metal interconnect layer is electrically connected to the third electrode. And / or, the front side of the fourth chip is provided with a fourth electrode and a fourth functional area, the fourth electrode is located around the fourth functional area, the second fence support layer covers the front side of the fourth chip and avoids the fourth electrode and the fourth functional area, and a fourth cavity is formed between the second coating layer and the fourth functional area, and the second metal interconnect layer is electrically connected to the fourth electrode.
[0007] In an optional embodiment, a permanent bonding layer is formed on the back side of the first chip and the back side of the second chip, the back side of the third chip is adhered to the back side of the first chip through the permanent bonding layer, and the back side of the fourth chip is adhered to the back side of the second chip through the permanent bonding layer.
[0008] In an optional embodiment, a molding layer is further provided on the side of the first coating layer away from the second coating layer, the molding layer covering the first metal interconnect layer, and a plurality of solder balls are further provided on the side of the second metal interconnect layer away from the first metal interconnect layer.
[0009] In an optional embodiment, a surface passivation layer is further provided on the side of the second coating layer away from the first coating layer. The surface passivation layer has multiple windows that partially expose the second metal interconnect layer, and the multiple solder balls are correspondingly disposed in the multiple windows.
[0010] In an optional embodiment, the width of the third chip is smaller than the width of the first chip, and the back side of the third chip is bonded to the center of the back side of the first chip; and / or, the width of the fourth chip is smaller than the width of the second chip, and the back side of the fourth chip is bonded to the center of the back side of the second chip.
[0011] In an optional implementation, the thickness of the first chip is the same as the thickness of the second chip; and / or, the thickness of the third chip is the same as the thickness of the fourth chip.
[0012] Secondly, the present invention provides a method for fabricating a three-dimensional integrated packaging structure for radio frequency devices, used to fabricate the three-dimensional integrated packaging structure for radio frequency devices as described in the foregoing embodiments, the method comprising: The back sides of the first chip and the back sides of the second chip are bonded together on a temporary substrate with a gap between them; A first fence support layer is formed on the temporary substrate to cover the first chip and the second chip, wherein a first interconnect via is provided in the first fence support layer; A first coating layer is formed on the first fence support layer, wherein the first coating layer has windows to avoid the first interconnecting through-hole; A first metal interconnect layer is formed in the first coating layer, wherein the first metal interconnect layer is electrically connected to the first chip and the second chip and extends to the first interconnect via; Remove the temporary substrate so that the back sides of the first chip and the second chip are on the same plane and both are exposed to the first fence support layer; The back side of the third chip is bonded to the back side of the first chip, and the back side of the fourth chip is bonded to the back side of the second chip. A second fence support layer is formed on the first fence support layer, covering the third chip and the fourth chip, wherein the second fence support layer is provided with a second interconnecting via; A second coating layer is formed on the second fence support layer, wherein the second coating layer has windows to avoid the second interconnecting through-hole; A second metal interconnect layer is formed in the second coating layer, wherein the second metal interconnect layer is electrically connected to the third chip and the fourth chip, and extends to the second interconnect via, so that the first metal interconnect layer and the second metal interconnect layer are electrically connected.
[0013] In an optional embodiment, the step of forming a first fence support layer covering the first chip and the second chip on the temporary substrate includes: A first fence support layer is formed on the temporary substrate; The first fence support layer is patterned, wherein a first interconnecting via is formed on the first fence support layer, and the first fence support layer opens a window to avoid the first electrode and the first functional area disposed on the front side of the first chip, and opens a window to avoid the second electrode and the second functional area disposed on the front side of the second chip.
[0014] In an optional embodiment, the step of forming a second fence support layer covering the third chip and the fourth chip on the first fence support layer includes: A second fence support layer is formed on the first fence support layer; The second fence support layer is patterned, wherein a second interconnecting hole corresponding to and connected to the first interconnecting hole is formed on the second fence support layer, and the second fence support layer opens a window to avoid the third electrode and the third functional area disposed on the front side of the third chip, and opens a window to avoid the fourth electrode and the fourth functional area disposed on the front side of the fourth chip.
[0015] In an optional implementation, prior to the step of removing the temporary substrate, the method further includes: A molding layer is formed on the first coating layer, wherein the molding layer covers the first metal interconnect layer.
[0016] In an optional embodiment, after the step of forming the second metal interconnect layer in the second coating layer, the method further includes: A surface passivation layer is provided on the side of the second coating layer away from the first coating layer, wherein the surface passivation layer has a plurality of windows that partially expose the second metal interconnect layer; Solder balls are formed in the plurality of windows, wherein the solder balls are connected to the second metal interconnect layer.
[0017] The beneficial effects of the embodiments of the present invention include: The three-dimensional integrated packaging structure and fabrication method for radio frequency devices provided in this invention firstly involves attaching a first chip and a second chip at intervals. Then, a first fence support layer is formed covering the first and second chips, with the back surfaces of the first and second chips exposed outside the first fence support layer. Next, a first coating layer is formed on the first fence support layer, and a first metal interconnect layer is formed within the first coating layer. The first metal interconnect layer is electrically connected to the first and second chips. Then, a third chip and a fourth chip are bonded to the back surfaces of the first and second chips respectively. A second fence support layer, a second coating layer, and a second metal interconnect layer are then formed sequentially, with the second metal interconnect layer electrically connected to the third and fourth chips. Specifically, a first interconnect via is provided in the first fence support layer, and the first metal interconnect layer extends to the first interconnect via. Correspondingly, a second interconnect via is provided in the second fence support layer, and the second metal interconnect layer extends to the second interconnect via. The first and second interconnect vias are connected to each other, thereby electrically connecting the first and second metal interconnect layers.
[0018] Compared to existing technologies, this invention uses a back-to-back direct bonding method to achieve chip stacking and integration, eliminating the need for a substrate, reducing package thickness and size, and avoiding buried trench design, thus reducing chip heat accumulation. Furthermore, metal interconnect vias do not need to be fabricated separately on the substrate, eliminating the need for separate design of conductive vias and buried trenches; conventional photolithography processes can be used during the film deposition stage, resulting in a simple, low-cost, and highly efficient process. Attached Figure Description
[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a schematic diagram of the three-dimensional integrated packaging structure of the radio frequency device provided in an embodiment of the present invention; Figure 2 This is a front view of step S1 in the method for fabricating a three-dimensional integrated packaging structure of a radio frequency device provided in this embodiment of the invention. Figure 3 This is a top view of step S1 in the method for fabricating a three-dimensional integrated packaging structure of a radio frequency device provided in an embodiment of the present invention. Figure 4 This is a front view of step S2 in the method for fabricating a three-dimensional integrated packaging structure for radio frequency devices provided in this embodiment of the invention. Figure 5This is a top view corresponding to step S2 in the method for fabricating a three-dimensional integrated packaging structure for radio frequency devices provided in this embodiment of the invention; Figure 6 This is a front view of step S3 in the method for fabricating a three-dimensional integrated packaging structure of a radio frequency device provided in this embodiment of the invention. Figure 7 This is a top view of step S3 in the method for fabricating a three-dimensional integrated packaging structure of a radio frequency device provided in an embodiment of the present invention. Figure 8 This is a front view of step S4 in the method for fabricating a three-dimensional integrated packaging structure for radio frequency devices provided in this embodiment of the invention. Figure 9 This is a front view of step S5 in the method for fabricating a three-dimensional integrated packaging structure for radio frequency devices provided in this embodiment of the invention. Figure 10 This is a front view of step S6 in the method for fabricating a three-dimensional integrated packaging structure for radio frequency devices provided in this embodiment of the invention. Figure 11 This is a front view of step S7 in the method for fabricating a three-dimensional integrated packaging structure for radio frequency devices provided in this embodiment of the invention. Figure 12 This is a front view of step S8 in the method for fabricating a three-dimensional integrated packaging structure for radio frequency devices provided in this embodiment of the invention. Figure 13 This is a front view of step S9 in the method for fabricating a three-dimensional integrated packaging structure for radio frequency devices provided in this embodiment of the invention. Figure 14 The front view of step S10 in the method for fabricating a three-dimensional integrated packaging structure of a radio frequency device provided in the embodiment of the present invention; Figure 15 This is a front view of step S11 in the method for fabricating a three-dimensional integrated packaging structure of a radio frequency device provided in an embodiment of the present invention.
[0021] Icons: 100 - 3D integrated package structure for RF devices; 110a - First chip; 110b - Second chip; 110c - Third chip; 110d - Fourth chip; 111 - First electrode; 112 - Second electrode; 113 - Third electrode; 114 - Fourth electrode; 115 - First functional area; 116 - Second functional area; 117 - Third functional area; 118 - Fourth functional area; 120a - First fence support layer; 120b - Second fence support layer; 130a - First interconnect via; 130b - Second interconnect via; 140a - First coating layer; 140b - Second coating layer; 150a - First metal interconnect layer; 150b - Second metal interconnect layer; 160 - Permanent bonding layer; 170 - Molding layer; 180 - Surface passivation layer; 190 - Solder ball; 200 - Temporary substrate. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0025] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.
[0026] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0027] As disclosed in the background section, existing RF device packaging structures, such as those disclosed in patent document CN112701115A, use a metal substrate as the base of the package. Chip embedding trenches are formed on both the front and back sides of the metal substrate, and the chip is placed into the embedding trenches. Furthermore, metal substrate vias need to be formed separately on the metal substrate as conductive vias.
[0028] This leads to the following problems: 1. The substrate process for chip embedding is complex, requiring the separate fabrication of conductive vias and embedding trenches, resulting in complex processes and high costs; 2. The embedded groove design presents challenges such as chip mounting alignment and difficulty in sealing the chip within the groove, resulting in significant yield control difficulties.
[0029] 3. The introduction of a substrate increases the overall package thickness and leads to greater heat accumulation in the chip.
[0030] 4. Interconnecting vias in multi-layer structures require separate fabrication, which is complex and costly.
[0031] To address the aforementioned issues, this invention provides a novel three-dimensional integrated packaging structure for radio frequency devices and its fabrication method. It should be noted that, unless otherwise specified, the features in the embodiments of this invention can be combined with each other.
[0032] See Figure 1 This invention provides a three-dimensional integrated packaging structure 100 for radio frequency devices, which eliminates the need for a substrate and enables direct back-to-back bonding of chips, reducing the package size. Furthermore, it eliminates the need to design conductive vias and buried grooves on the substrate, thereby reducing process difficulty and cost, and further reducing the package size.
[0033] The three-dimensional integrated packaging structure 100 for radio frequency devices provided in this embodiment of the invention includes a first chip 110a, a second chip 110b, a first fence support layer 120a, a first coating layer 140a, a first metal interconnect layer 150a, a third chip 110c, a fourth chip 110d, a second fence support layer 120b, a second coating layer 140b, and a second metal interconnect layer 150b. The first chip 110a and the second chip 110b are spaced apart. The first fence support layer 120a covers the first chip 110a and the second chip 110b, wherein the back surfaces of the first chip 110a and the second chip 110b are located on the same plane and are both exposed on the first fence support layer 120a. The first coating layer 140a is disposed on the first fence support layer 120a. The first metal interconnect layer 150a is disposed in the first coating layer 140a and is electrically connected to the first chip 110a and the second chip 110b. A third chip 110c and a fourth chip 110d are spaced apart, with the back side of the third chip 110c bonded to the back side of the first chip 110a, and the back side of the fourth chip 110d bonded to the back side of the second chip 110b. A second fence support layer 120b covers the third chip 110c and the fourth chip 110d. A second coating layer 140b is disposed on the side of the second fence support layer 120b away from the first fence support layer 120a. A second metal interconnect layer 150b is disposed in the second coating layer 140b and is electrically connected to the third chip 110c and the fourth chip 110d. The first fence support layer 120a is provided with a first interconnecting hole 130a, and a first metal interconnecting layer 150a extends to the first interconnecting hole 130a. The second fence support layer 120b is provided with a corresponding second interconnecting hole 130b, and a second metal interconnecting layer 150b extends to the second interconnecting hole 130b. The first interconnecting hole 130a and the second interconnecting hole 130b are connected to each other so that the first metal interconnecting layer 150a and the second metal interconnecting layer 150b are electrically connected.
[0034] It should be noted that both the first interconnect via 130a and the second interconnect via 130b are metal interconnect vias, which are connected to each other. The first metal interconnect layer 150a and the second metal interconnect layer 150b can be electrically interconnected through the first interconnect via 130a and the second interconnect via 130b, thereby guiding the lines and electrodes on the front side of the package structure to the back side. Simultaneously, the chip stacking and integration are achieved by directly bonding the chips back-to-back, eliminating the need for a substrate structure as in conventional technologies, reducing the package thickness and size, and avoiding buried trench design, thus reducing heat accumulation on the chip. Furthermore, the metal interconnect vias do not need to be fabricated separately on the substrate, eliminating the need for separate conductive vias and buried trenches on the substrate; conventional photolithography processes can be used during the film deposition stage, resulting in a simple, low-cost, and highly efficient process.
[0035] In some embodiments, a first chip 110a has a first electrode 111 and a first functional area 115 disposed on its front side. The first electrode 111 is located around the first functional area 115. A first fence support layer 120a covers the front side of the first chip 110a and avoids the first electrode 111 and the first functional area 115. A first cavity is formed between the first coating layer 140a and the first functional area 115. A first metal interconnect layer 150a is electrically connected to the first electrode 111. A second chip 110b has a second electrode 112 and a second functional area 116 disposed on its front side. The second electrode 112 is located around the second functional area 116. A first fence support layer 120a covers the front side of the second chip 110b and avoids the second electrode 112 and the second functional area 116. A second cavity is formed between the first coating layer 140a and the second functional area 116. A first metal interconnect layer 150a is electrically connected to the second electrode 112.
[0036] Furthermore, the front side of the third chip 110c is provided with a third electrode 113 and a third functional area 117. The third electrode 113 is located around the third functional area 117. The second fence support layer 120b covers the front side of the third chip 110c and avoids the third electrode 113 and the third functional area 117. A third cavity is formed between the second coating layer 140b and the third functional area 117. The second metal interconnect layer 150b is electrically connected to the third electrode 113. Similarly, the front side of the fourth chip 110d is provided with a fourth electrode 114 and a fourth functional area 118. The fourth electrode 114 is located around the fourth functional area 118. The second fence support layer 120b covers the front side of the fourth chip 110d and avoids the fourth electrode 114 and the fourth functional area 118. A fourth cavity is formed between the second coating layer 140b and the fourth functional area 118. The second metal interconnect layer 150b is electrically connected to the fourth electrode 114.
[0037] It should be noted that both the first coating layer 140a and the second coating layer 140b can be coating materials such as polymers or silicon. During the coating process, the first coating layer 140a can cover the first functional region 115 and the second functional region 116, thereby forming the first cavity and the second cavity respectively. Similarly, the second coating layer 140b covers the third functional region 117 and the fourth functional region 118, thereby forming the third cavity and the fourth cavity respectively. In this embodiment, the first chip 110a, the second chip 110b, the third chip 110c, and the fourth chip 110d can be different types of radio frequency chips, and different chips are integrated and packaged in one package. The specific types of the first chip 110a, the second chip 110b, the third chip 110c, and the fourth chip 110d are not specifically limited here. Of course, in other preferred embodiments of the present invention, the first chip 110a, the second chip 110b, the third chip 110c and the fourth chip 110d may also be memory chips or logic chips, etc., and the three-dimensional integrated packaging structure can integrate more different types of chips. The number of integrated chips is not specifically limited here.
[0038] In some embodiments, a permanent bonding layer 160 is formed on the back side of the first chip 110a and the back side of the second chip 110b. The back side of the third chip 110c is adhered to the back side of the first chip 110a through the permanent bonding layer 160, and the back side of the fourth chip 110d is adhered to the back side of the second chip 110b through the permanent bonding layer 160. Specifically, a permanent bonding layer 160 can be formed on the back side of the first chip 110a and the second chip 110b for adhering the third chip 110c and the fourth chip 110d. This permanent bonding layer 160 also covers the surface of the first fence support layer 120a and has an opening to expose the location of the first interconnect via 130a, facilitating the exposure of the first metal interconnect layer 150a. The material of the permanent bonding layer 160 is not limited here; for example, it can be an organic material or a metal material (if it is a metal material, a metal layer also needs to be pre-formed on the back side of the third chip 110c and the fourth chip 110d for bonding).
[0039] In some embodiments, a molding compound 170 is further disposed on the side of the first coating layer 140a away from the second coating layer 140b, covering the first metal interconnect layer 150a, and a plurality of solder balls 190 are disposed on the side of the second metal interconnect layer 150b away from the first metal interconnect layer 150a. Specifically, the molding compound 170 can encapsulate the first coating layer 140a on the front side of the first chip 110a and the second chip 110b, thereby sealing and protecting the entire surface of the chip, improving the overall sealing performance, and avoiding impact on the functional areas of the chip. The plurality of solder balls 190 can lead the second metal interconnect layer 150b to the outside, serving as electrical interconnection contacts for subsequent chips.
[0040] Furthermore, a surface passivation layer 180 is provided on the side of the second coating layer 140b away from the first coating layer 140a. The surface passivation layer 180 has multiple windows that partially expose the second metal interconnect layer 150b, and multiple solder balls 190 are correspondingly disposed in these windows. Specifically, the surface passivation layer 180 can cover and protect the entire chip surface, exposing only a portion of the metal interconnect surface, facilitating the formation of solder balls 190 in the multiple windows.
[0041] In some embodiments, the width of the third chip 110c is smaller than the width of the first chip 110a, and the back side of the third chip 110c is bonded to the center of the back side of the first chip 110a; the width of the fourth chip 110d is smaller than the width of the second chip 110b, and the back side of the fourth chip 110d is bonded to the center of the back side of the second chip 110b. Specifically, the chip sizes of the third chip 110c and the fourth chip 110d are relatively smaller, which facilitates alignment and bonding. Furthermore, by bonding chips of different sizes back-to-back, a stepped surface is formed at the chip edges, which helps to improve the bonding strength of the fence support layer, enhance the overall structural stability, and mitigate warping.
[0042] In some embodiments, the thickness of the first chip 110a is the same as the thickness of the second chip 110b; furthermore, the thickness of the third chip 110c is the same as the thickness of the fourth chip 110d. Specifically, the thickness of each chip can be set through a wafer thinning process. Setting the thickness of the first chip 110a and the second chip 110b to be substantially the same allows the front sides of the first chip 110a and the second chip 110b to be substantially on the same plane, facilitating the fabrication of the first fence support layer 120a and the first coating layer 140a. Similarly, setting the thickness of the third chip 110c and the fourth chip 110d to be substantially the same allows the front sides of the third chip 110c and the fourth chip 110d to be substantially on the same plane, facilitating the fabrication of the second fence support layer 120b and the second coating layer 140b.
[0043] This invention also provides a method for fabricating a three-dimensional integrated package structure 100 for radio frequency devices, the method comprising the following steps: S1: The back side of the first chip 110a and the back side of the second chip 110b are attached to the temporary substrate 200 at intervals.
[0044] See also Figure 2 and Figure 3Specifically, firstly, a conventional grinding process is used to fabricate individual chips 110a, 110b, 110c, and 110d. A thinning process can be used to make the thicknesses of chips 110a and 110b approximately the same, as well as the thicknesses of chips 110c and 110d. Then, a surface mount technology (SMT) is used to reconstruct chips 110a and 110b onto a temporary substrate 200, which can be made of materials such as glass, silicon dioxide, or metal. Temporary bonding adhesive is then used to bond and fix chips 110a and 110b together.
[0045] It should be noted that during the chip mounting process, the back sides of the first chip 110a and the second chip 110b can be attached to the surface of the temporary substrate 200, with the first electrode 111 and the first functional area 115 on the first chip 110a facing upwards, and the second electrode 112 and the second functional area 116 on the second chip 110b facing upwards.
[0046] S2: A first fence support layer 120a is formed on a temporary substrate 200 to cover the first chip 110a and the second chip 110b, wherein a first interconnect via 130a is provided in the first fence support layer 120a.
[0047] See also Figure 4 and Figure 5 Specifically, a first fence support layer 120a (wall) can be fabricated. First, the first fence support layer 120a is formed on a temporary substrate 200. Then, the first fence support layer 120a is patterned using photolithography and development processes. The first fence support layer 120a has a first interconnect via 130a formed on it. The first fence support layer 120a has a window to avoid the first electrode 111 and the first functional area 115 disposed on the front side of the first chip 110a, and also has a window to avoid the second electrode 112 and the second functional area 116 disposed on the front side of the second chip 110b.
[0048] In actual fabrication, a support layer can be fabricated on the surface of the temporary substrate 200 and the front side of the chip using photolithography, simultaneously exposing the electrodes, functional areas, and the locations of metal interconnects (i.e., forming the first interconnect via 130a). The first fence support layer 120a can be made of a dielectric material, and the first interconnect via 130a is located between the first chip 110a and the second chip 110b, penetrating the first fence support layer 120a, thereby exposing the surface of the temporary substrate 200.
[0049] S3: A first coating layer 140a is formed on the first fence support layer 120a, wherein the first coating layer 140a has a window to avoid the first interconnecting through hole 130a.
[0050] See Figure 6 Specifically, a coating process can be used to form a first coating layer 140a on the surface of the first fence support layer 120a. A photolithography process is then used to pattern the first coating layer 140a, thereby creating windows to avoid the positions of the first electrode 111, the second electrode 112, and the first interconnect via 130a, facilitating the subsequent fabrication of the metal interconnect layer. The corresponding functional areas are fully covered and not exposed. The first fence support layer 120a and the first coating layer 140a can be used to create sealed first and second cavities, thereby protecting the first functional area 115 and the second functional area 116.
[0051] S4: A first metal interconnect layer 150a is formed in the first coating layer 140a.
[0052] See Figure 7 and Figure 8 The first metal interconnect layer 150a is electrically connected to the first chip 110a and the second chip 110b, and extends to the first interconnect via 130a. Specifically, the first metal interconnect layer 150a can be fabricated in the reserved windows on the first coating layer 140a and the first fence support layer 120a and in the first interconnect via 130a through processes such as PVD (Physical Vapor Deposition), photolithography, electroplating, resist removal and etching. The first metal interconnect layer 150a can make electrical contact with the first electrode 111 and the second electrode 112 and extend to the first interconnect via 130a, thereby leading the first electrode 111 and the second electrode 112 to the other side surface of the package.
[0053] S5: A molding layer 170 is formed on the first coating layer 140a, wherein the molding layer 170 covers the first metal interconnect layer 150a.
[0054] See Figure 9 Specifically, a molding process is used to mold the first coating layer 140a on the front side of the first chip 110a and the second chip 110b. The resulting molding layer 170 can cover the entire surface of the first coating layer 140a, thereby sealing and protecting the entire front side of the first chip 110a and the second chip 110b.
[0055] S6: Remove temporary substrate 200. See Figure 10 Specifically, the temporary substrate 200 can be removed by a debonding process, and residual adhesive can be removed so that the back sides of the first chip 110a and the second chip 110b are on the same plane and both are exposed to the first fence support layer 120a.
[0056] S7: Bond the back side of the third chip 110c to the back side of the first chip 110a, and simultaneously bond the back side of the fourth chip 110d to the back side of the second chip 110b.
[0057] See Figure 11 Specifically, a permanent bonding layer 160 is first formed on the back side of the first chip 110a and the second chip 110b. The permanent bonding layer 160 is fabricated on the back side using processes such as photolithography to adhere the third chip 110c and the fourth chip 110d. This permanent bonding layer 160 covers the entire back side and exposes the location of the first interconnect via 130a. The specific material of the permanent bonding layer 160 is not limited here; it can be an organic material or a metallic material. Then, a surface mount technology (SMT) process can be used to permanently bond the third chip 110c and the fourth chip 110d to the permanent bonding layer 160, achieving a back-to-back mounting of the third chip 110c with the first chip 110a, and a back-to-back mounting of the fourth chip 110d with the second chip 110b.
[0058] S8: A second fence support layer 120b is formed on the first fence support layer 120a, covering the third chip 110c and the fourth chip 110d, wherein a second interconnecting via 130b is provided in the second fence support layer 120b.
[0059] See Figure 12 Specifically, a second fence support layer 120b (wall) can be fabricated. First, the second fence support layer 120b is formed on the surface of the permanent bonding layer 160 on the first fence support layer 120a. Then, the second fence support layer 120b is patterned using photolithography and development processes. A second interconnect via 130b is formed on the second fence support layer 120b, and this second interconnect via 130b is correspondingly connected to the first interconnect via 130a. Furthermore, the second fence support layer 120b has windows to avoid the third electrode 113 and the third functional area 117 on the front side of the third chip 110c, and also has windows to avoid the fourth electrode 114 and the fourth functional area 118 on the front side of the fourth chip 110d. See step S2 for details.
[0060] S9: A second coating layer 140b is formed on the second fence support layer, wherein the second coating layer 140b has a window to avoid the second interconnecting through hole 130b.
[0061] See Figure 13Specifically, a coating process can be used to form a second coating layer 140b on the surface of the second fence support layer 120b. A photolithography process is then used to pattern the second coating layer 140b, thereby creating windows to avoid the locations of the third electrode 113, the fourth electrode 114, and the second interconnect via 130b, facilitating the subsequent fabrication of the metal interconnect layer. The corresponding functional areas are fully covered and not exposed. The second fence support layer 120b and the second coating layer 140b can be used to create sealed third and fourth cavities, thus protecting the third functional area 117 and the fourth functional area 118. See step S3 for details.
[0062] S10: A second metal interconnect layer 150b is formed in the second coating layer 140b.
[0063] See Figure 14 The second metal interconnect layer 150b is electrically connected to the third chip 110c and the fourth chip 110d, and extends to the second interconnect via 130b, so that the first metal interconnect layer 150a and the second metal interconnect layer 150b are electrically connected. Specifically, the second metal interconnect layer 150b can be fabricated in the reserved window on the second coating layer 140b and the second fence support layer 120b and in the second interconnect via 130b through processes such as PVD (Physical Vapor Deposition), photolithography, electroplating, resist stripping and etching. The second metal interconnect layer 150b can make electrical contact with the third electrode 113 and the fourth electrode 114, and extends to the second interconnect via 130b, thereby bringing the first electrode 111 and the second electrode 112 to the same horizontal plane as the third electrode 113 and the fourth electrode 114, and performing partial circuit connection to achieve this.
[0064] S11: A surface passivation layer 180 is provided on the side of the second coating layer 140b away from the first coating layer 140a.
[0065] See Figure 15 The surface passivation layer 180 has multiple windows partially exposing the second metal interconnect layer 150b. Specifically, a photolithography process can be used to fabricate a passivation layer on the surface of the second coating layer 140b, thereby covering and protecting the entire chip surface, exposing only a portion of the second metal interconnect layer 150b, thus forming multiple windows.
[0066] S12: Solder balls 190 are formed in multiple windows, wherein the solder balls 190 are connected to the second metal interconnect layer 150b.
[0067] Please continue reading Figure 1 Specifically, solder balls 190 can be fabricated in multiple windows of the surface passivation layer 180 using printing or ball-planting processes to prepare for subsequent electrical interconnection.
[0068] The three-dimensional integrated packaging structure 100 for radio frequency devices and its fabrication method provided in this embodiment of the invention firstly involves attaching a first chip 110a and a second chip 110b at intervals. Then, a first fence support layer 120a is formed covering the first chip 110a and the second chip 110b, with the back surfaces of the first chip 110a and the second chip 110b exposed outside the first fence support layer 120a. Next, a first coating layer 140a is formed on the first fence support layer 120a, and a first metal interconnect layer 150a is formed within the first coating layer 140a. The first metal interconnect layer 150a is electrically connected to the first chip 110a and the second chip 110b. Then, a third chip 110c and a fourth chip 110d are respectively bonded to the back surfaces of the first chip 110a and the second chip 110b. Finally, a second fence support layer 120b, a second coating layer 140b, and a second metal interconnect layer 150b are formed sequentially. The second metal interconnect layer 150b is electrically connected to the third chip 110c and the fourth chip 110d. In this invention, a first interconnect via 130a is provided in the first fence support layer 120a, and a first metal interconnect layer 150a extends to the first interconnect via 130a. A second interconnect via 130b is correspondingly provided in the second fence support layer 120b, and a second metal interconnect layer 150b extends to the second interconnect via 130b. The first interconnect via 130a and the second interconnect via 130b are connected to each other, thereby electrically connecting the first metal interconnect layer 150a and the second metal interconnect layer 150b. Compared to existing technologies, this invention uses a back-to-back direct bonding method to achieve chip stacking and integration, eliminating the need for a substrate, reducing package thickness and size, and avoiding buried trench design, thus reducing chip heat accumulation. Furthermore, the metal interconnect vias do not need to be fabricated separately on the substrate, eliminating the need for separate design of conductive vias and buried trenches on the substrate. Conventional photolithography processes can be used during the film deposition stage, resulting in a simple, low-cost, and highly efficient process.
[0069] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A three-dimensional integrated packaging structure for radio frequency devices, characterized in that, include: The first and second chips are spaced apart; A first fence support layer covering the first chip and the second chip, wherein the back sides of the first chip and the second chip are located on the same plane and are both exposed outside the first fence support layer; A first coating layer disposed on the first fence support layer; A first metal interconnect layer is disposed in the first coating layer, and the first metal interconnect layer is electrically connected to the first chip and the second chip; A third chip and a fourth chip are spaced apart, wherein the back side of the third chip is bonded to the back side of the first chip, and the back side of the fourth chip is bonded to the back side of the second chip; A second fence support layer covering the third chip and the fourth chip; A second coating layer is disposed on the side of the second fence support layer away from the first fence support layer; A second metal interconnect layer is disposed in the second coating layer, and the second metal interconnect layer is electrically connected to the third chip and the fourth chip; The first fence support layer is provided with a first interconnecting hole, and the first metal interconnecting layer extends to the first interconnecting hole. The second fence support layer is provided with a corresponding second interconnecting hole, and the second metal interconnecting layer extends to the second interconnecting hole. The first interconnecting hole and the second interconnecting hole are connected to each other so that the first metal interconnecting layer and the second metal interconnecting layer are electrically connected.
2. The three-dimensional integrated packaging structure for radio frequency devices according to claim 1, characterized in that, The first chip has a first electrode and a first functional area on its front side. The first electrode is located around the first functional area. The first fence support layer covers the front side of the first chip and avoids the first electrode and the first functional area. A first cavity is formed between the first coating layer and the first functional area. The first metal interconnect layer is electrically connected to the first electrode. And / or, the front side of the second chip is provided with a second electrode and a second functional area, the second electrode is located around the second functional area, the first fence support layer covers the front side of the second chip and avoids the second electrode and the second functional area, and a second cavity is formed between the first coating layer and the second functional area, and the first metal interconnect layer is electrically connected to the second electrode.
3. The three-dimensional integrated packaging structure for radio frequency devices according to claim 2, characterized in that, The front side of the third chip is provided with a third electrode and a third functional area. The third electrode is located around the third functional area. The second fence support layer covers the front side of the third chip and avoids the third electrode and the third functional area. A third cavity is formed between the second coating layer and the third functional area. The second metal interconnect layer is electrically connected to the third electrode. And / or, the front side of the fourth chip is provided with a fourth electrode and a fourth functional area, the fourth electrode is located around the fourth functional area, the second fence support layer covers the front side of the fourth chip and avoids the fourth electrode and the fourth functional area, and a fourth cavity is formed between the second coating layer and the fourth functional area, and the second metal interconnect layer is electrically connected to the fourth electrode.
4. The three-dimensional integrated packaging structure for radio frequency devices according to claim 1, characterized in that, A permanent bonding layer is formed on the back side of the first chip and the back side of the second chip. The back side of the third chip is adhered to the back side of the first chip through the permanent bonding layer. The back side of the fourth chip is adhered to the back side of the second chip through the permanent bonding layer.
5. The three-dimensional integrated packaging structure for radio frequency devices according to claim 1, characterized in that, A molding layer is also provided on the side of the first coating layer away from the second coating layer, the molding layer covering the first metal interconnect layer, and a plurality of solder balls are also provided on the side of the second metal interconnect layer away from the first metal interconnect layer.
6. The three-dimensional integrated packaging structure for radio frequency devices according to claim 5, characterized in that, The second coating layer is further provided with a surface passivation layer on the side away from the first coating layer. The surface passivation layer is provided with multiple windows that partially expose the second metal interconnect layer, and the multiple solder balls are correspondingly disposed in the multiple windows.
7. The three-dimensional integrated packaging structure for radio frequency devices according to claim 1, characterized in that, The width of the third chip is smaller than the width of the first chip, and the back side of the third chip is bonded to the middle of the back side of the first chip; and / or, the width of the fourth chip is smaller than the width of the second chip, and the back side of the fourth chip is bonded to the middle of the back side of the second chip.
8. The three-dimensional integrated packaging structure for radio frequency devices according to claim 1, characterized in that, The thickness of the first chip is the same as the thickness of the second chip; and / or, the thickness of the third chip is the same as the thickness of the fourth chip.
9. A method for fabricating a three-dimensional integrated packaging structure for radio frequency devices, used to fabricate the three-dimensional integrated packaging structure for radio frequency devices as described in claim 1, characterized in that, The method includes: The back sides of the first chip and the back sides of the second chip are bonded together on a temporary substrate with a gap between them; A first fence support layer is formed on the temporary substrate to cover the first chip and the second chip, wherein a first interconnect via is provided in the first fence support layer; A first coating layer is formed on the first fence support layer, wherein the first coating layer has windows to avoid the first interconnecting through-hole; A first metal interconnect layer is formed in the first coating layer, wherein the first metal interconnect layer is electrically connected to the first chip and the second chip and extends to the first interconnect via; Remove the temporary substrate so that the back sides of the first chip and the second chip are on the same plane and both are exposed to the first fence support layer; The back side of the third chip is bonded to the back side of the first chip, and the back side of the fourth chip is bonded to the back side of the second chip. A second fence support layer is formed on the first fence support layer, covering the third chip and the fourth chip, wherein the second fence support layer is provided with a second interconnecting via; A second coating layer is formed on the second fence support layer, wherein the second coating layer has windows to avoid the second interconnecting through-hole; A second metal interconnect layer is formed in the second coating layer, wherein the second metal interconnect layer is electrically connected to the third chip and the fourth chip, and extends to the second interconnect via, so that the first metal interconnect layer and the second metal interconnect layer are electrically connected.
10. The method for fabricating a three-dimensional integrated packaging structure for radio frequency devices according to claim 9, characterized in that, The step of forming a first fence support layer covering the first chip and the second chip on the temporary substrate includes: A first fence support layer is formed on the temporary substrate; The first fence support layer is patterned, wherein a first interconnecting via is formed on the first fence support layer, and the first fence support layer opens a window to avoid the first electrode and the first functional area disposed on the front side of the first chip, and opens a window to avoid the second electrode and the second functional area disposed on the front side of the second chip.
11. The method for fabricating a three-dimensional integrated packaging structure for radio frequency devices according to claim 9, characterized in that, The step of forming a second fence support layer covering the third chip and the fourth chip on the first fence support layer includes: A second fence support layer is formed on the first fence support layer; The second fence support layer is patterned, wherein a second interconnecting hole corresponding to and connected to the first interconnecting hole is formed on the second fence support layer, and the second fence support layer opens a window to avoid the third electrode and the third functional area disposed on the front side of the third chip, and opens a window to avoid the fourth electrode and the fourth functional area disposed on the front side of the fourth chip.
12. The method for fabricating a three-dimensional integrated packaging structure for radio frequency devices according to claim 9, characterized in that, Prior to the step of removing the temporary substrate, the method further includes: A molding layer is formed on the first coating layer, wherein the molding layer covers the first metal interconnect layer.
13. The method for fabricating a three-dimensional integrated packaging structure for radio frequency devices according to claim 9, characterized in that, After the step of forming the second metal interconnect layer in the second coating layer, the method further includes: A surface passivation layer is provided on the side of the second coating layer away from the first coating layer, wherein the surface passivation layer has a plurality of windows that partially expose the second metal interconnect layer; Solder balls are formed in the plurality of windows, wherein the solder balls are connected to the second metal interconnect layer.