Semiconductor device including transistor

Abstract

A semiconductor device is provided. The semiconductor device includes a first NMOS transistor structure and a second NMOS transistor structure. The first NMOS transistor structure includes a first NMOS source / drain region, a first NMOS channel layer, a first NMOS gate electrode, a first NMOS gate dielectric layer, and a first NMOS insulating spacer structure between the first NMOS gate dielectric layer and the first NMOS source / drain region. The second NMOS transistor structure includes a second NMOS source / drain region, a second NMOS channel layer, a second NMOS gate electrode, a second NMOS gate dielectric layer, and a second NMOS insulating spacer structure between the second NMOS gate dielectric layer and the second NMOS source / drain region. The first NMOS insulating spacer structure includes an insulating spacer pattern, and the second NMOS insulating spacer structure includes an insulating oxide layer and does not include the same insulating spacer pattern as the insulating spacer pattern.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices including transistors and methods of forming the same. Background Technology

[0002] With the increasing demand for high performance, high speed, and / or versatility in semiconductor devices, the integration density of semiconductor devices has increased. To respond to this trend towards higher integration, it is important to fabricate semiconductor devices with finely patterned designs, achieving patterns with fine widths or fine spacing. Furthermore, efforts have been made to develop semiconductor devices including transistors with three-dimensional channel structures to overcome the limitations in operating characteristics caused by the miniaturization of planar metal-oxide-semiconductor FETs (MOSFETs). Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor device that can increase integration.

[0004] Embodiments of this disclosure provide a semiconductor device that can improve performance.

[0005] The embodiments of this disclosure provide a method for forming a semiconductor device.

[0006] According to an example embodiment of the technical concept of this disclosure, a semiconductor device is provided. The semiconductor device includes: a first NMOS transistor structure; and a second NMOS transistor structure. The first NMOS transistor structure includes: a first NMOS source / drain region; a first NMOS channel layer, the first NMOS channel layers being stacked and spaced apart from each other, and electrically connected to the first NMOS source / drain region in a first direction; a first NMOS gate electrode, the first NMOS gate electrode surrounding each of the first NMOS channel layers in a second direction intersecting the first direction; a first NMOS gate dielectric layer, the first NMOS gate dielectric layer being located between the first NMOS gate electrode and the first NMOS channel layer, and between the first NMOS gate electrode and the first NMOS source / drain region; and a first NMOS insulating spacer structure, the first NMOS insulating spacer structure being located between the first NMOS gate dielectric layer and the first NMOS source / drain region. The second NMOS transistor structure includes: a second NMOS source / drain region; a second NMOS channel layer, the second NMOS channel layers being stacked and spaced apart from each other, and electrically connected to the second NMOS source / drain region in the first direction; a second NMOS gate electrode, the second NMOS gate electrode extending in the second direction and surrounding each second NMOS channel layer in the second direction; a second NMOS gate dielectric layer, the second NMOS gate dielectric layer being located between the second NMOS gate electrode and the second NMOS channel layer, and between the second NMOS gate electrode and the second NMOS source / drain region; and a second NMOS insulating spacer structure, the second NMOS insulating spacer structure being located between the second NMOS gate dielectric layer and the second NMOS source / drain region. The first NMOS insulating spacer structure includes a first NMOS insulating spacer pattern, and the second NMOS insulating spacer structure includes a second NMOS insulating oxide layer and does not include an insulating spacer pattern identical to the first NMOS insulating spacer pattern.

[0007] According to an example embodiment of the technical concept of this disclosure, a semiconductor device is provided. The semiconductor device includes: a first NMOS transistor structure; and a second NMOS transistor structure. The first NMOS transistor structure includes: a first NMOS source / drain region; a first NMOS channel layer, the first NMOS channel layers being stacked and spaced apart from each other, and electrically connected to the first NMOS source / drain region in a first direction; a first NMOS gate electrode, the first NMOS gate electrode extending in a second direction intersecting the first direction, and surrounding each of the first NMOS channel layers in the second direction; a first NMOS gate dielectric layer, the first NMOS gate dielectric layer being located between the first NMOS gate electrode and the first NMOS channel layer, and between the first NMOS gate electrode and the first NMOS source / drain region; and a first NMOS insulating spacer structure, the first NMOS insulating spacer structure being located between the first NMOS gate dielectric layer and the first NMOS source / drain region. The second NMOS transistor structure includes: a second NMOS source / drain region; a second NMOS channel layer, the second NMOS channel layers being stacked and spaced apart from each other, and electrically connected to the second NMOS source / drain region in the first direction; a second NMOS gate electrode, the second NMOS gate electrode extending in the second direction and surrounding each second NMOS channel layer in the second direction; a second NMOS gate dielectric layer, the second NMOS gate dielectric layer being located between the second NMOS gate electrode and the second NMOS channel layer, and between the second NMOS gate electrode and the second NMOS source / drain region; and a second NMOS insulating spacer structure, the second NMOS insulating spacer structure being located between the second NMOS gate dielectric layer and the second NMOS source / drain region. The first NMOS channel layer includes a first NMOS lower channel layer, a first NMOS intermediate channel layer located on the first NMOS lower channel layer, and a first NMOS upper channel layer located on the first NMOS intermediate channel layer. The second NMOS channel layer includes a second NMOS lower channel layer, a second NMOS intermediate channel layer located on the second NMOS lower channel layer, and a second NMOS upper channel layer located on the second NMOS intermediate channel layer. The first NMOS gate electrode includes: a first NMOS lower gate portion located directly below the first NMOS lower channel layer; a first NMOS intermediate gate portion located directly below the first NMOS intermediate channel layer; and a first NMOS upper gate portion located directly below the first NMOS upper channel layer.The second NMOS gate electrode includes: a second NMOS lower gate portion located directly below the second NMOS lower channel layer; a second NMOS middle gate portion located directly below the second NMOS middle channel layer; and a second NMOS upper gate portion located directly below the second NMOS upper channel layer. The first NMOS insulating spacer structure includes a first NMOS middle spacer portion located between the first NMOS source / drain region and the first NMOS middle gate portion. The second NMOS insulating spacer structure includes a second NMOS middle spacer portion located between the second NMOS source / drain region and the second NMOS middle gate portion. The thickness of the first NMOS middle spacer portion is greater than the thickness of the second NMOS middle spacer portion. The thickness of the second NMOS middle spacer portion is the thickness in a direction perpendicular to the surface of the second NMOS middle spacer portion that contacts the second NMOS gate dielectric layer, and the thickness of the first NMOS middle spacer portion is the thickness in a direction perpendicular to the surface of the first NMOS gate dielectric layer that contacts or faces the first NMOS middle spacer portion.

[0008] According to an example embodiment of the technical concept of this disclosure, a semiconductor device is provided. The semiconductor device includes: a first NMOS transistor structure; and a second NMOS transistor structure. The first NMOS transistor structure includes: a first NMOS channel layer, the first NMOS channel layers being spaced apart from each other in a first direction; a first NMOS source / drain region, the first NMOS source / drain region being electrically connected to the first NMOS channel layer in a second direction perpendicular to the first direction; a first NMOS gate electrode, the first NMOS gate electrode including a first NMOS intermediate electrode portion located between the first NMOS channel layers; a first NMOS gate dielectric layer, the first NMOS gate dielectric layer being located between the first NMOS gate electrode and the first NMOS channel layer; and a first NMOS insulating spacer structure, the first NMOS insulating spacer structure being located between the first NMOS intermediate electrode portion and the first NMOS source / drain region. The second NMOS transistor structure includes: a second NMOS channel layer, the second NMOS channel layers being spaced apart from each other in the first direction; a second NMOS source / drain region, the second NMOS source / drain region being connected to the second NMOS channel layer in the second direction; a second NMOS gate electrode, the second NMOS gate electrode including a second NMOS intermediate electrode portion located between the second NMOS channel layers; a second NMOS gate dielectric layer, the second NMOS gate dielectric layer being located between the second NMOS gate electrode and the second NMOS channel layer; and a second NMOS insulating spacer structure, the second NMOS insulating spacer structure being located between the second NMOS intermediate electrode portion and the second NMOS source / drain region. The first NMOS insulating spacer structure includes a first insulating spacer pattern, and the second NMOS insulating spacer structure includes a second NMOS insulating oxide layer and does not include an insulating spacer pattern identical to the first insulating spacer pattern.

[0009] According to example embodiments, a first NMOS transistor structure and a second NMOS transistor structure can be provided, including source / drain regions of different widths and different insulating spacer structures. Therefore, a first NMOS transistor capable of preventing or minimizing leakage current caused by gate-induced drain leakage (GIDL) and a second NMOS transistor including source / drain regions that can be reliably formed can be provided.

[0010] The advantages and effects of this disclosure are not limited to the foregoing, and can be more easily understood in the process of describing specific exemplary embodiments of this disclosure. Attached Figure Description

[0011] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A , Figure 1B , Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6A , Figure 6B and Figure 7 This is a view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 8 This is a partially enlarged cross-sectional view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 9 This is a partially enlarged cross-sectional view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 10 This is a partially enlarged cross-sectional view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 11 , Figure 12 and Figure 13 This is a view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 14 and Figure 15 This is a cross-sectional view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; and Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figures 18 to 23 , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 26A and Figure 26B This is a view illustrating an example of a method for forming a semiconductor device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0012] In the following text, terms such as “upper,” “middle,” and “lower” may be replaced by other terms such as “first,” “second,” and “third,” and may be used to describe elements of the specification. Terms such as “first,” “second,” and “third” may be used to describe various elements, but the elements are not limited thereto, and a “first element” may be referred to as a “second element.” In the specification, terms such as “lower,” “upper,” “upper end,” and “lower end” may be terms interpreted based on the accompanying drawings. As used herein, the term “and / or” includes any and all combinations of one or more associated listed items. It should be noted that aspects described with respect to one embodiment may be incorporated into different embodiments, even if not specifically described therewith. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination.

[0013] In the specification, "NMOS transistor" can refer to N-channel MOSFET (N-channel metal-oxide-semiconductor field-effect transistor), and "PMOS transistor" can refer to P-channel MOSFET (P-channel metal-oxide-semiconductor field-effect transistor).

[0014] In order to clearly distinguish between the elements of an NMOS transistor and the elements of a PMOS transistor, the gate, channel layer, and source / drain of the element that is an "NMOS transistor" are referred to as NMOS gate, NMOS channel layer, and NMOS source / drain, respectively, and the gate, channel layer, and source / drain of the element that is a "PMOS transistor" are referred to as PMOS gate, PMOS channel layer, and PMOS source / drain, respectively.

[0015] In the specification, "transistor structure" can refer to a structure that includes "transistors".

[0016] In order to distinguish between the elements of the "first NMOS transistor structure", the elements of the "second NMOS transistor structure", the elements of the "first PMOS transistor structure" and the elements of the "second PMOS transistor structure", the elements of the "first NMOS transistor structure" are referred to as first NMOS elements, the elements of the "second NMOS transistor structure" are referred to as second NMOS elements, the elements of the "first PMOS transistor structure" are referred to as first PMOS elements, and the elements of the "second PMOS transistor structure" are referred to as second PMOS elements.

[0017] The term "around," as used herein, may not require complete surrounding of the described element or layer, but may refer, for example, to partial surrounding of the described element or layer where gaps or other spaces exist in various places. The term "connected" herein may be used to refer to physical and / or electrical connections. When a component or layer is referred to herein as being "directly" located, "directly in contact," or "directly connected," there are no intermediate components or layers. Similarly, when components are "closely" adjacent to each other, there may be no intermediate components.

[0018] refer to Figure 1A , Figure 1B , Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6A , Figure 6B and Figure 7 The following will describe a semiconductor device according to an example embodiment of the present disclosure. Figure 1A , Figure 1B , Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6A , Figure 6B and Figure 7 middle, Figure 1A This is a top view showing the first region C1 of a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 1B This is a top view showing the second region C2 of a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 2 It shows along Figure 1A The line I-I' and Figure 1B A cross-sectional view of the area intercepted by line II-II'. Figure 3A yes Figure 2 A magnified view of the portion indicated by "A". Figure 3B yes Figure 2 A magnified view of the portion indicated by "B". Figure 4 It shows along Figure 1A Line III-III' and Figure 1B A cross-sectional view of the area intercepted by line IV-IV'. Figure 5 It shows along Figure 1A The line V-V' and Figure 1B A cross-sectional view of the area intercepted by line VI-VI'. Figure 6A yes Figure 5 A magnified view of the part indicated by "C" in the image. Figure 6B yes Figure 5 A magnified view of the portion indicated by "D" in the image, and Figure 7 It shows along Figure 1A The lines VII-VII' and Figure 1B A cross-sectional view of the area intercepted by line VIII-VIII'.

[0019] refer to Figure 1A , Figure 1B , Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6A , Figure 6B and Figure 7 The semiconductor device 1 according to the example embodiment may include a first region C1 and a second region C2.

[0020] The first region C1 may include a first NMOS transistor region N1, and the second region C2 may include a second NMOS transistor region N2. The first region C1 may also include a first PMOS transistor region P1, and the second region C2 may also include a second PMOS transistor region P2.

[0021] The first NMOS transistor region N1 may include a first NMOS transistor structure nTR1S, and the second NMOS transistor region N2 may include a second NMOS transistor structure nTR2S. The first PMOS transistor region P1 may include a first PMOS transistor structure pTR1S, and the second PMOS transistor region P2 may include a second PMOS transistor structure pTR2S.

[0022] The first NMOS transistor region N1, the second NMOS transistor region N2, the first PMOS transistor region P1, and the second PMOS transistor region P2 may further include: a substrate 3, active regions 3a, 3b, 3c, and 3d located on the substrate 3, and device isolation regions 15 disposed on the side surfaces of the active regions 3a, 3b, 3c, and 3d on the substrate 3.

[0023] Substrate 3 may be a semiconductor substrate, such as a single-crystal silicon substrate. Each of the active regions 3a, 3b, 3c, and 3d may have a shape that protrudes vertically from substrate 3. Active regions 3a, 3b, 3c, and 3d may comprise a semiconductor material, such as single-crystal silicon. Device isolation region 15 may comprise an insulating material, such as silicon oxide.

[0024] The first NMOS transistor region N1 may include the first active region 3a among the active regions 3a, 3b, 3c and 3d; the second NMOS transistor region N2 may include the second active region 3b among the active regions 3a, 3b, 3c and 3d; the first PMOS transistor region P1 may include the third active region 3c among the active regions 3a, 3b, 3c and 3d; and the second PMOS transistor region P1 may include the fourth active region 3d among the active regions 3a, 3b, 3c and 3d.

[0025] The first NMOS transistor structure nTR1S (see...) Figure 3A It may include a first NMOS source / drain region 45, a first NMOS channel layer 9a, a first NMOS gate electrode 69n, a first NMOS gate dielectric layer 63n, and a first NMOS insulating spacer structure 41.

[0026] The first NMOS source / drain regions 45 may be spaced apart from each other in a first horizontal direction (X direction). Each first NMOS source / drain region 45 may have N-type conductivity. Each first NMOS source / drain region 45 may include an epitaxially grown semiconductor material. For example, each first NMOS source / drain region 45 may include silicon.

[0027] The first NMOS channel layer 9a can be disposed between the first NMOS source / drain regions 45. The first NMOS channel layer 9a can be disposed on the first active region 3a. The first NMOS channel layers 9a can be stacked and spaced apart from each other in a vertical direction (Z direction) perpendicular to the first horizontal direction (X direction). The first NMOS channel layer 9a can be connected to the first NMOS source / drain regions 45. The first NMOS channel layer 9a can include a semiconductor material, such as single-crystal silicon.

[0028] The first NMOS channel layer 9a may include a first NMOS lower channel layer 9a1 located on the first active region 3a, a first NMOS intermediate channel layer 9a2 located on the first NMOS lower channel layer 9a1, and a first NMOS upper channel layer 9a3 located on the first NMOS intermediate channel layer 9a2. Figure 2 and Figure 3A In this example, the number of first NMOS channel layers 9a is shown as three, but the example embodiment is not limited to this. For example, the first NMOS channel layers 9a may include four or more channel layers stacked in the vertical direction (Z direction) and spaced apart from each other.

[0029] The first NMOS gate electrode 69n can extend in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction) and the vertical direction (Z direction), and can surround each first NMOS channel layer 9a. The first NMOS gate electrode 69n can surround each first NMOS channel layer 9a and can extend in the second horizontal direction (Y direction), and can be disposed on the first active region 3a and the device isolation region 15.

[0030] The first NMOS gate electrode 69n may include a first NMOS lower gate portion 69n_1 located directly below the first NMOS lower channel layer 9a1, a first NMOS middle gate portion 69n_2 located directly below the first NMOS middle channel layer 9a2, a first NMOS upper gate portion 69n_3 located directly below the first NMOS upper channel layer 9a3, and a first NMOS uppermost gate portion 69n_4 located on the first NMOS upper channel layer 9a3. The first NMOS lower gate portion 69n_1 may be disposed between the first active region 3a and the first NMOS lower channel layer 9a1, the first NMOS middle gate portion 69n_2 may be disposed between the first NMOS lower channel layer 9a1 and the first NMOS middle channel layer 9a2, and the first NMOS upper gate portion 69n_3 may be disposed between the first NMOS middle channel layer 9a2 and the first NMOS upper channel layer 9a3.

[0031] The first NMOS gate dielectric layer 63n may be disposed between the first NMOS source / drain region 45 and the first NMOS gate electrode 69n, and may extend between the first NMOS gate electrode 69n and the first NMOS channel layer 9a. The first NMOS gate dielectric layer 63n may include a high-k dielectric. The high-k dielectric may be a dielectric with a dielectric constant higher than that of silicon oxide.

[0032] The first NMOS insulating spacer structure 41 can be disposed between the first NMOS gate dielectric layer 63n and the first NMOS source / drain region 45. The first NMOS insulating spacer structure 41 can overlap perpendicularly with the first NMOS channel layer 9a.

[0033] The first NMOS insulating spacer structure 41 may include an insulating spacer pattern 42. The insulating spacer pattern 42 may be disposed between the first NMOS source / drain regions 45. The insulating spacer pattern 42 may overlap vertically with the first NMOS channel layer 9a. The insulating spacer pattern 42 may include an insulating nitride. For example, the insulating spacer pattern 42 may include silicon nitride. The first NMOS source / drain regions 45 may include a first-first NMOS source / drain region 45_1 and a first-second NMOS source / drain region 45_2 spaced apart from each other in a first horizontal direction (X direction). The insulating spacer pattern 42 may include a first-first insulating spacer pattern 42_1 and a first-second insulating spacer pattern 42_2 disposed between the first NMOS source / drain regions 45. The first-first insulating spacer pattern 42_1 is disposed between the first-first NMOS source / drain regions 45_1 and the first NMOS gate dielectric layer 63n, and the first-second insulating spacer pattern 42_2 is disposed between the first-second NMOS source / drain regions 45_2 and the first NMOS gate dielectric layer 63n. The first-first insulating spacer pattern 42_1 may contact the first-first NMOS source / drain regions 45_1, and the first-second insulating spacer pattern 42_2 may contact the first-second NMOS source / drain regions 45_2.

[0034] In at least one first NMOS channel layer 9a, the maximum thickness of the portion perpendicularly overlapping the first NMOS gate electrode 69n in the vertical direction (Z direction) can be less than the maximum thickness of the portion perpendicularly overlapping the insulating spacer pattern 42 in the vertical direction (Z direction). Similarly, in at least one first NMOS channel layer 9a, the maximum thickness of the portion perpendicularly overlapping the first NMOS gate electrode 69n in the vertical direction (Z direction) can be less than the maximum thickness of the portion not perpendicularly overlapping the first NMOS gate electrode 69n in the vertical direction (Z direction). For example, the first NMOS intermediate channel layer 9a2 may have a first maximum thickness in the portion perpendicularly overlapping the first NMOS intermediate gate portion 69n_2, and may have a second maximum thickness greater than the first maximum thickness in the portion not perpendicularly overlapping the first NMOS intermediate gate portion 69n_2. This type of first NMOS channel layer 9a structure can increase the thickness of the first NMOS lower gate portion 69n_1, the first NMOS middle gate portion 69n_2, and the first NMOS upper gate portion 69n_3, thereby improving the electrical characteristics of the first NMOS gate electrode 69n. Therefore, the performance of the semiconductor device 1 can be improved.

[0035] In the first NMOS channel layer 9a, the thickness can refer to the thickness in the vertical direction (Z direction).

[0036] The first NMOS transistor structure nTR1S may further include a first NMOS insulating oxide layer 60. The first NMOS insulating oxide layer 60 may include silicon oxide. The minimum thickness of the insulating spacer pattern 42 may be greater than the minimum thickness of the first NMOS insulating oxide layer 60. Here, the thickness of the insulating spacer pattern 42 may be the thickness in the first horizontal direction (X direction), and the thickness of the first NMOS insulating oxide layer 60 may be the thickness in the direction perpendicular to the surface of the first NMOS gate dielectric layer 63n that contacts the first NMOS insulating oxide layer 60.

[0037] The first NMOS insulating oxide layer 60 may include a first NMOS lower insulating oxide layer 60_1 and a first NMOS upper insulating oxide layer 60_2.

[0038] The insulating oxide layer 60_2 on the first NMOS can contact the outer surface of the first NMOS gate dielectric layer 63n disposed on the side surface of the uppermost gate portion 69n_4 of the first NMOS and the lower surface of the first NMOS gate dielectric layer 63n disposed below the lower surface of the uppermost gate portion 69n_4 of the first NMOS.

[0039] The first NMOS lower insulating oxide layer 60_1 is disposed below each first NMOS channel layer 9a. A portion of the first NMOS lower insulating oxide layer 60_1 may include a spacer portion 60_1a and an interface portion 60_1b. The interface portion 60_1b may be an interface oxide layer.

[0040] The spacer portion 60_1a may be disposed between the insulating spacer pattern 42 and the first NMOS gate dielectric layer 63n. The interface portion 60_1b may extend from the spacer portion 60_1a, may overlap perpendicularly with the first NMOS gate electrode 69n, and may contact the first NMOS gate dielectric layer 63n. For example, spacer portion 60_1a may include: a portion disposed between the first insulating spacer pattern 42_1 and the first NMOS gate dielectric layer 63n, and a portion disposed between the first insulating spacer pattern 42_2 and the first NMOS gate dielectric layer 63n; and interface portion 60_1b may include: a portion contacting the lower surface of the first NMOS gate dielectric layer 63n disposed below the lower surface of each of the first NMOS lower gate portion 69n_1, the first NMOS intermediate gate portion 69n_2, and the first NMOS upper gate portion 69n_3, and a portion contacting the upper surface of the first NMOS gate dielectric layer 63n disposed on the upper surface of each of the first NMOS lower gate portion 69n_1, the first NMOS intermediate gate portion 69n_2, and the first NMOS upper gate portion 69n_3. For example, as Figure 3A As shown, when viewed with respect to the first NMOS intermediate gate portion 69n_2 as the center, the spacer portion 60_1a may include a portion disposed between the first-first insulating spacer pattern 42_1 and the first NMOS gate dielectric layer 63n, and a portion disposed between the first-second insulating spacer pattern 42_2 and the first NMOS gate dielectric layer 63n. The interface portion 60_1b may extend from the spacer portion 60_1a, and the interface portion 60_1b may include a portion disposed between the first NMOS lower channel layer 9a1 and the first NMOS gate dielectric layer 63n, and a portion disposed between the first NMOS intermediate channel layer 9a2 and the first NMOS gate dielectric layer 63n.

[0041] like Figure 3A As shown, when viewed with regard to the first-first insulating spacer pattern 42_1 and a spacer portion 60_1a in contact with the first-first insulating spacer pattern 42_1 as the center, the spacer portion 60_1a may include an intermediate portion 60_1a_M disposed between the first-first insulating spacer pattern 42_1 and the first NMOS gate dielectric layer 63n, a lower portion 60_1a_L extending downward from the intermediate portion 60_1a_M and having a maximum thickness greater than the thickness of the intermediate portion 60_1a_M, and an upper portion 60_1a_U extending upward from the intermediate portion 60_1a_M and having a maximum thickness greater than the thickness of the intermediate portion 60_1a_M.

[0042] In the first NMOS under insulating oxide layer 60_1, the thickness of each spacer portion 60_1a can be greater than the thickness of each interface portion 60_1b.

[0043] In the first NMOS lower insulating oxide layer 60_1, the thickness of each portion of the first NMOS lower insulating oxide layer 60_1 can refer to the thickness in the direction perpendicular to the surface of the first NMOS lower insulating oxide layer 60_1 that contacts the first NMOS gate dielectric layer 63n.

[0044] The first NMOS insulating spacer structure 41 may include an insulating spacer pattern 42 and a spacer portion 60_1a of the first NMOS lower insulating oxide layer 60_1.

[0045] The first NMOS source / drain region 45, the first NMOS channel layer 9a, the first NMOS gate electrode 69n, and the first NMOS gate dielectric layer 63n can form a first NMOS transistor. Figure 3A (45, 9a and 69n or 63n), and the first NMOS insulating spacer structure 41 can improve the first NMOS transistor ( Figure 3AThe performance of 45, 9a, and 69n or 63n). The first NMOS insulating spacer structure 41 can increase the separation distance between the drain region in the first NMOS source / drain region 45 and the first NMOS gate electrode 69n, thereby preventing the first NMOS transistor (45, 9a, and 69n or 63n) from the gate-induced drain leakage (GIDL) phenomenon. Figure 3A To minimize or reduce the leakage current of (45, 9a and 69n or 63n).

[0046] The interface portion 60_1b of the first NMOS lower insulating oxide layer 60_1 can be disposed between the first NMOS channel layer 9a and the first NMOS gate dielectric layer 63n, which can be formed of a high-k dielectric, thereby preventing interface defects that may occur when the first NMOS channel layer 9a and the first NMOS gate dielectric layer 63n come into contact with each other. Therefore, the interface portion 60_1b of the first NMOS lower insulating oxide layer 60_1 can improve the performance of the first NMOS transistor ( Figure 3A The performance and reliability of (45, 9a and 69n or 63n).

[0047] The second NMOS transistor structure nTR2S (see...) Figure 3B It may include a second NMOS source / drain region 30, a second NMOS channel layer 9b, a second NMOS gate electrode 72n, and a second NMOS gate dielectric layer 66n.

[0048] The second NMOS source / drain regions 30 may be spaced apart from each other in the first horizontal direction (X direction). Each second NMOS source / drain region 30 may have N-type conductivity. The second NMOS source / drain regions 30 may be formed of the same material as the first NMOS source / drain region 45.

[0049] In the first horizontal direction (X direction), the width of each second NMOS source / drain region 30 can be greater than the width of each first NMOS source / drain region 45. The maximum width of the second NMOS source / drain region 30 in the first horizontal direction (X direction) can be greater than the maximum width of the first NMOS source / drain region 45 in the first horizontal direction (X direction).

[0050] The second NMOS channel layer 9b can be disposed between the second NMOS source / drain regions 30. The second NMOS channel layer 9b can be disposed on the second active region 3b. The second NMOS channel layers 9b can be stacked in the vertical direction (Z direction) and spaced apart from each other. The second NMOS channel layer 9b can be connected to the second NMOS source / drain regions 30. The second NMOS channel layer 9b can include a semiconductor material, such as single-crystal silicon. The second NMOS channel layer 9b can be disposed at the same height as the first NMOS channel layer 9a.

[0051] The second NMOS channel layer 9b may include a second NMOS lower channel layer 9b1 located on the second active region 3b, a second NMOS intermediate channel layer 9b2 located on the second NMOS lower channel layer 9b1, and a second NMOS upper channel layer 9b3 located on the second NMOS intermediate channel layer 9b2. Although the number of second NMOS channel layers 9b is... Figure 2 and Figure 3B Three are shown, but the example embodiment is not limited to this. For example, the second NMOS channel layer 9b may include four or more channel layers stacked in the vertical direction (Z direction) and spaced apart from each other.

[0052] The width of the second NMOS channel layer 9b at a first height in the first horizontal direction (X direction) can be greater than the width of the first NMOS channel layer 9a at a first height in the first horizontal direction (X direction). For example, in the first horizontal direction (X direction), the width of the second NMOS intermediate channel layer 9b2 can be greater than the width of the first NMOS intermediate channel layer 9a2 at the same height as the second NMOS intermediate channel layer 9b2. The second NMOS gate electrode 72n can extend in the second horizontal direction (Y direction) and can surround each second NMOS channel layer 9b. The second NMOS gate electrode 72n can surround each second NMOS channel layer 9b and can extend in the second horizontal direction (Y direction), and can be disposed on the second active region 3b and the device isolation region 15.

[0053] The second NMOS gate electrode 72n may include a second NMOS lower gate portion 72n_1 located directly below the second NMOS lower channel layer 9b1, a second NMOS middle gate portion 72n_2 located directly below the second NMOS middle channel layer 9b2, a second NMOS upper gate portion 72n_3 located directly below the second NMOS upper channel layer 9b3, and a second NMOS uppermost gate portion 72n_4 located on the second NMOS upper channel layer 9b3. The second NMOS lower gate portion 72n_1 may be disposed between the second active region 3b and the second NMOS lower channel layer 9b1, the second NMOS middle gate portion 72n_2 may be disposed between the second NMOS lower channel layer 9b1 and the second NMOS middle channel layer 9b2, and the second NMOS upper gate portion 72n_3 may be disposed between the second NMOS middle channel layer 9b2 and the second NMOS upper channel layer 9b3.

[0054] The second NMOS gate dielectric layer 66n may be disposed between the second NMOS source / drain region 30 and the second NMOS gate electrode 72n, and may extend between the second NMOS gate electrode 72n and the second NMOS channel layer 9b. The second NMOS gate dielectric layer 66n may include a high-k dielectric.

[0055] In at least one second NMOS channel layer 9b, the maximum thickness of the portion that overlaps perpendicularly to the second NMOS gate electrode 72n in the vertical direction (Z direction) can be less than the maximum thickness of the portion that does not overlap perpendicularly to the second NMOS gate electrode 72n in the vertical direction (Z direction). In the second NMOS channel layer 9b, thickness can refer to the thickness in the vertical direction (Z direction).

[0056] The second NMOS transistor structure nTR2S may further include a second NMOS insulating oxide layer 57. The second NMOS insulating oxide layer 57 may include silicon oxide.

[0057] The second NMOS insulating oxide layer 57 may include a second NMOS lower insulating oxide layer 57_1 and a second NMOS upper insulating oxide layer 57_2.

[0058] The insulating oxide layer 57_2 on the second NMOS can contact the outer surface of the second NMOS gate dielectric layer 66n disposed on the side surface of the uppermost gate portion 72n_4 of the second NMOS and the lower surface of the second NMOS gate dielectric layer 66n disposed below the lower surface of the uppermost gate portion 72n_4 of the second NMOS.

[0059] In the second NMOS under insulating oxide layer 57_1, a portion of the second NMOS under insulating oxide layer 57_1 disposed below each second NMOS channel layer 9b may include a spacer portion 57_1a and an interface portion 57_1b. The interface portion 57_1b may be an interface oxide layer.

[0060] The spacer portion 57_1a can be disposed between the second NMOS source / drain region 30 and the second NMOS gate dielectric layer 66n. The spacer portion 57_1a can contact the second NMOS source / drain region 30 and the second NMOS gate dielectric layer 66n.

[0061] The spacer portion 57_1a can be defined as the second NMOS insulating spacer structure 57_1a.

[0062] Interface portion 57_1b may extend from spacer portion 57_1a and may contact the second NMOS gate dielectric layer 66n that is perpendicularly overlapping with the second NMOS gate electrode 72n. Interface portion 57_1b may include: a portion contacting the lower surface of the second NMOS gate dielectric layer 66n disposed below the lower surface of each of the second NMOS lower gate portion 72n_1, the second NMOS intermediate gate portion 72n_2, and the second NMOS upper gate portion 72n_3; and a portion contacting the upper surface of the second NMOS gate dielectric layer 66n disposed on the upper surface of each of the second NMOS lower gate portion 72n_1, the second NMOS intermediate gate portion 72n_2, and the second NMOS upper gate portion 72n_3. Interface portion 57_1b may extend from spacer portion 57_1a.

[0063] like Figure 3B As shown, when viewed with respect to the second NMOS intermediate gate portion 72n_2 as the center, the interface portion 57_1b may include a portion disposed between the second NMOS lower channel layer 9b1 and the second NMOS gate dielectric layer 66n, and a portion disposed between the second NMOS intermediate channel layer 9b2 and the second NMOS gate dielectric layer 66n.

[0064] like Figure 3B As shown, when viewed with respect to one of the spacer portions 57_1a, the spacer portion 57_1a may include a middle portion 57_1a_M disposed in the middle, a lower portion 57_1a_L extending downward from the middle portion 57_1a_M and having a maximum thickness greater than the thickness of the middle portion 57_1a_M, and an upper portion 57_1a_U extending upward from the middle portion 57_1a_M and having a maximum thickness greater than the thickness of the middle portion 57_1a_M.

[0065] In the insulating oxide layer 57_1 under the second NMOS, the thickness of each spacer portion 57_1a can be greater than the thickness of each interface portion 57_1b.

[0066] In the second NMOS lower insulating oxide layer 57_1, the thickness of each portion of the second NMOS lower insulating oxide layer 57_1 can refer to the thickness in the direction perpendicular to the surface of the second NMOS lower insulating oxide layer 57_1 that contacts the second NMOS gate dielectric layer 66n.

[0067] The second NMOS source / drain region 30, the second NMOS channel layer 9b, the second NMOS gate electrode 72n, and the second NMOS gate dielectric layer 66n can form a second NMOS transistor. Figure 3B(30, 9b and 72n or 66n), and the spacer portion 57_1a, that is, the second NMOS insulating spacer structure 57_1a, can improve the second NMOS transistor ( Figure 3B The performance of the 30, 9b, and 72n or 66n). The second NMOS insulating spacer structure 57_1a can increase the separation distance between the drain region of the second NMOS source / drain region 30 and the second NMOS gate electrode 72n, thereby preventing the second NMOS transistor ( ) from being affected by gate-induced drain leakage (GIDL). Figure 3B To minimize or reduce the leakage current of 30, 9b and 72n or 66n.

[0068] Since the second NMOS transistor structure nTR2S does not include the insulating spacer pattern 42 of the first NMOS insulating spacer structure 41, a second NMOS source / drain region 30 with a width greater than that of the first NMOS source / drain region 45 can be reliably formed. Therefore, the reliability of the second NMOS source / drain region 30, which has a width greater than that of the first NMOS source / drain region 45, can be increased.

[0069] The interface portion 57_1b of the second NMOS lower insulating oxide layer 57_1 can be disposed between the second NMOS channel layer 9b and the second NMOS gate dielectric layer 66n, which can be formed of a high-k dielectric, thereby preventing interface defects that may occur when the second NMOS channel layer 9b and the second NMOS gate dielectric layer 66n come into contact with each other. Therefore, the interface portion 57_1b of the second NMOS lower insulating oxide layer 57_1 can improve the performance of the second NMOS transistor ( Figure 3B The performance and reliability of (30, 9b and 72n or 66n).

[0070] The first PMOS transistor structure pTR1S (see...) Figure 6A It may include a first PMOS source / drain region 128, a first PMOS channel layer 9c, a first PMOS gate electrode 69p, and a first PMOS gate dielectric layer 63p.

[0071] The first PMOS source / drain regions 128 may be spaced apart from each other in a first horizontal direction (X direction). Each first PMOS source / drain region 128 may have P-type conductivity. Each first PMOS source / drain region 128 may include an epitaxially grown semiconductor material. For example, each first PMOS source / drain region 128 may include at least one of germanium (Ge) and silicon germanium (SiGe).

[0072] A first PMOS channel layer 9c may be disposed between the first PMOS source / drain regions 128. The first PMOS channel layer 9c may be disposed on the third active region 3c. The first PMOS channel layers 9c may be stacked in the vertical direction (Z direction) and spaced apart from each other. The first PMOS channel layer 9c may be connected to the first PMOS source / drain regions 128. The first PMOS channel layer 9c may comprise a semiconductor material, such as single-crystal silicon.

[0073] The first PMOS channel layer 9c may include a first PMOS lower channel layer 9c1 located on the third active region 3c, a first PMOS intermediate channel layer 9c2 located on the first PMOS lower channel layer 9c1, and a first PMOS upper channel layer 9c3 located on the first PMOS intermediate channel layer 9c2. Figure 5 and Figure 6A In this example, the number of first PMOS channel layers 9c is shown as three, but the example embodiment is not limited to this. For example, the first PMOS channel layers 9c may include four or more channel layers stacked in the vertical direction (Z direction) and spaced apart from each other.

[0074] The first PMOS gate electrode 69p may extend in the second horizontal direction (Y direction) and may surround each first PMOS channel layer 9c. The first PMOS gate electrode 69p may surround each first PMOS channel layer 9c and may extend in the second horizontal direction (Y direction), and may be disposed on the third active region 3c and the device isolation region 15.

[0075] The first PMOS gate electrode 69p may include a first PMOS lower gate portion 69p_1 located directly below the first PMOS lower channel layer 9c1, a first PMOS middle gate portion 69p_2 located directly below the first PMOS middle channel layer 9c2, a first PMOS upper gate portion 69p_3 located directly below the first PMOS upper channel layer 9c3, and a first PMOS uppermost gate portion 69p_4 located on the first PMOS upper channel layer 9c3. The first PMOS lower gate portion 69p_1 may be disposed between the third active region 3c and the first PMOS lower channel layer 9c1, the first PMOS middle gate portion 69p_2 may be disposed between the first PMOS lower channel layer 9c1 and the first PMOS middle channel layer 9c2, and the first PMOS upper gate portion 69p_3 may be disposed between the first PMOS middle channel layer 9c2 and the first PMOS upper channel layer 9c3.

[0076] The first PMOS gate dielectric layer 63p may be disposed between the first PMOS source / drain region 128 and the first PMOS gate electrode 69p, and may extend between the first PMOS gate electrode 69p and the first PMOS channel layer 9c. The first PMOS gate dielectric layer 63p may include a high-k dielectric.

[0077] In at least one first PMOS channel layer 9c, the maximum thickness of the portion that overlaps perpendicularly to the first PMOS gate electrode 69p in the vertical direction (Z direction) can be less than the maximum thickness of the portion that does not overlap perpendicularly to the first PMOS gate electrode 69p in the vertical direction (Z direction). In the first PMOS channel layer 9c, thickness can refer to the thickness in the vertical direction (Z direction).

[0078] The first PMOS transistor structure pTR1S may further include a first PMOS insulating oxide layer 158. The first PMOS insulating oxide layer 158 may include silicon oxide.

[0079] The first PMOS insulating oxide layer 158 may include a first PMOS lower insulating oxide layer 158_1 and a first PMOS upper insulating oxide layer 158_2.

[0080] The insulating oxide layer 158_2 on the first PMOS can contact the outer surface of the first PMOS gate dielectric layer 63p disposed on the side surface of the uppermost gate portion 69p_4 of the first PMOS and the lower surface of the first PMOS gate dielectric layer 63p disposed below the lower surface of the uppermost gate portion 69p_4 of the first PMOS.

[0081] In the first PMOS under insulating oxide layer 158_1, a portion of the first PMOS under insulating oxide layer 158_1 disposed below each first PMOS channel layer 9c may include a spacer portion 158_1a and an interface portion 158_1b.

[0082] The spacer portion 158_1a can be disposed between the first PMOS source / drain region 128 and the first PMOS gate dielectric layer 63p. The spacer portion 158_1a can contact the first PMOS source / drain region 128 and the first PMOS gate dielectric layer 63p.

[0083] The spacer portion 158_1a can be defined as the first PMOS insulating spacer structure 158_1a.

[0084] Interface portion 158_1b may extend from spacer portion 158_1a and may contact the first PMOS gate dielectric layer 63p that is perpendicularly overlapping with the first PMOS gate electrode 69p. Interface portion 158_1b may include: a portion contacting the lower surface of the first PMOS gate dielectric layer 63p disposed below the lower surface of each of the first PMOS lower gate portion 69p_1, the first PMOS intermediate gate portion 69p_2, and the first PMOS upper gate portion 69p_3; and a portion contacting the upper surface of the first PMOS gate dielectric layer 63p disposed on the upper surface of each of the first PMOS lower gate portion 69p_1, the first PMOS intermediate gate portion 69p_2, and the first PMOS upper gate portion 69p_3. Interface portion 158_1b may extend from spacer portion 158_1a.

[0085] like Figure 6A As shown, when viewed with respect to the first PMOS intermediate gate portion 69p_2 as the center, the interface portion 158_1b may include a portion disposed between the first PMOS lower channel layer 9c1 and the first PMOS gate dielectric layer 63p, and a portion disposed between the first PMOS intermediate channel layer 9c2 and the first PMOS gate dielectric layer 63p.

[0086] like Figure 6A As shown, when viewed with one of the spacer portions 158_1a as the center, the spacer portion 158_1a may include a middle portion 158_1a_M disposed in the middle, a lower portion 158_1a_L extending downward from the middle portion 158_1a_M and having a maximum thickness greater than the thickness of the middle portion 158_1a_M, and an upper portion 158_1a_U extending upward from the middle portion 158_1a_M and having a maximum thickness greater than the thickness of the middle portion 158_1a_M.

[0087] In the first PMOS lower insulating oxide layer 158_1, the thickness of each spacer portion 158_1a can be greater than the thickness of each interface portion 158_1b.

[0088] In the first PMOS lower insulating oxide layer 158_1, the thickness of each portion of the first PMOS lower insulating oxide layer 158_1 can refer to the thickness in the direction perpendicular to the surface of the first PMOS lower insulating oxide layer 158_1 that contacts the first PMOS gate dielectric layer 63p.

[0089] The first PMOS source / drain region 128, the first PMOS channel layer 9c, the first PMOS gate electrode 69p, and the first PMOS gate dielectric layer 63p can form a first PMOS transistor. Figure 6A 128, 9c and 69p or 63p), and the spacer portion 158_1a, that is, the first PMOS insulating spacer structure 158_1a, can improve the first PMOS transistor ( Figure 6A The performance of the 128, 9c, and 69p or 63p of the first PMOS transistor is improved. The first PMOS insulating spacer structure 158_1a can increase the separation distance between the drain region of the first PMOS source / drain region 128 and the first PMOS gate electrode 69p, thereby preventing the first PMOS transistor from being damaged by gate-induced drain leakage (GIDL). Figure 6A To minimize or reduce the leakage current of 128, 9c and 69p or 63p.

[0090] The interface portion 158_1b of the first PMOS lower insulating oxide layer 158_1 can be disposed between the first PMOS channel layer 9c and the first PMOS gate dielectric layer 63p, which can be formed of a high-k dielectric, thereby preventing interface defects that may occur when the first PMOS channel layer 9c and the first PMOS gate dielectric layer 63p come into contact with each other. Therefore, the interface portion 158_1b of the first PMOS lower insulating oxide layer 158_1 can improve the performance of the first PMOS transistor ( Figure 6A The performance and reliability of (128, 9c and 69p or 63p).

[0091] The second PMOS transistor structure pTR2S (see...) Figure 6B It may include a second PMOS source / drain region 129, a second PMOS channel layer 9d, a second PMOS gate electrode 72p, and a second PMOS gate dielectric layer 66p.

[0092] The second PMOS source / drain regions 129 may be spaced apart from each other in a first horizontal direction (X direction). Each second PMOS source / drain region 129 may have P-type conductivity. Each second PMOS source / drain region 129 may include an epitaxially grown semiconductor material. For example, each second PMOS source / drain region 129 may include at least one of germanium (Ge) or silicon germanium (SiGe).

[0093] In the first horizontal direction (X direction), the width of each second PMOS source / drain region 129 can be greater than the width of each first PMOS source / drain region 128.

[0094] The second PMOS channel layer 9d can be disposed between the second PMOS source / drain regions 129. The second PMOS channel layer 9d can be disposed on the fourth active region 3d. The second PMOS channel layers 9d can be stacked in the vertical direction (Z direction) and spaced apart from each other. The second PMOS channel layer 9d can be connected to the second PMOS source / drain regions 129. The second PMOS channel layer 9d can include a semiconductor material, such as single-crystal silicon.

[0095] The second PMOS channel layer 9d may include a second PMOS lower channel layer 9d1 located on the fourth active region 3d, a second PMOS intermediate channel layer 9d2 located on the second PMOS lower channel layer 9d1, and a second PMOS upper channel layer 9d3 located on the second PMOS intermediate channel layer 9d2. Although the number of second PMOS channel layers 9d is... Figure 5 and Figure 6B The example is shown as three, but the example embodiment is not limited to this. For example, the second PMOS channel layer 9d may include four or more channel layers stacked in the vertical direction (Z direction) and spaced apart from each other.

[0096] The second PMOS gate electrode 72p can extend in the second horizontal direction (Y direction) and can surround the second PMOS channel layer 9d. The second PMOS gate electrode 72p can surround the second PMOS channel layer 9d and can extend in the second horizontal direction (Y direction), and can be disposed on the fourth active region 3d and the device isolation region 15.

[0097] The second PMOS gate electrode 72p may include a second PMOS lower gate portion 72p_1 located directly below the second PMOS lower channel layer 9d1, a second PMOS middle gate portion 72p_2 located directly below the second PMOS middle channel layer 9d2, a second PMOS upper gate portion 72p_3 located directly below the second PMOS upper channel layer 9d3, and a second PMOS uppermost gate portion 72p_4 located on the second PMOS upper channel layer 9d3. The second PMOS lower gate portion 72p_1 may be disposed between the fourth active region 3d and the second PMOS lower channel layer 9d1, the second PMOS middle gate portion 72p_2 may be disposed between the second PMOS lower channel layer 9d1 and the second PMOS middle channel layer 9d2, and the second PMOS upper gate portion 72p_3 may be disposed between the second PMOS middle channel layer 9d2 and the second PMOS upper channel layer 9d3.

[0098] The second PMOS gate dielectric layer 66p can be disposed between the second PMOS source / drain region 129 and the second PMOS gate electrode 72p, and can extend between the second PMOS gate electrode 72p and the second PMOS channel layer 9d. The second PMOS gate dielectric layer 66p may include a high-k dielectric.

[0099] In at least one second PMOS channel layer 9d, the maximum thickness of the portion that overlaps perpendicularly to the second PMOS gate electrode 72p in the vertical direction (Z direction) can be less than the maximum thickness of the portion that does not overlap perpendicularly to the second PMOS gate electrode 72p in the vertical direction (Z direction). In the second PMOS channel layer 9d, thickness can refer to the thickness in the vertical direction (Z direction).

[0100] The second PMOS transistor structure pTR2S may further include a second PMOS insulating oxide layer 159. The second PMOS insulating oxide layer 159 may include silicon oxide.

[0101] The second PMOS insulating oxide layer 159 may include a second PMOS lower insulating oxide layer 159_1 and a second PMOS upper insulating oxide layer 159_2.

[0102] The insulating oxide layer 159_2 on the second PMOS can contact the outer surface of the second PMOS gate dielectric layer 66p disposed on the side surface of the gate portion 72p_4 on the second PMOS and the lower surface of the second PMOS gate dielectric layer 66p disposed below the lower surface of the gate portion 72p_4 on the second PMOS.

[0103] In the second PMOS under insulating oxide layer 159_1, a portion of the second PMOS under insulating oxide layer 159_1 disposed below each second PMOS channel layer 9d may include a spacer portion 159_1a and an interface portion 159_1b.

[0104] The spacer portion 159_1a can be disposed between the second PMOS source / drain region 129 and the second PMOS gate dielectric layer 66p. The spacer portion 159_1a can contact the second PMOS source / drain region 129 and the second PMOS gate dielectric layer 66p.

[0105] The spacer portion 159_1a can be defined as the second PMOS insulating spacer structure 159_1a.

[0106] Interface portion 159_1b may extend from spacer portion 159_1a and may contact the second PMOS gate dielectric layer 66p that is perpendicularly overlapping with the second PMOS gate electrode 72p. Interface portion 159_1b may include: a portion contacting the lower surface of the second PMOS gate dielectric layer 66p disposed below the lower surface of each of the second PMOS lower gate portion 72p_1, the second PMOS intermediate gate portion 72p_2, and the second PMOS upper gate portion 72p_3; and a portion contacting the upper surface of the second PMOS gate dielectric layer 66p disposed on the upper surface of each of the second PMOS lower gate portion 72p_1, the second PMOS intermediate gate portion 72p_2, and the second PMOS upper gate portion 72p_3. Interface portion 159_1b may extend from spacer portion 159_1a.

[0107] like Figure 6B As shown, when viewed with respect to the second PMOS intermediate gate portion 72p_2 as the center, the interface portion 159_1b may include a portion disposed between the second PMOS lower channel layer 9d1 and the second PMOS gate dielectric layer 66p, and a portion disposed between the second PMOS intermediate channel layer 9d2 and the second PMOS gate dielectric layer 66p.

[0108] like Figure 6B As shown, when viewed from the center with respect to one of the spacer portions 159_1a, the spacer portion 159_1a may include a middle portion 159_1a_M disposed in the middle, a lower portion 159_1a_L extending downward from the middle portion 159_1a_M and having a maximum thickness greater than the thickness of the middle portion 159_1a_M, and an upper portion 159_1a_U extending upward from the middle portion 159_1a_M and having a maximum thickness greater than the thickness of the middle portion 159_1a_M.

[0109] In the second PMOS under insulating oxide layer 159_1, the thickness of each spacer portion 159_1a can be greater than the thickness of each interface portion 159_1b.

[0110] In the second PMOS lower insulating oxide layer 159_1, the thickness of each portion of the second PMOS lower insulating oxide layer 159_1 can refer to the thickness in the direction perpendicular to the surface of the second PMOS lower insulating oxide layer 159_1 that contacts the second PMOS gate dielectric layer 66p.

[0111] The second PMOS source / drain region 129, the second PMOS channel layer 9d, the second PMOS gate electrode 72p, and the second PMOS gate dielectric layer 66p can form a second PMOS transistor. Figure 6B 129, 9d and 72p or 66p), and the spacer portion 159_1a, that is, the second PMOS insulating spacer structure 159_1a, can improve the second PMOS transistor ( Figure 6B The performance of the second PMOS transistor (129, 9d, and 72p or 66p) is improved. The second PMOS insulating spacer structure 159_1a can increase the separation distance between the drain region of the second PMOS source / drain region 129 and the second PMOS gate electrode 72p, thereby preventing the second PMOS transistor (129, 9d, and 72p or 66p) from being affected by gate-induced drain leakage (GIDL). Figure 6B To minimize or reduce the leakage current of 129, 9d and 72p or 66p.

[0112] The interface portion 159_1b of the second PMOS lower insulating oxide layer 159_1 can be disposed between the second PMOS channel layer 9d and the second PMOS gate dielectric layer 66p, which can be formed of a high-k dielectric, thereby preventing interface defects that may occur when the second PMOS channel layer 9d and the second PMOS gate dielectric layer 66p come into contact with each other. Therefore, the interface portion 159_1b of the second PMOS lower insulating oxide layer 159_1 can improve the performance of the second PMOS transistor ( Figure 6B The performance and reliability of (129, 9d and 72p or 66p).

[0113] The semiconductor device 1 may also include a first insulating liner 21, a second insulating liner 33, a third insulating liner 48, and an interlayer insulating layer 51.

[0114] Within the first NMOS region N1, an interlayer insulating layer 51 can be disposed on the source / drain region 45 of the first NMOS. A third insulating pad 48 can cover the side and bottom surfaces of the interlayer insulating layer 51. A second insulating pad 33 can be disposed between the third insulating pad 48 and the insulating oxide layer 60_2 on the first NMOS. Furthermore, a first insulating pad 21 can be disposed between the second insulating pad 33 and the insulating oxide layer 60_2 on the first NMOS, and can also be disposed between the second insulating pad 33 and the upper channel layer 9a3 of the first NMOS. Within the first NMOS region N1, the first insulating pad 21 and the second insulating pad 33 can be disposed on the upper channel layer 9a3 of the first NMOS, and the third insulating pad 48 can be disposed on the source / drain region 45 of the first NMOS.

[0115] Within the second NMOS region N2, an interlayer insulating layer 51 can be disposed on the source / drain region 30 of the second NMOS. A third insulating pad 48 can cover the side and bottom surfaces of the interlayer insulating layer 51. A second insulating pad 33 can be disposed between the third insulating pad 48 and the insulating oxide layer 57_2 on the second NMOS, and between the source / drain region 30 of the second NMOS and the third insulating pad 48. A first insulating pad 21 can be disposed between the second insulating pad 33 and the insulating oxide layer 57_2 on the second NMOS.

[0116] Within the first PMOS region P1, an interlayer insulating layer 51 can be disposed on the source / drain region 128 of the first PMOS. A third insulating pad 48 can cover the side and bottom surfaces of the interlayer insulating layer 51. A second insulating pad 33 can be disposed between the third insulating pad 48 and the insulating oxide layer 158_2 on the first PMOS, and between the source / drain region 128 of the first PMOS and the third insulating pad 48. Furthermore, a first insulating pad 21 can be disposed between the second insulating pad 33 and the insulating oxide layer 158_2 on the first PMOS.

[0117] Within the second PMOS region P2, an interlayer insulating layer 51 can be disposed on the source / drain region 129 of the second PMOS. A third insulating pad 48 can cover the side and bottom surfaces of the interlayer insulating layer 51. A second insulating pad 33 can be disposed between the third insulating pad 48 and the insulating oxide layer 159_2 on the second PMOS, as well as between the source / drain region 129 of the second PMOS and the third insulating pad 48. A first insulating pad 21 can be disposed between the second insulating pad 33 and the insulating oxide layer 159_2 on the second PMOS.

[0118] The upper surfaces of the first NMOS gate electrode 69n, the second NMOS gate electrode 72n, the first PMOS gate electrode 69p, the second PMOS gate electrode 72p, the first NMOS gate dielectric layer 63n, the second NMOS gate dielectric layer 66n, the first PMOS gate dielectric layer 63p, the second PMOS gate dielectric layer 66p, the first NMOS insulating oxide layer 60, the second NMOS insulating oxide layer 57, the first PMOS insulating oxide layer 158, the second PMOS insulating oxide layer 159, the first insulating pad 21, the second insulating pad 33, the third insulating pad 48, and the interlayer insulating layer 51 can be coplanar with each other.

[0119] The semiconductor device 1 may further include a first cover insulating layer 75, a first intermetallic insulating layer 78, a second cover insulating layer 88, a second intermetallic insulating layer 90, and a third intermetallic insulating layer 98 stacked sequentially.

[0120] The thickness of each of the first intermetallic insulating layer 78, the second intermetallic insulating layer 90, and the third intermetallic insulating layer 98 may be greater than the thickness of each of the first covering insulating layer 75 and the second covering insulating layer 88.

[0121] The first insulating layer 75 may cover or be located on the first NMOS gate electrode 69n, the second NMOS gate electrode 72n, the first PMOS gate electrode 69p, the second PMOS gate electrode 72p, the first NMOS gate dielectric layer 63n, the second NMOS gate dielectric layer 66n, the first PMOS gate dielectric layer 63p, the second PMOS gate dielectric layer 66p, the first NMOS insulating oxide layer 60, the second NMOS insulating oxide layer 57, the first PMOS insulating oxide layer 158, the second PMOS insulating oxide layer 159, the first insulating pad 21, the second insulating pad 33, the third insulating pad 48, and the interlayer insulating layer 51.

[0122] The first overlay insulating layer 75 and the second overlay insulating layer 88 may comprise materials different from those of the first intermetallic insulating layer 78, the second intermetallic insulating layer 90, the third intermetallic insulating layer 98, and the interlayer insulating layer 51. For example, the first overlay insulating layer 75 and the second overlay insulating layer 88 may comprise silicon nitride or metal oxide, and the first intermetallic insulating layer 78, the second intermetallic insulating layer 90, the third intermetallic insulating layer 98, and the interlayer insulating layer 51 may comprise silicon oxide or a low-k dielectric with a dielectric constant lower than that of silicon oxide.

[0123] The semiconductor device 1 may also include source / drain contact structures 81n1, 81n2, 81p1 and 81p2.

[0124] Each of the source / drain contact structures 81n1, 81n2, 81p1, and 81p2 can contact and be electrically connected to a corresponding source / drain region among the source / drain regions 45, 30, 128, and 129. For example, each source / drain contact structure 81n1, 81n2, 81p1, and 81p2 may include a metal-semiconductor compound layer 83 and a source / drain contact plug 85 located on the metal-semiconductor compound layer 83. The source / drain contact plug 85 may include a plug conductive pattern 85b and a conductive barrier layer 85a covering the side and bottom surfaces of the plug conductive pattern 85b. In each of the source / drain contact structures 81n1, 81n2, 81p1, and 81p2, the metal-semiconductor compound layer 83 can contact a corresponding source / drain region among the source / drain regions 45, 30, 128, and 129. In each of the source / drain contact structures 81n1, 81n2, 81p1, and 81p2, a metal-semiconductor compound layer 83 may be disposed between the respective source / drain region and the source / drain contact plug 85 in the source / drain regions 45, 30, 128, and 129.

[0125] The second covering insulating layer 88 can be disposed on the upper surface of the source / drain contact structures 81n1, 81n2, 81p1 and 81p2 and on the upper surface of the first intermetallic insulating layer 78.

[0126] The semiconductor device 1 may also include gate contact structures 93n1, 93n2, 93p1 and 93p2.

[0127] Gate contact structures 93n1, 93n2, 93p1, and 93p2 can penetrate the second intermetallic insulating layer 90, the second cover insulating layer 88, the first intermetallic insulating layer 78, and the first cover insulating layer 75, and can be electrically connected to gate electrodes 69n, 72n, 69p, and 72p. Each of the gate contact structures 93n1, 93n2, 93p1, and 93p2 can be electrically connected to a corresponding gate electrode among the gate electrodes 69n, 72n, 69p, and 72p. Gate contact structures 93n1, 93n2, 93p1, and 93p2 may include a first NMOS gate contact structure 93n1 connected to the first NMOS gate electrode 69n, a second NMOS gate contact structure 93n2 connected to the second NMOS gate electrode 72n, a first PMOS gate contact structure 93p1 connected to the first PMOS gate electrode 69p, and a second PMOS gate contact structure 93p2 connected to the second PMOS gate electrode 72p.

[0128] The semiconductor device 1 may further include interconnect structures 95n1, 95n2, 95p1, 95p2, 96n1, 96n2, 96p1, and 96p2 electrically connected to gate contact structures 93n1, 93n2, 93p1, and 93p2 and source / drain contact structures 81n1, 81n2, 81p1, and 81p2. The interconnect structures 95n1, 95n2, 95p1, 95p2, 96n1, 96n2, 96p1, and 96p2 may be disposed on the second intermetallic insulating layer 90, the gate contact structures 93n1, 93n2, 93p1, and 93p2, and the source / drain contact structures 81n1, 81n2, 81p1, and 81p2. Each of the interconnect structures 95n1, 95n2, 95p1, 95p2, 96n1, 96n2, 96p1, and 96p2 can be connected to a corresponding contact structure in the gate contact structures 93n1, 93n2, 93p1, and 93p2 and the source / drain contact structures 81n1, 81n2, 81p1, and 81p2. A third intermetallic insulating layer 98 can be disposed on the second intermetallic insulating layer 90 and the interconnect structures 95n1, 95n2, 95p1, 95p2, 96n1, 96n2, 96p1, and 96p2.

[0129] Next, various modified example embodiments of the elements of the above embodiments will be described. The various modified example embodiments of the elements of the above embodiments described below will focus on the modified or replaced elements. Here, previously described elements may be directly referenced without separate detailed description, or their description may be omitted. Furthermore, the modified or replaced elements described below will be described with reference to the accompanying drawings; however, according to the example embodiments of this disclosure, the modified or replaced elements may be combined with each other or with the previously described elements to form a semiconductor device 1.

[0130] Figure 8 It is shown Figure 3A A partially enlarged cross-sectional view of the modified portion in a partially enlarged view, illustrating an exemplary example of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0131] In the example embodiment, reference Figure 8 The first NMOS insulating oxide layer 60 described above (see above) Figure 3A ) can be formed as 60_1a with the spacer portion omitted (see Figure 3A The interface portion 60_1b (see...) was retained. Figure 3A The first NMOS insulating oxide layer 160 in the form of a ) is replaced. That is, the first NMOS insulating oxide layer 160 can replace Figure 3AThe interface portion 60_1b. The first NMOS insulating oxide layer 160 may be disposed between the first NMOS gate dielectric layer 63n and the first NMOS channel layer 9a, and between the first NMOS gate dielectric layer 63n and the first active region 3a.

[0132] Due to the first NMOS insulating oxide layer 60 described above (see...) Figure 3A The first NMOS insulating oxide layer 160 is used instead, therefore the first NMOS insulating spacer structure 41 described above (see...) Figure 3A The insulating spacer pattern 42 that contacts the first NMOS gate dielectric layer 63n can be used instead.

[0133] Figure 9 It is shown Figure 6A A partially enlarged cross-sectional view of a modified portion of a partial enlarged view, used to illustrate an exemplary example of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0134] In the example embodiment, reference Figure 9 The first PMOS insulating oxide layer 158 described above (see above) Figure 6A ) can be formed by omitting the spacer portion 158_1a (see Figure 6A The interface portion 158_1b (see...) was retained. Figure 6A The first PMOS insulating oxide layer 258 is replaced in the form of a ) . That is, the first PMOS insulating oxide layer 258 can replace Figure 6A The interface section 158_1b is omitted. The spacer section 158_1a (see [link to interface section]) is also omitted. Figure 6A Therefore, the size of the first PMOS gate electrode 69p can be increased, thereby improving the electrical characteristics of the gate electrode of the PMOS transistor including the first PMOS gate electrode 69p. The first PMOS insulating oxide layer 258 can be disposed between the first PMOS gate dielectric layer 63p and the first PMOS channel layer 9c, and between the first PMOS gate dielectric layer 63p and the third active region 3c. Therefore, the first PMOS gate dielectric layer 63p can contact the first PMOS source / drain region 128.

[0135] Figure 10 It is shown Figure 6B A partially enlarged cross-sectional view of a modified portion of a partial enlarged view, used to illustrate an exemplary example of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0136] In the example embodiment, reference Figure 10 The second PMOS insulating oxide layer 159 described above (see above) Figure 6B ) can be formed by omitting the spacer portion 159_1a (see Figure 6B The interface portion 159_1b (see...) was retained. Figure 6B The second PMOS insulating oxide layer 259 is replaced in the form of ) . Since the spacer portion 159_1a is omitted (see Figure 6B Therefore, the size of the second PMOS gate electrode 72p can be increased, thereby improving the electrical characteristics of the gate electrode of the PMOS transistor including the second PMOS gate electrode 72p. The second PMOS insulating oxide layer 259 can be disposed between the second PMOS gate dielectric layer 66p and the second PMOS channel layer 9d, and between the first PMOS gate dielectric layer 63p and the third active region 3c. Therefore, the first PMOS gate dielectric layer 63p can contact the first PMOS source / drain region 128.

[0137] Figure 11 It shows along Figure 1A The line I-I' and Figure 1B A cross-sectional view of the region intercepted by line II-II', to illustrate an exemplary example of a semiconductor device according to an exemplary embodiment of the present disclosure, and may show... Figure 2 The modified part in the sectional view. Figure 12 yes Figure 11 A magnified view of the area indicated by "Aa", and Figure 13 yes Figure 11 A magnified view of the area indicated by “Ba”.

[0138] refer to Figure 11 , Figure 12 and Figure 13 In the first NMOS gate electrode 69n, the first NMOS intermediate gate portion 69n_2 described above (see...) Figure 3A The first NMOS intermediate gate portion 69n_2', with its width increased in the first horizontal direction (X direction), and the first NMOS lower gate portion 69n_1 described above (see...) Figure 3A It can be modified to have a first NMOS lower gate portion 69n_1' with increased width in the first horizontal direction (X direction).

[0139] In the first horizontal direction (X direction), the first NMOS intermediate gate portion 69n_2' may have a wider width than the width of the first NMOS upper gate portion 69n_3 described above, and the first NMOS lower gate portion 69n_1' may have a wider width than the width of the first NMOS intermediate gate portion 69n_2'. Therefore, the overall size of the first NMOS gate electrode 69n can be increased, thereby improving the electrical characteristics of the gate electrode of the NMOS transistor including the first NMOS gate electrode 69n.

[0140] In the second NMOS gate electrode 72n, the second NMOS intermediate gate portion 72n_2 described above (see...) Figure 3B The second NMOS intermediate gate portion 72n_2', with its width increased in the first horizontal direction (X direction), can be modified to include the second NMOS lower gate portion 72n_1 described above (see [link to documentation]). Figure 3B It can be modified to be a second NMOS lower gate portion 72n_1' with increased width in the first horizontal direction (X direction).

[0141] In the first horizontal direction (X direction), the second NMOS intermediate gate portion 72n_2' can have a wider width than the width of the second NMOS upper gate portion 72n_3 described above, and the second NMOS lower gate portion 72n_1' can have a wider width than the width of the second NMOS intermediate gate portion 72n_2'. Therefore, the overall size of the second NMOS gate electrode 72n can be increased, thereby improving the electrical characteristics of the gate electrode of the NMOS transistor including the second NMOS gate electrode 72n.

[0142] Figure 14 It shows along Figure 1A A cross-sectional view of the region intercepted by line I-I' is provided to illustrate an exemplary example of a semiconductor device according to an exemplary embodiment of the present disclosure, and may show... Figure 2 The modified portion in the cross-sectional section of line I-I', and Figure 15 It shows along Figure 1B A cross-sectional view of the region intercepted by line II-II', to illustrate an exemplary example of a semiconductor device according to an exemplary embodiment of the present disclosure, and may show... Figure 2 The modified part in the section of line II-II'.

[0143] refer to Figure 14 and Figure 15 The first NMOS source / drain region 45 described above (see above) Figure 2 and Figure 3A The first NMOS source / drain region 345a and the second NMOS source / drain region 345b, which are spaced apart from each other in the first horizontal direction (X direction), can be replaced by the second NMOS source / drain region 30 described above (see...). Figure 2 and Figure 3B The first NMOS source / drain region 330a and the second NMOS source / drain region 330b, which are spaced apart from each other in the first horizontal direction (X direction), can be used instead.

[0144] Above Figure 2 , Figure 3A and Figure 3BThe substrate 3, the first active region 3a, and the second active region 3b described herein can be replaced by a semiconductor substrate 303a with reduced thickness. The semiconductor substrate 303a can be disposed below the first NMOS channel layer 9a and the second NMOS channel layer 9b, the first NMOS gate electrode 69n and the second NMOS gate electrode 72n, the first-first NMOS source / drain region 345a, the first-second NMOS source / drain region 345b, the second-first NMOS source / drain region 330a, and the second-second NMOS source / drain region 330b.

[0145] The semiconductor device 1 may further include a first back insulating layer 305 located below the semiconductor substrate 303a, back interconnect structures 395n1 and 395n2 disposed below the first back insulating layer 305, and a second back insulating layer 398 covering the back interconnect structures 395n1 and 395n2 below the first back insulating layer 305.

[0146] The semiconductor device 1 may further include an insulating separation structure 310 that penetrates the first back insulating layer 305 and the semiconductor substrate 303a. The insulating separation structure 310 can separate the portion of the semiconductor substrate 303a connected to the first-first NMOS source / drain region 345a and the portion of the semiconductor substrate 303a connected to the first-second NMOS source / drain region 345b, and can also separate the portion of the semiconductor substrate 303a connected to the second-first NMOS source / drain region 330a and the portion of the semiconductor substrate 303a connected to the second-second NMOS source / drain region 330b.

[0147] The connection described above to the first NMOS source / drain region 45 (see above) Figure 2 and Figure 3A At least one source / drain contact structure 81n1 (see) Figure 2 and Figure 3A ) or as described above, connected to the second NMOS source / drain region 30 (see Figure 2 and Figure 3B At least one source / drain contact structure 81n2 (see) Figure 2 and Figure 3B The source / drain contact structures 381n1 and 381n2, which penetrate the first back insulating layer 305 and the semiconductor substrate 303a, can be replaced by these structures. For example, they can be connected to the first NMOS source / drain region 45 (see [link]). Figure 2 and Figure 3A At least one source / drain contact structure 81n1 (see) Figure 2(and Figure 3a) can be replaced by a post-source / drain contact structure connected to at least one of the corresponding source / drain regions of the first-first NMOS source / drain region 345a and the first-second NMOS source / drain region 345b. For example, one of the source / drain contact structures 81n1 (see Figure 3a). Figure 2 and Figure 3A ) can be with Figure 2 and Figure 3A The first-second NMOS source / drain region 345a is electrically connected in the same form, and the other of them can be replaced by a first post-source / drain contact structure 381n1 that penetrates the first post-insulating layer 305 and the semiconductor substrate 303a, passes through the lower surface of the first-second NMOS source / drain region 345b, and extends into the first-second NMOS source / drain region 345b. One of the source / drain contact structures 81n2 (see...) Figure 2 and Figure 3B ) can be with Figure 2 and Figure 3B The same form of electrical connection is made to the second-first NMOS source / drain region 330a, and the other one of them can be replaced by a second rear source / drain contact structure 381n2 that penetrates the first rear insulating layer 305 and the semiconductor substrate 303a, passes through the lower surface of the second-second NMOS source / drain region 330b and extends into the second-second NMOS source / drain region 330b.

[0148] Each of the rear source / drain contact structures 381n1 and 381n2 may include a metal-semiconductor compound layer 383 and a source / drain contact plug 385 located beneath the metal-semiconductor compound layer 383. The source / drain contact plug 385 may include a plug conductive pattern 385b and a conductive barrier layer 385a covering the side and top surfaces of the plug conductive pattern 385b. In each of the rear source / drain contact structures 381n1 and 381n2, the metal-semiconductor compound layer 383 may contact a corresponding source / drain region in source / drain regions 345b and 330b and a corresponding semiconductor substrate in semiconductor substrate 303a. The rear source / drain contact structures 381n1 and 381n2 may be electrically connected to rear interconnect structures 395n1 and 395n2.

[0149] Next, refer to Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figures 18 to 23 , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 26Aand Figure 26B This section will describe examples of methods for forming semiconductor devices according to exemplary embodiments of the present disclosure. For example, a first NMOS insulating spacer structure 41 with different shapes and structures (see [link to documentation]) will be described. Figure 2 and Figure 3A ) and the second NMOS insulating spacer structure 57_1a (see Figure 2 and Figure 3B The formation method of ). In Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figures 18 to 23 , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 26A and Figure 26B middle, Figure 16A , Figure 17A , Figures 18 to 23 , Figure 24A , Figure 25A and Figure 26A It shows along Figure 1A The line I-I' and Figure 1B A cross-sectional view of the area intercepted by line II-II'. Figure 16B , Figure 17B , Figure 24B , Figure 25D and Figure 26B It shows along Figure 1A Line III-III' and Figure 1B A cross-sectional view of the area intercepted by line IV-IV'. Figure 25B It is shown Figure 25A A magnified view of the area indicated by "A1", and Figure 25C yes Figure 25A A magnified view of the area indicated by “B1”.

[0150] refer to Figure 1A , Figure 1B , Figure 16A and Figure 16BA structure comprising a substrate 3, a device isolation region 15 defining an active region 3a on the substrate 3, and stacked structures 12a and 12b located on the active region 3a can be fabricated. Stacked structures 12a and 12b may include a first stacked structure 12a formed in a first NMOS region N1 and a second stacked structure 12b formed in a second NMOS region N2. The first stacked structure 12a may include an alternately stacked first sacrificial semiconductor layer 6a and a first channel layer 9a. The second stacked structure 12b may include an alternately stacked second sacrificial semiconductor layer 6b and a second channel layer 9b. The first sacrificial semiconductor layer 6a may include a first lower sacrificial semiconductor layer 6a1, a first intermediate sacrificial semiconductor layer 6a2, and a first upper sacrificial semiconductor layer 6a3 stacked and spaced apart from each other in the vertical direction (Z direction). The second sacrificial semiconductor layer 6b may include a second lower sacrificial semiconductor layer 6b1, a second intermediate sacrificial semiconductor layer 6b2, and a second upper sacrificial semiconductor layer 6b3 stacked and spaced apart from each other in the vertical direction (Z direction). The first channel layer 9a may include a first NMOS lower channel layer 9a1, a first NMOS middle channel layer 9a2, and a first NMOS upper channel layer 9a3 stacked and spaced apart from each other in the vertical direction (Z direction). The second channel layer 9b may include a second NMOS lower channel layer 9b1, a second NMOS middle channel layer 9b2, and a second NMOS upper channel layer 9b3 stacked and spaced apart from each other in the vertical direction (Z direction).

[0151] The first channel layer 9a and the second channel layer 9b may be formed of a first semiconductor material such as silicon. The first sacrificial semiconductor layer 6a and the second sacrificial semiconductor layer 6b may be formed of a second semiconductor material other than the first channel layer 9a and the second channel layer 9b, such as silicon or germanium.

[0152] Gate mask patterns 18a and 18b extending in the second horizontal direction (Y direction) can be formed. Gate mask patterns 18a and 18b can be formed on stacked structures 12a and 12b and device isolation region 15. Gate mask patterns 18a and 18b may include a first NMOS mask pattern 18a formed in a first NMOS region N1 and a second NMOS mask pattern 18b formed in a second NMOS region N2.

[0153] The first NMOS mask pattern 18a can be extended by intersecting the first stacked structure 12a in the second horizontal direction (Y direction), and the second NMOS mask pattern 18b can be extended by intersecting the second stacked structure 12b in the second horizontal direction (Y direction).

[0154] The first NMOS mask pattern 18a may include a first lower mask layer 18a1 and a first upper mask layer 18a2 stacked in sequence, and the second NMOS mask pattern 18b may include a second lower mask layer 18b1 and a second upper mask layer 18b2 stacked in sequence.

[0155] A first insulating pad 21 can be formed to conformally cover the stacked structures 12a and 12b and the gate mask patterns 18a and 18b.

[0156] refer to Figure 1A , Figure 1B , Figure 17A and Figure 17B A first protective mask 24 covering the first insulating pad 21 can be formed on the first NMOS region N1. While the first NMOS region N1 is protected by the first protective mask 24, the first insulating pad 21 of the second NMOS region N2 can be etched anisotropically, and then the second stacked structure 12b can be etched to form a groove 27 penetrating the second stacked structure 12b.

[0157] refer to Figure 1A , Figure 1B and Figure 18 With the first NMOS region N1 protected by the first protective mask 24, a second NMOS source / drain epitaxial growth process can be performed to form a second NMOS source / drain region 30, which is formed by epitaxial growth from the side surface of the active region 3b exposed by the trench 27, the side surface of the second sacrificial semiconductor layer 6b, and the side surface of the second channel layer 9b. Each second NMOS source / drain region 30 may have an upper surface with a centrally recessed shape.

[0158] refer to Figure 1A , Figure 1B and Figure 19 The first protective mask 24 can be removed (see Figure 18 Next, a second insulating pad 33 can be formed to conformally cover the first insulating pad 21 and the second NMOS source / drain region 30. A second protective mask 36 covering the second insulating pad 33 can be formed on the second NMOS region N2.

[0159] refer to Figure 1A , Figure 1B and Figure 20 With the second NMOS region N2 protected by the second protective mask 36, the first insulating pad 21 and the second insulating pad 33 of the first NMOS region N1 can be etched anisotropically, and then the first stacked structure 12a can be etched to form a groove 39 penetrating the first stacked structure 12a.

[0160] The side surface of the first sacrificial semiconductor layer 6a exposed by the groove 39 may be further recessed than the side surface of the first channel layer 9a exposed by the groove 39. An insulating spacer pattern 42, contacting the side surface of the first sacrificial semiconductor layer 6a and formed beneath each first channel layer 9a, may then be formed. The insulating spacer pattern 42 may be formed of silicon nitride.

[0161] refer to Figure 1A , Figure 1B and Figure 21 While the second NMOS region N2 is protected by the second protective mask 36, the first NMOS source / drain epitaxial growth process can be performed to form the first NMOS source / drain region 45 formed by epitaxial growth from the active region 3a exposed by the groove 39 and the first channel layer 9a.

[0162] Since the first NMOS source / drain region 45 has a relatively small width, even if the first NMOS source / drain region 45 is epitaxially grown from the active region 3a exposed by the groove 39 and the first channel layer 9a, a defect-free first NMOS source / drain region 45 can be formed.

[0163] In the above Figure 18 The second NMOS source / drain region 30 described herein has a width larger than that of the first NMOS source / drain region 45. However, since the second NMOS source / drain region 30 is formed by epitaxial growth from the side surface of the active region 3b exposed by the recess 27, the side surface of the second sacrificial semiconductor layer 6b, and the side surface of the second channel layer 9b, a defect-free second NMOS source / drain region 30 can be formed.

[0164] According to the example embodiment, a defect-free first NMOS source / drain region 45 and a second NMOS source / drain region 30 can be reliably formed.

[0165] refer to Figure 1A , Figure 1B and Figure 22 The second protective mask 36 can be removed (see Figure 21 Subsequently, a third insulating pad 48 can be formed to conformally cover the first NMOS source / drain region 45 and the second insulating pad 33.

[0166] refer to Figure 1A , Figure 1B and Figure 23 An interlayer insulating layer 51 can be formed on the third insulating pad 48. A planarization process can be performed until the first lower mask layer 18a1 and the second lower mask layer 18b1 are exposed. The first upper mask layer 18a2 and the second upper mask layer 18b2 can be removed by the planarization process (see...). Figure 22Furthermore, the interlayer insulating layer 51 may be retained on the side surfaces of the first lower mask layer 18a1 and the second lower mask layer 18b1 on the third insulating pad 48.

[0167] refer to Figure 1A , Figure 1B , Figure 24A and Figure 24B The first lower mask layer 18a1 and the second lower mask layer 18b1 can be removed (see...). Figure 23 ) and the first sacrificial semiconductor layer 6a and the second sacrificial semiconductor layer 6b (see Figure 23 To simultaneously form the first opening 54a and the second opening 54b.

[0168] The first opening 54a may include a first upper opening 54a_2 formed by removing the first lower mask layer 18a1 and a first lower opening 54a_1 formed by removing the first sacrificial semiconductor layer 6a. The second opening 54b may include a second upper opening 54b_2 formed by removing the second lower mask layer 18b1 and a second lower opening 54b_1 formed by removing the second sacrificial semiconductor layer 6b.

[0169] The first lower opening 54a_1 can expose the insulating spacer pattern 42, and the second lower opening 54b_1 can expose the second NMOS source / drain region 30.

[0170] refer to Figure 1A , Figure 1B , Figure 25A , Figure 25B , Figure 25C and Figure 25D Insulating oxide layers 57 and 60 can be formed. Forming insulating oxide layers 57 and 60 may include: forming a preliminary oxide layer conformally covering the inner walls of each of the first opening 54a and the second opening 54b; advancing a process to densify at least a portion of the preliminary oxide layer; and etching the densified preliminary oxide layer to retain a thicker layer at the corners of the openings 54a and 54b and on the sidewalls of the lower openings 54a_1 and 54b_1. Insulating oxide layers 57 and 60 may include a first NMOS insulating oxide layer 60 formed on the inner wall of the first opening 54a and a second NMOS insulating oxide layer 57 formed on the inner wall of the second opening 54b.

[0171] refer to Figure 1A , Figure 1B , Figure 26A and Figure 26BGate dielectric layers 63n and 66n can be formed conformally covering the first opening 54a and the second opening 54b formed on their inner walls by insulating oxide layers 57 and 60. Conductive material can be formed to fill the first opening 54a and the second opening 54b covered by the gate dielectric layers 63n and 66n, and gate electrodes 69n and 72n can be formed by planarizing the conductive material. Through the process of planarizing the conductive material to form gate electrodes 69n and 72n, the interlayer insulating layer 51 and insulating pads 21, 33, and 48 can be formed to have an upper surface coplanar with the upper surfaces of the gate electrodes 69n and 72n.

[0172] Next, by performing contact and wiring processes, a structure such as... can be formed. Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6A and Figure 6B The source / drain contact structures 81n1, 81n2, 81p1 and 81p2, the gate contact structures 93n1, 93n2, 93p1 and 93p2, and the interconnect structures 95n1, 95n2, 95p1, 95p2, 96n1, 96n2, 96p1 and 96p2 are included.

[0173] While exemplary embodiments of this disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that this disclosure may be implemented in other specific forms without altering its technical concept or essential characteristics. Therefore, it should be understood that the above exemplary embodiments are, in all respects, examples and not limitations.

Claims

1. A semiconductor device, said semiconductor device comprising: First NMOS transistor structure; and Second NMOS transistor structure, The first NMOS transistor structure includes: First NMOS source / drain region; The first NMOS channel layer is stacked and spaced apart from each other, and is electrically connected to the source / drain region of the first NMOS in a first direction; A first NMOS gate electrode, the first NMOS gate electrode surrounding each first NMOS channel layer in a second direction intersecting the first direction; A first NMOS gate dielectric layer is located between the first NMOS gate electrode and the first NMOS channel layer, and between the first NMOS gate electrode and the first NMOS source / drain region; and The first NMOS insulating spacer structure is located between the first NMOS gate dielectric layer and the first NMOS source / drain region; The second NMOS transistor structure includes: Second NMOS source / drain region; The second NMOS channel layer is stacked and spaced apart from each other, and is electrically connected to the source / drain region of the second NMOS in the first direction; The second NMOS gate electrode extends in the second direction and surrounds each of the second NMOS channel layers in the second direction; A second NMOS gate dielectric layer is located between the second NMOS gate electrode and the second NMOS channel layer, and between the second NMOS gate electrode and the second NMOS source / drain region; and The second NMOS insulating spacer structure is located between the gate dielectric layer of the second NMOS and the source / drain region of the second NMOS. Wherein, the first NMOS insulating spacer structure includes a first NMOS insulating spacer pattern, and The second NMOS insulating spacer structure includes a second NMOS insulating oxide layer and does not include an insulating spacer pattern identical to the first NMOS insulating spacer pattern.

2. The semiconductor device according to claim 1, wherein, The width of the second NMOS channel layer at the first height in the first direction is greater than the width of the first NMOS channel layer at the first height in the first direction.

3. The semiconductor device according to claim 1, wherein, The maximum width of the second NMOS source / drain region in the first direction is greater than the maximum width of the first NMOS source / drain region in the first direction.

4. The semiconductor device according to claim 1, wherein, Each of the first NMOS gate dielectric layer and the second NMOS gate dielectric layer includes a high-k dielectric layer, and The high-k dielectric layer has a higher dielectric constant than that of silicon oxide.

5. The semiconductor device according to claim 4, wherein, The second NMOS insulating oxide layer is a dielectric material with a dielectric constant lower than that of the high-k dielectric layer of the second NMOS gate dielectric layer.

6. The semiconductor device according to claim 4, wherein, The first NMOS insulating spacer pattern includes silicon nitride, and The second NMOS insulating oxide layer includes silicon oxide.

7. The semiconductor device according to claim 1, wherein, The minimum thickness of the first NMOS insulating spacer pattern is greater than the minimum thickness of the second NMOS insulating oxide layer.

8. The semiconductor device according to claim 1, wherein, The second NMOS transistor structure also includes: An interface oxide layer extends from the second NMOS insulating oxide layer and is located between the second NMOS channel layer and the second NMOS gate dielectric layer.

9. The semiconductor device according to claim 1, wherein, The first NMOS insulating spacer structure further includes a first NMOS insulating oxide layer located between the first NMOS insulating spacer pattern and the first NMOS gate dielectric layer.

10. The semiconductor device according to claim 9, wherein, The minimum thickness of the first NMOS insulating spacer pattern is greater than the minimum thickness of the first NMOS insulating oxide layer.

11. The semiconductor device according to claim 9, further comprising: A first interface oxide layer extends from the first NMOS insulating oxide layer and is located between the first NMOS channel layer and the first NMOS gate dielectric layer.

12. The semiconductor device according to claim 1, further comprising: The first contact structure is electrically connected to the source / drain region of the first NMOS. and The second contact structure is electrically connected to the source / drain region of the second NMOS.

13. A semiconductor device, said semiconductor device comprising: First NMOS transistor structure; and Second NMOS transistor structure, The first NMOS transistor structure includes: First NMOS source / drain region; The first NMOS channel layer is stacked and spaced apart from each other, and is electrically connected to the source / drain region of the first NMOS in a first direction; A first NMOS gate electrode extends in a second direction intersecting the first direction and surrounds each of the first NMOS channel layers in the second direction; A first NMOS gate dielectric layer is located between the first NMOS gate electrode and the first NMOS channel layer, and between the first NMOS gate electrode and the first NMOS source / drain region; and The first NMOS insulating spacer structure is located between the first NMOS gate dielectric layer and the first NMOS source / drain region; The second NMOS transistor structure includes: Second NMOS source / drain region; The second NMOS channel layer is stacked and spaced apart from each other, and is electrically connected to the source / drain region of the second NMOS in the first direction; The second NMOS gate electrode extends in the second direction and surrounds each of the second NMOS channel layers in the second direction; A second NMOS gate dielectric layer is located between the second NMOS gate electrode and the second NMOS channel layer, and between the second NMOS gate electrode and the second NMOS source / drain region; and A second NMOS insulating spacer structure is located between the gate dielectric layer of the second NMOS and the source / drain region of the second NMOS. The first NMOS channel layer includes a first NMOS lower channel layer, a first NMOS intermediate channel layer located on the first NMOS lower channel layer, and a first NMOS upper channel layer located on the first NMOS intermediate channel layer. The second NMOS channel layer includes a second NMOS lower channel layer, a second NMOS intermediate channel layer located on the second NMOS lower channel layer, and a second NMOS upper channel layer located on the second NMOS intermediate channel layer. The first NMOS gate electrode includes: The lower gate portion of the first NMOS is located directly below the lower channel layer of the first NMOS. The first NMOS intermediate gate portion is located directly below the first NMOS intermediate channel layer; and The upper gate portion of the first NMOS is located directly below the upper channel layer of the first NMOS. The second NMOS gate electrode includes: The lower gate portion of the second NMOS is located directly below the lower channel layer of the second NMOS. The second NMOS intermediate gate portion is located directly below the second NMOS intermediate channel layer; and The upper gate portion of the second NMOS is located directly below the upper channel layer of the second NMOS. The first NMOS insulating spacer structure includes a first NMOS intermediate spacer portion located between the source / drain region of the first NMOS and the intermediate gate portion of the first NMOS. The second NMOS insulating spacer structure includes a second NMOS intermediate spacer portion located between the source / drain region of the second NMOS and the intermediate gate portion of the second NMOS. Wherein, the thickness of the first NMOS intermediate spacer portion is greater than the thickness of the second NMOS intermediate spacer portion. Wherein, the thickness of the second NMOS intermediate spacer portion is the thickness in a direction perpendicular to the surface of the second NMOS gate dielectric layer that contacts the second NMOS intermediate spacer portion, and The thickness of the first NMOS intermediate spacer portion is the thickness in a direction perpendicular to the contact of the first NMOS gate dielectric layer or to the surface facing the first NMOS intermediate spacer portion.

14. The semiconductor device according to claim 13, wherein, The second NMOS insulating spacer structure extends from between the second NMOS gate dielectric layer and the second NMOS source / drain region to between the second NMOS gate dielectric layer and the second NMOS channel layer.

15. The semiconductor device according to claim 13, wherein, The width of the second NMOS lower channel layer in the first direction is greater than the width of the first NMOS lower channel layer in the first direction.

16. The semiconductor device according to claim 13, wherein, The maximum width of the second NMOS source / drain region in the first direction is greater than the maximum width of the first NMOS source / drain region in the first direction.

17. A semiconductor device, said semiconductor device comprising: First NMOS transistor structure; and Second NMOS transistor structure, The first NMOS transistor structure includes: The first NMOS channel layer is spaced apart from each other in a first direction; The first NMOS source / drain region is electrically connected to the first NMOS channel layer in a second direction perpendicular to the first direction; The first NMOS gate electrode includes a first NMOS intermediate electrode portion located between the first NMOS channel layers; A first NMOS gate dielectric layer is located between the first NMOS gate electrode and the first NMOS channel layer; and A first NMOS insulating spacer structure is located between the middle electrode portion of the first NMOS and the source / drain region of the first NMOS, and The second NMOS transistor structure includes: The second NMOS channel layer is spaced apart from each other in the first direction; The second NMOS source / drain region is connected to the second NMOS channel layer in the second direction; The second NMOS gate electrode includes a second NMOS intermediate electrode portion located between the second NMOS channel layers; A second NMOS gate dielectric layer is located between the second NMOS gate electrode and the second NMOS channel layer; and A second NMOS insulating spacer structure is located between the middle electrode portion of the second NMOS and the source / drain region of the second NMOS. Wherein, the first NMOS insulating spacer structure includes a first insulating spacer pattern, and The second NMOS insulating spacer structure includes a second NMOS insulating oxide layer and does not include an insulating spacer pattern identical to the first insulating spacer pattern.

18. The semiconductor device of claim 17, wherein, In the second direction, the width of the second NMOS source / drain region is greater than the width of the first NMOS source / drain region. The first NMOS gate dielectric layer extends between the first NMOS intermediate electrode portion and the first NMOS insulating spacer structure, and The second NMOS gate dielectric layer extends between the second NMOS intermediate electrode portion and the second NMOS insulating spacer structure.

19. The semiconductor device according to claim 18, wherein, The first NMOS insulating spacer structure further includes a first NMOS insulating oxide layer located between the first insulating spacer pattern and the first NMOS gate dielectric layer.

20. The semiconductor device of claim 17, wherein, Each of the first NMOS gate dielectric layer and the second NMOS gate dielectric layer comprises a high-k dielectric material. The high-k dielectric material has a higher dielectric constant than silicon oxide, and Wherein, the dielectric constant of the second NMOS insulating oxide layer is lower than the dielectric constant of the high-k dielectric material of the second NMOS gate dielectric layer.

Images