Pixel array and image sensor thereof

Abstract

The invention discloses a pixel array and an image sensor thereof. The pixel array comprises at least one pixel unit; the pixel unit comprises a substrate having a first surface and a second surface opposite to each other; a photoelectric conversion region located in the substrate close to the first surface; the transmission channel region is positioned in the substrate on one side, close to the second surface, of the photoelectric conversion region; the transmission gate structure is positioned on the side surface of the substrate of the transmission channel region and surrounds the substrate of the transmission channel region; and the transmission drain doped region is positioned in the substrate on one side, close to the second surface, of the transmission gate structure. The transmission drain doped region is located in the substrate on one side, close to the second surface, of the transmission gate structure of the substrate surrounding the transmission channel region, and the transmission drain doped region and the transmission gate structure are stacked in the direction perpendicular to the surface of the substrate, so that a complete vertical channel transistor structure is formed, the occupied area of the transmission transistor can be effectively reduced, and the transmission efficiency is improved. And reduction of the area of the pixel unit is facilitated.

Description

Technical Field

[0001] This invention relates to the field of image acquisition, and in particular to a pixel array and its image sensor. Background Technology

[0002] Image sensors, as core devices for photoelectric conversion, are the cornerstone of modern visual imaging systems and are widely used in smartphones, security monitoring, medical imaging, autonomous driving, and many other fields. As end-user applications continue to demand higher resolution, higher sensitivity, lower noise, and miniaturization, the pixel density of image sensors is constantly increasing, and pixel size is gradually shrinking. This is highlighting the performance bottlenecks of traditional transmission transistor structures, driving innovation in device structure and materials technology.

[0003] The pixel unit of an image sensor mainly consists of a photodiode, a transfer transistor, a reset transistor, and a source follower. Among them, the transfer transistor, as the core switch for charge transport, is responsible for transferring electrons generated by photons absorbed by the photodiode to the floating diffusion region for subsequent signal processing. Its performance directly determines key indicators of the image sensor such as dynamic range, transmission efficiency, and noise level. In image sensors, transfer transistors mostly adopt a horizontal channel structure. The channel of the transfer transistor is parallel to the chip surface, and the channel current flows horizontally through the channel along the chip surface. Its structural design is simple, the manufacturing process is mature, and it can meet basic performance requirements in low pixel density scenarios.

[0004] However, with the advancement of Moore's Law, image sensors are rapidly developing towards ultra-high pixel counts and miniaturization, with pixel sizes shrinking to the sub-micron level. The inherent defects of the horizontal channel structure are gradually being exposed: the increase in pixel density leads to a reduction in the effective area of ​​a single pixel unit, thereby compressing the layout space of photodiodes and transmission transistors. Moreover, in the transmission transistor, the limited layout space leads to a reduction in gate size, which easily generates short-channel effects, charge residues, and image ghosting. At the same time, stray capacitance and leakage current increase, resulting in increased transmission noise and affecting the image signal-to-noise ratio and color reproduction accuracy.

[0005] To overcome these bottlenecks, researchers began to introduce vertical channel structures into transmission transistors, but the introduction of vertical channels could not meet the need for smaller pixel sizes. Summary of the Invention

[0006] The problem addressed by this invention is how to further reduce the size of pixel units.

[0007] To address the aforementioned problems, the present invention provides a pixel array, comprising: at least one pixel unit; the pixel unit comprising: a substrate having a first surface and a second surface facing away from each other; a photoelectric conversion region located within the substrate near the first surface; a transmission channel region located within the substrate on the side of the photoelectric conversion region near the second surface; a transmission gate structure located on the side of the substrate of the transmission channel region, the transmission gate structure surrounding the substrate of the transmission channel region; and a transmission drain doped region located within the substrate on the side of the transmission gate structure near the second surface.

[0008] Accordingly, the present invention also provides an image sensor, comprising: a first bonding unit and a second bonding unit bonded together; wherein the first bonding unit comprises the pixel array of the present invention.

[0009] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0010] In this invention, a transmission channel region is located within the substrate of the photoelectric conversion region on the side near the second surface; a transmission gate structure is located on the side of the substrate of the transmission channel region, surrounding the substrate of the transmission channel region; and a transmission drain doped region is located within the substrate of the transmission gate structure on the side near the second surface. The transmission drain doped region is located within the substrate of the transmission gate structure surrounding the substrate of the transmission channel region on the side near the second surface. The transmission drain doped region and the transmission gate structure are stacked along a direction perpendicular to the substrate surface, thereby forming a completely vertical channel transistor structure. This effectively reduces the area occupied by the transmission transistor, which is beneficial for reducing the pixel unit area. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the cross-sectional structure of a pixel unit in a pixel array.

[0012] Figure 2 This is a top view of a pixel array structure consistent with some embodiments of the present invention.

[0013] Figure 3 This is a three-dimensional structural diagram of a single pixel unit in a pixel array, consistent with some embodiments of the present invention.

[0014] Figure 4 This is a top view of a single pixel unit in a pixel array, consistent with some embodiments of the present invention.

[0015] Figure 5 The pixel units in the pixel array are consistent with some embodiments of the present invention. Figure 4A schematic diagram of the cross-sectional structure at the location of line A1A2 in the middle.

[0016] Figure 6 This is a three-dimensional structural diagram of a single pixel unit in a pixel array, consistent with some embodiments of the present invention.

[0017] Figure 7 This is a cross-sectional structural diagram of a pixel unit in a pixel array, consistent with some embodiments of the present invention.

[0018] Figure 8 This is a top view of a pixel array structure consistent with some embodiments of the present invention.

[0019] Figure 9 This is a cross-sectional structural diagram of a pixel array consistent with some embodiments of the present invention.

[0020] Figure 10 This is a cross-sectional structural diagram of an image sensor consistent with some embodiments of the present invention. Detailed Implementation

[0021] As is known from the background art, existing CMOS image sensors suffer from the problem that the pixel unit area cannot be further reduced. This paper analyzes the reasons why the area of ​​a pixel unit in a CMOS image sensor cannot be further reduced by examining its cross-sectional structure:

[0022] In the pixel unit of a CMOS image sensor, the charge generated by the photodiode collecting light signals and performing photoelectric conversion gradually transfers from the region of the photodiode away from the transmission gate structure to the region closer to the transmission gate structure. Then, through the channel opened below the gate structure of the transmission transistor, it is transferred to the floating diffusion (FD) node and then to the subsequent circuit.

[0023] like Figure 1 As shown, in the pixel unit, the transfer transistor uses a transfer gate (TG) structure embedded in the silicon substrate to increase the channel depth, thereby achieving a vertical channel. Figure 1 As shown, the transmission gate structure tg is located on the surface of the substrate 10 on the side away from the photoelectric conversion region pd and extends into the substrate 10 into the photoelectric conversion region pd. The source doped region s and the drain doped region d of the transmission transistor are located in the substrate 10 on both sides of the transmission gate structure tg, respectively, and the floating node fd is located in the substrate 10 between the drain doped region d and the transmission gate structure tg.

[0024] like Figure 1As shown, although the transmission gate structure tg extends from the surface of the substrate 10 into the photoelectric conversion region pd to achieve a vertical channel, the source doped region s and the drain doped region d are still distributed within the substrate 10 on both sides of the transmission gate structure tg, remaining a planar structure. The transmission transistor occupies a large area of ​​the substrate 10, making it difficult to further reduce the area of ​​the pixel unit.

[0025] To address the aforementioned technical problem, the present invention provides a pixel array. In the pixel array, the transmission drain doped region is located within the substrate of the substrate surrounding the transmission gate structure near the second surface. The transmission drain doped region and the transmission gate structure are stacked along a direction perpendicular to the substrate surface, thereby forming a completely vertical channel transistor structure. This effectively reduces the area occupied by the transmission transistor, which is beneficial for reducing the area of ​​the pixel unit.

[0026] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] refer to Figure 2 ,in Figure 2 A top view of a pixel array consistent with some embodiments of the present invention is shown.

[0028] The pixel array includes at least one pixel unit 100.

[0029] like Figure 2 In some embodiments shown, the pixel array has a plurality of pixel units 100. The plurality of pixel units 100 are arranged in an array. For example... Figure 2 In some embodiments shown, a plurality of pixel units 100 in the pixel array are arranged in an array along a first direction x and a second direction y, wherein the first direction x and the second direction y may be perpendicular to each other.

[0030] Reference Figures 3 to 5 ,in Figure 3 A three-dimensional structural schematic diagram of a single pixel unit in a pixel array consistent with some embodiments of the present invention is shown; Figure 4 A top view of a single pixel unit in a pixel array, consistent with some embodiments of the present invention, is shown. Figure 5 This illustrates pixel units in a pixel array consistent with some embodiments of the present invention. Figure 4 A schematic diagram of the cross-sectional structure at the location of line A1A2 in the middle.

[0031] The pixel unit 100 includes: a substrate 110 having a first surface 111 and a second surface 112 facing away from each other; a photoelectric conversion region 120 located within the substrate 110 near the first surface 111; a transmission channel region 130 located within the substrate 110 on the side of the photoelectric conversion region 120 near the second surface 112; a transmission gate structure 140 located on the side of the substrate 110 of the transmission channel region 130, the transmission gate structure 140 surrounding the substrate 110 of the transmission channel region 130; and a transmission drain doped region 150 located within the substrate 110 on the side of the transmission gate structure 140 near the second surface 112.

[0032] The transfer drain doped region and the transfer gate structure are stacked along the direction perpendicular to the substrate surface to form a complete vertical channel transistor structure, which can effectively reduce the area occupied by the transfer transistor and is beneficial to the reduction of the pixel unit area.

[0033] The substrate is used to provide the basis for the formation of pixel units in the pixel array.

[0034] Specifically, the substrate material can be silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments of the invention, the substrate material can also be other semiconductor materials; for example, the substrate material can also be group IV semiconductors or group III-V semiconductor materials such as germanium and gallium arsenide, and the substrate material can even be a group II-VI semiconductor material. The substrate material can be selected from any material suitable for forming pixel units. Figures 2 to 5 In some of the embodiments shown, the substrate 110 is a silicon substrate. The material of the substrate 110 is monocrystalline silicon.

[0035] The substrate has two opposing surfaces, namely the first surface and the second surface.

[0036] Specifically, the array plane of the substrate parallel pixel array has two surfaces, namely a first surface and a second surface. The first surface is configured as the light-incident surface. Light rays enter the pixel unit from the first surface. The second surface is the surface opposite to the first surface.

[0037] For example, such as Figures 2 to 5 As shown, in a plane parallel to at least one of the first surface 111 and the second surface 112, a plurality of pixel units 100 of the pixel array are arranged in an array along a first direction x and a second direction y. Light rays are incident on the pixel units 100 from the first surface 111.

[0038] The photoelectric conversion region is used to receive light and perform photoelectric conversion, generating electrons based on the received light.

[0039] Specifically, the photoelectric conversion region has doped regions to form a photodiode (PD). For example, the doped regions in the photoelectric conversion region form a clamped photodiode. In the photoelectric conversion region, the first surface of the substrate has a clamping doped region. The clamping doped region is a heavily P-type doped region. The clamping doped region allows the N-type doped region constituting the photodiode to be separated from the first surface of the substrate, achieving complete embedding of the N-type doped region. This prevents the recombination of fixed holes (positive charges) and interface states in the oxide layer on the first surface with electrons generated during photoelectric conversion.

[0040] like Figures 2 to 5 In some embodiments shown, the photoelectric conversion region 120 is located within the substrate 110, near the first surface 111. A clamped doped region (not shown) is located on the first surface of the photoelectric conversion region 120. The photoelectric conversion region 120 performs photoelectric conversion on light incident from the first surface 111, generating electrons.

[0041] In some embodiments of the present invention, the pixel array further includes: a deep trench isolation structure (DTI), the deep trench isolation structure being located between adjacent pixel units; and a photoelectric conversion region covering the substrate between adjacent deep trench isolation structures. The deep trench isolation structure between adjacent pixel units is used to isolate optical and electrical signals between adjacent pixel units. In the pixel unit, the photoelectric conversion region and the transmission transistor are stacked along a direction perpendicular to at least one of the first and second surfaces. The photoelectric conversion region covers the substrate between adjacent deep trench isolation structures to improve the fill rate of the pixel unit and reduce the area of ​​the substrate occupied by the pixel unit. In the plane parallel to at least one of the first and second surfaces, the photoelectric conversion region is in contact with the deep trench isolation structure.

[0042] like Figures 2 to 5 In some embodiments shown, the deep trench isolation structure 170 extends from the first surface 111 to the second surface 112. The deep trench isolation structure 170 is located between adjacent pixel units 100. The photoelectric conversion region 120 extends along a first direction x and a second direction y parallel to the first surface 111 to cover the substrate 110 between adjacent deep trench isolation structures 170.

[0043] The transmission channel region provides the basis for the formation of the channel for the transmission transistor.

[0044] Specifically, the transmission channel region is located within the substrate on the side of the photoelectric conversion region closest to the second surface. Both the transmission channel region and the photoelectric conversion region are located within the substrate. The substrates of the transmission channel region and the photoelectric conversion region are integrally connected.

[0045] In some embodiments of the present invention, the substrate of the transmission channel region and the substrate of the photoelectric conversion region are integrally connected. Specifically, there is no clear boundary between the substrate of the transmission channel region and the substrate of the photoelectric conversion region. The transmission channel region and the photoelectric conversion region can be formed in different regions of the same substrate.

[0046] like Figures 2 to 5 In some embodiments shown, the transmission channel region 130 is located on the side of the photoelectric conversion region 120 near the second surface 112. Electrons generated in the photoelectric conversion region 120 are transported from the photoelectric conversion region 120 to the side of the transmission channel region 130 near the second surface 112 via an open channel in the transmission channel region 130.

[0047] The transfer gate structure is used to open the channel of the transfer transistor within the transfer channel region.

[0048] Specifically, the transfer gate structure is located on the side of the substrate in the transfer channel region. The transfer gate structure opens a vertically extending channel within the transfer channel region. The channel extends along a direction perpendicular to at least one of the first and second surfaces.

[0049] The transmission gate structure surrounds the substrate of the transmission channel region. Within a plane parallel to at least one of the first and second surfaces, the transmission gate structure circumferentially surrounds the substrate of the transmission channel region. The transmission gate structure can open a channel around the circumference of the substrate of the transmission channel region.

[0050] The transmission gate structure surrounds the substrate of the transmission channel region, thereby enabling the channel to be opened around the transmission channel region, which can effectively improve the electronic transport efficiency and the performance of the pixel unit.

[0051] like Figures 2 to 5 In some embodiments shown, the transmission gate structure 140 is located laterally to the substrate 110 of the transmission channel region 130 along a direction parallel to at least one of the first surface 111 and the second surface 112. The transmission transistor 140 surrounds the transmission channel region 130 in a plane parallel to at least one of the first and second surfaces. Electrons generated in the photoelectric conversion region 120 are transported through the channel surrounding the transmission channel region 130.

[0052] In some embodiments of the present invention, the pixel array further comprises a deep trench isolation structure; the transmission gate structure is located between the deep trench isolation structure and the substrate of the transmission channel region. The location of the transmission gate structure between the deep trench isolation structure and the substrate of the transmission channel region effectively saves the substrate area occupied by the transmission transistor, effectively reduces the area of ​​the pixel unit, and facilitates the miniaturization of the pixel unit.

[0053] like Figures 2 to 5In some embodiments shown, the transmission gate structure 140 includes a gate dielectric layer 141 and a gate electrode 142 stacked on the sidewall of the transmission channel region 130, wherein the gate dielectric layer 141 is located on the sidewall of the transmission channel region 130, the gate electrode 142 is located on the surface of the gate dielectric layer 141 facing away from the transmission channel region 130, and the gate electrode 142 is located between the gate dielectric layer 141 and the deep trench isolation structure 170. For example, the gate dielectric layer 141 is made of silicon oxide, and the gate electrode 142 is made of polysilicon.

[0054] In some embodiments, the transmission gate structure fills the space between the deep trench isolation structure and the substrate of the transmission channel region. Specifically, the transmission gate structure fills the gap between the deep trench isolation structure and the substrate of the transmission channel region.

[0055] like Figures 2 to 5 In some embodiments shown, in the transmission gate structure 140, the gate dielectric layer 141 is located on the sidewall of the transmission channel region 130, and the gate electrode 142 is filled between the gate dielectric layer 141 and the deep trench isolation structure 170.

[0056] In some embodiments, within at least one of the first and second surfaces, the overall projection of the transmission gate structure and the transmission channel region coincides with the projection of the photoelectric conversion region. Specifically, the photoelectric conversion region covers the substrate between adjacent deep trench isolation structures, and the transmission gate structure fills the gap between the transmission channel region and the deep trench isolation structure; therefore, the overall projection of the transmission gate structure and the transmission channel region on the first surface coincides with the photoelectric conversion region.

[0057] like Figures 2 to 5 In some embodiments shown, the projection of the entire transmission gate structure 140 and transmission channel region 130 onto the first surface 111 coincides with the photoelectric conversion region 120. The projection of the entire transmission gate structure 140 and transmission channel region 130 onto the first surface 111 and the photoelectric conversion region 120 are both square, and have the same size and corresponding positions.

[0058] The transport drain doped region serves as the drain region of the transport transistor, used to collect electrons transported through the channel of the transport transistor in the transport channel region.

[0059] Specifically, the transport drain doped region is located within the substrate on the side of the transport gate structure furthest from the photoelectric conversion region. Both the transport drain doped region and the transport channel region are located within the substrate. The substrate of the transport drain doped region and the substrate of the transport channel region are integrally connected.

[0060] For example, the transport drain doped region, the transport channel region, and the photoelectric conversion region are all located within the substrate. The substrates of the transport drain doped region, the transport channel region, and the photoelectric conversion region are integrally connected.

[0061] Along the direction perpendicular to the substrate surface, the photoelectric conversion region, the transmission channel region, and the transmission drain doped region are stacked to form a complete vertical channel transistor structure, which can effectively reduce the area of ​​the substrate occupied by the transmission transistor and effectively control the area of ​​the pixel unit.

[0062] In some embodiments of the present invention, the transfer drain doped region covers the substrate in a plane parallel to at least one of the first and second surfaces. This ensures the area of ​​the transfer drain doped region within the pixel unit is adequately maintained, reducing the difficulty of extracting the transfer drain doped region. Furthermore, the transfer drain doped region is connected to the floating diffusion region, further enhancing electron transfer efficiency, reducing image ghosting and inter-frame crosstalk, and ensuring signal integrity.

[0063] like Figures 2 to 5 In some embodiments shown, the transfer drain doped region 150 is located within the substrate 110 of the transfer gate structure 140 on the side away from the photoelectric conversion region 120 and closer to the second surface 112. The transfer drain doped region 150 extends in a direction parallel to the second surface 112 to cover the substrate 110 of the pixel unit 100.

[0064] In some embodiments of the present invention, the pixel unit further includes a transport source doped region, which is located in the substrate on the side of the transport gate structure closest to the photoelectric conversion region. The transport source doped region serves as the source region of the transport transistor, enabling connection between the photoelectric conversion region and the channel of the transport transistor, thereby providing electrons to the channel of the transport transistor in the transport channel region.

[0065] Specifically, along the direction perpendicular to at least one of the first and second surfaces, the transmission source doped region and the transmission gate doped region are respectively located in the substrate on both sides of the transmission gate structure, thereby making the transmission transistor present a completely vertical channel transistor structure, which can effectively control the area occupied by the transmission transistor and effectively control the area of ​​the pixel unit.

[0066] like Figures 2 to 5 In some embodiments shown, the transport source doped region 160 is located within the substrate 110 of the transport gate structure 140 on the side closest to the photoelectric conversion region 120. The transport source doped region 160 is located within the substrate 110 between the transport channel region 130 and the photoelectric conversion region 120. For example, the transport source doped region 160 is in contact with the photoelectric conversion region 120.

[0067] In some embodiments of the present invention, the pixel unit further includes a dielectric layer located on the side of the substrate of the transport drain doped region. The dielectric layer serves to provide insulation between the transport gate structure and the transport drain doped region.

[0068] like Figures 2 to 5 In some embodiments shown, the dielectric layer 180 is located on the side of the transmission gate structure 140 away from the photoelectric conversion region 120, and is situated between the transmission drain doped region and the deep trench isolation structure 170. For example, the dielectric layer 180 fills the gap between the transmission drain doped region and the deep trench isolation structure 170. For example, the material of the dielectric layer 180 is silicon oxide.

[0069] Continue to refer to Figure 1 In some embodiments of the present invention, the pixel array further includes: a word line, which is connected to a transmission gate structure; and the transmission gate structures of adjacent pixel units along a first direction are electrically connected to the same word line. The word line is used to control the selection of pixel units. Specifically, the word line is electrically connected to the transmission gate structure via a word line lead-out element to control the conduction and cutoff of the transmission transistor channel.

[0070] like Figures 2 to 5 In some embodiments shown, word lines 191 extend along a first direction x. Multiple word lines 191 are arranged in parallel along a second direction y. In the transmission gate structure 140 of adjacent pixel units 100 along the first direction x, gate electrodes 142 are connected to the same word line 191.

[0071] In some embodiments of the present invention, the pixel array further includes: a bit line, which is connected to a transmission drain doped region; the transmission drain doped regions of adjacent pixel units along the second direction are electrically connected to the same bit line. The bit line is used to transmit signals generated by the pixel units. Specifically, the bit line and the transmission drain doped region are electrically connected through a bit line lead-out element to realize the transmission and readout of electrons generated by the photoelectric conversion region.

[0072] like Figures 2 to 5 In some embodiments shown, bit lines 192 extend along a second direction x. Multiple bit lines 192 are arranged in parallel along a first direction x. The transfer drain doped regions of adjacent pixel units 100 along the second direction y are connected to the same bit line 192. Bit lines 192 are electrically connected between the transfer drain doped region 150 and the floating diffusion (FD) node.

[0073] It should be noted that in the foregoing embodiments, the transport drain doped region is connected to the floating diffusion node via a bit line. In other embodiments of the present invention, the transport drain doped region and the floating diffusion region may also be electrically connected in other ways.

[0074] refer to Figure 6 and Figure 7 ,in Figure 6 A three-dimensional structural schematic diagram of a single pixel unit in a pixel array consistent with some embodiments of the present invention is shown; Figure 7 A cross-sectional structural diagram of a pixel unit in a pixel array consistent with some embodiments of the present invention is shown.

[0075] Unlike the aforementioned embodiments, in some embodiments of the present invention, the floating diffusion node is disposed in the pixel unit.

[0076] In some embodiments of the present invention, the pixel unit further includes a floating diffusion region located between the transport drain doped region and the second surface. Specifically, the floating diffusion region serves as a floating diffusion node located between the transport drain doped region and the second surface. Along a direction perpendicular to at least one of the first and second surfaces, the photoelectric conversion region, the transport channel region, the transport doped region, and the floating diffusion region are sequentially arranged. The floating diffusion region directly contacts the fully vertical channel transport transistor, resulting in a smoother electron transport path and higher transport efficiency. Furthermore, it reduces the area of ​​the substrate occupied by the pixel unit while maintaining the size of the floating diffusion region, which is beneficial for the miniaturization of the pixel unit.

[0077] Moreover, the direct contact between the floating diffusion region and the transport drain doped region eliminates the intermediate potential barrier for electron transport between the transport drain doped region and the floating diffusion region, eliminates contact resistance, and significantly reduces the charge retention probability, achieving a charge transfer efficiency close to 100%. At the same time, it shortens the charge transfer distance, improves the transfer speed, and adapts to the needs of high frame rate imaging.

[0078] Furthermore, the floating diffusion region is in direct contact with the transport drain doped region, realizing an integrated structure of the floating diffusion region and the transport drain doped region. This results in a more uniform doping concentration distribution and a smoother electric field distribution, which can effectively reduce hot carrier injection and dark current generation caused by local high electric fields. Moreover, it has a higher tolerance for external electromagnetic interference and process defects, thus improving the long-term operational reliability of the pixel unit.

[0079] In addition, the floating diffusion region is in direct contact with the transport drain doped region, and there is no additional electron transfer path between the floating diffusion region and the transport drain doped region. This can significantly reduce parasitic capacitance and parasitic resistance, effectively improve the charge-voltage conversion gain of the floating diffusion region, effectively improve the voltage response sensitivity of the floating diffusion region, effectively reduce resistive thermal noise and capacitive coupling noise, improve the signal-to-noise ratio of pixels, and optimize imaging quality in low-light environments.

[0080] like Figure 6 and Figure 7 In some embodiments shown, the floating diffusion region 252 is located between the transport drain doped region 251 and the second surface 212. Along a third direction z perpendicular to at least one of the first surface 211 and the second surface 212, the two sides of the floating diffusion region 252 are in contact with the transport drain doped region 251 and the second surface 212, respectively.

[0081] In some embodiments, the floating diffusion region covers the substrate in a plane parallel to at least one of the first and second surfaces. Specifically, by covering the substrate within the pixel unit area, the floating diffusion region can maximize its area, effectively increase the full well capacity (FWC) of the pixel unit, effectively reduce the equivalent resistance of the floating diffusion region, and effectively suppress resistive thermal noise.

[0082] like Figure 6 and Figure 7 In some embodiments shown, the floating diffusion region 252 extends along a direction parallel to at least one of the first surface 211 and the second surface 212 (e.g., one of the first direction x and the second direction y) until it comes into contact with the deep trench isolation structure 270.

[0083] In some embodiments of the present invention, the bit line includes a bit line lead-out portion located on the second surface of the substrate. Specifically, the bit line lead-out portion directly contacts the second surface of the substrate, which can effectively reduce the intermediate potential barrier for electron transport between the two and reduce the contact resistance. Moreover, without setting an additional electron transfer path, it can effectively reduce parasitic capacitance and parasitic resistance.

[0084] like Figure 6 and Figure 7 In some embodiments shown, the bit line lead-out portion 292 is located on the second surface 212 of the substrate 210. The bit line lead-out portion 292 is located on the surface of the floating diffusion region 252 opposite to the transport drain doped region 251 and is in direct contact with the surface of the floating diffusion region 252.

[0085] In some embodiments, the bit line leads of adjacent pixel units along the second direction extend and connect in the second direction. By forming bit lines through the extension of the bit line leads, it is possible to avoid setting additional connection structures between the bit lines and the substrate, effectively reducing additional electron transfer paths and effectively reducing parasitic capacitance and parasitic resistance.

[0086] like Figure 6 and Figure 7 In some embodiments shown, the bit line lead-out portion 292 extends along a second direction y parallel to at least one of the first surface 211 and the second surface 212 until it contacts and connects with the bit line lead-out portion 292 of the pixel unit adjacent along the second direction y.

[0087] In some embodiments, the bit line leads and the substrate are made of the same material. Using the same material for the bit line leads as the substrate effectively reduces the intermediate potential barrier for electron transport between the directly contacting substrate and the bit line leads, and lowers the contact resistance.

[0088] like Figures 6 to 7In some embodiments shown, the substrate 210 is made of silicon, and the bit line lead 292 is made of the same material as the substrate, namely silicon. For example, the bit line lead 292 can be made of doped silicon to reduce bit line resistance and increase conductivity.

[0089] In some embodiments, the bit line lead-out portion and the substrate are integrally connected. Integrating the bit line lead-out portion and the substrate, with no clear boundary between them, eliminates intermediate potential barriers for electron transport between them, eliminates contact resistance, and, without providing additional electron transfer paths, effectively reduces parasitic capacitance and parasitic resistance.

[0090] like Figures 6 to 7 In some embodiments shown, the bit line lead-out 292 and the substrate 210 are integrally connected. There is no clear boundary between the bit line lead-out 292 and the second surface of the substrate 210.

[0091] It should be noted that in the foregoing embodiments, pixel units are led out one by one through bit lines and word lines extending in the row and column directions. In other embodiments of the present invention, pixel units may also be led out in other ways.

[0092] refer to Figure 8 and Figure 9 This illustrates a schematic diagram of a pixel array structure consistent with some embodiments of the present invention. Figure 8 This is a top view schematic diagram of a pixel array structure consistent with some embodiments of the present invention. Figure 9 This is a cross-sectional structural diagram of a pixel array consistent with some embodiments of the present invention.

[0093] Unlike the aforementioned embodiments, in some embodiments of the present invention, pixel units are led out in groups.

[0094] Specifically, in some embodiments of the present invention, the pixel array further includes: a pixel group, the pixel group including: a plurality of adjacent pixel units; the pixel group further includes: a group lead-out, the group lead-out being located at the intersection of the plurality of pixel units in the pixel group; the group lead-out is electrically connected to the transfer drain doped region of the pixel unit in the pixel group through a bit line lead-out.

[0095] like Figures 8 to 9 In some embodiments shown, the pixel array includes: a pixel group 301, the pixel group 301 including a plurality of pixel units 301 adjacent to each other; a group lead-out 302 located at the intersection of the plurality of pixel units 300 in the same pixel group 301; and the group lead-out 302 is electrically connected to the substrate of the plurality of pixel units 300 in the pixel group 301 via a bit line lead-out 302.

[0096] For example, pixel group 301 has four pixel units 301. Group lead-out 302 is located at the intersection of the four pixel units 300 in the same pixel group 301. In the second surface of the substrate, the projection of group lead-out 302 overlaps with the transfer drain doped regions 350 of the four pixel units 300 in the same pixel group 301. Bit line lead-out 393 is located at the corresponding position in the overlapping region to realize the electrical connection between the transfer drain doped regions 350 and group lead-out 302.

[0097] In some embodiments, the pixel unit further includes a word line lead, the word line lead being located on the side of the gate electrode of the transmission gate structure away from the photoelectric conversion region, and the word line lead being electrically connected to the gate electrode of the transmission gate structure.

[0098] like Figures 8 to 9 In some embodiments shown, word line lead 394 is located on the side of the transmission gate structure 340 facing the second surface and is electrically connected to the gate electrode of the transmission gate structure 340.

[0099] In some embodiments, the word line leads and the bit line leads are located at opposite ends of the diagonal of the pixel unit. Positioning the word line leads and bit line leads of the same pixel unit at opposite ends of the diagonal of the pixel unit's projection increases the distance between them, reducing manufacturing complexity and suppressing mutual interference.

[0100] like Figures 8 to 9 In some embodiments shown, the projection of the pixel unit on the second surface of the substrate is square. Bit line lead-out structure 393 and word line lead-out structure 394 are located at opposite ends of the square diagonal.

[0101] In some embodiments of the present invention, the pixel array further includes a color filter layer and a microlens; the color filter layer and the microlens are stacked one-time on a first surface of the substrate. The color filter layers of different pixel units within the same pixel group have different colors. The grouping of pixel units allows the pixel unit leads to adapt to the distribution of different color filter layers, resulting in a greater mismatch between the pixel unit leads and the color filter layer distribution. This effectively reduces the difficulty of pixel unit control and simplifies subsequent circuitry.

[0102] like Figures 8 to 9 In some embodiments shown, in pixel units 300 of pixel group 301, color filter layer 381 and microlens 382 are sequentially stacked on the first surface of the substrate. In the same pixel group 301, the color filter layer 381 of one pixel unit 300 is blue, and the color filter layer 381 of another pixel unit 300 is green.

[0103] Accordingly, the present invention also provides an image sensor.

[0104] refer to Figure 9 The diagram shows a cross-sectional structural schematic of an image sensor consistent with some embodiments of the present invention.

[0105] The image sensor includes: a first bonding unit and a second bonding unit bonded together; wherein the first bonding unit includes the pixel array of the present invention.

[0106] The first bonding unit is a photodiode unit. Specifically, the first bonding unit includes the pixel array of the present invention. The specific technical solution of the first bonding unit is described above. Figures 1 to 9 An example of a pixel array is shown.

[0107] The second bonding unit is a pixel transistor unit. Specifically, the second bonding unit includes pixel circuitry connected to the pixel units in the pixel array. For example, the pixel circuitry includes devices such as a source follower, a reset transistor, and a row selector connected to the pixel units.

[0108] like Figure 9 In some embodiments shown, the image sensor includes a first bonding unit 409 and a second bonding unit 408 bonded together. The first bonding unit 409 includes the pixel array of the present invention; the second bonding unit 408 is bonded to the side of the first bonding unit 409 near the second surface of the substrate. The first bonding unit 409 and the second bonding unit 408 are connected by a hybrid bonding method.

[0109] It should be noted that, Figure 9 In some embodiments shown, within the image sensor, the second bonding unit 408 and the first bonding unit 409 can be bonded in a face-to-back manner, that is, in the second bonding unit 409, the back side of the first bonding unit 409 is bonded to the back side of the second bonding unit 408. For example... Figure 9 As shown, in the second bonding unit 408, the pixel circuit is led out on the side opposite to the first bonding unit 409 and is electrically connected to the pixel array in the first bonding unit 409 through a through-silicon via (TSV) structure.

[0110] In other embodiments of the present invention, the second bonding unit may also be bonded to the first bonding unit in a face-to-face manner, that is, the second bonding unit is bonded to the front side of the first bonding unit. In the second bonding unit, the pixel circuit is led out on the side facing the first bonding unit and is directly electrically connected to the pixel array in the first bonding unit.

[0111] In some embodiments of the present invention, the image sensor further includes a third bonding unit, the third bonding unit being bonded to the side of the second bonding unit away from the first bonding unit.

[0112] The third bonding unit is a control unit. Specifically, the third bonding unit includes a control circuit.

[0113] like Figure 9 In some embodiments shown, the second bonding unit 408 is located between the first bonding unit 409 and the third bonding unit 407. One side surface of the second bonding unit 408 is connected to the first bonding unit 409 by a hybrid bonding method; the other side surface of the second bonding unit 408 is connected to the third bonding unit 407 by a hybrid bonding method.

[0114] Example, Figure 9 In some embodiments shown, the second bonding unit 408 and the first bonding unit 409 can be bonded in a face-to-back manner. The third bonding unit 407 is bonded to the second bonding unit 408 in a face-to-face manner. The third bonding unit 407 is bonded to one side of the pixel circuit leading out from the second bonding unit 408.

[0115] It should be noted that in the foregoing embodiments, the floating diffusion region 452, which serves as a top-view diffusion node, is disposed within the pixel unit 300 of the first bonding unit 409. In other embodiments of the present invention, the floating diffusion node may also be disposed in the second bonding unit.

[0116] Specifically, in some embodiments of the present invention, the second bonding unit includes a floating diffusion region, which is electrically connected to the transfer drain doped region of a pixel unit in the first bonding unit. By placing the floating diffusion region in a location different from the other bonding unit, the placement and design space of the floating diffusion region can be expanded, effectively increasing the full-well capacity of the pixel unit.

[0117] like Figure 10 In some embodiments shown, the floating diffusion region 552, which serves as a floating diffusion node, is located in the second bonding unit 508. The floating diffusion region 552 is electrically connected to the transfer drain doped region (not shown) of the pixel unit in the first bonding unit 509 via interconnect structures including through-silicon vias.

[0118] In summary, the transmission drain doped region is located in the substrate of the substrate surrounding the transmission gate structure near the second surface. The transmission drain doped region and the transmission gate structure are stacked along the direction perpendicular to the substrate surface, thereby forming a complete vertical channel transistor structure, which can effectively reduce the area occupied by the transmission transistor and is beneficial to the reduction of the pixel unit area.

[0119] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A pixel array, characterized in that, include: At least one pixel unit; The pixel unit includes: A substrate having a first surface and a second surface facing away from each other; A photoelectric conversion region, wherein the photoelectric conversion region is located within a substrate near the first surface; The transmission channel region is located within the substrate on the side of the photoelectric conversion region closest to the second surface; A transmission gate structure is located on the side of the substrate of the transmission channel region and surrounds the substrate of the transmission channel region; The transport drain doped region is located within the substrate on the side of the transport gate structure closest to the second surface.

2. The pixel array as described in claim 1, characterized in that, Also includes: A deep trench isolation structure, wherein the deep trench isolation structure is located between adjacent pixel units; The transmission gate structure is located between the deep trench isolation structure and the substrate of the transmission channel region.

3. The pixel array as described in claim 2, characterized in that, The transmission gate structure is filled between the deep trench isolation structure and the substrate of the transmission channel region.

4. The pixel array as described in claim 1, characterized in that, The transport drain doped region covers the substrate in a plane parallel to at least one of the first and second surfaces.

5. The pixel array as described in claim 1, characterized in that, The pixel unit further includes a dielectric layer located on the side of the substrate of the transport drain doped region.

6. The pixel array as described in claim 1, characterized in that, Within at least one of the first and second surfaces, the projection of the entire transmission gate structure and the transmission channel region coincides with the projection of the photoelectric conversion region.

7. The pixel array as described in claim 1, characterized in that, The pixel unit further includes a transmission source doped region, which is located in the substrate of the transmission gate structure on the side close to the photoelectric conversion region.

8. The pixel array as described in claim 1, characterized in that, The transfer drain doped regions of adjacent pixel units along the second direction are connected to the same bit line.

9. The pixel array as described in claim 8, characterized in that, The bit line includes a bit line lead-out portion located on the second surface of the transport drain doped region.

10. The pixel array as described in claim 9, characterized in that, The bit line leads of adjacent pixel units along the second direction extend and connect in the second direction.

11. The pixel array as described in claim 9 or 10, characterized in that, The bit line lead-out portion is made of the same material as the substrate.

12. The pixel array as described in claim 11, characterized in that, The bit line lead-out portion is integrally connected to the substrate.

13. The pixel array as claimed in claim 1, characterized in that, The transmission gate structure of adjacent pixel units along the first direction is electrically connected to the same word line.

14. The pixel array as claimed in claim 1, characterized in that, Also includes: A pixel group, comprising: a plurality of adjacent pixel units; The pixel group further includes: a group lead-out, which is located at the intersection of multiple pixel units in the pixel group; The group of leads is electrically connected to the substrate of the pixel unit in the pixel group via a bit line lead.

15. The pixel array as described in claim 14, characterized in that, The pixel unit further includes: a word line lead-out, the word line lead-out being located on the side of the gate electrode of the transmission gate structure away from the photoelectric conversion region, and the word line lead-out being electrically connected to the gate electrode of the transmission gate structure.

16. The pixel array as claimed in claim 15, characterized in that, The word line leader and the bit line leader are located at opposite ends of the diagonal of the pixel unit.

17. The pixel array as claimed in claim 1, characterized in that, The pixel unit further includes a floating diffusion region located between the transport drain doped region and the second surface.

18. The pixel array as claimed in claim 17, characterized in that, In a plane parallel to at least one of the first and second surfaces, the floating diffusion region covers the substrate of the pixel unit.

19. An image sensor, characterized in that, include: A first bonding unit and a second bonding unit that are bonded together; wherein the first bonding unit comprises a pixel array according to any one of claims 1 to 18.

20. The image sensor as claimed in claim 19, characterized in that, Also includes: The third bonding unit is bonded to the side of the second bonding unit away from the first bonding unit.

21. The image sensor as claimed in claim 19, characterized in that, The second bonding unit includes a floating diffusion region, which is electrically connected to the transfer drain doped region of a pixel unit in the first bonding unit.

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