TOPCon solar cell, preparation method thereof and photovoltaic module

Abstract

The invention provides a TOPCon solar cell, a preparation method thereof and a photovoltaic module. The cell comprises an n-type silicon wafer, a tunneling oxide layer and a doped polycrystalline silicon layer, the tunneling oxide layer and the doped polycrystalline silicon layer are located on the back face of the silicon wafer, and the cell is characterized in that the concentration of the doped polycrystalline silicon layer is larger than 5E20, and the tunneling oxide layer is compact in intrinsic, complete in structure and free of pinhole defects. The preparation method comprises the following steps: depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back surface of a silicon wafer by adopting an LPCVD (Low Pressure Chemical Vapor Deposition) mode; and performing in-situ doping on the intrinsic polycrystalline silicon layer by adopting a PECVD (Plasma Enhanced Chemical Vapor Deposition) mode to form a heavily doped amorphous silicon layer and an oxidation protection layer. According to the TOPCon solar cell, the uniform and compact tunneling oxide layer and the heavily-doped amorphous silicon layer can be obtained, excellent ohmic contact can be formed when the TOPCon solar cell and the metal electrode are sintered, the contact resistance is remarkably reduced, and the TOPCon solar cell has higher open-circuit voltage and FF.

Description

Technical Field

[0001] This disclosure relates to the field of solar cell technology, and in particular to a TOPCon solar cell and its preparation method, as well as a photovoltaic module. Background Technology

[0002] TOPCon is a tunnel oxide passivated contact solar cell technology based on the selective carrier principle. The tunnel oxide layer and the doped polycrystalline silicon layer together form a passivated contact structure, effectively reducing surface recombination and metal-to-metal recombination. Currently, the industry mainly uses two process routes: low-pressure chemical vapor deposition (LPCVD) and ion-enhanced chemical vapor deposition (PECVD), each with its advantages and disadvantages. The LP route produces a more uniform and dense tunnel layer, but its lower doping concentration leads to lower fill power (FF) and higher resistance (Rs). The PE route uses in-situ doping, resulting in a higher doping concentration, which facilitates ohmic contacts, but the tunnel layer uniformity is poorer, affecting cell efficiency. Summary of the Invention

[0003] In a first aspect, this disclosure provides a TOPCon solar cell, which includes an n-type silicon wafer, a tunneling oxide layer and a doped polycrystalline silicon layer located on the back side of the silicon wafer, wherein the doping concentration of the doped polycrystalline silicon layer is greater than 5E20.

[0004] According to the TOPCon solar cell described in this disclosure, the thickness of the tunneling oxide layer is 1.2-1.8 nm, and the tunneling oxide layer is intrinsically dense, structurally complete, and free of pinhole defects.

[0005] According to the TOPCon solar cell described in this disclosure, the thickness of the doped polycrystalline silicon layer is 120-150 nm, and the sheet resistance is 45-50 Ω / □.

[0006] According to the TOPCon solar cell described in this disclosure, the cell has a Voc greater than 740 mV, Rs less than 0.5 mΩ, FF greater than 86.3%, and Eff greater than 26.5%.

[0007] Secondly, this disclosure also provides a photovoltaic module comprising multiple TOPCon solar cells described in the first aspect of this disclosure, encapsulated in a series-parallel manner within a double-glass structure.

[0008] Thirdly, this disclosure also provides a method for fabricating a TOPCon solar cell, comprising: depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back side of a silicon wafer using LPCVD; and The intrinsic polycrystalline silicon layer was in-situ doped using PECVD to form a heavily doped amorphous silicon layer and an oxide protective layer, wherein the doping concentration was greater than 5E20.

[0009] According to the method for fabricating TOPCon solar cells described in this disclosure, a tunneling oxide layer and an intrinsic polycrystalline silicon layer are deposited by LPCVD under the following conditions: temperature 580-600℃, O2 flow rate 20000-22000 sccm, and SiH4 flow rate 2000-2400 sccm.

[0010] According to the TOPCon solar cell fabrication method described in this disclosure, an intrinsic polycrystalline silicon layer is in-situ doped using PECVD to form a heavily doped amorphous silicon layer and an oxide protective layer under the following conditions: The following parameters were used for deposition: PH3 flow rate 1500-3000 sccm, H2 flow rate 1000-1500 sccm, and SiH4 flow rate 1000-1500 sccm; RF power 9000-10000 W; pressure 1000-1200 mTorr; deposition time 150-300 s. The SiH4 flow rate is 1000-1500 sccm and the N2O flow rate is 1500-3000 sccm, the RF power is 9000-10000 W, the pressure is 1000-1200 mTorr, and the deposition time is 60-120 s.

[0011] According to the TOPCon solar cell fabrication method described in this disclosure, before depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back side of a silicon wafer using LPCVD, the method further includes steps of texturing the silicon wafer and boron doping.

[0012] According to the TOPCon solar cell fabrication method described in this disclosure, after in-situ doping of the intrinsic polycrystalline silicon layer using PECVD to form a heavily doped amorphous silicon layer and an oxide protective layer, the method further includes: Annealing is performed on the silicon wafers; Passivation and / or antireflection films are formed on the front and back sides of the silicon wafer; and Metallization is performed on the front and back sides of the silicon wafer to form electrodes.

[0013] The TOPCon solar cell described in this disclosure can obtain a uniform and dense tunneling oxide layer and a heavily doped amorphous silicon layer, which can form excellent ohmic contact during sintering with metal electrodes, significantly reducing contact resistance and having higher open-circuit voltage and FF. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of the TOPCon solar cell described in this disclosure.

[0015] Figure 2 This is a schematic flowchart of the method for fabricating the TOPCon solar cell described in this disclosure.

[0016] Figures 3 to 13 This is a step-by-step structural diagram of the fabrication method of the TOPCon solar cell described in this disclosure. Detailed Implementation

[0017] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions of this disclosure will be described in detail below with reference to the accompanying drawings.

[0018] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0019] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0020] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the said feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded.

[0022] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0023] like Figure 1 As shown, this disclosure provides a TOPCon solar cell, which includes an n-type silicon wafer, a tunneling oxide layer and a doped polycrystalline silicon layer located on the back of the silicon wafer, wherein the doping concentration of the doped polycrystalline silicon layer is greater than 5E20, and the tunneling oxide layer is intrinsically dense, structurally complete, and free of pinhole defects.

[0024] In the TOPCon solar cell described in this disclosure, the n-type silicon wafer can be (M)CZ silicon with a resistivity of 0.5-1.5 Ω·cm and a thickness of 100-130 μm.

[0025] According to the TOPCon solar cell described in this disclosure, the thickness of the tunneling oxide layer is 1.2-1.8 nm, and the tunneling oxide layer is SiO2 formed by thermal oxidation or plasma / ozone-assisted oxidation. x .

[0026] According to the TOPCon solar cell described in this disclosure, the thickness of the doped polycrystalline silicon layer is 120-150 nm, and the sheet resistance is 45-50 Ω / □.

[0027] The doped polycrystalline silicon layer is obtained by forming intrinsic polycrystalline silicon by LPCVD, followed by PECVD doping, annealing, and crystallization.

[0028] According to the TOPCon solar cell described in this disclosure, the cell has an open-circuit voltage (Voc) greater than 740 mV, a series resistance (Rs) less than 0.5 mΩ, a fill factor (FF) greater than 86.3%, and a photoelectric conversion efficiency (Eff) greater than 26.5%.

[0029] This disclosure also provides a photovoltaic module comprising multiple TOPCon solar cells described herein, encapsulated in a series-parallel configuration within a double-glass structure.

[0030] This disclosure also provides a method for fabricating a TOPCon solar cell, comprising: depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back side of a silicon wafer using LPCVD; and The intrinsic polycrystalline silicon layer was in-situ doped using PECVD to form a heavily doped amorphous silicon layer and an oxide protective layer, wherein the doping concentration was greater than 5E20.

[0031] According to the method for fabricating TOPCon solar cells described in this disclosure, a tunneling oxide layer and an intrinsic polycrystalline silicon layer are deposited by LPCVD under the following conditions: Temperature 580-600℃, O2 flow rate 20000-22000 sccm, SiH4 flow rate 2000-2400 sccm.

[0032] According to the TOPCon solar cell fabrication method described in this disclosure, an intrinsic polycrystalline silicon layer is in-situ doped using PECVD to form a heavily doped amorphous silicon layer and an oxide protective layer under the following conditions: The following parameters were used for deposition: PH3 flow rate 1500-3000 sccm, H2 flow rate 1000-1500 sccm, and SiH4 flow rate 1000-1500 sccm; RF power 9000-10000 W; pressure 1000-1200 mTorr; deposition time 150-300 s. The SiH4 flow rate is 1000-1500 sccm and the N2O flow rate is 1500-3000 sccm, the RF power is 9000-10000 W, the pressure is 1000-1200 mTorr, and the deposition time is 60-120 s.

[0033] According to the TOPCon solar cell fabrication method described in this disclosure, before depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back side of a silicon wafer using LPCVD, the method further includes steps of texturing the silicon wafer and boron doping.

[0034] Specifically, taking advantage of the anisotropic corrosion characteristics of silicon in low-concentration alkaline solutions, Si undergoes a series of chemical reactions with the alkaline solution (NaOH). Texturing is performed using a texturing tank, and organic matter and metal impurities are removed using the alkaline solution. Boron doping is then performed to form a PN junction. After removing the edges and applying a plating layer, the back side is polished to form a flat surface.

[0035] According to the TOPCon solar cell fabrication method described in this disclosure, after in-situ doping of the intrinsic polycrystalline silicon layer using PECVD to form a heavily doped amorphous silicon layer and an oxide protective layer, the method further includes: Annealing is performed on the silicon wafers; Passivation and / or antireflection films are formed on the front and back sides of the silicon wafer; and Metallization is performed on the front and back sides of the silicon wafer to form electrodes.

[0036] Figure 2 This is a schematic flowchart of a method for fabricating a TOPCon solar cell according to an embodiment of this disclosure. Figures 3 to 13 This is a schematic diagram of the step-by-step structure of the corresponding TOPCon solar cell fabrication process, in which... Figures 3 to 13 The cross-sectional views of the layered structure formed by each process step are shown in sequence.

[0037] like Figures 2 to 13 As shown, according to one embodiment of this disclosure, the method for fabricating the TOPCon solar cell includes: S1: Texturing and boron doping treatment of silicon wafers; S2: A tunneling oxide layer and an intrinsic polysilicon layer are deposited on the back side of a silicon wafer using LPCVD. S3: The intrinsic polycrystalline silicon layer is in-situ doped using PECVD to form a heavily doped amorphous silicon layer and an oxide protective layer; S4: Annealing the silicon wafer; S5: Form passivation and / or antireflection films on the front and back sides of the silicon wafer; and S6: Metallize the front and back sides of the silicon wafer to form electrodes.

[0038] In step S1, under the conditions of temperature 32-35℃, NaOH solution concentration of 4.8%-6%, and reaction time of 200-250s, the anisotropic corrosion characteristics of silicon in low-concentration alkaline solution are used to form a pyramid textured surface on the N-type silicon wafer, removing organic dirt and metal impurities from the silicon wafer surface. The reaction equation is: 2NaOH+Si+H2O=Na2SiO3+2H2.

[0039] Then, P-type impurities are diffused onto the surface of the N-type silicon wafer to form a PN junction. The silicon wafer is placed in a furnace at 950-1000℃, and B2O3 is generated using the impurity source BCl3. The reaction equation is: 4BCl3+3O2→2B2O3+6Cl2↑. The generated B2O3 reacts with silicon, and the reaction equation is: 2B2O3+3Si→3SiO2+4B. The PN junction is formed by high temperature.

[0040] In step S2, a tunneling oxide layer and an intrinsic polysilicon layer can be deposited by LPCVD under the following conditions: Temperature 580-600℃, O2 flow rate 20000-22000 sccm, SiH4 flow rate 2000-2400 sccm.

[0041] In step S3, the intrinsic polycrystalline silicon layer can be in-situ doped using PECVD to form a heavily doped amorphous silicon layer and an oxide protective layer under the following conditions: The following parameters were used for deposition: PH3 flow rate 1500-3000 sccm, H2 flow rate 1000-1500 sccm, and SiH4 flow rate 1000-1500 sccm; RF power 9000-10000 W; pressure 1000-1200 mTorr; deposition time 150-300 s. The SiH4 flow rate is 1000-1500 sccm and the N2O flow rate is 1500-3000 sccm, the RF power is 9000-10000 W, the pressure is 1000-1200 mTorr, and the deposition time is 60-120 s.

[0042] Crystallization is achieved through annealing, transforming amorphous silicon into polycrystalline silicon and activating dopant atoms, thereby forming a complete composite polycrystalline silicon structure with high interface quality and high doping concentration.

[0043] The passivation and / or antireflection film can be a conventionally used film layer, such as a single layer or a combination of SiOx, SiNx, SiNxOy, AlOx, etc.

[0044] Metallization can be achieved using Ag-containing gate lines, Ag-containing gate lines, or Ag / Al composite gate lines. The linewidth of the metal gate lines is 5-40 μm, and the number of gate lines is 50-500.

[0045] The TOPCon solar cell described in this disclosure has the following significant advantages in terms of structural design and performance optimization: 1) Excellent surface passivation and superior Euclidean contact with the metal electrode A uniform and dense tunneling oxide layer was formed by LPCVD, which provides excellent surface passivation for the silicon wafer and effectively reduces carrier recombination loss. At the same time, a heavily doped polycrystalline silicon layer was formed by PECVD. The high doping concentration enables excellent ohmic contact to be formed when sintering with metal electrodes, which significantly reduces contact resistance.

[0046] 2) Good process compatibility Both LPCVD and PECVD are mature processes with smooth integration and good industrial feasibility and repeatability.

[0047] To enable those skilled in the art to better understand the technical solutions provided in this disclosure, the technical solutions provided in this disclosure will be described in detail below through specific embodiments.

[0048] Example 1 (1) Cleaning + Boron expansion + Back polishing Under the conditions of 35℃, 6% NaOH concentration, and 200s reaction time, a pyramidal textured surface is formed on the surface of an N-type silicon wafer, removing organic dirt and metallic impurities from the silicon wafer surface.

[0049] P-type impurities are diffused onto an N-type silicon wafer to form a PN junction. The silicon wafer is placed in a furnace at 1000°C, and the impurity source BCl3 is used to propel the PN junction through high temperature.

[0050] Using a chain-type device, the oxide layer on the back side is removed. The silicon wafer is then placed in a tank for a chemical reaction, with appropriate amounts of NaOH solution and polishing additives added (1.6% NaOH solution, 1% polishing agent). Both sides of the silicon wafer are then polished at 65℃. After alkaline polishing, it is rinsed with pure water.

[0051] (2) Sedimentary tunneling layer + intrinsic layer Using a Laplace test chamber, the sample was placed in a furnace tube, the chamber temperature was set to 600℃, and O2 was introduced at a flow rate of 20000 sccm. O2 reacted with Si to form SiOx over a time of 400 s and a pressure of 180 mTorr, resulting in an ultrathin tunneling layer with a thickness of 1.8 nm. At the same temperature, SiH4 was introduced at a flow rate of 2000 sccm. SiH4 thermally decomposed to form Si and H2 over a time of 150 s and a pressure of 200 mTorr, resulting in an intrinsic silicon layer of 30 nm.

[0052] (3) Deposition of heavily doped + oxide protective layer Using the Jiejia Weichuang tubular PECVD machine, the silicon wafer was placed in a graphite boat and fed into the cavity. PH3 with a flow rate of 1500 sccm, H2 with a flow rate of 1000 sccm, and SiH4 with a flow rate of 1000 sccm were introduced. 10000W of RF power was applied, the pressure was set to 1200 mTorr, and the deposition time was 200 s to obtain a heavily doped poly layer. Then, SiH4 with a flow rate of 1000 sccm and N2O with a flow rate of 1500 sccm were introduced. 10000W of RF power was applied, the pressure was set to 1200 mTorr, and the deposition time was 90 s to deposit a silicon oxide protective layer.

[0053] (4) Annealing The silicon wafer is placed in the cavity and annealed at 900℃ for 900s to convert amorphous silicon into polycrystalline silicon. Phosphorus atoms are activated to advance the junction depth.

[0054] (5) Alkali washing + ALD + SIN Using a chain-type device, a 5% HF solution is used to remove the oxide layer on the front and edges.

[0055] Alkaline washing: Place the silicon wafer in a tank containing H2O and KOH solutions in a 5:1 ratio, heat to 35°C, and immerse for 100 seconds to remove the poly coating on the front and edges. Then, use a 5% HF solution to remove the BSG on the front and PSG on the back. After rinsing with pure water, dry the wafer.

[0056] AL2O3 deposition: By alternately introducing gaseous precursors TMA and H2O into the reaction chamber, AL2O3 is deposited on the silicon wafer through chemical adsorption reaction.

[0057] Deposition of anti-reflection silicon nitride thin films on the front and back sides: Using PECVD deposition, the silicon wafer is placed in a graphite boat, SiH4 and NH3 are introduced, the temperature inside the boat is heated to 500℃, 10000W of RF power is applied, the pressure is set to 2000mTorr, and the deposition time is 600S, depositing a layer of SiN anti-reflection passivation film on the front and back sides of the silicon wafer.

[0058] (6) Metallization Metal paste is printed on both sides and then sintered at high temperature using a screen to form an ohmic contact between the silicon substrate and the metal electrode.

[0059] Example 2 Solar cells were prepared according to the method of Example 1, with the following differences: (2) Sedimentary tunneling layer + intrinsic layer Using a Laplace test chamber, the sample was placed in a furnace tube with the chamber temperature set to 590℃. O2 was introduced at a flow rate of 22000 sccm, and O2 reacted with Si to form SiOx over a time of 450 s. The pressure was set to 180 mTorr, resulting in an ultrathin tunneling layer with a thickness of 1.5 nm. At the same temperature, SiH4 was introduced at a flow rate of 2200 sccm, and SiH4 thermally decomposed to form Si and H2 over a time of 180 s. The pressure was set to 200 mTorr, resulting in an intrinsic silicon layer of 35 nm.

[0060] (3) Deposition of heavily doped + oxide protective layer Using the Jiejia Weichuang tubular PECVD machine, the silicon wafer was placed in a graphite boat and fed into the cavity. PH3 with a flow rate of 2000 sccm, H2 with a flow rate of 1200 sccm, and SiH4 with a flow rate of 1200 sccm were introduced. 9000W of RF power was applied, the pressure was set to 1000 mTorr, and the deposition time was 150 s to obtain a heavily doped poly layer. Then, SiH4 with a flow rate of 1200 sccm and N2O with a flow rate of 2000 sccm were introduced. 9000W of RF power was applied, the pressure was set to 1200 mTorr, and the deposition time was 60 s to deposit a silicon oxide protective layer.

[0061] Example 3 Solar cells were prepared according to the method of Example 1, with the following differences: (2) Sedimentary tunneling layer + intrinsic layer Using a Laplace test chamber, the sample was placed in a furnace tube, the chamber temperature was set to 580℃, and O2 was introduced at a flow rate of 20000 sccm. O2 reacted with Si to form SiOx over a time of 400 s and a pressure of 180 mTorr, resulting in an ultrathin tunneling layer with a thickness of 1.2 nm. At the same temperature, SiH4 was introduced at a flow rate of 2400 sccm. SiH4 thermally decomposed to form Si and H2 over a time of 200 s and a pressure of 200 mTorr, resulting in an intrinsic silicon layer of 32 nm.

[0062] (3) Deposition of heavily doped + oxide protective layer Using the Jiejia Weichuang tubular PECVD machine, the silicon wafer was placed in a graphite boat and fed into the cavity. PH3 with a flow rate of 3000 sccm, H2 with a flow rate of 1500 sccm, and SiH4 with a flow rate of 1500 sccm were introduced. 9500W of RF power was applied, the pressure was set to 1000 mTorr, and the deposition time was 300 s to obtain a heavily doped poly layer. Then, SiH4 with a flow rate of 1500 sccm and N2O with a flow rate of 3000 sccm were introduced. 9500W of RF power was applied, the pressure was set to 1200 mTorr, and the deposition time was 120 s to deposit a silicon oxide protective layer.

[0063] Comparative Example 1 Solar cells were prepared according to the method of Example 1, with the following differences: Using a Laplace apparatus, the sample was placed in a furnace tube, the temperature was set to 600℃, oxygen flow rate was 20000 sccm, time was 400s, and pressure was set to 180mTorr to obtain an ultrathin tunneling layer of 1.8nm. Then, SiH4 flow rate was introduced at 2400 sccm for 900s and pressure was set to 200mTorr to obtain 120nm intrinsic silicon. The sample was removed and loaded into a phosphorus diffusion apparatus, the temperature was set to 850℃, phosphine flow rate was introduced at 3400 sccm for 600s and pressure was set to 180mTorr to obtain doped polycrystalline silicon.

[0064] Comparative Example 2 Solar cells were prepared according to the method of Example 1, with the following differences: Using the Jiejia Weichuang tubular PECVD instrument, the sample was placed in a graphite boat and fed into the chamber. PH3 with a flow rate of 2000 sccm, H2 with a flow rate of 1000 sccm, and SiH4 with a flow rate of 1000 sccm were introduced. The RF power was 10000W, the pressure was 1200 mTorr, and the deposition time was 600 s to obtain 100 nm doped amorphous silicon. The sample was then removed and placed in an annealing furnace for 1000 s at a temperature of 980℃ to obtain doped polycrystalline silicon.

[0065] The performance of the batteries prepared in the above embodiments was tested, and the results are shown in Table 1 below.

[0066] Table 1 - Battery Performance Test Results

[0067] Compared to Comparative Example 1, Example 1 has the same Voc and Isc, Rs is 0.29mΩ lower, Rsh is 1801Ω lower, FF is 0.55% higher, IRev2 is increased by 0.0108A, and Eff is increased by 0.22%.

[0068] Compared to Comparative Example 2, Example 1 has a Voc that is 2.8 mV higher, an Isc that is 0.085 A higher, an Rs that is 0.02 mΩ lower, an Rsh that is 439 Ω lower, an FF that is 0.03% lower, an IREV2 that is 0.0202 A higher, and an Eff that is 0.25% higher.

[0069] Examples 2 and 3 have similar effects, thus demonstrating that the solar cells according to this disclosure have superior performance, such as higher voltage fill, better passivation, and better contact.

[0070] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A TOPCon solar cell, comprising an n-type silicon wafer, and a tunneling oxide layer and a doped polycrystalline silicon layer located on the back side of the silicon wafer, characterized in that, The doping concentration of the doped polycrystalline silicon layer is greater than 5E20.

2. The TOPCon solar cell according to claim 1, characterized in that, The thickness of the tunneling oxide layer is 1.2-1.8 nm, and the tunneling oxide layer is intrinsically dense, structurally complete, and free of pinhole defects.

3. The TOPCon solar cell according to claim 1, characterized in that, The thickness of the doped polycrystalline silicon layer is 120-150 nm, and the sheet resistance is 45-50 Ω / □.

4. The TOPCon solar cell according to claim 1, characterized in that, The battery has a Voc greater than 740 mV, Rs less than 0.5 mΩ, FF greater than 86.3%, and Eff greater than 26.5%.

5. A photovoltaic module, characterized in that, The photovoltaic module comprises multiple TOPCon solar cells according to any one of claims 1-4, encapsulated in a series-parallel manner within a double-glass structure.

6. A method for fabricating a TOPCon solar cell, characterized in that, The preparation method includes: A tunneling oxide layer and an intrinsic polysilicon layer are deposited on the back side of a silicon wafer using LPCVD; and The intrinsic polycrystalline silicon layer was in-situ doped using PECVD to form a heavily doped amorphous silicon layer and an oxide protective layer, wherein the doping concentration was greater than 5E20.

7. The method for preparing a TOPCon solar cell according to claim 6, characterized in that, Deposit tunneling oxide and intrinsic polysilicon layers via LPCVD under the following conditions: Temperature 580-600℃, O2 flow rate 20000-22000 sccm, SiH4 flow rate 2000-2400 sccm.

8. The method for preparing a TOPCon solar cell according to claim 6, characterized in that, Under the following conditions, an intrinsic polycrystalline silicon layer is in-situ doped using PECVD to form a heavily doped polycrystalline silicon layer and an oxide protective layer: The following parameters were used for deposition: PH3 flow rate 1500-3000 sccm, H2 flow rate 1000-1500 sccm, and SiH4 flow rate 1000-1500 sccm; RF power 9000-10000 W; pressure 1000-1200 mTorr; deposition time 150-300 s. The SiH4 flow rate is 1000-1500 sccm and the N2O flow rate is 1500-3000 sccm, the RF power is 9000-10000 W, the pressure is 1000-1200 mTorr, and the deposition time is 60-120 s.

9. The method for preparing a TOPCon solar cell according to claim 6, characterized in that, Before depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back side of a silicon wafer using LPCVD, the process also includes texturing and boron doping of the silicon wafer.

10. The method for preparing a TOPCon solar cell according to claim 6, characterized in that, After in-situ doping of the intrinsic polycrystalline silicon layer using PECVD to form a heavily doped polycrystalline silicon layer and an oxide protective layer, the process also includes: Annealing is performed on the silicon wafers; Passivation and / or antireflection films are formed on the front and back sides of the silicon wafer; and Metallization is performed on the front and back sides of the silicon wafer to form electrodes.

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