memory

Abstract

The embodiment of the present application provides a memory, which can at least include: a storage array containing a plurality of word lines; a word line contact structure including a first word line contact structure and a second word line contact structure located on opposite sides of the storage array, the first word line contact structure being used for connecting a first word line driver, the second word line contact structure being used for connecting a second word line driver, and each word line in the storage array being driven by the first word line driver and the second word line driver simultaneously.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a memory. Background Technology

[0002] In memory design, especially in the design of Dynamic Random Access Memory (DRAM), increasing the density of memory cells is a major concern. There are generally two ways to increase the density of memory cells: the first is to reduce the area of ​​the control circuitry corresponding to the same capacity of memory cells, and the second is to increase the number of memory cells corresponding to a unit of control circuitry. The former, due to the reduction in the area of ​​the control circuitry, helps to reduce the overall size of the chip, thereby increasing the number of complete wafers (dies) that can be successfully processed and ultimately cut from each wafer. Summary of the Invention

[0003] This application provides a memory that at least helps to improve the storage efficiency of the memory.

[0004] According to some embodiments of this application, one aspect of this application provides a memory, which may include at least: a memory array, the memory array including a plurality of word lines; word line contact structures, including a first word line contact structure and a second word line contact structure located on opposite sides of the memory array, the first word line contact structure being used to connect to a first word line driver, the second word line contact structure being used to connect to a second word line driver, and each word line in the memory array being driven by both the first word line driver and the second word line driver.

[0005] In some embodiments, each of the word lines has a first end and a second end, and the first end of at least one word line is directly connected to the first word line contact structure, and the second end is directly connected to the second word line contact structure.

[0006] In some embodiments, the at least one word line comprises two word lines connected end-to-end, the two word lines forming a closed loop surrounding the memory cell.

[0007] In some embodiments, each of the memory arrays includes multiple memory rows, all memory cells in the same memory row share the same word line, adjacent memory rows in the same memory array are connected to different local bit lines, and at least two adjacent word lines are simultaneously connected to the first word line contact structure and the second word line contact structure.

[0008] In some embodiments, the character lines extend along a first horizontal direction, while all character lines connected to the first character line contact structure and the second character line contact structure are continuously arranged in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction and the vertical direction.

[0009] In some embodiments, each of the memory arrays includes multiple memory rows, all memory cells in the same memory row share the same word line, and every two memory cells arranged along a second horizontal direction share a local bit line, the second horizontal direction being perpendicular to the first horizontal direction; the word line contact structure further includes: a third word line contact structure and a fourth word line contact structure, the first word line contact structure, the second word line contact structure, the third word line contact structure, and the fourth word line contact structure corresponding to the same memory array, the third word line contact structure being used to connect to a third word line driver, the fourth word line contact structure being used to connect to a fourth word line driver, the first word line contact structure and the third word line contact structure being located on the same side of the corresponding memory array, the second word line contact structure and the fourth word line contact structure being located on the same side of the corresponding memory array, the third word line contact structure and the fourth word line contact structure being disposed opposite to each other, and adjacent word lines corresponding to the same local bit line being connected to different word line contact structures on the same side.

[0010] In some embodiments, the memory includes a vertically stacked multi-layer memory array, wherein different stacked memory cells share a local bit line extending in a vertical direction perpendicular to the first horizontal direction.

[0011] In some embodiments, among adjacent word lines corresponding to the same group of local bit lines, one is connected to the word line contact structure at only one end, while the other is connected to two opposite word line contact structures at both ends.

[0012] In some embodiments, the memory array has edge word lines, each edge word line corresponding to a different local bit line from its adjacent word lines, and the edge word lines and adjacent word lines are connected to at least the same word line contact structure.

[0013] In some embodiments, the edge character line and the adjacent character line are simultaneously connected to two opposite character line contact structures. Attached Figure Description

[0014] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0015] Figure 1This is a schematic diagram of the word line contact structure and the connection relationship of word lines in a memory.

[0016] Figures 2 to 4 A schematic diagram illustrating the word line contact structure and the connection relationship of word lines in a memory provided in an embodiment of this application;

[0017] Figure 5 This is a schematic diagram illustrating the relationship between the storage array and the storage block provided in an embodiment of this application. Detailed Implementation

[0018] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0019] Figure 1 This is a schematic diagram illustrating the word line contact structure and the connection relationship of word lines in a memory. (Reference) Figure 1 The memory includes: a memory array subMat, which contains multiple word lines WL extending along a first direction D1 and arranged along a second direction D2 perpendicular to the first direction D1; and word line contact structures, including a first word line contact structure SC1 and a second word line contact structure SC2 located on opposite sides of the memory array subMat. The first word line contact structure SC1 is connected to a first word line driver SWD1, and the second word line contact structure SC2 is connected to a second word line driver SWD2. The first word line contact structure SC1 is connected to odd-numbered lines (shown as dashed lines) in the adjacent memory array subMat, and the second word line contact structure SC2 is connected to even-numbered lines (shown as solid lines) in the adjacent memory array subMat. In other words, the first word line driver SWD1 drives the odd-numbered lines in two adjacent memory array subMats simultaneously through the first word line contact structure SC1, and the second word line driver SWD2 drives the even-numbered lines in two adjacent memory array subMats simultaneously through the second word line contact structure SC2.

[0020] exist Figure 1In the illustrated embodiment, the memory array subMat contains four memory rows, each corresponding to the same word line WL. Each memory row contains N memory cells, arranged in the second direction D2, with every two memory cells sharing a bit line BL. Since each word line driver needs to provide drive for both memory arrays simultaneously, for a given memory array, it can be considered that it only enjoys half the driving capability of the first word line driver SWD1 and half of the driving capability of the second word line driver SWD2. In other words, each memory array only enjoys the driving capability of one complete word line driver. At this time, the ratio of the number of memory cells in the memory array to the number of word line drivers (or the number of word line contact structures) enjoyed by the memory array is 4N / 1. This ratio, to a certain extent, characterizes the memory's storage density and storage efficiency.

[0021] It should be noted that the number of storage cells contained in each storage row is limited by the driving capability of the word line driver, or in other words, by the driving capability enjoyed by the word line. The stronger the driving force enjoyed by the word line, the longer the word line can be, and the more storage cells can be contained in a storage row sharing the same word line.

[0022] Figures 2 to 4 This is a schematic diagram of the word line contact structure and the connection relationship of word lines in a memory provided in an embodiment of this application.

[0023] refer to Figures 2 to 3 The memory includes: a memory array subMat, which contains multiple word lines WL; and word line contact structures SC, including a first word line contact structure SC1 and a second word line contact structure SC2 located on opposite sides of the memory array subMat. The first word line contact structure SC1 is used to connect to a first word line driver SWD1, and the second word line contact structure SC2 is used to connect to a second word line driver SWD2. Each word line WL in the memory array subMat is simultaneously driven by the first word line driver SWD1 and the second word line driver SWD2.

[0024] In this embodiment, by controlling each word line WL to be simultaneously driven by the first word line driver SWD1 and the second word line driver SWD2 located on opposite sides of the relative memory array subMat, compared to being driven by only one word line contactor, it is beneficial to extend the length of the word line WL, ensure that longer word lines can also be effectively driven, increase the number of memory cells sharing the same word line, and thus increase the memory density.

[0025] The embodiments of this application will be described in more detail below with reference to the accompanying drawings. It should be understood that the drawings illustrate only a portion of the embodiments included in this application and are not intended to limit the actual scope of protection of this application. Furthermore, Figure 2, Figure 3 as well as Figure 4 The use of both solid and dashed lines to represent character lines is merely for clearer contrast and no longer indicates odd and even number lines.

[0026] In this embodiment, the memory further includes word line drivers, each corresponding to a word line contact structure. The word line driver drives the word line connected to the corresponding word line contact structure. Therefore, the connection between a word line and a word line contact structure indicates that the word line is driven by the word line driver connected to the word line contact structure. The word line driver can control the potential state of the word line by outputting a high or low level, pulling the potential of the word line high or low.

[0027] It should be noted that the term "connection" in this application includes direct connection and indirect connection, with indirect connection including complete indirect connection and partial indirect connection. In a direct connection scenario, a word line can connect to a word line contact structure through endpoints or non-endpoints; in an indirect connection scenario, a word line can be indirectly connected to a word line contact structure through another word line. A complete indirect connection refers to a word line that is not directly connected to any word line contact structure, but is entirely connected indirectly through other word lines; a partial indirect connection refers to a word line that is directly connected to some word line contact structures and indirectly connected to others, essentially meaning that both direct and partial connections exist simultaneously.

[0028] exist Figure 2 In the illustrated embodiment, a first word line WL1 is provided in the storage array subMat. The first end T1 of the first word line WL1 is connected to a first word line contact structure SC1, and the second end T2 is connected to a second word line contact structure SC2. That is, the first word line WL1 is directly connected to the first word line contact structure SC1 and the second word line contact structure SC2 through different endpoints. Figure 3 In the illustrated embodiment, the storage array is provided with a first word line WL1 and a second word line WL2. The first end T1 of the first word line WL1 is connected to the first word line contact structure SC1 and to the first end T1 of the second word line WL2. The second end T2 of the second word line WL2 is connected to the second word line contact structure SC2. That is, the first word line WL1 is directly connected to the first word line contact structure SC1 through its endpoint and indirectly connected to the second word line contact structure SC2 through the second word line WL2. The second word line WL2 is directly connected to the first word line contact structure SC1 and the second word line contact structure SC2 through different endpoints.

[0029] In this embodiment, the first word line contact structure SC1 and the second word line contact structure SC2 are merely general terms, representing two word line contact structures SC located on opposite sides of any memory array subMat, and not specifically referring to any particular word line contact structure SC. Each non-edge memory array has word line contact structures on opposite sides, or in other words, word line contact structures are provided between adjacent memory arrays. When discussing the connection relationship between word lines in any memory array and adjacent word line contact structures, the word line contact structures on opposite sides can be defined as the first word line contact structure and the second word line contact structure.

[0030] The word line contact structure and the corresponding word line driver can be on the same wafer or on different wafers. When the word line contact structure and the word line driver are on different transistors, the two wafers can be manufactured separately and then connected together by hybrid bonding or other methods.

[0031] In some embodiments, when reading and writing data in the memory, multiple memory blocks arranged along the word line extension direction can be opened at once, and each memory block outputs a portion of the data. (See reference) Figure 5 At least some memory blocks (e.g., the first memory block Mat1 and the second memory block Mat2) are arranged along the word line extension direction. Each memory block contains N memory arrays subMat (subMat1 to subMatN), and the arrangement direction of the memory arrays subMat is perpendicular to the word line extension direction. A word line contact area (SCR) can be provided between adjacent memory blocks. Figures 2 to 4 The word line contact structure SC shown in the diagram is located in the word line contact area SCR.

[0032] In some embodiments, in the subMat memory array, each word line WL has a first end and a second end. The first end of at least one word line WL is directly connected to the first word line contact structure SC1, and the second end is directly connected to the second word line contact structure SC2. This helps to prevent the potential of the end of the word line WL furthest from the word line contact structure SC from being pulled up or down too slowly, or even failing to be pulled to the preset level. This ensures that the potential at any position of at least some word lines WL can be adjusted in a timely manner, ensuring that the data access path of the memory cell is turned on or off in a timely manner.

[0033] exist Figure 2 In the illustrated embodiment, the first ends T1 of the first character line WL1, the second character line WL2, and the third character line WL3 are all directly connected to the first character line contact structure SC1, and the second ends T2 are all directly connected to the second character line contact structure SC2; Figure 3 In the illustrated embodiment, the first end T1 of the second character line WL2 is directly connected to the first character line contact structure SC1, and the second end T2 is directly connected to the second character line contact structure SC2; in Figure 4 In the embodiment shown, the first end T1 of the first character line WL1 and the second character line WL2 are both directly connected to the first character line contact structure SC1, and the second end T2 is both directly connected to the second character line contact structure SC2.

[0034] It should be noted that when two or more character lines are involved, one end of each line is directly connected to a character line contact structure. This can be achieved by first connecting segments of multiple character lines together and then connecting them to the character line contact structure through a common connection point, or by connecting different character lines to the character line contact structure separately. Figures 2 to 4 The former is used as an example in the illustrated embodiment.

[0035] In some embodiments, the memory structure includes at least two word lines connected end-to-end. These two word lines form a closed loop surrounding the memory cell, and the first ends of both word lines are directly connected to a first word line contact structure, while their second ends are directly connected to a second word line contact structure. "Two word lines connected end-to-end" means that both the first and second ends of the two word lines are interconnected. This facilitates further balancing of the word line driver's driving capabilities for different word lines, ensuring that different positions of each word line can be effectively driven.

[0036] exist Figure 2 In the illustrated embodiment, the second word line WL2 and the third word line WL3 are connected end-to-end and form a closed loop surrounding the memory cell; further, they form a closed loop surrounding at least one memory row; Figure 4 In the illustrated embodiment, the first word line WL1 and the second word line WL2 are connected end to end and form a closed loop surrounding the memory cell; further, they form a closed environment surrounding at least one memory row. Here, "surrounding" refers to the projection of the two word lines connected end to end surrounding the projection of the memory cell in the vertical direction Z; the memory cell refers to a device used to store data information, such as a storage capacitor and a storage resistor, and does not include access transistors whose switches are controlled by the word lines.

[0037] It should be noted that this is only based on Figure 2 The second letter line WL2 and the third letter line WL3 in the middle, and Figure 4 The first character line WL1 and the second character line WL2 are used as examples for illustration. In fact, Figure 2 and Figure 4 In the storage array shown, there may also be other word line pairs connected end to end to form a closed ring around the storage cell.

[0038] In some embodiments, each memory array subMat contains multiple memory rows, all memory cells in the same memory row share the same word line WL, adjacent memory rows in the same memory array are connected to different local bit lines LBL, and at least two adjacent word lines are simultaneously connected to the first word line contact structure SC1 and the second word line contact structure SC2.

[0039] Furthermore, the character lines WL extend along the first horizontal direction X, and all the character lines WL connected to the first character line contact structure SC1 and the second character line contact structure SC2 are continuously arranged in the second horizontal direction Y, which is perpendicular to the first horizontal direction X.

[0040] refer to Figure 2 The first character line WL1, the second character line WL2, and the third character line WL3 are arranged continuously in the second horizontal direction Y. The first character line WL1 is adjacent to the second character line WL2, and the second character line WL2 and the third character line WL3 are adjacent to each other. The first end of the first character line WL1, the second character line WL2, and the third character line WL3 are all connected to the first character line contact structure SC1, and the second end of each character line is connected to the second character line contact structure SC2.

[0041] exist Figure 2 In the illustrated embodiment, the word line contact structure further includes a third word line contact structure SC3 and a fourth word line contact structure SC4, with multiple storage rows disposed between the third word line contact structure SC3 and the fourth word line contact structure SC4. It can be considered that the storage cells located between the first word line contact structure SC1 and the second word line contact structure SC2 constitute one storage array, and the storage cells located between the third word line contact structure SC3 and the fourth word line contact structure SC4 constitute another storage array; alternatively, it can be considered that the storage cells located between the first word line contact structure SC1 and the second word line contact structure SC2, and the storage cells located between the third word line contact structure SC3 and the fourth word line contact structure SC4, together constitute one storage array. Further details regarding... Figure 2 The description of the illustrated embodiment takes the latter as an example, and the entire array of memory cells located between the first word line contact structure SC1 and the second word line contact structure SC2 is referred to as the first memory subarray, and the entire array of memory cells located between the third word line contact structure SC3 and the fourth word line contact structure SC4 is referred to as the second memory subarray.

[0042] according to Figure 2It can be seen that the connection relationship between the word lines and the contact structures of adjacent word lines in the second storage subarray is the same as that between the first storage subarray and the contact structures of adjacent word lines. The status of the second storage subarray is completely equivalent to that of the first storage subarray, and there is no interaction between them. The first ends of all word lines in the second storage subarray can be interconnected and connected to the first word line contact structure SC1, and the second ends can be interconnected and connected to the second word line contact structure SC2.

[0043] Since the three word lines of each of the first and second storage subarrays are activated simultaneously, but the word lines in the first and second storage subarrays are not activated simultaneously, the local bit lines of the first storage subarray itself cannot be connected to the same shared bit line CBL. They can only be connected to the same shared bit line CBL with the local bit lines of the second storage subarray. For example, the first storage cell of the first storage row in the first storage subarray and the first storage cell of the first storage row in the second storage subarray are simultaneously connected to the first shared bit line CBL1. For example, the first storage cell of the second storage row in the first storage subarray and the first storage cell of the second storage row in the second storage subarray are simultaneously connected to the second shared bit line CBL2. For example, the first storage cell of the third storage row in the first storage subarray and the first storage cell of the third storage row in the second storage subarray are simultaneously connected to the third shared bit line CBL3.

[0044] In some embodiments, the shared bit line CBL can be connected to a bit line amplifier, which is used to sense and amplify the voltage difference between the shared bit line CBL and the reference shared bit line.

[0045] In addition, Figure 2 In the illustrated embodiment, the storage units located at the outermost edge of the storage array are functional storage units that are capable of storing data information; while... Figure 3 and Figure 4 In the illustrated embodiment, the outermost memory cells of the memory array are dummy cells or virtual access transistors. This is to avoid crosstalk between local bit lines in the second horizontal direction Y, which would otherwise occur due to the local bit lines being located on the outermost edge of the memory array, thus ensuring data transmission stability. Simultaneously, bit lines are relatively fragile, and placing dummy cells or virtual access transistors on the outermost edge helps prevent damage to the local bit lines. The size of a dummy cell is generally the same as that of a normal memory cell, the difference being that a dummy cell does not have data storage functionality. Similarly, a dummy transistor is generally the same size as a conventional access transistor, the difference being that a dummy transistor does not have data transmission functionality; word lines are used to control the conduction and cutoff of conventional access transistors.

[0046] In some embodiments, reference Figure 3and Figure 4 Each memory array contains multiple memory rows. All memory cells in the same memory row share the same word line. Every two memory cells arranged along the second horizontal direction Y share a local bit line LBL. The second horizontal direction Y is perpendicular to the first horizontal direction X (i.e., the extension direction of the word line). The word line contact structure also includes a third word line contact structure SC3 and a fourth word line contact structure SC4. The first word line contact structure SC1, the second word line contact structure SC2, the third word line contact structure SC3, and the fourth word line contact structure SC4 correspond to the same memory array. The third word line contact structure SC3 is used to connect to the third word line driver SWD3, and the fourth word line contact structure SC4 is used to connect to the fourth word line driver SWD4. The first word line contact structure SC1 and the third word line contact structure SC3 are located on the same side of the corresponding memory array. The second word line contact structure SC2 and the fourth word line contact structure SC4 are located on the same side of the corresponding memory array. The third word line contact structure SC3 and the fourth word line contact structure SC4 are arranged opposite to each other. Adjacent word lines corresponding to the same local bit line are connected to different word line contact structures on the same side.

[0047] In this configuration, both the first word line contact structure SC1 and the third word line contact structure SC3 extend along the second horizontal direction Y, and are arranged along this direction. Each pair of memory cells arranged along the second horizontal direction Y refers to two non-repeating memory cells. Furthermore, memory rows located on opposite sides of the memory array along the second horizontal direction Y can be defined as edge memory rows. Edge memory rows are normally functioning memory rows, but memory cells in these edge memory rows do not share the local bit line LBL with any normally functioning memory cell.

[0048] In some embodiments, the first character line contact structure SC1 and the second character line contact structure SC2 are directly opposite each other, and the third character line contact structure SC3 and the fourth character line contact structure SC4 are directly opposite each other. "Directly opposite" means that they are aligned in the second horizontal direction without misalignment. In other embodiments, the first character line contact structure SC1 and the second character line contact structure SC2 are misaligned in the second horizontal direction Y, and the third character line contact structure SC3 and the fourth character line contact structure SC4 are also misaligned in the second horizontal direction Y.

[0049] because Figure 3 and Figure 4In the illustrated embodiment, every two memory cells arranged along the second horizontal direction Y share a local bit line, and two memory rows arranged along the second horizontal direction Y share the same set of local bit lines. Therefore, two adjacent word lines corresponding to the same set of local bit lines cannot be connected to the same word line contact structure; they can only be connected to different word line contact structures on the same side. Otherwise, the two memory cells sharing the local bit line will read data simultaneously, leading to data errors. Note that the requirement that two adjacent word lines can only be connected to different word line contact structures on the same side does not mean that each word line can only be connected to one word line contact structure; it only requires ensuring that the word line contact structures connected to the two words are different.

[0050] In some embodiments, among adjacent word lines WL corresponding to the same set of local bit lines LBL, one is connected to a word line contact structure at only one end, or in other words, one is connected to only one word line contact structure, and the other is connected to two opposite word line contact structures at both ends. For example, refer to... Figure 3 The storage array includes a third word line WL3 and a fourth word line WL4. The third word line WL3 and the fourth word line WL4 correspond to the same set of local bit lines LBL. The first end T1 of the third word line WL3 is connected to the third word line contact structure SC3, and the second end T2 is connected to the fourth word line contact structure SC4. The fourth word line WL4 is only connected to the second word line contact structure SC at its second end, and the first end is left unconnected.

[0051] It should be noted that, according to Figure 3 As shown in the plan view, the reason why the first end of the fourth character line WL4 is unused is that it is surrounded by the character line connected to the contact structure of the third character line, preventing the first end of the fourth character line WL4 from connecting to the first end of the second character line WL2 in the plane. However, in other embodiments, the first end of the fourth character line WL4 can be connected to the first end of the second character line WL2 via a trace in another plane; similarly, the second end of the fifth character line WL5 can be connected to the second end of the third character line WL3 via a trace in another plane, i.e., connected via a jumper.

[0052] Understandable Figure 2 , Figure 3 as well as Figure 4 The diagram illustrates a planar layout. The storage structure used to store data in a memory can be either a single-layer structure or a multi-layer structure stacked vertically. Each layer can have, for example, a planar layout. Figure 2 , Figure 3 as well as Figure 4 The characteristics are as shown. In some embodiments, the memory includes a vertically stacked multi-layer memory array, where different vertically stacked memory cells share a local bit line (BLB) extending along a vertical direction Z, which is perpendicular to a first horizontal direction X (i.e., the extension direction of the word line) and a second horizontal direction Y.

[0053] It should be noted that the word line contact structures corresponding to the different layers of memory arrays subMat stacked in the vertical direction Z need to be at least partially misaligned in the vertical direction Z, so that the word line contact structures of different layers can be connected to the outside through different contact holes extending along the vertical direction Z, and thus connect to different word line drivers.

[0054] In some embodiments, the memory array has edge word lines, or rather, the outermost word line located within the same memory array is defined as the edge word line, and each memory array has two opposing edge word lines. Each edge word line corresponds to a different local bit line as its adjacent word line, and each edge word line connects to at least the same word line contact structure as its adjacent word line. Figure 3 For example, the first word line WL1 is an edge word line, and the word line adjacent to it is the second word line WL2. Since the second word line WL2 is connected to both the first word line contact structure SC1 and the second word line contact structure SC2, and blocks the path for the first word line WL1 to connect with other word lines in the plane, if the first word line WL1 is not connected to at least the same word line contact structure as the second word line WL2 (i.e., not simultaneously activated or deactivated), then the first word line WL1 needs to be connected to other word lines or other word line contact structures via jumpers. This will greatly increase the complexity of the wiring. Furthermore, in multi-layered storage structures, jumpers in non-edge layers of the storage array are extremely difficult to connect. Therefore, setting the edge word line to be connected to at least the same word line contact structure as the adjacent word line helps reduce the complexity of the wiring.

[0055] In some embodiments, for example Figure 3 In the illustrated embodiment, the edge character line is connected to only one character line contact structure. Specifically, the second character line WL2 is connected to both the first character line contact structure SC1 and the second character line contact structure, while the first character line WL1 is connected only to the first character line contact structure SC1. Figure 4 In the illustrated embodiment, the edge character line and the adjacent character line are simultaneously connected to two opposite character line contact structures. Specifically, the first character line WL1 and the second character line WL2 are both simultaneously connected to the first character line contact structure SC1 and the second character line contact structure SC2.

[0056] In some embodiments, for example Figure 3 and Figure 4 In the illustrated embodiment, since every two storage lines share the same set of local bit lines (BLBs), it is inevitable that three consecutive word lines cannot be connected to the same word line contact structure. In other words, among the multiple word lines connected to the same word line contact structure, at least one word line is not adjacent to other word lines in the second horizontal direction.

[0057] by Figure 2 , Figure 3 as well as Figure 4As an example, the embodiments of this application are analyzed relative to... Figure 1 The improvement in the illustrated embodiment is that, since each word line is driven by two word line drivers simultaneously, the degree of driving of the word line is higher, allowing for a longer length of each word line and a greater number of memory cells corresponding to each word line. Experimental calculations show that the number of memory cells in a memory row can increase from the original N to 1.6N. Since the number of memory rows in the memory array becomes 6 rows, each memory array can fully utilize 2 word line drivers. Therefore, the ratio of the number of memory cells in the memory array to the number of fully utilized word line drivers / the number of word line contact structures is 6 × 1.6N / 2 = 4.8N, which is 1.2 times higher than the original ratio of 4N.

[0058] The area of ​​the word line contact structure corresponding to the memory array depends only on the layer number of the memory array. Figure 2 , Figure 3 as well as Figure 4 The number of storage array layers in the illustrated embodiment is compared to Figure 1 Without any changes, the area of ​​the word line contact structure corresponding to each layer of the memory array remains unchanged. Assuming the area of ​​each word line contact structure is 1, the ratio of the number of memory cells in the memory array to the area of ​​the corresponding word line contact structure is 4.8N. This effectively reduces the area proportion of the word line contact structure in the entire memory, thereby improving memory efficiency. Simultaneously, since the projected area of ​​a memory array of the same capacity in the vertical direction Z is a fixed value, reducing the area proportion of the word line contact structure is equivalent to reducing the sum of the area of ​​the improved unit capacity memory array and the area of ​​the corresponding word line contact structure. This helps to increase the number of wafers that can be cut from each wafer.

[0059] Furthermore, due to the long activation time required for word lines, calculations show that the improved memory, compared to... Figure 1 The illustrated embodiment reduces the time required to boost the word line voltage to 90% of the target voltage by 1.98 ns. In fact, in Figures 2 to 4 In the illustrated embodiment, each word line in the memory array is driven not only by word line drivers connected to adjacent word line contact structures, but also by word line drivers connected to more distant word line contact structures, thereby making the degree of driving of word lines in different memory arrays in the first horizontal direction X more uniform and consistent.

[0060] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A memory, characterized in that, include: A storage array comprising multiple word lines; The word line contact structure includes a first word line contact structure and a second word line contact structure located on opposite sides of the memory array. The first word line contact structure is used to connect to a first word line driver, and the second word line contact structure is used to connect to a second word line driver. Each word line in the memory array is driven by both the first word line driver and the second word line driver.

2. The memory according to claim 1, characterized in that, Each of the word lines has a first end and a second end, and the first end of at least one word line is directly connected to the first word line contact structure, and the second end is directly connected to the second word line contact structure.

3. The memory according to claim 2, characterized in that, The at least one word line comprises two word lines connected end to end, and the two word lines connected end to end form a closed loop surrounding the storage cell.

4. The memory according to claim 1, characterized in that, Each of the memory arrays comprises multiple memory rows, all memory cells in the same memory row share the same word line, adjacent memory rows in the same memory array are connected to different local bit lines, and at least two adjacent word lines are simultaneously connected to the first word line contact structure and the second word line contact structure.

5. The memory according to claim 4, characterized in that, The character lines extend along a first horizontal direction, and all character lines connected to the first character line contact structure and the second character line contact structure are continuously arranged in a second horizontal direction, which is perpendicular to the first horizontal direction and the vertical direction.

6. The memory according to claim 1, characterized in that, Each of the memory arrays comprises multiple memory rows, all memory cells in the same memory row share the same word line, and every two memory cells arranged along a second horizontal direction share a local bit line, the second horizontal direction being perpendicular to the extension direction of the word line; The word line contact structure further includes a third word line contact structure and a fourth word line contact structure. The first word line contact structure, the second word line contact structure, the third word line contact structure, and the fourth word line contact structure correspond to the same memory array. The third word line contact structure is used to connect to a third word line driver, and the fourth word line contact structure is used to connect to a fourth word line driver. The first word line contact structure and the third word line contact structure are located on the same side of the corresponding memory array, and the second word line contact structure and the fourth word line contact structure are located on the same side of the corresponding memory array. The third word line contact structure and the fourth word line contact structure are arranged opposite to each other, and adjacent word lines corresponding to the same local bit line are connected to different word line contact structures on the same side.

7. The memory according to claim 4 or 6, characterized in that, The memory comprises multiple layers of the memory array stacked vertically, with different stacked memory cells sharing a local bit line extending in a vertical direction perpendicular to the extension direction of the word line.

8. The memory according to claim 6, characterized in that, In adjacent word lines corresponding to the same group of local bit lines, one is connected to the word line contact structure at only one end, while the other is connected to two opposite word line contact structures at both ends.

9. The memory according to claim 6, characterized in that, The storage array has edge word lines, each edge word line corresponding to a different local bit line from its adjacent word lines, and each edge word line and its adjacent word line are connected to at least the same word line contact structure.

10. The memory according to claim 9, characterized in that, The edge character line and the adjacent character line are simultaneously connected to the two opposite character line contact structures.

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