Flexible design method of refractive index constraint in vertical cavity surface emitting laser based on overgrowth

Abstract

The invention relates to a flexible design method of refractive index constraint in an overgrowth-based vertical cavity surface emitting laser. A vertical cavity surface emitting laser (VCSEL) has a body including a vertical stack of semiconductor layers one above the other, including a current confinement region including a region of low resistance to current flow defined by a region of high resistance to current flow, and a first epitaxial sub-layer disposed proximate to the current confinement region, comprising protrusions or depressions defines a main cavity, and the remainder of the first epitaxial sub-layer defines an outer cavity; wherein the protrusions or recesses are defined by a physical step h predetermined according to the following formula: q [lambda] 0-m [lambda] 1 = n0h, where [lambda] 0 is the resonant wavelength of light in the main cavity, [lambda] 1 is the resonant wavelength of light in the outer cavity, q is a positive half integer, n0 is the effective refractive index in the main cavity, and m is a constant.

Description

Technical Field

[0001] This disclosure describes a vertical-cavity surface-emitting laser (VCSEL) with customizable refractive index constraints. Background Technology

[0002] To date, VCSELs with oxide apertures have provided guiding waveguides with an effective refractive index contrast of approximately 1–2%, thereby effectively confining optical modes. In prior art VCSELs, the oxide aperture is used to define both current confinement and refractive index confinement or optical confinement. When single-mode behavior is required, the oxide aperture needs to be reduced to below 4 μm, which is challenging to achieve reproducibly.

[0003] Additional mode selection elements on top of the VCSEL device can be used to provide mode selectivity. In one example, a small metal aperture can be introduced on top of the VCSEL device to filter out unwanted higher-order modes. (See Ueki et al., “Single-Transverse-Mode 3.4-mW Emission of Oxide-Confined 780-nm VCSELs,” IEEE Photonics Technology Letters, Vol. 11, No. 12, pp. 1539-1541, 1999). In another example, the “mode filtering” method can achieve surface relief on the top surface of the VCSEL device within the emission region. A VCSEL with a single-mode power up to 6.5mW has been reported using this technique. (See Haglund et al., “High-Power SingleTransverse and Polarization Mode VCSEL for Silicon Photonics Integration,” Vol. 27, No. 13, Optics Express 18892, 2019). Another example utilizes impurity-induced disorder in the top distributed Bragg reflector (DBR) mirror to reduce reflectivity, thereby suppressing higher-order modes. This results in a VCSEL emitting approximately 10 mW of single-mode power (see Su et al., “High-power single-mode vertical-cavity surface-emitting lasers using strain-controlled disorder-defined apertures,” Appl. Phys. Lett. 119, 241101, 2021). All these methods rely on the optical losses that introduce higher-order modes.

[0004] Another example is customizing mode shapes by designing refractive index confinement, for instance, by etching photonic crystal-like structures in epitaxial layers. (See Sirani et al., "Mode Control in Photonic Crystal Vertical-Cavity Surface-Emitting Lasers and Coherent Arrays," IEEE Journal of Selected Topics in Quantum Electronics, Vol. 15, No. 3, pp. 909-917, 2009). The methods discussed so far use one or more current-confined layers, which typically also result in optical confinement by introducing an increase in refractive index into the VCSEL aperture. The magnitude of the refractive index step introduced in such methods usually has some inherent technical limitations.

[0005] Modal control in VCSELs is crucial for many applications. In some cases, single-mode or few-mode operation is beneficial, and sometimes even necessary. This is the case, for example, in optical communication, where the presence of many optical modes, due to the increased linewidth, reduces relative noise or increases optical dispersion. In other cases, such as when the VCSEL is used as a projection light source, for example, in sensing applications, higher-order mode operation is advantageous for achieving a uniform energy distribution across the emission angle. In both cases, limiting the degrees of freedom of the optical modes can be advantageous for obtaining the desired performance.

[0006] In conventional oxide aperture VCSELs, the oxide aperture defines both the current-constrained and refractive-index-constrained regions. While the process is simple, this method has limitations: for example, it cannot define very small mode volumes, such as to facilitate single-mode operation, or variations in oxide depth can affect the mode shape and yield on the wafer. Furthermore, the magnitude of the refractive index contrast between the emitting region and its surrounding environment is primarily determined by the difference in refractive index between the oxidized and unoxidized oxide apertures formed within a single AlGaAs layer, a commonly used material for fabricating oxide aperture VCSELs.

[0007] Some methods rely on defining refractive index constraints by modifying the structure within the resonant cavity of a VCSEL. In some cases, structuring can constrain both the refractive index and current, for example, by achieving different thicknesses and / or etching tunnel junctions or barrier layers. Refractive index constraints can be used interchangeably with modal constraints, optical constraints, or light constraints, as they are understood as the guided propagation of electromagnetic waves through a confined region. Due to its dependence on various factors (material, temperature, carrier), refractive index constraints often face limitations, making it difficult to maintain fine variations in a controllable manner.

[0008] Therefore, the desired outcome is to provide VCSELs with refractive index constraints that are not so restricted and are associated with a modifiable physical structure. Summary of the Invention

[0009] This paper discloses VCSELs fabricated using epitaxial growth techniques such as metal-organic chemical vapor deposition (MOCVD). The achievement of overgrowth means that the fully epitaxial structure of the VCSEL is fabricated in two steps. In the first step of growth, the final epitaxial layer is patterned and partially etched away to define the current-constrained region that defines the VCSEL aperture. Then, the VCSEL structure is completed through a second epitaxial growth (overgrowth), which adds a second epitaxial layer and an upper DBR mirror layer on top of the patterned structure.

[0010] Between two epitaxial growth processes, the first epitaxial layer is patterned to create protrusions or depressions that define refractive index constraints. This patterning defines the characteristics of the emission region of the VCSEL. This feature, identified by height h, can be obtained via a photolithography process involving masking the epitaxial layer with a suitable mask (e.g., photoresist), exposing it, and developing a portion of it. The exposed area is then etched to a total depth h using standard wet or dry etching techniques. The remaining mask is then removed, the surface is cleaned, and it is prepared for subsequent epitaxial growth processes (overgrowth).

[0011] According to a non-limiting embodiment or aspect, a vertical-cavity surface-emitting laser (VCSEL) is provided, comprising: a body comprising a vertical stack of semiconductor layers one on top of another, the stack of semiconductor layers comprising: a current-constrained region including a region with low resistance to current flow defined by a region with high resistance to current flow, such that vertical current flow in the stack of semiconductor layers is guided through the region with high resistance to current flow of the current-constrained region through the region with low resistance to current flow of the current-constrained region; and a first epitaxial sublayer disposed adjacent to the current-constrained region, the first epitaxial sublayer comprising a protrusion or recess disposed adjacent to the region with low resistance to current flow of the current-constrained region, the protrusion or recess defining a main cavity, and the remainder of the first epitaxial sublayer defining an outer cavity; the protrusion or recess being defined by a physical step h predetermined according to the equation: qλ0-mλ1=n0h, where λ0 is the resonant wavelength of light in the main cavity, λ1 is the resonant wavelength of light in the outer cavity, q is a half-integer positive number, n0 is the effective refractive index in the main cavity, and m is a constant.

[0012] In a non-limiting embodiment or aspect, the stack of semiconductor layers sequentially includes: a first distributed Bragg reflector (DBR) mirror layer; a cavity layer including an active region; a first epitaxial sublayer and the current confinement region; and a second DBR mirror layer. In a non-limiting embodiment or aspect, the stack of semiconductor layers further includes: a substrate layer beneath the stack of semiconductor layers; a first contact located on the side of the stack of semiconductor layers opposite to the substrate layer; and a second contact located on the side of the substrate layer opposite to the stack of semiconductor layers, or on one side of the body, or on the side of the stack of semiconductor layers opposite to the substrate layer, wherein the first contact is electrically contacted only on the side of the stack of semiconductor layers opposite to the substrate layer, and the second contact is electrically contacted only on the side of the substrate layer opposite to the stack of semiconductor layers.

[0013] In a non-limiting embodiment or aspect, the region of the current-constrained region with high resistance to current flow surrounds the region of the current-constrained region with low resistance to current flow. In a non-limiting embodiment or aspect, the protrusions or recesses of the first epitaxial sublayer are positioned aligned with the region of the current-constrained region with low resistance to current flow. In a non-limiting embodiment or aspect, the region of the current-constrained region with low resistance to current flow is circular. In a non-limiting embodiment or aspect, the protrusions or recesses of the first epitaxial sublayer are coaxial with the circular current-constrained region.

[0014] In a non-limiting embodiment or aspect, the protrusion includes one or more tunnel knots.

[0015] In a non-limiting embodiment or aspect, the recess includes one or more etched areas.

[0016] In a non-limiting embodiment or aspect, the current-constrained region includes one or more oxidized or implanted semiconductor layers.

[0017] In non-limiting embodiments or aspects, m is selected from a set of positive half-integer values.

[0018] In non-limiting embodiments or aspects, λ0 is in the range of about 680 to 2600 nm.

[0019] In non-limiting embodiments or aspects, h is selected in the range of -500 to 500 nm.

[0020] In a non-limiting embodiment or aspect, the first epitaxial sublayer includes a recess, and h is a negative value.

[0021] In a non-limiting embodiment or aspect, the VCSEL operates in a first guided mode defined by a refractive index contrast Δn < 0, where Δn is an effective refractive index constraint given by: Δn / n0 = (λ1 - λ0) / λ0. In a non-limiting embodiment or aspect, h is negative and λ1 < λ0. In a non-limiting embodiment or aspect, the VCSEL also includes a portion supporting an anti-guided mode with a refractive index contrast Δn > 0.

[0022] In a non-limiting embodiment or aspect, the VCSEL further includes a second epitaxial sublayer adjacent to the first epitaxial sublayer. In a non-limiting embodiment or aspect, the stack of semiconductor layers further includes: a substrate layer beneath the stack of semiconductor layers; a first contact located on the side of the stack of semiconductor layers opposite to the substrate layer; and a second contact located on the side of the substrate layer opposite to the stack of semiconductor layers, or on one side of the body, or on the side of the stack of semiconductor layers opposite to the substrate layer, wherein the first contact is electrically contacted only on the side of the stack of semiconductor layers opposite to the substrate layer, and the second contact is electrically contacted only on the side of the substrate layer opposite to the stack of semiconductor layers.

[0023] In a non-limiting embodiment or aspect, for the VCSEL: when the first epitaxial sublayer includes protrusions, the second epitaxial sublayer also includes protrusions aligned with the protrusions of the first epitaxial sublayer; and the protrusions of the second epitaxial sublayer protrude into the space surrounded by the region of the current-constrained region that has high resistance to current flow.

[0024] Further embodiments or aspects are set forth in the following numbered clauses:

[0025] Clause 1: A vertical-cavity surface-emitting laser (VCSEL) comprising: a body comprising a vertical stack of semiconductor layers, one on top of the other, wherein the stack of semiconductor layers includes: a current-constrained region comprising a region with low resistance to current flow defined by a region with high resistance to current flow, such that vertical current flow in the stack of semiconductor layers is guided by the region with high resistance to current flow of the current-constrained region through the region with low resistance to current flow of the current-constrained region; and a first epitaxial sublayer disposed adjacent to the current-constrained region, the first epitaxial sublayer including a protrusion or recess disposed adjacent to the region with low resistance to current flow of the current-constrained region, wherein the protrusion or recess defines a main cavity, and the remainder of the first epitaxial sublayer defines an outer cavity; wherein the protrusion or recess is defined by a physical step h predetermined according to the equation: qλ0 - mλ1 = n0h, where λ0 is the resonant wavelength of light in the main cavity, λ1 is the resonant wavelength of light in the outer cavity, q is a half-integer positive number, n0 is the effective refractive index in the main cavity, and m is a constant.

[0026] Clause 2: The VCSEL of Clause 1, wherein the stack of said semiconductor layers comprises, in sequence: a first distributed Bragg reflector (DBR) mirror layer; a cavity layer including an active region; a first epitaxial sublayer and the current-constrained region; and a second DBR mirror layer.

[0027] Clause 3: A VCSEL of either Clause 1 or 2, wherein the stack of semiconductor layers further comprises: a substrate layer beneath the stack of semiconductor layers; a first contact located on the side of the stack of semiconductor layers opposite to the substrate layer; and a second contact located on the side of the substrate layer opposite to the stack of semiconductor layers, or on one side of the body, or on the side of the stack of semiconductor layers opposite to the substrate layer, wherein the first contact is electrically contacted only on the side of the stack of semiconductor layers opposite to the substrate layer, and the second contact is electrically contacted only on the side of the substrate layer opposite to the stack of semiconductor layers.

[0028] Clause 4: Any one of Clauses 1 to 3, wherein the region of the current-constrained region with high resistance to current flow surrounds the region of the current-constrained region with low resistance to current flow.

[0029] Clause 5: VCSEL of any one of Clauses 1 to 4, wherein the protrusions or recesses of the first epitaxial sublayer are positioned in alignment with the region of the current-constrained region that has low resistance to current flow.

[0030] Clause 6: Any one of Clauses 1 to 5, wherein the region of the current-constrained area with low resistance to current flow is circular.

[0031] Clause 7: VCSEL of any one of Clauses 1 to 6, wherein the protrusions or depressions of the first epitaxial sublayer are coaxial with the circular current-constrained region.

[0032] Clause 8: Any one of Clauses 1 to 7, wherein the protrusion comprises one or more tunnel knots.

[0033] Clause 9: VCSEL of any one of Clauses 1 to 8, wherein the recess includes one or more etched areas.

[0034] Clause 10: A VCSEL of any one of Clauses 1 to 9, wherein the current-constrained region comprises one or more oxidized or implanted semiconductor layers.

[0035] Clause 11: A VCSEL of any one of Clauses 1 to 10, where m is selected from a set of positive half-integer values.

[0036] Clause 12: VCSEL of any one of Clauses 1 to 11, wherein λ0 is in the range of about 680 to 2600 nm.

[0037] Clause 13: Any one of Clauses 1 to 12, wherein h is selected in the range of -500 to 500 nm.

[0038] Clause 14: A VCSEL of any one of Clauses 1 to 13, wherein the first epitaxial sublayer includes a recess and h is a negative value.

[0039] Article 15: VCSEL of any one of Clauses 1 to 14, wherein the VCSEL operates in a first guided mode defined by the refractive index contrast Δn < 0, where Δn is an effective refractive index constraint given by the following formula: Δn / n0 = (λ1 - λ0) / λ0.

[0040] Article 16: Any one of Articles 1 to 15, where h is negative and λ1 < λ0.

[0041] Article 17: Any one of Clauses 1 to 16, wherein the VCSEL further includes a portion supporting an anti-conductive mode with a refractive index contrast Δn > 0.

[0042] Clause 18: Any VCSEL of any one of Clauses 1 to 17 further includes a second epitaxial sublayer adjacent to the first epitaxial sublayer.

[0043] Clause 19: A VCSEL of any one of Clauses 1 to 18, wherein the stack of semiconductor layers further comprises: a substrate layer beneath the stack of semiconductor layers; a first contact located on the side of the stack of semiconductor layers opposite to the substrate layer; and a second contact located on the side of the substrate layer opposite to the stack of semiconductor layers, or on one side of the body, or on the side of the stack of semiconductor layers opposite to the substrate layer, wherein the first contact is electrically contacted only on the side of the stack of semiconductor layers opposite to the substrate layer, and the second contact is electrically contacted only on the side of the substrate layer opposite to the stack of semiconductor layers.

[0044] Article 20: VCSEL of any one of Clauses 1 to 19, wherein: when the first epitaxial sublayer includes a protrusion, the second epitaxial sublayer also includes a protrusion aligned with the protrusion of the first epitaxial sublayer; and the protrusion of the second epitaxial sublayer protrudes into the space surrounded by the region of the current-constrained region that has high resistance to current flow. Attached Figure Description

[0045] Figure 1 This is an enlarged schematic side view of an example VCSEL based on the principles of this disclosure, including a first epitaxial sublayer containing a tunnel junction and / or a current-constrained region and a second epitaxial sublayer above the current-constrained region.

[0046] Figure 2 yes Figure 1The example VCSEL shown is a schematic side view of the first epitaxial sublayer, the current-constrained region, and the second epitaxial sublayer.

[0047] Figure 3 This is an enlarged schematic side view of another example VCSEL based on the principles of this disclosure, including a first epitaxial sublayer containing a recess, a current-constrained region adjacent to the first epitaxial sublayer, and a second epitaxial sublayer above the current-constrained region.

[0048] Figure 4 yes Figure 3 The diagram shows an example of a VCSEL with a separate schematic of the first epitaxial sublayer, the current-constrained region, and the second epitaxial sublayer.

[0049] Figure 5 This is an enlarged schematic side view of an example VCSEL based on the principles of this disclosure, including a first epitaxial sublayer containing a tunnel junction having a height h, a current-constrained region adjacent to the first epitaxial sublayer, and a second epitaxial sublayer above the current-constrained region.

[0050] Figure 6 This is an enlarged schematic side view of an example VCSEL based on the principles of this disclosure, including a first epitaxial sublayer containing a tunnel junction having a height h, a current-constrained region adjacent to the first epitaxial sublayer, and a second epitaxial sublayer above the current-constrained region.

[0051] Figure 7 This is an enlarged schematic side view of another example VCSEL based on the principles of this disclosure, including a first epitaxial sublayer containing a tunnel junction and a current-confined region adjacent to the first epitaxial sublayer, but excluding... Figure 1 The second epitaxial sublayer is shown in the diagram.

[0052] Figure 8 This is an enlarged schematic side view of another example VCSEL based on the principles of this disclosure, including a recessed first epitaxial sublayer and a current-containment region adjacent to the first epitaxial sublayer, but excluding... Figure 3 The second epitaxial sublayer is shown in the diagram.

[0053] Figure 9 This is an enlarged schematic side view of another example VCSEL based on the principles of this disclosure, including a first epitaxial sublayer containing a tunnel junction, a current-constrained region adjacent to the first epitaxial sublayer, and a second epitaxial sublayer containing a protrusion or bump above the current-constrained region.

[0054] Figure 10 This is an enlarged schematic side view of another example VCSEL based on the principles of this disclosure, including a first epitaxial sublayer containing a recess, a current-constrained region adjacent to the first epitaxial sublayer, and a second epitaxial sublayer with an optional recess above the recess containing the current-constrained region.

[0055] Figure 11A This is an enlarged schematic side view of an example VCSEL based on the principles of this disclosure, including a first epitaxial sublayer with a tunnel junction, wherein etching of the first sublayer realizes an optical guiding portion and an anti-guiding portion combined with a current-constrained region.

[0056] Figure 11B yes Figure 11A The example VCSEL shown is shown as a standalone top view.

[0057] Figure 11C yes Figure 11A The effective refractive index distribution of the example VCSEL shown is illustrated.

[0058] Figure 12A This is an enlarged schematic side view of an example VCSEL based on the principles of this disclosure, including a first epitaxial sublayer with a current-blocking layer, and illustrating the confinement region, wherein etching of the first sublayer realizes optical guiding and anti-guiding portions combined with the current-constrained portion.

[0059] Figure 12B yes Figure 12A The example VCSEL shown is shown as a standalone top view.

[0060] Figure 12C yes Figure 12A The effective refractive index distribution of the example VCSEL shown is illustrated. Detailed Implementation

[0061] Various non-limiting examples will now be described with reference to the accompanying drawings, wherein the same reference numerals correspond to the same or functionally equivalent elements.

[0062] For the purposes of the description below, terms such as “end,” “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “lateral,” and “longitudinal,” and their derivatives, should be used in relation to the orientation examples shown in the accompanying drawings. However, it is to be understood that various alternative variations and sequences of steps may be contemplated in the examples unless the opposite is explicitly specified. It should also be understood that the specific examples illustrated in the accompanying drawings and described in the following specification are merely exemplary examples or aspects of this disclosure. Therefore, the specific examples or aspects disclosed herein should not be construed as limiting.

[0063] refer to Figure 1 and Figure 2A non-limiting embodiment or example VCSEL according to the principles of this disclosure includes a body 2 comprising a vertically stacked 4 of semiconductor layers (e.g., but not limited to GaAs, AlGaAs, AlInGaAsP, InGaAs, InP, or InAlGaN layers) grown or deposited layer by layer, for example by chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). From bottom to top of the body 2, the stacked semiconductor layers 4 may include a substrate 6, a lower distributed Bragg reflector (DBR) mirror layer 8, a cavity layer 10 including an active region 12, a first epitaxial sublayer 14, a current confinement region 18 which may be part of or separate from the first epitaxial sublayer 14, a second epitaxial sublayer 16, and an upper DBR mirror layer 20. Continued growth of the upper DBR mirror layer 20 may form or define an optional capping layer as part of the upper DBR mirror layer 20.

[0064] The first epitaxial layer used in this paper is any layer grown on substrate 6 during the first growth process. Therefore, Figure 1 The first epitaxial layer comprises sublayers 8, 10, and 14. Similarly, the second epitaxial layer is any layer grown during the second growth process and includes sublayers 16 and 20. Figure 1 As shown, each sublayer in the first and second epitaxial layers is typically planar.

[0065] In this document, the terms "first," "lower," "second," and "upper," when used in conjunction with DBR mirror layers 8 and 20, are used for descriptive, illustrative, and clarity purposes only and should not be construed as restrictive. Furthermore, when used in conjunction with DBR mirror layers 8 and 20, the terms "lower" and "upper" are used only in connection with the orientation shown in the figures and should not be construed as restrictive. Additionally, in this document, for descriptive, illustrative, and clarity purposes only, one of the DBR mirror layers may be referred to as the first DBR mirror layer, and the other may be referred to as the second DBR mirror layer, and should not be construed as restrictive.

[0066] The first electrical contact 24 may be positioned to make electrical contact with the top side of the upper DBR mirror layer 20. In this example, the first electrical contact 24 may be annular, including an opening D for light generated by the operation of the VCSEL. However, this should not be construed as limiting, as it is conceivable that the first electrical contact 24 may be any suitable and / or desired shape or geometry that allows light generated by the operation of the VCSEL (discussed below) to exit from the top side of the upper DBR mirror layer 20.

[0067] In one example, the second electrical contact 25 can be positioned as a bottom-side electrical contact of the substrate layer 6 opposite to the lower DBR mirror layer 8. In another example, Figure 1 The second electrical contact 25, shown by a dashed line, may be located on one side of the body 2 and make electrical contact with the substrate 6. In this document, the terms “first” and “second” are used for descriptive, illustrative and clarity purposes only and should not be construed as restrictive.

[0068] In yet another example, the same Figure 1 As shown by dashed lines, the second electrical contact 25 may be located on the top side of the upper DBR mirror layer 20, for example, close to or adjacent to the first electrical contact 24. In this example, the second electrical contact 25 may be electrically isolated from the top side of the upper DBR mirror layer 20 by, for example, an oxide layer, and may be electrically connected to the substrate layer 6 via an electrical conductor (not specifically shown) arranged through the body 2 or on one side of the body 2.

[0069] Regardless of where the second electrical contact 25 can be arranged or positioned, the first electrical contact 24 makes electrical contact only with the top side of the capping layer 22, while the second electrical contact 25 makes electrical contact only with the substrate layer 6. An electrical bias voltage can be applied to the body 2 via the first electrical contact 24 and the second electrical contact 25. This electrical bias voltage may cause a current 22 ( Figure 1 (Indicated by a dashed line) flows in the body 2 between the substrate 6 and the first electrical contact 24.

[0070] Details regarding the growth or fabrication of one or more of the substrate 6, the lower DBR mirror layer 8, the cavity layer 10 including the active region 12, the upper DBR mirror layer 20, and / or the first and second electrical contacts 24 and 25 are known in the art and will not be described further herein for simplicity. Furthermore, details regarding the growth or fabrication of one or more of the first epitaxial sublayer 14 and the second epitaxial sublayer 16 are known in the art, except as may be necessary for the purposes of this description, and will not be described further herein for simplicity.

[0071] For example, VCSELs can be fabricated using epitaxial growth techniques such as metal-organic chemical vapor deposition (MOCVD). The achievement of overgrowth means that the fully epitaxial structure of the VCSEL is fabricated in two steps. In the first step of growth, the first epitaxial sublayer 14 is patterned and etched away to define the current-constrained region that defines the VCSEL aperture. Then, the VCSEL structure is completed through a second epitaxial growth (overgrowth), which adds a second epitaxial sublayer 16 and an upper DBR mirror layer 20 on top of the patterned structure.

[0072] As described above, between the two epitaxial growth processes, the first epitaxial sublayer 14 is patterned to create protrusions or depressions 30 that define refractive index constraints. Thus, in some embodiments, the current-constrained region may be the same as the optically-constrained region, while in other embodiments, the current-constrained region is independent of the optical constraint. This patterning of the layer defines the characteristics of the emission region of the VCSEL. This feature, identified by height h, can be obtained by a photolithography process involving masking the first epitaxial sublayer 14 with a suitable mask (e.g., photoresist), exposing it, and developing a portion thereof. The exposed area is then etched to a total depth h using standard wet or dry etching techniques. The remaining mask is then removed, the surface is cleaned, and it is prepared for the subsequent growth of the second epitaxial layer 16.

[0073] As shown in the figure, the first epitaxial sublayer 14 includes or defines one or more bumps or protrusions 30 on its top surface 29, having the properties of a tunnel junction formed on the top surface 29 of the first epitaxial sublayer 14 by a photolithography process known in the art. Hereinafter, the terms "bump," "protrusion," and "tunnel junction" are used interchangeably in conjunction with reference to reference numeral 30. The tunnel junction 30 is conductive and is etched away except at the center of the structure, resulting in a height h for the tunnel junction 30. This protrusion 30 causes current confinement because the formation of the tunnel junction 30 between the first epitaxial sublayer 14 and the second epitaxial sublayer 16 creates a current-constrained region 18, which includes one or more blocking regions 18a, 18b that prevent current flow and a region 18c of width D in which current 22 can flow.

[0074] In different embodiments using the same fabrication technique, instead of etching around the aperture, the barrier layer (not shown) already present on the first epitaxial sublayer 14 is etched away before overgrowth to create the current confinement region 18 (see [link to documentation]). Figure 3 In both cases, the central portion of the structure is where current can flow, and stimulated emission leads to laser emission. As shown, the current-confined region 18 is planar and coincides with the first and second epitaxial sublayers.

[0075] In some embodiments, the barrier layer may include an oxide layer, a reverse-biased pn junction, an implantation region, etc. In some embodiments, such as oxide and ion implantation, the barrier layer may be created by subsequent processes. For example, see below. Figure 9 The discussion.

[0076] In this example, the current-confining region 18 may exist as part of (e.g., integrated with or integral with) the first epitaxial sublayer 14, or may be implemented, for example, over the first epitaxial sublayer 14 via an oxidation step. In examples where the current-confining region 18 and the first epitaxial sublayer 14 are provided by different layers, the first epitaxial sublayer 14 may include the current-confining region 18 (e.g., an oxide layer), such as... Figure 3 As shown in the image.

[0077] In some embodiments, the current-constrained region 18 includes a low-current-flow-resistance region 18c defined by regions 18a and 18b with high resistance to current flow, such that current flow in the body 2 is guided or constrained through the low-current-flow-resistance region 18c by the regions 18a and 18b with high resistance to current flow. In a non-limiting example, the regions 18a and 18b with high resistance to current flow surround the low-current-flow-resistance region 18c, such that current flow in the body 2 is guided through the regions 18a and 18b with high resistance to current flow through the low-current-flow-resistance region 18c.

[0078] In the example, the resistivity per unit area for regions 18a and 18b with high resistance to current flow is, for example, ohms-cm. 2 This is at least 10 times greater than the resistivity per unit area of ​​the region with low resistance to current flow. In the example, the region 18c with low resistance to current flow can have a resistivity of 10. -3 ohm-cm 2 Or even lower resistance, while regions 18a and 18b with high resistance to current flow can have 0.1 ohm-cm. 2 Or higher resistance. However, this should not be interpreted as limiting.

[0079] exist Figure 1 and Figure 2 In one specific, non-limiting example shown, the region 18c with low resistance to current flow may be circular, defined by the annular inner diameter of the regions 18a and 18b with high resistance to current flow. However, these shapes or geometries should not be construed as limiting, as other shapes or geometries may be contemplated for the regions with low and / or high resistance to current flow.

[0080] In this example, regions 18a and 18b with high resistance to current flow can be formed or defined, for example, by oxidation, implantation, or growth of such regions within the current-constrained region 18, which serves to define regions with high resistance to current flow. In this example, region 18c with low resistance to current flow is the unoxidized or unimplanted region of the current-constrained region 18.

[0081] Typically, the optical mode of laser emission is defined by refractive index constraints. These constraints are, in turn, defined by the etching depth h in layer 4, as described later. In many cases, the value of h is subject to certain physical or technical limitations, for example:

[0082] • The minimum thickness h that a conductive layer (such as a tunnel junction) can have (see...) Figure 1 Therefore, the minimum etching depth required is determined.

[0083] • Minimum thickness that the current blocking layer may need to have (see Figure 3 ).

[0084] • The minimum depth at which etching can be reliably or reproducibly performed (e.g., technical limitations).

[0085] In addition, although Figure 1 The obtained geometry facilitates light confinement, but... Figure 3 In these cases, no optical constraint (e.g., anti-guidance) is introduced. In all these cases, the number of refractive index constraints that can be introduced is limited. This disclosure provides a method to overcome this limitation by fully utilizing the characteristics of the physical mechanisms that lead to refractive index constraints.

[0086] See back Figure 1 In the example VCSEL shown, the first epitaxial sublayer 14 may be positioned or arranged close to the current-constrained region 18, which is positioned or arranged below the second epitaxial sublayer 16. In this example, the first epitaxial sublayer 14 may include or define one or more tunnel junctions or protrusions 30 on its top surface 29, the tunnel junctions or protrusions 30 being positioned close to and aligned with the region 18c of the current-constrained region 18 that has low resistance to current flow. Figure 1 As shown, the current confinement region 18 is shown as a junction between the first epitaxial sublayer 14 and the second epitaxial sublayer 16.

[0087] See now Figure 2 The tunnel junction 30 of the first epitaxial sublayer 14 may be circular and aligned or coaxially positioned with the circular region 18c of the current confinement region 18, which has low resistance to current flow. However, this should not be construed as limiting, as it is conceivable that the tunnel junction 30 of the first epitaxial sublayer 14 may have any suitable and / or desired shape or geometry (described in more detail below), and / or the circular region 18c of the current confinement region 18, which has low resistance to current flow, may have any suitable and / or desired shape or geometry, which may be the same as or different from the shape or geometry of the tunnel junction 30 of the first epitaxial sublayer 14.

[0088] See Figure 5 and Figure 6 In some examples, the patterning of the first epitaxial sublayer 14 can create two regions or cavities. Specifically, a primary region or cavity 62 and a secondary region or cavity 64. The primary region or cavity 62 is perpendicularly aligned with the tunnel junction 30 and (e.g., emits light 32 through width D). The secondary region or cavity 64 is perpendicularly aligned with a region of the non-perpendicularly aligned tunnel junction 30 of the first epitaxial sublayer 14 (i.e., the region surrounding the tunnel junction or protrusion 30). It should be appreciated that... Figure 5 and Figure 6 It shows the relationship with Figure 1Similar to VCSEL, but with additional details and protrusions of varying heights. For example, Figure 5 and Figure 6 Both demonstrate VCSELs with physical step h, but Figure 6 h ratio in Figure 5 The value of h is much larger.

[0089] In some embodiments, the current-confined region is adjacent to the first epitaxial sublayer and the second epitaxial sublayer above the current-confined region. It should be appreciated that in some embodiments, the current-confined region may be contained within the first and / or second epitaxial sublayer, or independent of the epitaxial sublayer.

[0090] The resonant wavelengths of light 32 in the primary region 62 and the secondary region 64 are different, and can be equal to λ0 and λ1, respectively. These wavelength differences define the effective refractive index constraint of the first epitaxial sublayer 14, which determines the optical modes. Specifically, the effective refractive index constraint (Δn) is given by the following equation:

[0091] Δn / n0=(λ1-λ0) / λ0 (Equation 1)

[0092] Where n0 is the effective refractive index in the main region 62. Δn determines the refractive index contrast and is correlated with the given shape or geometry of the first epitaxial sublayer 14 (e.g., Figure 1 The maximum size D of the light guide pattern in the middle defines the supported lateral optical modes for single-mode operation.

[0093] In other words, the higher Δn is, the smaller D must be to achieve single-mode operation. Therefore, the size of Δn determines the maximum size of D for single-mode operation. In some embodiments, λ1 is chosen such that the refractive index contrast ranges from approximately 0% to 50%.

[0094] λ0 > λ1 means the cavity is refractive index guided, while λ0 < λ1 means no guidance (anti-guidance). Efficient laser emission typically requires guiding behavior. Setting λ0 and λ1 makes refractive index-constrained designs possible.

[0095] See now Figure 1 , 5 From equations 6 and 7, we observe that qλ0 = n0L0, where q is a positive half-integer (q = 1 / 2, 1, 3 / 2, 2, etc.). The physical height L0 refers to the distance the light travels back and forth within the main cavity. Therefore, we choose the physical height L0 = qλ0 / n0 such that the VCSEL emits at an appropriate wavelength λ0. The external cavity resonant wavelength λ1 is determined by its physical height L1. We observe that for any positive value of the other half-integer m, mλ1 = n0L1.

[0096] Controlling refractive index contrast is crucial for some applications. For example, a small refractive index contrast can facilitate single-mode operation in VCSELs. The refractive index contrast is proportional to the difference in length between the two cavities. Due to the often-existing technical limitations on how small a physical step h = L1 - L0 can be practically fabricated, an alternative method is desired to determine λ1 based on the degree of freedom defining m, and thus the refractive index contrast. In fact, the step h can vary over a wide range of values, and the desired values ​​for λ0 and λ1 can still be obtained. The general formulation of this principle is given by the following equation:

[0097] qλ0-mλ1=n0h (Equation 2)

[0098] Where λ0 is set based on the desired emission wavelength, q determines the cavity height under λ0 and is typically subject to application-based constraints, while λ1 is set to achieve the desired refractive index contrast (according to Equation 1).

[0099] Based on Equations 1 and / or 2, it should be appreciated that q can be chosen to determine λ0. Similarly, m can be chosen to determine a practical and manufacturable value for h. For example, in some embodiments, λ0 is in the range of approximately 680–2600 nm.

[0100] See still Figure 5 and Figure 6 Each graph illustrates different ways to achieve the same result. If for different values ​​of m, Figure 5 h and Figure 6 If both h satisfy Equation 2, then the two devices have similar refractive index-constrained properties. This provides a solution for achieving single-mode emission in VCSELs in other otherwise impractical cases. For example, in the case of refractive index guidance (i.e., Δn < 0), the magnitude of Δn also sets the maximum size / diameter of the aperture (D) to have single-mode behavior.

[0101] In some embodiments, a very negative value of Δn means that a very low D value is required to achieve single-mode behavior, for example, a small aperture. Reducing h is the most straightforward way to achieve a smaller negative Δn. However, due to technological or process limitations, a small h is often not practically or reliably achievable. Fully utilizing... Figure 6 The alternative shown allows the same result to be achieved with a larger manufacturable value h.

[0102] In some embodiments, having a high h value may be the only way to achieve the desired refractive index contrast. For example, see Figure 3The device is fabricated by etching a layer within the emission region to create a recess 40 instead of a protrusion or bump. As described in more detail below, the current-blocking region is etched away to allow current to flow within the aperture. It is noteworthy that in this case, h < 0, because it represents a recess rather than a protrusion. Small etching can lead to anti-guiding behavior because λ1 > λ0, therefore Δn > 0, thus hindering effective laser emission from the device. However, assuming q = 1 / 2 and setting m = 1, we can still create a guiding refractive index distribution (Δn < 0, λ1 < λ0) by etching to a deeper depth, such that Equation 2 still gives a negative value for h (etching).

[0103] In some embodiments, having a high h value may be the only way to achieve the desired refractive index contrast. For example, refer to Figure 3 The device is fabricated by etching the first epitaxial sublayer 14 within the emission region, rather than by protrusions or bumps. As described in more detail below, the current-blocking region is etched away to allow current to flow within the aperture D. It is worth noting that in this case, h < 0, because it represents a depression rather than a protrusion. Small etching results in anti-guiding behavior because λ1 > λ0, and therefore Δn > 0, thus hindering effective laser emission from the device. However, assuming q = 1 / 2 and setting m = 1, we can still create a guiding refractive index distribution (Δn < 0, λ1 < λ0) by etching to a deeper depth, such that Equation 2 still gives a negative value for h (etching).

[0104] In some embodiments, h is selected in the range of about -500 to 500 nm. In some embodiments, h is selected in the range of about -300 to 300 nm. In some embodiments, h is selected in the range of about 100 to 300 nm. In some embodiments, h is selected in the range of about 200 to 300 nm.

[0105] exist Figure 1In this context, the refractive index contrast increases with the value of the height h of the protrusion or bump 30. In use, the electrical bias applied to the first electrical contact 24 and the second electrical contact 25 causes a current 22 to flow vertically or substantially vertically between the substrate layer 6 and the first electrical contact 24 within the body 2. This flow of current 22 in the body 2 is guided or constrained by regions 18a, 18b of the current-constrained region 18 that have high resistance to current flow, to flow through a region 18c that has low resistance to current flow. This current 22 also flows through the active region 12 of the cavity layer 10, in which, in response, the active region 12 of the cavity layer 10 emits light 32 (indicated by an ellipse in the body 2 and an arrow emanating from the top side of the upper DBR mirror layer 20). By leveraging the difference in refractive index between the primary region of the first epitaxial sublayer 14 aligned with the tunnel junction 30 and the secondary region of the first epitaxial sublayer 14 not aligned with the tunnel junction 30, the emitted light 32 is guided or constrained to flow through the region 18c of the current-constrained region 18 with low resistance to current flow, and exits from the top surface of the upper DBR reflector layer 20 above the protrusion or bump 30 and the region 18c of the current-constrained region 18 with low resistance to current flow.

[0106] Figure 2 The shape or geometry of the first epitaxial sublayer 14 shown is merely a non-limiting example of the shape or geometry that the first epitaxial sublayer 14 may have, which includes one or more protrusions or bumps, such as tunnel junctions 30. The shape or geometry of the first epitaxial sublayer 14 should not be construed as limiting, as it is conceivable that the first epitaxial sublayer 14 may have any suitable and / or desired shape or geometry that is considered desirable for VCSEL to emit light 32 with a specific shape, geometry, and / or mode required for a particular application.

[0107] See Figure 3 and Figure 4 And continue to see Figure 1 and Figure 2 With one exception, other non-limiting embodiments or example VCSELs based on the principles of this disclosure can be similar to Figure 1 and 2 The example VCSEL shown and described above. The exception is... Figure 3 and Figure 4 The first epitaxial sublayer 14 of the VCSEL shown may include one or more recesses or cavities 40 in the top surface 29 of the first epitaxial sublayer 14, rather than the top surface 29 of the first epitaxial sublayer 14 including one or more protrusions or bumps 30. Figure 1 and Figure 2 The operating principles of the VCSEL shown and described above are respectively applicable to Figure 3 and Figure 4The operating principle of VCSEL shown will not be further described in this article to avoid unnecessary redundancy.

[0108] Typically, using one or more recesses or cavities 40 on the top surface 29 of the first epitaxial sublayer 14, compared to using one or more protrusions or bumps 30, may affect the shape, geometry, and / or mode of light 32 emitted from the top side of the upper DBR mirror layer 20. In other words, for example, for Figure 1 and Figure 3 The VCSEL shown, due to in Figure 1 The top surface 29 of the first epitaxial sublayer 14 of the VCSEL shown contains one or more protrusions or bumps 30, while... Figure 3 The VCSEL shown has one or more recesses or cavities 40 in the top surface 29 of the first epitaxial sublayer 14, so the light 32 emitted from the top side of the upper DBR mirror layer 20 may have different shapes, geometries and / or modes (which can be used for different applications).

[0109] As described above, instead of etching around the aperture, a barrier layer (not shown) already present on the first epitaxial sublayer 14 is etched away before overgrowth to create a current-confining region 18. The current-confining region may include barrier layers 18a and 18b adjacent to one or more regions of the first epitaxial sublayer 14. In some embodiments, barrier layers 18a and 18b represent annular regions surrounding a circular recess 40. The etched portion forms the recess 40, which coincides with a region 18c with low resistance to current flow.

[0110] In some embodiments, the barrier layer may include an oxide layer, a reverse pn junction, an implantation region, or the like.

[0111] Figure 4 The shape or geometry of the first epitaxial sublayer 14 shown is merely a non-limiting example of the shape or geometry that the first epitaxial sublayer 14, including one or more recesses or cavities 40, may have. The shape or geometry of the first epitaxial sublayer 14 should not be construed as limiting, as it is conceivable that the first epitaxial sublayer 14 may have any suitable and / or desired shape or geometry that is considered desirable for VCSEL to emit light 32 having a shape, geometry, and / or mode required for a particular application.

[0112] refer to Figure 7 With exceptions, another non-limiting embodiment or example VCSEL based on the principles of this disclosure may be similar to Figure 1 The example VCSEL shown and described above. An exception may be included in... Figure 7 The VCSEL shown is omitted or missing Figure 1The second epitaxial sublayer 16 is shown in the figure.

[0113] Figure 7 The protrusions or bumps 30 of the first epitaxial sublayer 14 may have any shape or geometry considered suitable and / or desirable for emitting light 32 with a specific shape, geometry, and / or mode required for a particular application by the VCSEL. Non-limiting examples of such shapes or geometries may include, for example, Figure 2 The first epitaxial sublayer 14 shown has one or more protrusions or bumps 30. Therefore, Figure 7 The shape of the protrusions or bumps 30 shown should not be interpreted as restrictive.

[0114] refer to Figure 8 With exceptions, another non-limiting embodiment or example VCSEL based on the principles of this disclosure may be similar to Figure 3 The example VCSEL shown and described above. An exception may be included in... Figure 8 The VCSEL shown is omitted or missing Figure 3 The second epitaxial sublayer 16 is shown in the figure.

[0115] Figure 8 The recess 40 of the first epitaxial sublayer 14 can have any shape or geometry that is considered suitable and / or desirable for emitting light 32 with a specific shape, geometry, and / or mode required for a particular application by the VCSEL. Non-limiting examples of such shapes or geometries may include, for example, Figure 4 The first epitaxial sublayer 14 shown has one or more recesses or cavities 40. Therefore, Figure 8 The shape of the recess 40 shown should not be interpreted as restrictive.

[0116] refer to Figure 9 And continue to refer to Figure 1 and Figure 2 In one example, another non-limiting embodiment or example VCSEL according to the principles of this disclosure may include one or more protrusions or bumps 30 on the top surface 29 of the first epitaxial sublayer 14, protrusions or bumps 50 on the second epitaxial sublayer 16, and / or protrusions or bumps 54 (shown in dashed lines) on the upper DBR mirror layer 20. The one or more protrusions or bumps 30 on the top surface 29 of the first epitaxial sublayer 14 may cause one or more corresponding protrusions or bumps to be formed on some or all of the subsequent layers during the growth of subsequent layers on the first epitaxial sublayer 14 (for simplicity). Figure 1(Not shown in the image). In another example, the second epitaxial sublayer 16 and the upper DBR mirror layer 20 may have progressively smaller (relative to height h) protrusions or bumps above one or more protrusions or bumps 30 on the top surface 29 of the first epitaxial sublayer 14, including, in one example, a planar top side of the upper DBR mirror layer 20, etc. However, these examples should not be construed as limiting, as the top surface of each layer above the protrusions or bumps 30 on the top surface 29 of the first epitaxial sublayer 14 may have protrusions or bumps, or may be planar, such as... Figure 1 and Figure 2 As shown in the image.

[0117] In addition, such as Figure 9 As shown, due to the difference in doping types between the first epitaxial sublayer 14 and the second epitaxial sublayer 16, and the polarity bias applied during operation, the current confinement layer 18 may be a carrier depletion region. Carrier depletion in the current confinement region 18 prevents current from passing through. The bumps or protrusions 30 may comprise two layers doped at a higher level. The higher doping level enables conduction via Esaki interband tunneling. Tunneling through the bumps or protrusions 30 allows current to pass through.

[0118] refer to Figure 10 And continue to refer to Figure 3 and Figure 4 In one example, another non-limiting embodiment or example VCSEL according to the principles of this disclosure may include one or more recesses or cavities 40 on the top surface 29 of the first epitaxial sublayer 14, a recess 53 in the second epitaxial sublayer 16, and / or a recess 55 (shown in dashed lines) in the upper DBR mirror layer 20. The one or more recesses or cavities 40 on the top surface 29 of the first epitaxial sublayer 14 may result in the formation of one or more corresponding recesses or cavities 40 on some or all of the subsequent layers during the growth of subsequent layers on the first epitaxial sublayer 14 (for simplicity, ...). Figure 3 and Figure 4 (Not shown in the image). In another example, the second epitaxial sublayer 16 and the upper DBR mirror layer 20 may have gradually decreasing (relative to height H) recesses or cavities above one or more recesses or cavities 40 in the top surface 29 of the first epitaxial sublayer 14, including, in one example, a planar top side of the upper DBR mirror layer 20, etc. However, these examples should not be construed as limiting, as the top surface of each layer above one or more recesses or cavities 40 in the top surface 29 of the first epitaxial sublayer 14 may have a recess, or may be planar, such as... Figure 3 and Figure 4 As shown in the image.

[0119] Finally, in this document, light 32 is depicted and shown in the figures as emanating upward from the top side of the upper DBR mirror layer 20. However, in one example, it is conceivable that each non-limiting embodiment or example VCSEL shown and described herein can be modified such that the upper DBR layer 20 has a higher reflectivity than the lower DBR layer 8, such that light 32 can be reflected by the upper DBR film 20 through the stack of semiconductor layers 4 and emanate downward through the substrate layer 6 retained at the bottom of the stack of semiconductor layers 4.

[0120] In this example, the second electrical contact 25 can be positioned to make electrical contact with the bottom side of the substrate layer 6, and can be formed with an opening O′. Figure 1 , Figure 3 and Figures 7-10 The opening O shown in the figures, indicated by dashed lines, is similar to the opening O shown in these figures, used to allow light 32 to pass downward through the substrate layer 6 and exit from the bottom side of the substrate layer 6 through the opening O′. In one example, the first electrical contact 24 may be located on the top side of the semiconductor layer stack 4, for example, on the top side of the upper DBR mirror layer 20, and its opening O may be omitted.

[0121] In another example, such as Figure 1 , Figure 3 and Figures 7-10 As shown by dashed lines, the second electrical contact 25 can be located on one side of the body 2, making electrical contact with the substrate 6. In yet another example, as... Figure 1 , Figure 3 and Figures 7-10 As shown by dashed lines, the second electrical contact 25 may be close to or adjacent to the first electrical contact 24, located on the top side of the semiconductor layer stack 4, that is, on the top side of the upper DBR mirror layer 20. In this latter example, the second electrical contact 25 may be electrically isolated from the top side of the semiconductor layer stack 4 by, for example, an oxide layer, and may be electrically connected to the substrate layer 6 via an electrical conductor (not specifically shown) arranged through the body 2 or on one side of the body 2.

[0122] This disclosure also allows for the use of multi-step refractive index distributions to achieve guiding and anti-guiding (coupling) portions within a single overgrowth step. Figure 11A ~C and Figure 12A ~C provides an example of this implementation. By adjusting the etching depth according to Equation 2 and appropriately patterning the wafer, regions with guiding and anti-guiding (coupling) properties can be freely defined according to Equation 1.

[0123] exist Figure 11A ~C and Figure 12AIn the example of ~C, the etching depths of the guiding and anti-guiding sections are set to achieve a lower resonant wavelength (λ2 < λ0) in the middle section relative to the guiding section, but higher than the resonant wavelength in the outermost cavity (λ2 > λ1). By fully utilizing Equation 2, this design can be achieved with the most manufacturable etching depth. This method can enhance / control the coupling strength in multi-cavity / emitter VCSEL arrays. Figure 11A The middle combination tunnel structure and Figure 12A The combined barrier layer is shown in a schematic implementation with two cavities. The flexibility of this technology allows for [specific implementation details]. Figure 11C and Figure 12C When different refractive index distributions are shown, different etching depths are selected to pattern the VCSEL cavity during the same photolithography process steps.

[0124] refer to Figure 11A ~C and Figure 12A ~C, the “constraint” portion is defined in this paper as the outer part of the VCSEL, which acts as the “cladding” portion by confining light toward the inner region. The constrained region is usually also the region with the lowest refractive index.

[0125] In addition to the confinement region, this disclosure also provides any number of regions with different refractive index contrasts (i.e., different optical and current confinement properties) based on the VCSEL structure and method for confining current.

[0126] Figure 11A ~C and Figure 12A ~C Diagram illustrating tunnel junction 30 ( Figure 11A ) or barrier layer 18 ( Figure 12A An example of implementing a current-constrained coupled cavity. In Figure 11A The present invention provides a combination of current and optical constraints by etching the tunnel junction 30 and shaping the cavity forming the guiding portion 62 and the coupling portion 66. Figure 11A In this process, the present disclosure is fully utilized to define the etching depth h' and obtain Figure 11C The effective refractive index distribution is shown in the diagram. Specifically, after the first epitaxial growth, an etching depth h is first achieved by etching to a depth at least the same as that of the tunnel junction 30 to provide current confinement in the inner portion 64. Then, a second epitaxial etching depth h' is achieved. Since current flow must be confined only within the guide portion 62, the second etching depth h' must be at least as deep as the tunnel junction 30; however, achieving a lower refractive index contrast means that h' is less than h, and due to the incomplete etching of the tunnel junction 30, current cannot be confined within the guide portion 62. Using the method described in this disclosure, deeper etching can be achieved while simultaneously achieving a small refractive index difference relative to the guide portion 62 and appropriate current confinement.

[0127] exist Figure 12A The embodiment provides a combination of current constraint and optical constraint through etching that blocks current and shapes the cavity forming the guiding portion 62 and the coupling portion 66. In this embodiment, the current is blocked by a blocking layer 18 marked in black. Thus, current flow is made possible by etching the blocking layer 18. Similar to... Figure 11A First, a shallow etching depth h is achieved to introduce an external refractive index constraint 64. To enable current flow only in the guiding portion 62, we then need to etch at least as deep as the barrier layer 18, thus removing the barrier layer 18 and enabling current flow. Leveraging this disclosure, the epitaxial layer stack can then be designed such that a deeper etching depth h' achieves a very small effective refractive index difference between the guiding portion 62 and the coupling portion 66, while simultaneously achieving current constraint by removing the barrier layer 18. The final optical distribution is shown in… Figure 12C In the middle, the central portion corresponds to the coupling portion 66, which has a slightly lower effective refractive index than the guiding portion 62.

[0128] In both embodiments, the current can be constrained to flow within the guide portion 62. To achieve this, the tunnel junction 30 or the barrier layer 18 can be retained or etched away only in the regions where the current should flow. This sets a minimum technical requirement for an etching depth h equal to the thickness of the tunnel junction 30 or the barrier layer 18.

[0129] In the embodiments shown in Figures 11 and 12, and illustrated in Figure 11C and Figure 12C In this process, the same refractive index distribution can be obtained, but with different etching depths h, which can then be determined using Equation 2. Depending on the application requirements, the effective optical refractive index of the coupling portion 66 can be equal to, lower than, or higher than the effective optical refractive index of the guiding portion 62.

[0130] In some embodiments, the number of coupled emitters can be arbitrary, having a 2D arrangement. The same technique with different geometries can be used to achieve single-cavity or multi-cavity modal selection. In some embodiments, such as Figure 11C and Figure 12C The number of refractive index steps, as shown in the refractive index distribution, is not limited to three.

[0131] Although this disclosure has been described in detail for illustrative purposes based on examples that are currently considered to be the most practical and preferred, it should be understood that such details are for that purpose only, and that this disclosure is not limited to the disclosed examples, but rather is intended to cover modifications and equivalent arrangements within the spirit and scope of the appended claims. For example, it should be understood that this disclosure contemplates that, to the extent possible, one or more features of any example may be combined with one or more features of any other example.

[0132] For example, this disclosure provides a method for determining a manufacturable etching depth h for the case of photolithographically constrained cavity patterning, considering a wide range of refractive index contrasts Δn. This method is also effective when the cavity patterning only constrains the refractive index contrast, and is independent of current constraints.

[0133] The benefits associated with VCSELs manufactured according to the disclosed methods include:

[0134] • A VCSEL in which the desired optical modes are obtained by etching an arbitrary thickness of its epitaxial structure and by overgrowth utilizing multiple resonances within the same cavity.

[0135] • A VCSEL in which the refractive index contrast has an arbitrarily low value, while the etching is maintained at a fabricable depth of >10 nm.

[0136] • A VCSEL in which modal selection is achieved by utilizing cavity patterning and defining the coupling and guiding regions using a single overgrowth process.

[0137] • A VCSEL in which guiding and anti-guiding (coupling) properties are achieved through a single overgrowth step to enhance coupling between two or more cavities.

[0138] • A VCSEL in which multiple refractive index steps realizing the guiding and coupling portions exist in the same device and are achieved through a single overgrowth step.

[0139] • A VCSEL in which multiple refractive index steps for implementing the guiding and coupling portions exist in the same device and are achieved by a single overgrowth step and current constraint defined in the same processing step.

Claims

1. A vertical-cavity surface-emitting laser (VCSEL), comprising: The body comprises a vertical stack of semiconductor layers, one on top of the other, wherein the stack of semiconductor layers includes: A current-constrained region includes a region with low current-flow resistance defined by a region with high resistance to current flow, such that vertical current flow in the stack of semiconductor layers is guided from the region with high resistance to current flow through the region with low resistance to current flow within the current-constrained region; and A first epitaxial sublayer is arranged near the current-constrained region. The first epitaxial sublayer includes protrusions or depressions arranged near a region of low resistance to current flow in the current-constrained region, wherein the protrusions or depressions define a main cavity, and the remainder of the first epitaxial sublayer defines an outer cavity. The protrusion or depression is defined by the physical step h, which is predetermined according to the following formula: qλ0-mλ1=n0h Where λ0 is the resonant wavelength of light in the main cavity, λ1 is the resonant wavelength of light in the outer cavity, q is a half-integer positive number, n0 is the effective refractive index in the main cavity, and m is a constant.

2. The VCSEL according to claim 1, wherein the stacking of the semiconductor layers comprises, in sequence: First Distributed Bragg Reflector (DBR) mirror layer; Includes the cavity layer of the active region; First epitaxial sublayer and the current confinement region as well as Second DBR reflector layer.

3. The VCSEL according to claim 2, wherein the stacking of the semiconductor layers further comprises: The substrate layer beneath the stack of the semiconductor layers; The first contact is located on the side of the stack of semiconductor layers opposite to the substrate layer; as well as The second contact is located on the side of the substrate layer opposite to the stack of the semiconductor layers, or on one side of the body, or on the side of the stack of the semiconductor layers opposite to the substrate layer, wherein the first contact is electrically contacted only on the side of the stack of the semiconductor layers opposite to the substrate layer, and the second contact is electrically contacted only on the side of the substrate layer opposite to the stack of the semiconductor layers.

4. The VCSEL according to claim 1, wherein the region of the current constraint region with high resistance to current flow surrounds the region of the current constraint region with low resistance to current flow.

5. The VCSEL according to claim 4, wherein the protrusions or recesses of the first epitaxial sublayer are positioned in alignment with the region of the current-constrained region that has low resistance to current flow.

6. The VCSEL according to claim 5, wherein the region of the current-constrained region with low resistance to current flow is circular.

7. The VCSEL according to claim 6, wherein the protrusions or recesses of the first epitaxial sublayer are coaxial with the circular current confinement region.

8. The VCSEL according to claim 1, wherein the protrusion comprises one or more tunnel knots.

9. The VCSEL according to claim 1, wherein the recess includes one or more etched regions.

10. The VCSEL according to claim 1, wherein the current confinement region comprises one or more oxidized or implanted semiconductor layers.

11. The VCSEL according to claim 1, wherein m is selected from a set of positive half-integer values.

12. The VCSEL according to claim 1, wherein λ0 is in the range of about 680 to 2600 nm.

13. The VCSEL according to claim 1, wherein h is selected in the range of -500 to 500 nm.

14. The VCSEL according to claim 1, wherein the first epitaxial sublayer includes a recess, and h is a negative value.

15. The VCSEL according to claim 1, wherein the VCSEL operates in a first guided mode defined by a refractive index contrast Δn < 0, wherein Δn is an effective refractive index constraint given by the following formula: Δn / n0=(λ1-λ0) / λ0.

16. The VCSEL according to claim 15, wherein h is negative and λ1 < λ0.

17. The VCSEL of claim 15, wherein the VCSEL further comprises a portion supporting an anti-conductive mode with a refractive index contrast Δn > 0.

18. The VCSEL according to claim 1 further includes a second epitaxial sublayer adjacent to the first epitaxial sublayer.

19. The VCSEL of claim 18, wherein the stacking of the semiconductor layers further comprises: The substrate layer beneath the stack of the semiconductor layers; The first contact is located on the side of the stack of semiconductor layers opposite to the substrate layer; as well as The second contact is located on the side of the substrate layer opposite to the stack of the semiconductor layers, or on one side of the body, or on the side of the stack of the semiconductor layers opposite to the substrate layer, wherein the first contact is electrically contacted only on the side of the stack of the semiconductor layers opposite to the substrate layer, and the second contact is electrically contacted only on the side of the substrate layer opposite to the stack of the semiconductor layers.

20. The VCSEL according to claim 19, wherein: When the first epitaxial sublayer includes protrusions, the second epitaxial sublayer also includes protrusions aligned with the protrusions of the first epitaxial sublayer; and The protrusion of the second epitaxial sublayer extends into the space surrounded by the region of high resistance to current flow in the current-constrained region.

Images