Audio output switching frequency control

Abstract

The invention relates to audio output switching frequency control. An apparatus includes a logic circuit (120) having a clock input, a first logic circuit control output, and a second logic circuit control output. The clock generation circuit (110) has a first clocked input, a second clocked input, and a clock output. The clock output is coupled to the clock input. A turn-off timer circuit (160) has a turn-off timer output. The comparator (140) has a comparator output. An audio output (OOA) circuit (170) has a first OOA input, a second OOA input, a third OOA input, a first OOA output, and a second OOA output. The first OOA input is coupled to the comparator output. The second OOA input is coupled to the clock output. The third OOA input is coupled to the turn-off timer output. The first OOA output is coupled to the first clocked input. The second OOA output is coupled to the second clocked input.

Description

Technical Field

[0001] This application relates to the frequency control of audio output switching. Background Technology

[0002] A power converter transforms an input voltage into a higher or lower output voltage. One type of power converter is a switching converter. A switching converter contains one or more switches (e.g., transistors) that are turned on and off at a switching frequency. The switching frequency of a switching converter can be a fixed frequency or can vary based on the converter's operating conditions. Summary of the Invention

[0003] In one example, a device includes logic circuitry having a clock input, a first logic circuit control output, and a second logic circuit control output. A clock generation circuit has a first clock control input, a second clock control input, and a clock output. The clock output is coupled to the clock input. A timer shutdown circuit has a timer shutdown output. A comparator has a comparator output. An audio output (OOA) circuit has a first OOA input, a second OOA input, a third OOA input, a first OOA output, and a second OOA output. The first OOA input is coupled to the comparator output. The second OOA input is coupled to the clock output. The third OOA input is coupled to the timer shutdown output. The first OOA output is coupled to the first clock control input. The second OOA output is coupled to the second clock control input.

[0004] In another example, a device includes logic circuitry having a clock input, a first logic circuit control output, and a second logic circuit control output. A clock generation circuit has a clock output, a first clock control input, and a second clock control input, the clock output being coupled to the clock input. A timer shutdown circuit has a timer shutdown output. A comparator has a comparator output. An OOA circuit is coupled to the comparator output, the clock output, the first clock control input, the second clock control input, and the timer shutdown output. The OOA circuitry is configured to start a timer based on a comparator signal from the comparator output and to cause the logic circuitry to initiate a switching cycle outside the audible frequency range, wherein the initiation of the switching cycle is based on the expiration of the timer.

[0005] In another example, a power converter includes a power stage having a first power stage input and a second power stage input. A logic circuit has a clock input, a first logic circuit control output, and a second logic circuit control output. The first logic circuit control output is coupled to the first power stage input, and the second logic circuit control output is coupled to the second power stage input. A clock generation circuit has a clock output, a first clock control input, and a second clock control input, the clock output being coupled to the clock input. A timer shutdown circuit has a timer shutdown output. A comparator has a comparator output. An OOA circuit is coupled to the comparator output, the clock output, the first clock control input, the second clock control input, and the timer shutdown output. The OOA circuit is configured to start an OOA circuit timer based on a comparator signal from the comparator output, and to cause the logic circuit to initiate a switching cycle when the OOA circuit timer expires. Attached Figure Description

[0006] Figure 1A and 1B (Collectively referred to as Figure 1) is a schematic diagram of a power converter containing audio output circuitry in an example.

[0007] Figure 2 This is also a flowchart illustrating the operation of the audio output circuit in Figure 1 of the example.

[0008] Figure 3 The waveforms illustrate the operation of the audio output circuit in Figure 1 of the example. Detailed Implementation

[0009] Use the same reference numerals or other reference indicators in the drawings to indicate (functionally and / or structurally) the same or similar features.

[0010] As described above, the switching frequency of a switching converter can vary based on the converter's operating conditions. For example, under low load conditions, a switching converter can reduce its switching frequency to maintain the output voltage at its target (regulated) level. If the switching frequency is to be reduced below the upper limit of human hearing, the switching converter may produce audible sounds at the switching frequency. For example, the output capacitor of the switching converter may vibrate at the switching frequency, and the vibration of the capacitor may be audible to humans, which is undesirable. The examples described herein relate to an audio output circuit included within or coupled to a switching converter that ensures the converter's switching frequency remains above the upper limit of human hearing (e.g., 20 kHz, 25 kHz) while reducing the risk of converter misalignment.

[0011] Figure 1 is a schematic diagram of the power converter 100 in the example. The power converter 100 includes a clock generation circuit 110, a first logic circuit 120, a power stage 130, a comparator 140, an inverter 142, a second logic circuit 148, an error amplifier 150, a comparator 154, a slope compensator 156, a shutdown timer circuit 160, and an audio output (OOA) circuit 170. The power converter 100 has an input voltage terminal 101 and an output voltage terminal 102, to which an input voltage VIN can be supplied, and the output voltage terminal generates an output voltage VOUT. The power stage 130 has power stage inputs 130a and 130b and a power stage output 130c. The power stage output 130c is coupled to the output voltage terminal 102. A capacitor C1 is coupled between the power stage output 130c and ground. The load resistor RL represents the load powered by the power converter 100.

[0012] In one example, all components shown in Figure 1, except for the load resistor RL, are fabricated on the same integrated circuit (IC) or the same module (e.g., a multi-die module), and such IC or module is power converter 100. In another example, clock generation circuit 110, first logic circuit 120, comparator 140, inverter 142, second logic circuit 148, error amplifier 150, comparator 154, slope compensator 156, shutdown timer circuit 160, and OOA circuit 170 (but not power stage 130 and capacitor C1) are fabricated on the same IC, and power stage 130 and capacitor C1 are external to the IC. In a further example, the IC containing clock generation circuit 110, first logic circuit 120, comparator 140, inverter 142, second logic circuit 148, error amplifier 150, comparator 154, slope compensator 156, shutdown timer circuit 160, and OOA circuit 170 is an IC containing a controller for the power converter.

[0013] Clock generation circuit 110 has clock control inputs 110a and 110b and a clock output terminal 110c. First logic circuit 120 has clock input 120a, logic input 120b, and logic control outputs 120c and 120d. Second logic circuit 148 has logic control inputs 148a, 148b, and 148c and output 148d. Timer shutdown circuit 160 has timer shutdown input 160a and timer shutdown output 160b. OOA circuit 170 has OOA inputs 170a, 170b, and 170c and OOA outputs 170d, 170e, and 170f.

[0014] The clock output terminal 110c of the clock generation circuit 110 is coupled to the clock input 120a of the first logic circuit 120. The output of comparator 154 is coupled to the logic circuit input 120b. The logic circuit control output 120c is coupled to the power stage input 130a. The logic circuit control output 120d is coupled to the logic circuit control input 148b. The OOA output 170f is coupled to the logic circuit control input 148c. The output 148d of the second logic circuit 148 is coupled to the power stage input 130b.

[0015] Power stage 130 includes a high-side (HS) switch coupled in series with a low-side (LS) switch between input voltage terminal 101 and ground. In the example of Figure 1, each of the HS and LS switches is a transistor, such as a field-effect transistor. The connection between the transistors is a switch terminal SW 135, coupled to one terminal of inductor L1. The current through inductor L1 is current IL. The other terminal of the inductor is coupled to output voltage terminal 102 and capacitor C1. Power converter 100 in Figure 1 is an example of a buck converter, but power converter 100 could also be other types of switching power converters. Power stage 130 also has a minimum on-time control circuit 132 for the HS switch and a minimum on-time control circuit 134 for the LS switch. Minimum on-time control circuit 132 has an input 132a coupled to power stage input 130a and an output 132b coupled to a control input (e.g., gate) of the HS switch. Similarly, the minimum on-time control circuit 134 has an input 134a coupled to the power stage input 130b and an output 134b coupled to the control input (e.g., the gate) of the LS switch. A current sensing circuit 136 is coupled to the HS switch to generate a signal indicating (e.g., proportional to) the current flowing through the HS switch when the HS switch is closed. A current sensing circuit 137 is coupled to the LS switch to generate a signal indicating (e.g., proportional to) the current flowing through the LS switch when the LS switch is closed.

[0016] The output of current sensing circuit 137 is coupled to the negative (-) input of comparator 140. The positive (+) input of comparator 140 is coupled to ground. The output 140a of comparator 140 is coupled to the input of inverter 142, and the output of inverter 142 is coupled to logic control input 148c. The output 170f of OOA circuit 170 is coupled to logic control input 148b. The OOA outputs 170d and 170e of OOA circuit 170 are coupled to clock control inputs 110a and 110b of clock generation circuit 110, respectively. OOA output 170d provides the OOA_MODE signal 193, and OOA output 170e provides the OOA_TIMEOUT signal 192.

[0017] Error amplifier 150 has inputs that receive a feedback voltage VFB and a reference voltage VREF, the feedback voltage VFB being derived from the output voltage VOUT, for example, by means of a resistor divider. The output of error amplifier 150 provides the signal VCOMP. The output of error amplifier 150 is coupled to a timer shutdown input 160a and to the negative input of comparator 154. The timer shutdown output 160b provides the Toff signal 194 and is coupled to the OOA input 170c. Slope compensator 156 is coupled to the positive input of comparator 154, and the output of current sensing circuit 136 is coupled to another positive input of comparator 154. The output of comparator 154 is coupled to logic circuit input 120b.

[0018] Clock generation circuit 110 includes clock circuit 112, logic circuit 114, and falling edge delay circuit 118. Clock circuit 112 has output 112b. Logic gate circuit 114 has inputs 114a, 114b, 114c, and 114d and output 114e. Output 112b of clock circuit 112 is coupled to input 114c of logic gate circuit 114. Output 160b of timer shutdown circuit 160 is coupled to input 114d of logic gate circuit 114. Clock control input 110a of clock generation circuit 110 is coupled to input 114a of logic gate circuit 114. Clock control input 110b of clock generation circuit 110 is coupled to input 114b of logic gate circuit 114. Output 114e of logic gate circuit 114 is coupled to input 118a of falling edge delay circuit 118, and output 118b of falling edge delay circuit 118 is coupled to clock output terminal 110c of clock generation circuit 110. The falling edge delay circuit 118 will output a predefined amount of time for the falling edge delay.

[0019] Clock circuit 112 includes current source circuit I1, transistor M1, capacitor C5, and comparator 111. Logic gate circuit 114 includes AND gate 115 and OR gate 116. The clock output terminal 110c of clock generation circuit 110 is coupled to the gate of transistor M1, thus providing a clock signal Clock to the gate of transistor M1. The drain and source of transistor M1 are coupled across capacitor C5. Current source circuit I1 is coupled between voltage terminal 103 (e.g., an internally generated voltage or an externally supplied voltage) and capacitor C5. When clock signal Clock becomes logic high, transistor M1 is turned on, and capacitor C5 discharges to ground through transistor M5. Current source circuit I1 is coupled to capacitor C5. When clock signal Clock is logic low, transistor M1 is turned off, and current from current source circuit I1 charges capacitor C5. Capacitor C5 is coupled to the positive input of comparator 111, and a reference voltage Vref_clock is provided to the negative input of the comparator.

[0020] The output of comparator 111 is coupled to the output 112b of clock circuit 112 and to the input 114c of logic gate 114. AND gate 115 has inputs 115a (inverting input), 115b, and 115c. Inputs 115a, 115b, and 116c are coupled to inputs 114a, 114d, and 114c of logic gate 114, respectively. The output of AND gate 115 is coupled to input 116a of OR gate 116. Input 114b of logic gate 114 is coupled to input 116b of OR gate 116. The output of OR gate 116 is coupled to output 114e of logic gate 114 and to input 118a of falling edge delay circuit 118. Falling edge delay circuit 118 generates the output signal Clock. The output 118b of falling edge delay circuit 118 is coupled to clock output terminal 110c and to clock input 120a of first logic circuit 120. Therefore, in each clock cycle, current source circuit I1 charges capacitor C5, and the voltage of the capacitor reaches the reference voltage Vref_clock, thereby causing comparator 111 to generate a logic high signal at its output. Assuming signal Toff is logic high and OOA_MODE is logic low, the logic high output of comparator 111 causes the clock signal Clock to become logic high. When the clock signal Clock becomes logic high, transistor M1 turns on, thereby discharging capacitor C5 and causing the output of comparator 111 to become logic low. After a delay implemented by falling edge delay circuit 118, the clock signal Clock also becomes logic low, thereby turning off transistor M1. The process is repeated. The clock signal Clock is a fixed-frequency clock signal with a pulse width approximately equal to the falling edge delay time implemented by falling edge delay circuit 118.

[0021] If the Toff signal 194 is logic high and the OOA_MODE signal 193 and the OOA_TIMEOUT signal 192 are logic low, the output signal from comparator 111 is provided to the clock input 120a of the first logic circuit 120 through AND gate 115 and OR gate 116 and through falling edge delay circuit 118. Otherwise, if the Toff signal 194 is logic low and / or the OOA_MODE signal 193 is logic high, the output signal from comparator 111 is gated at input 115c of AND gate 115 to prevent it from reaching input 120a of the first logic circuit 120. A rising edge on either or both of the output signal from AND gate 115 or the OOA_TIMEOUT signal causes OR gate 116 to output a rising edge to the clock input 120a of the first logic circuit 120 through falling edge delay circuit 118.

[0022] Error amplifier 150 includes transconductance amplifier 152, resistor R1, and capacitors C2 and C3. Transconductance amplifier 152 generates an output current proportional to the difference between voltage VFB and VREF. Resistor R1 is coupled in series with capacitor C3. Capacitor C2 is coupled in parallel with the series combination of resistor R1 and capacitor C3. Capacitor C2 and the series combination of resistor R1 and capacitor C3 are coupled between the output of transconductance amplifier 152 and ground. The output current from transconductance amplifier 152 charges capacitor C2 to voltage Vcomp.

[0023] The output of transconductance amplifier 152 is coupled to the shutdown timer input 160a. The shutdown timer circuit 160 includes transistors M2-M5, resistor R2, capacitor C4, current source circuits I2 and I3, and a Schmitt trigger 164. Current source circuit I2 is coupled to the drain of transistor M2, and resistor R2 is coupled between the source of transistor M2 and ground. The drain of transistor M2 is coupled to the gates of transistors M3 and M4. The sources of transistors M3 and M4 are coupled together and to a power supply terminal. The drain of transistor M3 is coupled to the source of transistor M2. Transistor M5, current source I3, and capacitor C4 are coupled in parallel between the drain of transistor M4 and ground. The signal (e.g., voltage) on capacitor C4 is the V_toff signal 195, and is converted to a logic high or logic low signal (Toff signal 194) by the Schmitt trigger 164.

[0024] If the output voltage VOUT rises, the voltage VFB also rises, and the voltage Vcomp falls. Transistor M2 is configured as a source follower, and therefore, the voltage across resistor R2 also falls. The smaller voltage across resistor R2 reduces the current through resistor R2. Transistors M3 and M4 are configured as current mirrors. As the current through transistor M3 and resistor R2 decreases, the current through transistor M4 also decreases. The smaller current through resistor M4 charges capacitor C4 with a smaller current, thereby causing the V_toff signal 195 to rise at a smaller rate. Because the V_toff signal rises at a smaller rate, the rising edge of the Toff signal 194 is delayed. In contrast, the decrease in voltage VFB causes the rising edge of the Toff signal 194 to occur earlier. Therefore, the timing of the rising edge of the Toff signal is based on the amplitude of the output voltage VOUT.

[0025] The second logic circuit 148 includes an OR gate 144 with inputs 144a and 144b, and an AND gate 146 with inputs 146a and 146b. Inputs 144a and 144b are coupled to logic circuit control inputs 148b and 148c, respectively. The output of OR gate 144 is coupled to input 146b of AND gate 146, and input 146a of AND gate 146 is coupled to logic circuit control input 148a. Therefore, OR gate 144 performs a logical OR operation on the signal from OOA output 170f and the signal from inverter 142. AND gate 146 performs a logical AND operation on the signal from logic circuit control output 120d and the signal from the output of OR gate 144. The output of AND gate 146 is coupled to input 134a of minimum on-time control circuit 134. A logic high signal level from the output of AND gate 146 turns on the LS switch. Logic circuit control output 120c is coupled to input 132a of minimum on-time control circuit 132. A logic high signal level from logic circuit control output 120c turns on the HS switch.

[0026] The OOA circuit 170 includes a comparator 171, a timer 172, a set-reset (SR) latch 173, and AND gates 174 and 176. A voltage VFB is provided to the negative input of comparator 171, and a reference voltage VREF_OOA (which may be the same as or different from the reference voltage VREF) is provided to the positive input of comparator 171. The reference voltage VREF_OOA may be generated by a reference voltage circuit. The output 171a of comparator 171 is coupled to the input 176a of AND gate 176. The Q output of SR latch 173 is coupled to the input 176b of AND gate 176. Comparator 140 generates a ZERO_CROSS signal 191 at its output 140a, which is coupled to the OOA input 170a and to the enable (EN) input of timer 172. The output 118b of falling edge delay circuit 118 is coupled to the OOA input 170b of OOA circuit 170. Therefore, the clock signal Clock is provided to the reset (RST) input of timer 172. Timer 172 generates an OOA_TIMEOUT signal 192 at timer output 172a, which is coupled to OOA output 170e and to the set (S) input of SR latch 173. The output of AND gate 176 is coupled to the reset (R) input of SR latch 173. SR latch 173 generates an OOA_MODE signal 193 at its Q output, which is coupled to the input 174a of AND gate 174. The timer shutdown output 160b is coupled to the OOA input 170c of OOA circuit 170 and to the input 174b of AND gate 174. The output of AND gate 174 is coupled to the logic control input 148b and to the input 144a of OR gate 144.

[0027] refer to Figure 2 Flowcharts and Figure 3 The example waveforms are used to explain the operation of the power converter 100. Figure 2 The operations illustrated in the flowchart represent at least some of the operations performed during each switching cycle of the power converter 100 when the power converter operates in discontinuous current mode (DCM). DCM is an operating mode in which the current IL through inductor L1 drops to zero amps and remains at zero amps until the next PWM signal pulse. DCM operation may occur when the load is low. During each switching cycle of DCM operation, switch HS is turned on, followed by switch LS, and then neither switch HS nor switch LS is turned on for the remainder of the switching cycle. Figure 3The waveforms described include inductor current 301, output voltage VOUT 302, voltage VFB, OOA_TIMEOUT signal 192, OOA_MODE signal 193, V_toff signal 306, ZERO_CROSS signal 191, and Toff signal 194.

[0028] Figure 2 The flowchart is essentially cyclical, meaning that the processes depicted are continuously looped. The first operation discussed below is operation 202, where the HS switch is turned on and the first logic circuit 120 now turns on the LS switch. The first logic circuit 120 asserts a short positive pulse at its logic circuit control output 120d. With the LS switch on, the inductor current IL decreases, as indicated by 316. The output voltages VOUT and VFB also decrease, as indicated by 302b and 303b. When the inductor current IL reaches the minimum current level (e.g., 0 amps) determined by decision operation 204 (“y” branch), as indicated by 316a, comparator 140 forces its output ZERO_CROSS signal 191 to a logic high state (rising edge 308a), which causes the output signal from inverter 142 to go low.

[0029] In response to the ZERO_CROSS signal 191 being logic high, two actions occur. First, at operation 206, the rising edge (or logic high state) of the ZERO_CROSS signal 191 at the enable input of timer 172 causes timer 172 to begin counting its internal clock. Timer 172 determines whether the minimum (e.g., zero-amp) inductor current state during DCM operation has persisted long enough that the switching frequency of power converter 100 risks falling below a level that could cause audible noise (e.g., generated by capacitor C1 as described above). In one example, the counting period for timer 172 is preset within timer 172. In this example, the counting period for timer 172 is between 25 microseconds and 35 microseconds. At the moment timer 172 is enabled, the OOA_MODE signal 193 has been at logic "1" since the timer last expired.

[0030] Secondly, at operation 208, when the Toff signal 194 at the inverting input of AND gate 174 becomes logic "1", the LS switch is turned off. Since the ZERO_CROSS signal is logic high, inverter 142 forces its output signal to be logic low. When the Toff signal becomes logic high, the output of AND gate 174 is also logic low. Therefore, the output of OR gate 144 is a logic low signal. The signal from logic control output 120d used to initially turn on the LS transistor is a short-duration positive pulse. When the ZERO_CROSS signal becomes logic high, the signal from logic control output 120d has returned to logic low. Therefore, the output signal from AND gate 146 is logic low, which causes the LS switch to turn off.

[0031] With both HS and LS off, the current to the load RL is supplied by capacitor C1, causing capacitor C1 to discharge at least partially. As capacitor C1 discharges, the output voltage VOUT continues to decrease, as shown in 302b. Consequently, the voltage VFB also continues to decrease. In response to the voltage VFB dropping below the reference voltage VREF_OOA, comparator 171 generates a logic high signal at its output to AND gate 176. While the OOA_MODE 193 signal is still logic high, the output signal from AND gate 176 becomes logic high, thereby resetting SR latch 173 and forcing the OOA_MODE signal output from SR latch 173 to a logic low state (operation 210), as indicated by falling edge 305a.

[0032] Decision operation 212 determines whether timer 172 has expired. When timer 172 expires (“Y” branch), the OOA_TIMEOUT signal 192 is pulsed high at the timer output (304). With the OOA_TIMEOUT signal high, the first logic circuit 120 receives the rising edge of the clock signal Clock through OR gate 116 in clock generation circuit 110 and initiates the next switching cycle at operation 214. The next switching cycle involves the first logic circuit 120 turning on the HS switch by generating a positive pulse at logic circuit control output 120c. With the HS switch on, the inductor current IL rises, as indicated by 315. The output voltages VOUT and VFB also rise, as indicated by 302a and 303a, and the logic-high OOA_TIMEOUT signal 192 sets the SR latch 173, thereby forcing the OOA_MODE signal 193 back to a logic-high state (rising edge 305b).

[0033] At operation 218, the first logic circuit 120 responds to a logic high HS_OFF signal from comparator 154 by turning off the HS switch (this occurs when the signal from current sensing circuit 136 exceeds the signal Vcomp from error amplifier 150). After a blanking period (implemented by the first logic circuit 120 to ensure that neither the HS switch nor the LS switch is turned on simultaneously), control returns to operation 202, and the process is repeated.

[0034] The technical advantage of the example OOA circuit 170 in Figure 1 is that the expiration of timer 172 triggers the start of the next switching cycle, in which the inductor current rises (315) before the LS switch is turned on, causing the inductor current to decrease (316). Due to this behavior, the output voltage experiences a small increase, as shown in 302a, before it quickly returns to its target level. Therefore, the power converter 100 does not experience regulation losses over multiple switching cycles, which conventional OOA circuits may experience. For example, in a conventional OOA circuit, such a circuit might initiate a new switching cycle in response to the expiration of a timer by first turning on the LS switch and then allowing the control circuitry system's control mechanism. This type of OOA circuit can lead to regulation losses throughout multiple switching cycles. The OOA circuit 170 described herein advantageously avoids such regulation losses.

[0035] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0036] Furthermore, in this specification, the term "based on" means "at least partially based on". Therefore, if X is based on Y, then X may depend on Y and any number of other factors.

[0037] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or a combination thereof.

[0038] As used herein, the terms “terminal,” “node,” “interconnect,” “lead,” and “pin” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnects or the ends of device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0039] The circuits or devices described herein as containing certain components may be practically adaptable to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may practically contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the said passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0040] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used in practice with minimal alteration to the rest of the circuitry. For example, field-effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, such as NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0041] The claims may refer to the control input and current terminals of a transistor. In the case of a FET, the control input is the gate, and the current terminals are the drain and source. In the case of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0042] In this article, "FET on" or "enabled" means that a conductive channel exists in the FET and drain current can flow through it. "FET off" or "disabled" means that no conductive channel exists and therefore drain current does not flow through the FET. However, "off" the FET allows current to flow through the body diode of the transistor.

[0043] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0044] While some elements of the described examples are contained within the integrated circuit, while others are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit may be contained within the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0045] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter, or, if the parameter is zero, within a reasonable range of approximately zero.

[0046] Within the scope of the claims, modifications to the described examples are possible, and other examples are also possible.

Claims

1. An apparatus comprising: A logic circuit having a clock input, a first logic circuit control output, and a second logic circuit control output; A clock generation circuit having a first clock control input, a second clock control input, and a clock output, wherein the clock output is coupled to the clock input; The timer shutdown circuit has a timer shutdown output. A comparator having a comparator output; and An audio output OOA circuit has a first OOA input, a second OOA input, a third OOA input, a first OOA output, and a second OOA output. The first OOA input is coupled to the comparator output, the second OOA input is coupled to the clock output, the third OOA input is coupled to the shutdown timer output, the first OOA output is coupled to the first clock control input, and the second OOA output is coupled to the second clock control input.

2. The device of claim 1, wherein the OOA circuit includes a timer having an output, the output of the timer being coupled to the second OOA output.

3. The device of claim 2, wherein the timer is configured to determine when the output current has been at a minimum current level for 25 microseconds to 35 microseconds.

4. The device according to claim 2, further comprising: A logic gate, which has a first logic gate input and a second logic gate input; as well as A latch having a first latch input and a latch output, the first latch input being coupled to the output of the timer, and the latch output being coupled to the first logic gate input.

5. The device of claim 4, wherein the logic gate comprises an AND gate.

6. The device of claim 4, wherein the comparator is a first comparator, the comparator output is a first comparator output, and the logic gate is a first logic gate, and the device further comprises: The second logic gate has a third logic gate input, a second logic gate input, and a logic gate output, wherein the second logic gate input is coupled to the first OOA output; as well as The second comparator has a first comparator input, a second comparator input, and a second comparator output, the second comparator output being coupled to the third logic gate input.

7. The device of claim 6, wherein the latch has a second latch input and the logic gate output is coupled to the second latch input.

8. The device of claim 1, wherein the clock generating circuit comprises: A clock circuit having an output; and A logic gate circuit having a first input, a second input, and a third input, wherein the first input of the logic gate circuit is coupled to a first clock control input, the second input of the logic gate circuit is coupled to a second clock control input, and the third input of the logic gate circuit is coupled to the output of the clock circuit.

9. The device of claim 8, wherein the logic gate circuit comprises: An AND gate having a first input coupled to the first input of the logic gate circuit, a second input coupled to the third input of the logic gate circuit, and an output; and An OR gate having a first input coupled to the output of the AND gate, a second input coupled to the second input of the logic gate circuit, and an output coupled to the clock output.

10. An apparatus comprising: A logic circuit having a clock input, a first logic circuit control output, and a second logic circuit control output; A clock generation circuit having a clock output, a first clock control input, and a second clock control input, wherein the clock output is coupled to the clock input; The timer shutdown circuit has a timer shutdown output. A comparator that has a comparator output; as well as An audio output OOA circuit is coupled to the comparator output, the clock output, the first clock control input, the second clock control input, and the shutdown timer output. The OOA circuit is configured to start a timer based on a comparator signal from the comparator output and to cause the logic circuit to initiate a switching cycle outside the audible frequency range, wherein the initiation of the switching cycle is based on the expiration of the timer.

11. The device of claim 10, wherein the logic circuit is a first logic circuit and the OOA circuit has an output, and the device further comprises: The second logic circuit has a third logic circuit control input, a fourth logic circuit control input, a fifth logic circuit control input, and an output. The third logic circuit control input is coupled to the second logic circuit control output, the fourth logic circuit control input is coupled to the output of the OOA circuit, and the fifth logic circuit control input is coupled to the comparator output. Specifically, the OOA circuit is configured to assert the second signal at the output of the second logic circuit only when the first signal at the output of the timer is in the first logic state, regardless of the logic state of the signal at the output of the comparator.

12. The device of claim 10, wherein the OOA circuit includes a latch, and wherein the OOA circuit is configured to set the latch in response to the expiration of the timer.

13. The device of claim 12, wherein the OOA circuit is configured to reset the latch in response to a voltage lower than a reference voltage.

14. The device of claim 12, wherein the latch has a reset input, and the OOA circuit comprises: A comparator that has an output; and A logic gate having a first input coupled to the output of the comparator and an output coupled to the reset input.

15. The device of claim 14, wherein the logic gate has a second input and the latch has an output coupled to the second input of the latch.

16. A power converter comprising: A power stage having a first power stage input and a second power stage input; A logic circuit having a clock input, a first logic circuit control output, and a second logic circuit control output, wherein the first logic circuit control output is coupled to a first power stage input, and the second logic circuit control output is coupled to a second power stage input; A clock generation circuit having a clock output, a first clock control input, and a second clock control input, wherein the clock output is coupled to the clock input; The timer shutdown circuit has a timer shutdown output. A comparator that has a comparator output; as well as An audio output OOA circuit is coupled to the comparator output, the clock output, the first clock control input, the second clock control input, and the shutdown timer output. The OOA circuit is configured to start an OOA circuit timer based on a comparator signal from the comparator output and to cause the logic circuit to initiate a switching cycle when the OOA circuit timer expires.

17. The power converter of claim 16, wherein the power converter is a buck converter.

18. The power converter according to claim 16, wherein: The power stage has a first transistor coupled in series with a second transistor between a first voltage terminal and a second voltage terminal, the second transistor having a control input; The OOA circuit timer has an output; The OOA circuit includes a latch having a first input, a second input, and a latch output, wherein the first input of the latch is coupled to the output of the OOA circuit timer; and The OOA circuit is configured to turn off the second transistor in response to a signal at the output of the shutdown timer being in a first logic state and the latch output being in a first logic state, wherein the first logic state indicates the expiration of the OOA circuit timer.

19. The power converter of claim 18, further comprising a minimum on-time circuit coupled between the control output of the second logic circuit and the control input of the second transistor.

20. The power converter of claim 16, wherein the power converter has a switching frequency, and the OOA circuit is configured such that the switching frequency is higher than approximately 20 kHz.

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