Image processing apparatus, image sensor, and image processing method

Abstract

The embodiment of the invention provides an image processing device, an image sensor and an image processing method, relates to the technical field of sensors, improves the signal receiving range of the image processing device, and can effectively convert output signals of a pixel array of a CIS (Contact Image Sensor). According to the specific scheme, a slope generation circuit is used for generating a slope signal, a frequency dividing circuit is used for receiving a first clock signal and generating a plurality of second clock signals with different frequencies based on the first clock signal, and a time schedule controller is used for controlling the slope generation circuit to generate the slope signals with different gains based on the second clock signals with different frequencies. The analog-to-digital converter comprises a first input end and a second input end, the first input end is used for inputting a pixel signal, the second input end is used for inputting a ramp signal, and the analog-to-digital converter is used for comparing the pixel signal with the ramp signal in the current gain to obtain a pixel quantized value. The embodiment of the invention is used for the process of converting the pixel signal into the pixel quantized value.

Description

Technical Field

[0001] This application relates to the field of sensor technology, and in particular to an image processing apparatus, an image sensor, and an image processing method. Background Technology

[0002] Currently, complementary metal oxide semiconductor image sensors (CIS) are a widely used technology in the field of digital imaging, integrating image sensing capabilities with the functions of microelectronic circuits. CIS is widely used in digital cameras, drones, robots, medical imaging, industrial automation, astronomical observation, and smart homes.

[0003] A CIS typically includes a pixel array and an image processing device. After receiving light, the pixel array converts the light energy into an electrical signal. The image processing device then quantizes this electrical signal into a digital signal for further processing.

[0004] As application requirements increase, the demands on the dynamic range of CIS (CMOS Image Sensor) are also rising, necessitating improvements in manufacturing processes to enhance pixel photosensitive performance. The most direct method is to expand the output range of the pixel array; however, the signal receiving range of image processing devices is limited. Therefore, effectively converting the output signal of the CIS pixel array has become a pressing issue. Summary of the Invention

[0005] This application provides an image processing apparatus, an image sensor, and an image processing method, which improves the signal receiving range of the image processing apparatus and can effectively convert the output signal of the pixel array of a CIS.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions.

[0007] In a first aspect, embodiments of this application provide an image processing apparatus, comprising: a ramp generation circuit, a frequency divider circuit, a timing controller, and an analog-to-digital converter (ADC). The ramp generation circuit generates a ramp signal; the frequency divider circuit receives a first clock signal and generates multiple second clock signals of different frequencies based on the first clock signal; and the timing controller controls the ramp generation circuit to generate ramp signals with different gains based on the second clock signals of different frequencies. The ADC includes a first input terminal and a second input terminal. The first input terminal is used to input a pixel signal, and the second input terminal is used to input the ramp signal. The ADC compares the pixel signal with the ramp signal at the current gain to obtain a pixel quantization value.

[0008] Therefore, in the image processing apparatus provided in this application embodiment, a frequency divider circuit can be used to divide the first clock signal to obtain multiple second clock signals of different frequencies, and a timing controller can be used to control a ramp generation circuit to generate a ramp signal with a gain corresponding to the frequency of the second clock signal. In other words, the image processing apparatus can obtain ramp signals with different gains as needed. The ramp signal can serve as a reference signal for the analog-to-digital converter (ADC), and different gain reference signals can be adapted to different signal receiving ranges of the ADC. This effectively converts the output signal of the pixel array of the CIS, improving the performance of the CIS. Furthermore, compared to gain adjustment methods such as using resistors, capacitors, or current, the gain adjustment method using the frequency of the clock signal in the image processing apparatus results in lower gain error.

[0009] In one possible design, the gain of the ramp signal is positively correlated with the frequency of the second clock signal. That is, the higher the frequency of the second clock signal, the steeper the slope of the ramp signal, i.e., the greater the gain of the ramp signal; the lower the frequency of the second clock signal, the gentler the slope of the ramp signal, i.e., the smaller the gain of the ramp signal.

[0010] In one possible design, the ramp generation circuit includes a first gain circuit and a second gain circuit. The output of the first gain circuit is coupled to the input of the second gain circuit, and the output of the second gain circuit is coupled to the second input of the analog-to-digital converter (ADC). The first gain circuit generates the ramp signal, and the second gain circuit adjusts the ramp signal. Thus, the ramp generation circuit can progressively adjust the ramp signal using the first and second gain circuits to obtain ramp signals with different gains, thereby improving the signal reception range of the ADC and enhancing the performance of the image processing device.

[0011] In one possible design, the second gain circuit includes an adjustable resistor and multiple first gain branches connected in parallel. A timing controller is also used to control the number of first gain branches that are turned on and / or the resistance value of the adjustable resistor to obtain ramp signals with different gains. Thus, the second gain circuit can adjust the gain of the ramp signal by the number of first gain branches or the resistance value of the adjustable resistor. Adjusting the resistance value of the adjustable resistor can reduce the resistive thermal noise of the image processing device and improve its performance.

[0012] In one possible design, the first gain circuit includes multiple second gain branches connected in parallel. A timing controller is also used to control the number of second gain branches that are turned on to obtain ramp signals with different gains.

[0013] In one possible design, the image processing device further includes a third gain circuit. The input of the third gain circuit is used to input the pixel signal, and the output of the third gain circuit is coupled to the first input of the analog-to-digital converter. The third gain circuit is used to adjust the pixel signal.

[0014] In one possible design, the third gain circuit includes a first capacitor and multiple capacitor modules connected in parallel. Each capacitor module includes a first switch, a second switch, and a second capacitor. The first terminal of the first switch is coupled to the input terminal of the third gain circuit, the second terminal of the first switch is coupled to the first terminal of the second capacitor, the first terminal of the second switch is coupled to the first terminal of the second capacitor, the second terminal of the second switch is grounded, and the second terminal of the second capacitor is coupled to the output terminal of the third gain circuit. Therefore, the image processing device can adjust the pixel signal through the third gain circuit to improve the signal reception range of the analog-to-digital converter (ADC). Furthermore, compared to adjusting gain using current and resistance, the third gain circuit uses capacitor adjustment, resulting in lower power consumption. This reduces the power consumption of the image processing device while maintaining the signal reception range of the ADC.

[0015] Secondly, embodiments of this application provide an image sensor, which includes a pixel array and an image processing device according to the first aspect and any implementation thereof, wherein the pixel array and the image processing device are coupled, and the pixel array is used to generate pixel signals.

[0016] Thirdly, embodiments of this application provide an image processing method applied to an image processing apparatus, which includes a ramp generation circuit, a frequency divider circuit, a timing controller, and an analog-to-digital converter. The image processing method includes: the frequency divider circuit receiving a first clock signal and generating second clock signals of different frequencies based on the first clock signal; the timing controller controlling the ramp generation circuit to generate ramp signals of different gains based on the second clock signals of different frequencies; and the analog-to-digital converter comparing a pixel signal with a ramp signal at the current gain to obtain a pixel quantization value.

[0017] Fourthly, embodiments of this application provide a computer-readable storage medium including computer instructions that, when executed on an electronic device, cause the electronic device to perform the image processing method in the possible implementation of the third aspect described above.

[0018] Fifthly, embodiments of this application provide a computer program product that, when run on a computer or processor, causes the computer or processor to execute the image processing method in the possible implementation of the third aspect described above.

[0019] It is understood that any of the image sensors, image processing methods, computer-readable storage media or computer program products provided above are related to image processing devices. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding image processing devices, and will not be elaborated here.

[0020] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a CIS provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of the structure of a CIS readout circuit provided in an embodiment of this application;

[0024] Figure 4 This is a schematic diagram of the structure of an IPGC provided in an embodiment of this application;

[0025] Figure 5 This is a schematic diagram of the structure of an image processing apparatus provided in an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of another image processing apparatus provided in an embodiment of this application;

[0027] Figure 7 This is a schematic diagram of a ramp generation circuit provided in an embodiment of this application;

[0028] Figure 8 This is a schematic diagram of the structure of a first gain circuit provided in an embodiment of this application;

[0029] Figure 9 This is a schematic diagram of the structure of another image processing apparatus provided in the embodiments of this application;

[0030] Figure 10 This is a flowchart of an image processing method provided in an embodiment of this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments, unless otherwise stated, "multiple" means two or more.

[0032] Furthermore, the term "coupling" is used to refer to electrical connections, including direct connections via wires or terminals or indirect connections via other devices. Therefore, "coupling" should be considered a broad type of electronic communication connection.

[0033] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0034] In the embodiments of this application, the transistor can be a field-effect transistor (FET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). Taking MOSFET as an example, transistors are divided into two types: N-type transistors (NMOS transistors) and P-type transistors (PMOS transistors). A transistor can include a source, a drain, and a gate. The conduction or cutoff of the transistor can be controlled by controlling the voltage input to the gate. When the transistor is on, the source and drain conduct, generating a conduction current. Furthermore, the magnitude of the conduction current generated between the source and drain varies depending on the gate voltage. When the transistor is off, the source and drain do not conduct, and no current is generated. In the embodiments of this application, the source of the transistor is referred to as the first terminal, and the drain of the transistor is referred to as the second terminal; or, the drain of the transistor is referred to as the first terminal, and the source of the transistor is referred to as the second terminal.

[0035] To facilitate understanding, the complementary metal oxide semiconductor image sensor (CIS) will be further introduced below with reference to the accompanying drawings.

[0036] like Figure 1 As shown, Figure 1 The diagram illustrates a structural schematic of a CIS (CMOS Image Sensor), which may include a pixel array and peripheral circuitry. Specifically, the pixel array consists of multiple pixel circuits arranged in a two-dimensional layout of rows and columns. Each pixel circuit includes at least one photosensitive device, which may be a photodiode (PD). The peripheral circuitry may include a vertical scanning circuit, a horizontal scanning circuit, and a timing controller.

[0037] Figure 1 In the diagram, the x-direction represents the row direction, and the y-direction represents the column direction. Signal lines connected to the pixel circuit along the row direction are pixel signal lines, with one end connected to the vertical scanning circuit. Signal lines connected to the pixel circuit along the column direction are vertical signal lines, with one end connected to the horizontal scanning circuit. The horizontal scanning circuit may include an analog-to-digital converter (ADC), which performs quantization and correlated double sampling processing. Under the control of the timing controller, the horizontal scanning circuit sequentially scans the ADCs on each vertical signal line, thereby outputting the temporarily stored digital code values ​​(i.e., the read-out image) to the signal processing module in sequence.

[0038] The timing controller is used to perform drive control of the vertical and horizontal scanning circuits. It generates various drive signals for the operation of these circuits. For example, the timing controller generates control signals based on an externally provided vertical synchronization signal or external trigger signal, as well as a horizontal synchronization signal. These control signals are then provided to the vertical scanning circuit. Based on the control signals provided by the timing controller, the vertical scanning circuit provides various signals, including drive pulses, to each pixel circuit line-by-line through the selected pixel signal lines, causing each pixel circuit to output a pixel signal to the vertical signal lines.

[0039] Figure 1 The structure of the pixel circuit in the image is as follows: Figure 2 As shown, the pixel circuit includes a photosensitive device ( Figure 2 (represented by PD), transfer tube ( Figure 2 (represented by Tx), floating diffusion region ( Figure 2 (represented by FD), floating diffusion region capacitor ( Figure 2 China-Israel C FD (indication) and reset tube ( Figure 2 (Represented by RST in Chinese). The photosensitive device can be a photodiode with photosensitive function, which generates photocharge after receiving light. The transfer transistor transfers the photocharge from the photosensitive device to the floating diffusion region, which has an equivalent floating diffusion region capacitance. The reset transistor is used to apply the power supply voltage (…). Figure 2 The reset voltage (represented by VDD) is introduced into the floating diffusion region to reset the voltage of the floating diffusion region. The pixel circuit also includes an active follower transistor (VDD). Figure 2 (represented by SF) and row selection tube ( Figure 2 (represented by SEL in Chinese), where the source follower transistor is used to receive the voltage of the floating diffusion region and provide the amplified voltage, and the row select transistor is used to receive the amplified voltage and output the amplified voltage to the vertical signal line.

[0040] In addition, the gates of the transfer transistor, reset transistor, and row select transistor are all connected to the corresponding timing controllers. The timing controllers control the gate voltage of the corresponding functional transistors to turn the corresponding functional transistors on or off.

[0041] Continue reading Figure 1 CIS can also include a ramp generator circuit, which can generate ramp signals with different gains to effectively adapt to varying light intensities and avoid motion artifacts. In one possible example, the ramp generator circuit can generate ramp signals with different gains by controlling different unit currents flowing through a fixed resistor.

[0042] In one possible implementation, such as Figure 3 As shown, Figure 3 The diagram illustrates a CIS readout circuit, which may include an analog-to-digital converter (ADC) and a ramp generation circuit. Specifically, to reduce the output signal amplitude of the ramp generation circuit, the pixel signal at the input of the ADC can be adjusted with different gains. For example, the first input of the ADC (…) Figure 3 (represented by 'a' in the diagram) is coupled to the first terminal of capacitor C1, and the second terminal of capacitor C1 is used for input pixel signals. The first terminal of capacitor C2 is coupled to the first input terminal of the analog-to-digital converter, and the second terminal of capacitor C2 is coupled to switch S1. The second terminal of switch S1 is coupled to the second terminal of capacitor C1, and the second terminal of capacitor C2 is also coupled to the first terminal of switch S2. The second terminal of switch S2 is grounded. Additionally, the second input terminal of the analog-to-digital converter (… Figure 3 (represented by b) Circuit coupling is generated through capacitor C3 and ramp.

[0043] Therefore, when switch S1 is on and switch S2 is off, capacitors C1 and C2 are connected in parallel. Assuming the capacitance of the parallel capacitors C1 and C2 is the same as the capacitance of capacitor C3, this means the CIS readout circuit amplifies the pixel signal with a gain of 1. When switch S1 is off and switch S2 is on, capacitors C1 and C2 are connected in series. This is equivalent to capacitors C1 and C2 dividing the pixel signal, meaning the CIS readout circuit multiplies the pixel signal by a gain less than 1. Assuming the capacitances of capacitors C1 and C2 are equal, this is equivalent to the CIS readout circuit having a gain of 2, meaning the CIS readout circuit halves the amplitude of the pixel signal.

[0044] It is understood that in the embodiments of this application, the signal is given an N-fold gain, that is, the amplitude of the signal is multiplied by 1 / N, and the same applies below.

[0045] In one possible example, assuming the maximum signal receiving range of the analog-to-digital converter is 1.2V, and the capacitance values ​​of capacitors C1 and C2 are equal, the CIS readout circuit can control switch S1 to be turned off and switch S2 to be turned on in order to convert the pixel signal with an amplitude of 2V output by the pixel array. At this time, the pixel signal with an amplitude of 2V is adjusted to a pixel signal with an amplitude of 1V to meet the signal receiving range of the analog-to-digital converter.

[0046] In addition, to meet the signal receiving range requirements of the analog-to-digital converter (ADC), besides adjusting the gain of the ADC's pixel signals, the gain of the ramp signal from the ramp generation circuit can also be adjusted. The ramp generation circuit can achieve gain adjustment by different factors using a current intensity programmable gain controller (IPGC).

[0047] Specifically, such as Figure 4 As shown, Figure 4 The diagram shows a schematic of an IPGC structure. The IPGC may include a current source ( Figure 4 The current source is represented by I), transistor N1, transistor N2, and multiple current branches, such as current branch_1 to current branch_n. The output terminal of the current source is coupled to the first terminal of transistor N1, and the output terminal of the current source is also coupled to the gate of transistor N2. The second terminal of transistor N1 is coupled to the first terminal of transistor N2. Taking current branch_1 as an example, current branch_1 includes transistors N3, N4, N5, and N6. Among them, the first terminal of transistor N3 is coupled to the output terminal of IPGC (… Figure 4 (represented by IPGC_out) coupling, the gate of transistor N3 is used to input the first enable signal ( Figure 4(represented by EN in Chinese), the second terminal of transistor N3 is coupled to the first terminal of transistor N5. The second terminal of transistor N5 is also coupled to the second terminal of transistor N4, and the first terminal of transistor N4 is coupled to the power supply terminal (…). Figure 4 (represented by VDD) coupling, the gate of transistor N4 is used to input the second enable signal ( Figure 4 (referred to as ENB in ​​Chinese). The gate of transistor N5 is coupled to the gate of transistor N1, the second terminal of transistor N5 is coupled to the first terminal of transistor N6, the gate of transistor N6 is coupled to the gate of transistor N2, and the second terminal of transistor N6 is coupled to the second terminal of transistor N2.

[0048] Therefore, the timing controller can control the number of current branches that are turned on through the first enable signal and the second enable signal to adjust the output current and achieve gain adjustment of different multiples. In one possible example, if the number of current branches that are turned on is 2, then the gain of the ramp generation circuit is 2. Or, if n = 16, if the number of current branches that are turned on is 16, then the gain of the ramp generation circuit is 16.

[0049] In one possible example Figure 3 In the scheme shown, the first input terminal of the analog-to-digital converter can achieve a gain of 1 to 2 times, and the second input terminal of the analog-to-digital converter can achieve a gain of 2 to 16 times. Thus, the overall CIS readout circuit can achieve a gain of 1 to 16 times.

[0050] However, this scheme involves relatively high current, which leads to high power consumption in the CIS readout circuit. Additionally, if the gain factor is high (i.e., the output signal amplitude is small), the resistive thermal noise of the CIS readout circuit becomes significant.

[0051] Therefore, this application provides an image processing device that can divide the clock signal of the ramp generation circuit by a frequency divider circuit to obtain clock signals of different frequencies, thereby controlling the ramp generation circuit to generate ramp signals of different gains. The ramp signals of different gains can be adapted to the signal receiving range of the analog-to-digital converter, thereby effectively converting pixel signals and improving the performance of the image processing device.

[0052] In the above scenarios, the image processing apparatus provided in this application embodiment can be applied to different systems or devices, such as electronic devices. The electronic device can be a terminal, such as a mobile phone terminal, tablet computer, laptop, augmented reality (AR) device, virtual reality (VR) device, and in-vehicle terminal, etc. The electronic device may include a pixel array (CIS), which can acquire light signals through the pixel array in the CIS and convert the light signals through the image processing apparatus for subsequent processing.

[0053] In some embodiments, the image processing apparatus provided in this application can be applied to an image sensor. The image sensor may include a pixel array and an image processing apparatus, which are coupled together. The pixel array is used to generate pixel signals, and the image processing apparatus is used to process the pixel signals, such as converting the pixel signals into pixel quantization values.

[0054] The image processing apparatus provided in the embodiments of this application will be further described below with reference to the accompanying drawings.

[0055] This application provides an image processing apparatus, such as... Figure 5 As shown, Figure 5 The diagram shows a schematic of an image processing device. This device includes a ramp generation circuit, a frequency divider circuit, a timing controller, and an analog-to-digital converter.

[0056] The ramp generation circuit is used to generate ramp signals.

[0057] For example, a ramp signal, also known as a step signal or rising edge pulse, is a basic waveform in digital signal processing. A ramp signal represents a periodic process that gradually rises from 0 to a preset value and then returns to 0. In this embodiment, the ramp signal can be used as a reference signal for the pixel signal to obtain the pixel quantization value.

[0058] The frequency divider circuit is used to receive the first clock signal. Figure 5 (represented by CLK1 in the code), and generates multiple second clock signals of different frequencies based on the first clock signal, such as CLK2_1 to CLK2_4.

[0059] For example, a frequency divider circuit can generate multiple second clock signals of different frequencies by changing the period of a first clock signal, where the frequency of the first clock signal is greater than the frequency of the second clock signal. Specifically, the frequency divider circuit can divide the input signal into successively decreasing integer multiples using a counter or filter. For instance, if the frequency of the first clock signal is 100 MHz, the frequency divider circuit can divide it by two to obtain a 50 MHz second clock signal; or it can divide it by four to obtain a 25 MHz second clock signal. That is, the frequency divider circuit can control the length of the clock signal period using delay elements (such as resistors, capacitors, and transistors), with each division stage adding a fixed delay, causing the frequency of the output clock signal to decrease proportionally. Furthermore, the frequency divider circuit can obtain any desired low-frequency clock signal by adjusting the division ratio.

[0060] The timing controller is used to control the ramp generation circuit to generate ramp signals with different gains based on the second clock signal of different frequencies.

[0061] Optionally, the gain of the ramp signal and the frequency of the second clock signal are positively correlated.

[0062] For example, such as Figure 6 As shown, Figure 6 The diagram shows the structure of another image processing device. Figure 6 The diagram specifically illustrates the frequency divider circuit, timing controller, and ramp generation circuit. Specifically, Figure 6 The diagram shows four different frequency second clock signals, and four different gain ramp signals corresponding to these four second clock signals.

[0063] Specifically, the higher the frequency of the second clock signal, the steeper the slope of the ramp signal, meaning the greater the gain of the ramp signal; conversely, the lower the frequency of the second clock signal, the gentler the slope of the ramp signal, meaning the smaller the gain of the ramp signal.

[0064] Continue reading Figure 6 The ramp generation circuit may include multiple ramp units and multiple resistors (e.g., R1 and R2), and each ramp unit may include multiple transistors (e.g., N7, N8, N9, and N10). Specifically, the first terminal of transistor N7 is coupled to the power supply terminal VDD, the second terminal of transistor N7 is coupled to the first terminal of transistor N8, the second terminal of transistor N8 is coupled to the first terminal of transistor N9, the second terminal of transistor N8 is also coupled to the first terminal of transistor N10, the second terminal of transistor N9 is coupled to the first terminal of R1, the second terminal of resistor R1 is grounded, the second terminal of transistor N10 is coupled to the first terminal of resistor R2, and the second terminal of resistor R2 is grounded.

[0065] The gate of transistor N9 is used to input the first turn-on signal from the timing controller. Figure 6 (Indicated by IN), the gate of transistor N10 is used to input the second turn-on signal from the timing controller. Figure 6 (represented by IP in Chinese). The timing controller can generate a first turn-on signal and a second turn-on signal based on the frequency of the second clock signal to control the turn-on frequency of transistors N9 and N10, thereby generating ramp signals with different gains.

[0066] See also Figure 5 The analog-to-digital converter includes a first input terminal ( Figure 5 (represented by 'a') and the second input terminal ( Figure 5(represented by b in the diagram), the first input terminal is used to input the pixel signal, and the second input terminal is used to input the ramp signal. The analog-to-digital converter (ADC) compares the pixel signal and the ramp signal at the current gain to obtain the pixel quantization value. The pixel signal can come from... Figure 2 The pixel circuit shown.

[0067] For example, an analog-to-digital converter (ADC) is an electronic device that converts continuously changing analog signals (such as sound, voltage, or current) into discrete digital signals (typically represented as binary values). In this embodiment, a ramp signal is used as a reference voltage, forming a step called a "reference voltage level." The ADC compares the input pixel signal with the ramp signal, dividing the pixel signal into different intervals using this step. When a pixel signal falls within a certain reference voltage interval, the ADC selects the boundary value of that interval as the representative of the corresponding digital signal. Specifically, the ADC can perform this through a successive approximation method, starting from the lowest reference voltage and gradually approaching the pixel signal until the closest reference voltage point is found, and then converting that closest reference voltage point into the corresponding binary value, i.e., the pixel quantization value.

[0068] Therefore, the image processing apparatus provided in this application embodiment can obtain ramp signals with different gains as needed. The ramp signals can serve as reference signals for analog-to-digital converters (ADCs). Reference signals with different gains can be adapted to different signal receiving ranges of ADCs, thereby effectively converting the output signals of the pixel array of the CIS and improving the performance of the CIS. In addition, compared with gain adjustment methods such as resistors, capacitors, or current, the gain adjustment method using the frequency of the clock signal in the image processing apparatus has lower gain error.

[0069] Optionally, the ramp generation circuit includes a first gain circuit and a second gain circuit, such as... Figure 7 As shown, Figure 7 The diagram illustrates a specific structure of a ramp generation circuit. The output of the first gain circuit is coupled to the input of the second gain circuit, and the output of the second gain circuit is coupled to the second input of the analog-to-digital converter. The first gain circuit generates the ramp signal, and the second gain circuit adjusts the ramp signal.

[0070] For example, the timing controller can adjust the gain factor of the first gain circuit and the second gain circuit by adjusting the current. In addition, the ramp generation circuit can perform step-by-step gain on the ramp signal through the first gain circuit and the second gain circuit to improve the signal reception range of the analog-to-digital converter receiving the pixel signal and improve the performance of the image processing device.

[0071] In one possible example, given the gain requirements of the image processing device and after the gain at the first input of the analog-to-digital converter is determined, the gain adjustment of the ramp generation circuit can be expressed as: first gain circuit (i) + second gain circuit (j), where i and j represent the gain multipliers, respectively. In one possible example, i = 8 bits, j = 2 bits. That is, the first gain circuit can achieve a gain of 1 to 8 times, and the second gain circuit can achieve a gain of 1 to 2 times.

[0072] Optional, please continue reading Figure 7 The second gain circuit includes an adjustable resistor and multiple first gain branches connected in parallel. Figure 7 (Represented by A_1 and A_2 in the diagram). The timing controller is also used to control the number of the first gain branches that are turned on and / or the resistance value of the adjustable resistor to obtain the ramp signal with different gains. It is understood that the second gain circuit may include a gain higher than... Figure 7 The diagram shows a larger number of first gain branches. Figure 7 The example shown is for illustrative purposes only and does not constitute a limitation on the second gain circuit.

[0073] Taking the first gain branch A_1 as an example, the first gain branch may include multiple transistors (e.g., N11 and N12) and switches (e.g., S4). The first terminal of transistor N11 is coupled to the power supply terminal VDD, the second terminal of transistor N11 is coupled to the first terminal of transistor N12, the second terminal of transistor N12 is coupled to the first terminal of switch S4, and the second terminal of switch S4 is also coupled to another gain branch.

[0074] Therefore, when switch S4 is open, the first gain circuit includes only one first gain branch, and the first gain circuit adjusts the ramp signal with a gain of 1. When switch S4 is on, the first gain circuit includes only two first gain branches, and the first gain circuit adjusts the ramp signal with a gain of 2.

[0075] Continue reading Figure 7 The second gain circuit also includes multiple transistors (e.g., N13, N14, N15, N16, N17, and N18), multiple resistors (e.g., R3 and R4), and multiple switches (e.g., S5 and S6). For details on the connection of the multiple transistors and switches, please refer to [link to documentation]. Figure 7 This will not be elaborated upon here.

[0076] Taking an adjustable resistor consisting of resistor R3 and switch S5 as an example, resistor R3 may include multiple resistors connected in parallel, and switch S5 may include multiple switches connected in parallel (the switches may be transistors). The multiple parallel resistors and multiple parallel switches are connected in series in a one-to-one correspondence. Therefore, the timing controller can control the number of parallel resistors by turning the switches on or off, thereby controlling the resistance value of the adjustable resistor and obtaining ramp signals with different gains.

[0077] For example, the adjustable resistor may also be a resistive analog-to-digital converter (RDAC) or other forms, which are not limited in this application embodiment.

[0078] In other words, image processing devices can adjust the gain by adjusting the resistance value. When the pixel signal amplitude is low, a smaller resistance value can be adjusted to achieve a higher gain. Resistors with smaller resistance values ​​have lower thermal noise and can be used in scenarios with high noise requirements.

[0079] Optionally, the first gain circuit includes multiple second gain branches connected in parallel, such as... Figure 8 As shown, Figure 8 The diagram shows a schematic of a first gain circuit. In this circuit, n second gain branches are... Figure 8 The numbers are represented by B_1 to B_n.

[0080] Taking the second gain branch B_1 as an example, the second gain branch includes multiple transistors (e.g., N19, N20, N21, N22, N23, and N24) and resistor R5. The first terminal of transistor N19 and the output terminal of the second gain branch ( Figure 8 (represented by IPGC_out) coupling, the gate of transistor N19 is used for input gate voltage ( Figure 8 (represented by VG in the diagram), the second terminal of transistor N19 is coupled to the first terminal of transistor N21, and the gate of transistor N21 is used to input the first enable signal ( Figure 8 (represented by EN in Chinese), the second terminal of transistor N21 is coupled to the first terminal of transistor N23. The first terminal of transistor N20 is coupled to the power supply terminal VDD, and the gate of transistor N20 is used to input the gate voltage. The second terminal of transistor N20 is coupled to the first terminal of transistor N22, and the gate of transistor N22 is used to input the second enable signal (…). Figure 8 (Represented as ENB in ​​the diagram), the second terminal of transistor N22 is coupled to the first terminal of transistor N23. The second terminal of transistor N23 is coupled to the first terminal of transistor N24, and the second terminal of transistor N24 is coupled to the first terminal of resistor R5, with the second terminal of resistor R5 grounded. For the specific connection method of the first gain circuit, please refer to [reference needed]. Figure 8 This will not be elaborated upon here.

[0081] The timing controller is also used to control the number of second gain branches that are turned on, so as to obtain ramp signals with different gains.

[0082] For example, the timing controller can send a first enable signal and a second enable signal to control transistors N21 and N22 to turn on or off, thereby controlling the number of second gain branches connected in parallel in the first gain circuit. The number of second gain branches affects the current at the output of the first gain circuit. Specifically, the more second gain branches there are, the greater the current at the output of the first gain circuit, and the greater the gain of the ramp signal.

[0083] In one possible example, see Figure 7 The second gain circuit and are shown in the figure. Figure 8 The first gain circuit shown in the figure can achieve a gain of 1 to 2 times. The first gain circuit and the adjustable resistor can achieve a gain of 8 to 16 times as well as a fractional gain. The ramp generation circuit as a whole can generate a gain of 1 to 16 times.

[0084] Optionally, the image processing device may also include a third gain circuit, such as Figure 9 As shown, Figure 9 The diagram shows a schematic of another image processing device. The input of the third gain circuit is used to input the pixel signal, and the output of the third gain circuit is coupled to the first input of the analog-to-digital converter. The third gain circuit is used to adjust the pixel signal.

[0085] For example, in addition to amplifying the ramp signal, the image processing device can also amplify the pixel signal, for example by adding a third gain circuit before the first input of the analog-to-digital converter to adjust the pixel signal.

[0086] Optional, please continue reading Figure 9 The third gain circuit includes a first capacitor connected in parallel ( Figure 9 (represented by C4) and multiple capacitor modules ( Figure 9 (Represented by C_1, C_2, and C_3). Taking capacitor module C_1 as an example, the capacitor module includes a first switch ( Figure 9 (represented by S7 in the middle), the second switch ( Figure 9 (represented by S8) and the second capacitor ( Figure 9 (represented by C5 in the diagram). The first terminal of the first switch S7 is coupled to the input terminal of the third gain circuit. The second terminal of the first switch S7 is coupled to the first terminal of the second capacitor C5. The first terminal of the second switch S8 is coupled to the first terminal of the second capacitor C5. The second terminal of the second switch S8 is grounded. The second terminal of the second capacitor C5 is coupled to the output terminal of the third gain circuit.

[0087] For example, the method by which the first capacitor C4 and capacitor module C_1 achieve a gain of 1 to 2 times can be found in [reference needed]. Figure 3 The description will not be repeated here.

[0088] In this embodiment, if capacitor module C_1 achieves a gain of 2x, capacitor module C_2 achieves a gain of 2x, and capacitor module C_3 achieves a gain of 1x, then the third gain circuit can achieve a gain of 3x. If capacitor module C_1 achieves a gain of 2x, capacitor module C_2 achieves a gain of 2x, and capacitor module C_3 achieves a gain of 2x, then the third gain circuit can achieve a gain of 4x. That is to say, Figure 9 The third gain circuit shown can achieve a gain of 1 to 4 times.

[0089] Therefore, the image processing device can guarantee the signal reception range of the analog-to-digital converter, and the gain requirement that the ramp generation circuit needs to achieve is correspondingly reduced. For example, if the third gain circuit can achieve N times the gain, the gain requirement that the ramp generation circuit needs to achieve is reduced by 1 / N times, the power consumption is reduced by N times, and the current adjustment range of the ramp generation circuit is reduced by N times.

[0090] Understandably, the third gain circuit can include a greater number of capacitor modules to achieve greater gain adjustment of the pixel signal.

[0091] Therefore, the image transmission device provided in this application embodiment can implement four gain adjustment methods: clock frequency adjustment gain method implemented by a frequency divider circuit, current adjustment gain method implemented by a first gain circuit, resistance adjustment gain method implemented by a second gain circuit, and capacitor adjustment gain method implemented by a third gain circuit. The image processing device can select at least one gain adjustment method for gain adjustment in different scenarios (such as low noise, low power consumption, and low gain error scenarios), thereby achieving higher energy efficiency.

[0092] Applied to the above-mentioned image processing apparatus, embodiments of this application also provide an image processing method, such as... Figure 10 As shown, Figure 10 The diagram shows a flowchart of an image processing method. This image processing method includes the following steps:

[0093] S1001, the frequency divider circuit receives the first clock signal and generates multiple second clock signals of different frequencies based on the first clock signal.

[0094] S1002 and the timing controller control the ramp generation circuit to generate ramp signals with different gains based on the second clock signal of different frequencies.

[0095] S1003, the analog-to-digital converter compares the pixel signal with the ramp signal at the current gain to obtain the pixel quantization value.

[0096] Therefore, in the image processing method provided in this application embodiment, a frequency divider circuit can divide a first clock signal into multiple second clock signals of different frequencies, and a timing controller can further control a ramp generation circuit to generate a ramp signal with a gain corresponding to the frequency of the second clock signals. In other words, the image processing device can obtain ramp signals with different gains as needed. The ramp signal can serve as a reference signal for the analog-to-digital converter (ADC), and different gain reference signals can be adapted to different signal receiving ranges of the ADC. This effectively converts the output signal of the pixel array of the CIS, improving the performance of the CIS. Furthermore, compared to gain adjustment methods using resistors, capacitors, or current, the gain adjustment method using the frequency of the clock signal in the image processing device results in lower gain error.

[0097] Optionally, the image processing method may further include: a timing controller controlling the number of first gain branches turned on or the resistance value of an adjustable resistor to obtain ramp signals with different gains.

[0098] Optionally, the image processing method may further include: a timing controller controlling the number of activated second gain branches to obtain ramp signals with different gains.

[0099] This application also provides an electronic device, including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program code, including computer instructions. When the one or more processors execute the computer instructions, the electronic device performs the aforementioned method steps to implement the image processing method described in the above embodiments.

[0100] Embodiments of this application also provide a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device performs the aforementioned method steps to implement the image processing method described in the above embodiments.

[0101] Embodiments of this application also provide a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the image processing method executed by the electronic device in the above embodiments.

[0102] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component, or module. The apparatus may include a connected processor and a memory; wherein the memory is used to store computer execution instructions, and when the apparatus is running, the processor may execute the computer execution instructions stored in the memory to cause the chip to execute the image processing methods executed by the electronic devices in the above-described method embodiments.

[0103] In this embodiment, the electronic device, computer storage medium, computer program product or chip are all used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding method provided above, and will not be repeated here.

[0104] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0105] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0106] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0107] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0108] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0109] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An image processing apparatus, characterized in that, The image processing device includes: a ramp generation circuit, a frequency division circuit, a timing controller, and an analog-to-digital converter; The ramp generation circuit is used to generate a ramp signal; The frequency divider circuit is used to receive a first clock signal and generate multiple second clock signals of different frequencies based on the first clock signal. The timing controller is used to control the ramp generation circuit to generate ramp signals with different gains based on second clock signals of different frequencies. The analog-to-digital converter includes a first input terminal and a second input terminal. The first input terminal is used to input a pixel signal, and the second input terminal is used to input the ramp signal. The analog-to-digital converter is used to compare the pixel signal and the ramp signal at the current gain to obtain a pixel quantization value.

2. The image processing apparatus according to claim 1, characterized in that, The gain of the ramp signal and the frequency of the second clock signal are positively correlated.

3. The image processing apparatus according to claim 1 or 2, characterized in that, The ramp generation circuit includes a first gain circuit and a second gain circuit. The output terminal of the first gain circuit is coupled to the input terminal of the second gain circuit, and the output terminal of the second gain circuit is coupled to the second input terminal of the analog-to-digital converter. The first gain circuit is used to generate the ramp signal; The second gain circuit is used to adjust the ramp signal.

4. The image processing apparatus according to claim 3, characterized in that, The second gain circuit includes: an adjustable resistor and multiple first gain branches connected in parallel; The timing controller is also used to control the number of the first gain branches that are turned on and / or the resistance value of the adjustable resistor, so as to obtain the ramp signal with different gains.

5. The image processing apparatus according to claim 3, characterized in that, The first gain circuit includes multiple second gain branches connected in parallel; The timing controller is also used to control the number of the second gain branches that are turned on, so as to obtain the ramp signals with different gains.

6. The image processing apparatus according to any one of claims 1-5, characterized in that, The image processing device also includes a third gain circuit; The input terminal of the third gain circuit is used to input the pixel signal, and the output terminal of the third gain circuit is coupled to the first input terminal of the analog-to-digital converter. The third gain circuit is used to adjust the pixel signal.

7. The image processing apparatus according to claim 6, characterized in that, The third gain circuit includes a first capacitor and multiple capacitor modules connected in parallel. The capacitor module includes a first switch, a second switch, and a second capacitor. The first terminal of the first switch is coupled to the input terminal of the third gain circuit, the second terminal of the first switch is coupled to the first terminal of the second capacitor, the first terminal of the second switch is coupled to the first terminal of the second capacitor, the second terminal of the second switch is grounded, and the second terminal of the second capacitor is coupled to the output terminal of the third gain circuit.

8. An image sensor, characterized in that, The image sensor includes: a pixel array and an image processing device as described in any one of claims 1-7, wherein the pixel array and the image processing device are coupled. The pixel array is used to generate pixel signals.

9. An image processing method, characterized in that, The image processing method is applied to an image processing device, which includes a ramp generation circuit, a frequency divider circuit, a timing controller, and an analog-to-digital converter. The method includes: The frequency divider circuit receives a first clock signal and generates a second clock signal of a different frequency based on the first clock signal; The timing controller controls the ramp generation circuit to generate ramp signals with different gains based on second clock signals of different frequencies. The analog-to-digital converter compares the pixel signal with the ramp signal at the current gain to obtain the pixel quantization value.

10. A computer-readable storage medium, characterized in that, It includes computer instructions that, when executed on an electronic device, cause the electronic device to perform the method described in claim 9.

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