Semiconductor device and preparation method thereof, and electronic equipment
By fabricating a transistor structure with vertical gate electrodes and a semiconductor layer covering the sidewalls in DRAM, the problem of increasing storage density and integration was solved, achieving higher storage cell density and better performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2024-11-20
- Publication Date
- 2026-05-22
AI Technical Summary
How to improve the storage density and integration of semiconductor devices within a limited space, especially the storage cell density and integration of dynamic random access memory (DRAM).
By alternately stacking insulating layers on a substrate and forming holes and trenches with specific structures, a transistor structure with a vertical gate electrode and a semiconductor layer covering the sidewalls of the gate electrode is fabricated, increasing the contact area between the semiconductor layer and the gate electrode, thereby improving the channel width and the control capability of the gate electrode.
In a limited space, the on-state current of transistors is increased, thereby improving the performance of semiconductor devices and enhancing the storage density and integration of memory cells.
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Figure CN122073793A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to, but is not limited to, the field of semiconductor manufacturing, specifically to a semiconductor device and its fabrication method, and an electronic device. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and is widely used in various consumer electronics products, such as computers, mobile phones, and digital cameras. With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Summary of the Invention
[0003] In view of the above, this disclosure provides a semiconductor device and a method for fabricating the same, as well as an electronic device.
[0004] On one hand, embodiments of this disclosure provide a semiconductor device, including:
[0005] Substrate;
[0006] A plurality of memory cell layers are stacked at intervals along a first direction perpendicular to the substrate, each memory cell layer including a plurality of memory cells arranged in an array; each memory cell includes a transistor, the transistor including a gate electrode extending along a second direction parallel to the substrate and a semiconductor layer covering a portion of the gate electrode;
[0007] The gate electrode includes a body and a first end and a second end opposite to each other along the second direction; the semiconductor layer covers the first end of the gate electrode and surrounds at least a portion of the sidewalls of the gate electrode; the first direction and the second direction are perpendicular.
[0008] In some embodiments, the semiconductor device further includes:
[0009] Multiple bit lines extending along the first direction, each bit line being connected to a semiconductor layer covering the first end of the gate electrode in a plurality of memory cells arranged along the first direction;
[0010] Multiple word lines extending along a third direction parallel to the substrate, each word line being connected to the second end of the gate electrode of a plurality of memory cells arranged along the third direction in the same memory cell layer;
[0011] Wherein, the first direction is perpendicular to the third direction, and the second direction intersects the third direction.
[0012] In some embodiments, along the second direction, two adjacent memory cells and the two bit lines between the memory cells are symmetrically distributed.
[0013] In some embodiments, the storage unit further includes a storage structure;
[0014] The semiconductor layer has an arcuate side surface on the portion of the transistor along the third direction, and the transistor is connected to the memory structure through the arcuate side surface.
[0015] In some embodiments, the storage structure includes a first electrode, a dielectric layer, and a second electrode; wherein the first electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode connecting the first sub-electrode and the second sub-electrode, the third sub-electrode extending along the first direction and having opposing inner and outer sidewalls.
[0016] The second electrode covers the inner wall of the dielectric layer;
[0017] The dielectric layer covers the inner wall of the third sub-electrode and the entire surface of the first and second sub-electrodes; the outer wall of the third sub-electrode is in contact with the arcuate side surface.
[0018] In some embodiments, the first electrodes of the plurality of memory cells arranged along the first direction are spaced apart along the first direction;
[0019] The dielectric layers of the plurality of memory cells arranged along the first direction are interconnected, and the second electrodes are interconnected.
[0020] In some embodiments, the semiconductor device further includes an isolation layer located between the semiconductor layer and the word line, and between the memory structure and the word line;
[0021] The isolation layer surrounds a portion of the sidewall of the gate electrode.
[0022] In some embodiments, the dimension of the storage structure along the second direction is smaller than the sum of the dimensions of the semiconductor layer and the isolation layer along the second direction.
[0023] In some embodiments, the transistor further includes a gate insulating layer located at least between the gate electrode and the semiconductor layer.
[0024] On the other hand, embodiments of this disclosure provide a method for fabricating a memory device, comprising:
[0025] Provide substrate;
[0026] A stacked layer is formed by alternately stacking a first insulating layer and a second insulating layer on the substrate along a first direction perpendicular to the substrate;
[0027] A first hole and a first trench are formed through the stacked layers; wherein the first hole is located on opposite sides of the first trench along a second direction parallel to the substrate surface, and the first trench extends along a third direction parallel to the substrate surface;
[0028] A bit line extending along the first direction is formed through the first trench;
[0029] A storage structure is formed in the first hole;
[0030] A second trench is formed that penetrates the stacked layer and extends along the third direction; wherein the second trench is located on opposite sides of the first hole along the second direction;
[0031] The second insulating layer is removed along the second trench to expose the bit line and the memory structure, forming a plurality of first gaps spaced apart along the first direction and extending along the second direction;
[0032] A semiconductor layer and a gate electrode are sequentially formed in the first gap to form a plurality of transistors stacked at intervals along the first direction; the gate electrode includes a body and a first end and a second end opposite to each other along the second direction; the semiconductor layer covers the first end of the gate electrode and surrounds at least a portion of the sidewalls of the gate electrode;
[0033] Wherein, the first direction is perpendicular to the second direction and perpendicular to the third direction, and the second direction intersects the third direction.
[0034] In some embodiments, forming a bit line extending along the first direction through the first trench includes:
[0035] A first sacrificial layer is formed in the first trench;
[0036] A portion of the first sacrificial layer is removed to form a plurality of second holes spaced apart along the third direction;
[0037] A first conductive layer is formed in the second hole;
[0038] Remove the first conductive layer located at the bottom of the second hole;
[0039] A third insulating layer covering the first conductive layer is formed in the second hole;
[0040] Remove the first sacrificial layer between adjacent second holes to form a plurality of third holes spaced apart along the third direction, so as to expose the first conductive layer;
[0041] A portion of the first conductive layer is removed along the third hole, and the remaining portion of the first conductive layer located on the two opposite sidewalls of the third insulating layer along the second direction constitutes the bit line.
[0042] In some embodiments, forming the storage structure in the first hole includes:
[0043] Based on the removal of part of the second insulating layer through the first hole, a second gap is formed that is spaced apart along the first direction;
[0044] A second conductive layer is formed in the first hole and the second void;
[0045] Remove the second conductive layer located in the first hole, and the remaining second conductive layer located in the second gap constitutes the first electrode;
[0046] Based on the first hole, the first insulating layer is etched to form a third gap that is spaced apart along the first direction;
[0047] A dielectric layer and a second electrode are formed in the first hole, the second gap, and the third gap; wherein the second electrode covers the inner sidewall of the dielectric layer, and the dielectric layer covers the inner sidewall of the first electrode as well as the inner sidewall of the first hole and the third gap.
[0048] In some embodiments, forming a plurality of transistors stacked at intervals along the first direction includes:
[0049] A fourth hole is formed through the stacked layer, the fourth hole being located between adjacent bit lines along the third direction;
[0050] A fourth insulating layer is formed in the fourth hole; the material of the fourth insulating layer is different from the material of the second insulating layer.
[0051] The second trench is formed, and the second insulating layer is removed along the second trench to form a first gap spaced apart along the first direction, so as to expose the fourth insulating layer.
[0052] Semiconductor material, gate insulating material, and gate electrode material are sequentially deposited in the first gap;
[0053] A portion of the semiconductor material, a portion of the gate insulating material, and a portion of the gate electrode material are removed along the second direction to form a semiconductor layer, a gate insulating layer, and a gate electrode, respectively; the gate insulating layer is located at least between the gate electrode and the semiconductor layer; the semiconductor layer has an arcuate side surface on one side of the transistor along the third direction.
[0054] In some embodiments, the method further includes:
[0055] A fifth insulating layer is formed at locations where a portion of the semiconductor material, a portion of the gate insulating material, and a portion of the gate electrode material are removed;
[0056] Remove part of the fifth insulating layer to expose the gate electrode;
[0057] Conductive material is deposited at least at the location where a portion of the fifth insulating layer is removed to form initial word lines, and the initial word lines located on the sidewalls of the first insulating layer are removed to form word lines extending along the third direction and spaced apart along the first direction.
[0058] On the other hand, embodiments of this disclosure provide an electronic device, including the semiconductor device provided in any of the above embodiments, or a semiconductor device manufactured according to the method of the semiconductor device provided in any of the above embodiments.
[0059] The transistor in the semiconductor device provided in this disclosure includes a gate electrode extending along a second direction parallel to the substrate and a semiconductor layer covering a portion of the gate electrode; wherein the gate electrode includes a body and a first end and a second end opposite to each other along the second direction; the semiconductor layer covers the first end of the gate electrode and surrounds at least a portion of the sidewalls of the gate electrode. This increases the contact area between the semiconductor layer and the gate electrode, effectively increasing the channel width and thus the on-state current of the transistor, while also improving the gate electrode's control over the channel, effectively improving the performance of the semiconductor device within a limited space. Attached Figure Description
[0060] Figure 1 This is a schematic diagram illustrating the specific implementation process of a method for fabricating a semiconductor device according to an embodiment of the present disclosure;
[0061] Figure 2 A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 1 ;
[0062] Figure 3 for Figure 2 The diagram shows cross-sectional views along the tangents AA', BB', CC', and DD' directions.
[0063] Figure 4 A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 2 ;
[0064] Figure 5 for Figure 4 The diagram shows cross-sectional views along the tangents AA', BB', CC', and DD' directions.
[0065] Figure 6 A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 3 ;
[0066] Figure 7 for Figure 6 The cross-sectional schematic diagram shown is along the tangents AA', BB', CC' and DD' directions;
[0067] Figure 8 A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 4 ;
[0068] Figure 9 for Figure 8 The cross-sectional schematic diagram shown is along the tangents AA', BB', CC' and DD' directions;
[0069] Figure 10 A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 5 ;
[0070] Figure 11 for Figure 10 The cross-sectional schematic diagram shown is along the tangents AA', BB', CC' and EE' directions;
[0071] Figure 12 A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 6 ;
[0072] Figure 13 for Figure 12 The cross-sectional schematic diagram shown is along the tangents AA', BB', CC' and EE' directions;
[0073] Figure 14A When forming the third gap and Figure 13 A cross-sectional view of the location corresponding to the EE' direction in the middle;
[0074] Figure 14B for Figure 14A Enlarged view of the structure within the dashed box in the cross-sectional schematic diagram along the EE' direction;
[0075] Figure 15 A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 7 ;
[0076] Figure 16A for Figure 15 The cross-sectional schematic diagram shown is along the tangent AA' direction, BB' direction, CC' direction and EE' direction;
[0077] Figure 16B for Figure 16A Enlarged view of the structure within the dashed box in the cross-sectional schematic diagram along the EE' direction;
[0078] Figure 17 A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 8 ;
[0079] Figure 18 for Figure 17 The cross-sectional schematic diagram shown is along the tangent AA' direction, BB' direction, CC' direction and EE' direction;
[0080] Figure 19 A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 9 ;
[0081] Figure 20 for Figure 19 The cross-sectional schematic diagram shown is along the tangents AA', BB', CC' and EE' directions;
[0082] Figure 21 A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 10 ;
[0083] Figure 22A for Figure 21 The cross-sectional schematic diagram shown is along the tangents AA', BB', CC' and EE' directions;
[0084] Figure 22B for Figure 22A Enlarged view of the structure within the dashed box in the cross-sectional schematic diagram along the CC' direction;
[0085] Figure 23A A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 10 one;
[0086] Figure 23B for Figure 23A The diagram shows a three-dimensional structure of the semiconductor device after some insulating material has been removed.
[0087] Figure 24A for Figure 23A The cross-sectional schematic diagram shown is along the tangents AA', BB', CC' and EE' directions;
[0088] Figure 24B for Figure 24A A cross-sectional view along the AA' direction, enlarged view of the structure within the dashed box;
[0089] Figure 24C for Figure 24A A cross-sectional view along the CC' direction, enlarged view of the structure within the dashed box. Detailed Implementation
[0090] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0091] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise scale, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0092] In this disclosure, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order, sequence, quantity, or importance.
[0093] In the embodiments of this disclosure, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" may be used to describe the positional relationships of the constituent elements with reference to the accompanying drawings. These terms are used solely for ease of description and simplification and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this disclosure. The positional relationships and orientations of the constituent elements may change depending on the placement direction of each constituent element.
[0094] In this embodiment of the disclosure, "parallel" means approximately parallel or nearly parallel, and the included angle between the two elements defined therein may be within the allowable range of process tolerance. Similarly, "perpendicular" means approximately perpendicular or nearly perpendicular, and the included angle between the two elements defined therein may be an error angle relative to a 90° right angle that is within the allowable range of process tolerance.
[0095] In the embodiments of this disclosure, "integrated structure" can refer to a structure in which A and B have no obvious boundary interface such as discontinuity or gap in their microstructure. Generally, a film layer patterned on a single film layer to form a connected structure is considered integrated. For example, A and B are formed using the same material to form a single film layer and are simultaneously formed into a structure with a connection relationship through the same patterning process.
[0096] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict. In the methods involved in the embodiments of this disclosure, unless otherwise specified or described, the execution order of each step can be adjusted according to actual circumstances or needs. That is, different combinations of the sequences of steps involved in the embodiments of this disclosure all fall within the protection scope of this disclosure.
[0097] The transistor involved in the embodiments of this disclosure refers to a device that includes at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode). The gate can control the conductivity of the channel region, thereby enabling current to flow between the source, the channel region, and the drain based on gate control.
[0098] The deposition processes involved in the embodiments of this disclosure include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.
[0099] The growth processes described in this disclosure include, but are not limited to: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), ion beam epitaxy, solid phase epitaxy, and combinations thereof.
[0100] The etching processes described in this disclosure include, but are not limited to, dry etching, wet etching, and combinations thereof.
[0101] With the rapid development of semiconductor manufacturing technology, the requirements for storage capacity of various products are constantly increasing. How to further improve the storage density and integration of semiconductor devices has become an urgent problem to be solved.
[0102] Based on this, the present disclosure provides a method for fabricating a semiconductor device. Figure 1 This is a schematic diagram illustrating the specific implementation flow of a semiconductor device fabrication method provided in an embodiment of this disclosure. For example... Figure 1 As shown, the specific steps of the fabrication method for this semiconductor device include:
[0103] Step S10: Provide a substrate;
[0104] Step S20: Alternately stack a first insulating layer and a second insulating layer on the substrate along a first direction perpendicular to the substrate to form a stacked layer;
[0105] Step S30: Form the first hole and the first trench through the stacked layers;
[0106] Step S40: Form a bit line extending in the first direction through the first trench;
[0107] Step S50: Form a storage structure in the first hole;
[0108] Step S60: Form a second trench that penetrates the stacked layers and extends along a third direction;
[0109] Step S70: Remove the second insulating layer along the second trench to expose the bit lines and storage structure, forming a plurality of first gaps spaced apart along the first direction and extending along the second direction;
[0110] Step S80: A semiconductor layer and a gate electrode are sequentially formed in the first gap to form a plurality of transistors stacked at intervals along the first direction.
[0111] The first direction is perpendicular to the second direction, and is perpendicular to the third direction. The second direction intersects with the third direction.
[0112] It should be understood that Figure 1 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 1 The steps shown can be adjusted in order according to actual needs.
[0113] It should be noted that, here and below, the first direction can be the direction in which the bit line extends, the second direction can be the direction in which the gate electrode extends, and the third direction can be the direction in which the word line extends. Both the second direction and the third direction are perpendicular to the first direction. The second direction and the third direction intersect each other; in some specific embodiments, the second direction is perpendicular to the third direction. For example, the first direction can be the extension direction of the Z-axis shown in the figures, the second direction can be the extension direction of the Y-axis shown in the figures, and the third direction can be the extension direction of the X-axis shown in the figures.
[0114] Please refer to the following. Figures 2 to 24C The process of fabricating the semiconductor device provided in the embodiments of this disclosure will be further described in detail.
[0115] like Figure 2 and Figure 3As shown, a substrate 100 is provided, and a stacked layer 103 is formed by alternately stacking a first insulating layer 101 and a second insulating layer 102 along a first direction perpendicular to the substrate 100. Exemplarily, the substrate 100 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as silicon-germanium-on-insulator (SGOI), etc.
[0116] In some embodiments, the process of forming the first insulating layer 101 and the second insulating layer 102 may include any process known in the art, including but not limited to CVD, PVD, sputtering, and ALD.
[0117] Here, the first insulating layer 101 and the second insulating layer 102 may be partially retained or not retained in the final formed memory device, for example, replaced with other materials, or formed into other specific structures. Exemplarily, the materials of the first insulating layer 101 and the second insulating layer 102 may be silicon oxide and silicon nitride, respectively.
[0118] In some embodiments, a first hole and a first trench are formed through the stacked layers; wherein the first hole is located on opposite sides of the first trench along a second direction parallel to the substrate surface, and the first trench extends along a third direction parallel to the substrate surface.
[0119] After the stacked layers are formed, the stacked layers can be patterned to form the first hole and the first trench. That is, the material of the stacked layer 103 in the area where the first hole and the first trench are located is removed by etching process, thereby forming the first hole and the first trench that penetrate the stacked layers.
[0120] It should be noted that the first hole and the first trench can be formed in the same etching process or in different etching processes. This embodiment will be illustrated using the example of the first hole and the first trench being formed in different etching processes.
[0121] In some embodiments, a first trench is formed through the stacked layer 103. Figure 2 and Figure 3 (not shown in the image); wherein the first trench extends along a third direction parallel to the surface of the substrate 100.
[0122] For example, one or more first trenches may be formed in the stacked layer 103. If multiple first trenches are included, these first trenches extend along the third direction X and are distributed in parallel at intervals in the second direction Y, with a certain distance between any two adjacent first trenches.
[0123] In some embodiments, a first sacrificial material is deposited in a first trench, and a chemical mechanical polishing (CMP) operation is performed on the first sacrificial material to form a first sacrificial layer 104.
[0124] In some implementations, the material of the first sacrificial layer 104 includes, but is not limited to, polysilicon.
[0125] refer to Figures 4 to 5 Part of the first sacrificial layer is removed to form multiple second holes spaced apart along the third direction.
[0126] In some embodiments, a plurality of second holes 107 are formed by using a patterning process, which penetrate the first sacrificial layer 104 and are spaced apart along a third direction.
[0127] In some embodiments, such as Figure 4 and Figure 5 As shown, a first conductive layer 105 and a second sacrificial layer 106 are formed in the second hole 107.
[0128] In some embodiments, the material of the first conductive layer 105 may be a metal or a metal nitride containing a metal, or the main component may be a metal, such as a single metal or alloy or metal nitride selected from W, Ti, Al, etc. For example, the material of the first conductive layer 105 is titanium nitride (TiN).
[0129] In some implementations, the material of the second sacrificial layer 106 includes, but is not limited to, polysilicon.
[0130] like Figure 6 and Figure 7 As shown, the second sacrificial layer and part of the first conductive layer are removed, leaving the first conductive layer located on the sidewall of the second hole. For example, the second sacrificial layer and the first conductive layer located at the bottom of the second hole 107 are removed by a dry etching process, and the second sacrificial layer located on the sidewall of the second hole 107 is removed by a wet etching process, leaving only the first conductive layer 105 located on the sidewall of the second hole 107.
[0131] like Figure 8 and Figure 9As shown, a third insulating layer covering the first conductive layer is formed in the second hole; the first sacrificial layer between adjacent second holes is removed to form a plurality of third holes spaced apart along the third direction to expose a portion of the first conductive layer; a portion of the first conductive layer is removed along the third hole, and the remaining first conductive layers located on the two opposite sidewalls of the third insulating layer along the second direction constitute bit lines.
[0132] Exemplarily, an insulating material is deposited in the second hole, the insulating material at least filling the second hole and covering the stacked layer 103 to form a third insulating layer 109. Here, the insulating material includes, but is not limited to, silicon oxide. A CMP operation is performed on the third insulating layer 109 until the surface of the first sacrificial layer 104 is exposed, the first sacrificial layer 104 is removed, and a plurality of third holes 110 spaced apart along a third direction are formed to expose portions of the first conductive layer.
[0133] In some embodiments, a first sacrificial layer between adjacent second holes is removed by a wet etching process to form a third hole 110.
[0134] A portion of the first conductive layer is removed by a wet etching process along the third hole 110, and the remaining first conductive layer located on the two opposite sidewalls of the third insulating layer along the second direction forms a bit line 108 extending along the first direction.
[0135] refer to Figures 10 to 15 The storage structure is formed in the first hole.
[0136] like Figure 10 and Figure 11 As shown, a sixth insulating layer 111 is formed, at least covering the second hole and the stacked layer; a first hole 121 is formed penetrating the sixth insulating layer 111 and the stacked layer 103, the first hole 121 being located on opposite sides of the first trench along a second direction parallel to the substrate surface. Reference can be found here. Figure 2 and Figure 3 The location of the first sacrificial layer 104 is used to understand the location of the first trench, and further to understand the location of the first hole 121.
[0137] By removing part of the second insulating layer 102 based on the first hole 121, a second gap 122 is formed that is spaced apart along the first direction.
[0138] Figure 12 and Figure 13 A second conductive layer and a third sacrificial layer 124 are formed in the first hole 121 and the second gap 122. The second conductive layer covers the inner sidewalls of the second gap and the first hole, and the third sacrificial layer 124 covers the inner sidewalls of the second conductive layer. The third sacrificial layer 124 and the second conductive layer located in the first hole 121 are removed, and the second conductive layer remaining in the second gap 122 constitutes the first electrode 123.
[0139] For example, a wet etching process is used to remove the third sacrificial layer 124 and the second conductive layer located in the first hole 121.
[0140] In some embodiments, the material of the second conductive layer can be the same as that of the first conductive layer; for example, the material of the second conductive layer is titanium nitride.
[0141] Figure 14B yes Figure 14A Enlarged view of the structure within the dashed box, as shown below. Figure 14A and Figure 14B As shown, the first insulating layer 101 is etched based on the first hole 121 to form a third gap 120 spaced apart along the first direction; the third sacrificial layer in the second gap 122 is removed.
[0142] like Figure 15 and Figure 16A As shown, a dielectric layer 125 and a second electrode 126 are formed in the first hole 121, the second gap 122 and the third gap 120 shown in 14B.
[0143] Figure 16B yes Figure 16A Enlarged view of the structure within the dashed box, as shown below. Figure 16B As shown, the second electrode 126 covers the inner wall of the dielectric layer 125, and the dielectric layer 125 covers the inner wall of the first electrode 123 as well as the inner walls of the first hole and the third gap. The first electrode 123, the dielectric layer 125, and the second electrode 126 constitute a storage structure.
[0144] In some embodiments, the memory structure further includes a conductive layer 127, which can serve as a common electrode of the memory structure. Exemplarily, the material of the conductive layer 127 includes, but is not limited to, polycrystalline silicon.
[0145] It should be noted that, Figure 16A The diagram only provides a simplified representation of the memory structure. The positional relationships between the first electrode, dielectric layer, and second electrode of the memory structure can be found in the reference diagram. Figure 16B To understand.
[0146] In some embodiments, the dielectric layer 125 can be made of a high-k dielectric (High-K, HK) insulating material, such as a dielectric material with a dielectric constant K greater than or equal to 3.9. Examples include, but are not limited to, high-k materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2). The material of the second electrode 126 includes, but is not limited to, titanium nitride. The material of the conductive layer 127 includes, but is not limited to, tungsten (W), cobalt (Co), and nickel (Ni).
[0147] refer to Figures 17 to 22BThis forms multiple transistors stacked at intervals along a first direction.
[0148] like Figure 17 and Figure 18 As shown, a seventh insulating layer is formed covering the stacked layer 103, and a fourth hole 128 is formed through the seventh insulating layer and the stacked layer 103 by a patterning process. The fourth hole 128 is located between adjacent bit lines 108 along the third direction.
[0149] In some implementations, the fourth hole 128 exposes a portion of the first electrode 123 of the storage structure.
[0150] In some embodiments, a portion of the second insulating layer 102 is removed along the fourth hole 128 to form a plurality of fourth gaps 129 spaced apart along the first direction.
[0151] like Figure 19 and Figure 20 As shown, insulating material is deposited into the fourth hole and the fourth void to form a fourth insulating layer 130; the material of the fourth insulating layer 130 is different from the material of the second insulating layer.
[0152] For example, the fourth insulating layer 130 is made of silicon oxide, and the second insulating layer 102 is made of silicon nitride.
[0153] In some embodiments, a second trench 131 is formed that penetrates the stacked layer and extends along a third direction, wherein the second trench is located on opposite sides of the first hole along a second direction to avoid damage to the storage structure already formed in the first hole.
[0154] In some embodiments, a portion of the second insulating layer 102 is removed along the second trench 131 to form first gaps 132 spaced apart along a first direction, thereby exposing the fourth insulating layer 130. Since the material of the fourth insulating layer 130 is different from that of the second insulating layer, the fourth insulating layer 130 can be used as a stop layer when the portion of the second insulating layer 102 is removed to form the first gaps 132.
[0155] In some embodiments, a CMP operation may be performed on the fourth insulating layer 130 before the second trench 131 is formed.
[0156] refer to Figures 21 to 22B Semiconductor material, gate insulating material, and gate electrode material are sequentially deposited in the first gap; then, a portion of the semiconductor material, a portion of the gate insulating material, and a portion of the gate electrode material are removed along the second direction to form [the desired structures]. Figure 22B The diagram shows a semiconductor layer 133, a gate insulating layer 134, and a gate electrode 135; the gate insulating layer 134 is located at least between the gate electrode 135 and the semiconductor layer 133. The gate insulating layer 134 and the gate electrode 135 constitute the gate structure of a transistor.
[0157] here, Figure 22B for Figure 22A Enlarged view of the structure within the dashed box 136 in the cross-sectional schematic diagram along the CC' direction.
[0158] In some embodiments, the semiconductor layer has an arcuate side surface on the portion of the transistor along the third direction.
[0159] In some embodiments, the semiconductor layer material includes at least one of indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), and indium zinc oxide (IZO).
[0160] When the semiconductor layer material is IGZO, the transistor leakage current is relatively small (leakage current less than or equal to 10). -15A), thus ensuring a low refresh rate for the dynamic access memory. It should be noted that the semiconductor layer material can be In2O3 (Indium Oxide), SnO2 (Tin Dioxide), TiOx (Tin Dioxide), ZnxOyNz (Zinc Nitride Oxide), MgxZnyOz (Magnesium Zinc Oxide), ZrxInyZnzOa (Zirconium Indium Zinc Oxide), HfxInyZnzOa (Hafnium Indium Zinc Oxide), SnxInyZnzOa (Tin Indium Zinc Oxide), AlxSnyInzZnaOd (Aluminum Tin Indium Zinc Oxide), SixInyZnzOa (Silicon Indium Zinc Oxide), and ZnxSnyOz (Zinc Tin Indium Zinc Oxide). Materials such as zinc tin oxide (ZTI), AlxZnySnzOa (Aluminum Indium Tin Oxide), GaxZnySnzOa (Gallium Indium Tin Oxide), ZrxZnySnzOa (Zirconium Indium Tin Oxide), InGaSiO (Indium Gallium Silicon Oxide), IAZO (Indium Aluminum Zinc Oxide), and IGO (Indium Gallium Oxide) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.
[0161] Furthermore, the gate insulating layer 134 can be made of a high-k dielectric (High-K, HK) insulating material, such as a dielectric material with a dielectric constant K greater than or equal to 3.9. Examples include, but are not limited to, high-k materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2).
[0162] The material of the gate electrode 135 can be any of the conductive materials used in the memory structure that forms the memory cell, as described above, and will not be elaborated here.
[0163] It should be noted that, Figure 20 and Figure 22A The dashed box shown is only used to indicate the location where the second trench 131 is formed; in actual semiconductor devices, this dashed box does not exist.
[0164] refer to Figure 23A , Figure 23B , Figure 24A , Figure 24B and Figure 24C The method further includes: forming a fifth insulating layer at locations where a portion of the semiconductor material, a portion of the gate insulating material, and a portion of the gate electrode material are removed; removing a portion of the fifth insulating layer to expose the gate electrode; depositing a conductive material at least at locations where a portion of the fifth insulating layer is removed to form initial word lines; and removing the initial word lines located on the sidewalls of the first insulating layer to form word lines extending along the third direction and spaced apart along the first direction.
[0165] Figure 24B for Figure 24A A cross-sectional view along the AA' direction, with an enlarged view of the structure within the dashed box 139; Figure 24C for Figure 24A A cross-sectional view along the CC' direction, enlarged view of the structure within the dashed box 140. (See attached image.) Figure 24B and Figure 24C As shown, the gate electrode of the transistor includes a body 135-3 and a first end 135-1 and a second end 135-2 opposite to each other along the second direction; a semiconductor layer covers the first end 135-1 of the gate electrode and surrounds at least a portion of the sidewalls of the gate electrode.
[0166] In some implementations, such as Figure 24B and Figure 24C As shown, the semiconductor layer includes a first sub-semiconductor layer 133-1 covering the first end 135-1 of the gate electrode and a second sub-semiconductor layer 133-2 surrounding at least a portion of the sidewalls of the gate electrode body 135-3. The first sub-semiconductor layer 133-1 is in contact with the bit line 108.
[0167] In some embodiments, the semiconductor layer has an arcuate side on the side of the transistor along a third direction. Specifically, the second sub-semiconductor layer 133-2 of the semiconductor layer has an arcuate side, and the transistor is connected to the first electrode 123 of the storage structure through the arcuate side.
[0168] The semiconductor layer of the transistor covers the first end of the gate electrode and surrounds at least part of the sidewall of the gate electrode, increasing the contact area between the semiconductor layer and the gate electrode. This can increase the effective channel width, thereby increasing the on-state current of the transistor, and also improve the gate electrode's control over the channel.
[0169] In some implementations, the fifth insulating layer may be made of silicon oxide.
[0170] In some embodiments, a portion of the fifth insulating layer is removed to expose the second end 135-2 of the gate electrode, and conductive material is deposited from the exposed second end 135-2 of the gate electrode to form an initial word line. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), gold (Au), silver (Ag), nickel (Ni), etc.
[0171] The aforementioned initial word lines include a first initial word line and a second initial word line extending along the third direction and alternately arranged in the first direction. The first initial word line is located at the second end 135-2 of the gate electrode, and the second initial word line is located on the sidewall of the first insulating layer. The second initial word line and a portion of the first initial word line are removed to disconnect the gate electrodes of the transistors arranged along the first direction in different layers from each other. The remaining portion of the first initial word line located at the second end 135-2 of the gate electrode constitutes a word line 137 extending along the third direction.
[0172] In some implementations, the second initial word line and part of the first initial word line can be removed by a wet etching process.
[0173] It should be noted that in some embodiments, the initial character lines are layered on the XZ plane, that is, the first initial character line and the second initial character line are an integral structure. The distinction between the first initial character line and the second initial character line is to more clearly describe the formation process of the character lines.
[0174] The embodiments disclosed herein achieve shared bit lines for memory cells in different layers by forming a plurality of transistors stacked at intervals along a first direction, a plurality of vertical bit lines extending along the first direction, and a horizontal word line extending along a third direction. This facilitates 3D stacking, improves the integration of semiconductor devices, and significantly reduces the number of bit lines, thereby reducing the coupling capacitance between bit lines.
[0175] In some embodiments, the method for fabricating a semiconductor device further includes: depositing an insulating material into a second trench and a first void, and performing a CMP operation on the insulating material to form an isolation structure, the isolation structure including an isolation layer located between the semiconductor layer 133 and the word line 137 and between the memory structure 141 and the word line 137.
[0176] It should be noted that the aforementioned elements such as the first trench, second trench, first hole, second hole, and third hole only appear as "holes" or "trenches" at certain stages of the manufacturing process. In other stages and in the final formed memory device, the aforementioned "holes" and "trenches" will be partially or completely filled with solid structures. Therefore, in the embodiments of this disclosure, the aforementioned "holes" and "trenches" can be understood as defining areas or locations.
[0177] The gate electrode of the transistor formed in this embodiment includes a body and a first end and a second end opposite to each other along a second direction. The semiconductor layer of the transistor covers the first end of the gate electrode and surrounds at least a portion of the sidewall of the gate electrode, increasing the contact area between the semiconductor layer and the gate electrode. This increases the effective channel width, thereby increasing the on-state current of the transistor, and also improves the gate electrode's control over the channel. Thus, the performance of the semiconductor device is effectively improved in a limited space.
[0178] This disclosure also provides a semiconductor device, comprising: a substrate; a plurality of memory cell layers stacked at intervals along a first direction perpendicular to the substrate, each memory cell layer including a plurality of memory cells arranged in an array; each memory cell including a transistor, the transistor including a gate electrode extending along a second direction parallel to the substrate and a semiconductor layer covering a portion of the gate electrode; wherein the gate electrode includes a body and a first end and a second end opposite to each other along the second direction; the semiconductor layer covers the first end of the gate electrode and surrounds at least a portion of the sidewall of the gate electrode; the first direction and the second direction are perpendicular.
[0179] Figure 23B for Figure 23A The diagram shows a three-dimensional structure of a semiconductor device after some insulating material has been removed, to more clearly illustrate the relationship between different structures in the formed semiconductor device.
[0180] refer to Figure 23B , Figure 24A , Figure 24B and Figure 24C The semiconductor device includes: a substrate; a plurality of memory cell layers stacked at intervals along a first direction perpendicular to the substrate, each memory cell layer including a plurality of memory cells arranged in an array; each memory cell including a transistor, the transistor including a gate electrode extending along a second direction parallel to the substrate and a semiconductor layer 133 covering a portion of the gate electrode; wherein the gate electrode includes a body 135-3 and a first end 135-1 and a second end 135-2 opposite to each other along a third direction; the semiconductor layer covers the first end 135-1 of the gate electrode and surrounds at least a portion of the sidewall of the gate electrode; the first direction and the second direction are perpendicular.
[0181] In some embodiments, the semiconductor device further includes: a plurality of bit lines 108 extending along a first direction; each bit line 108 being connected to a semiconductor layer covering a first end of the gate electrode in a plurality of memory cells arranged along the first direction; a plurality of word lines 137 extending along a third direction parallel to the substrate; each word line being connected to a second end 135-2 of the gate electrode of a plurality of memory cells arranged along a third direction in the same memory cell layer.
[0182] In some embodiments, such as Figure 23BAs shown, along the second direction, two adjacent memory cells and two bit lines 108 between memory cells are symmetrically distributed, thereby achieving a more compact layout, saving planar space to increase storage density, and shortening the signal path, which can reduce parasitic capacitance and help improve signal transmission speed.
[0183] In some embodiments, the storage unit further includes Figure 23B The storage structure shown is 141.
[0184] In some embodiments, each memory structure is located on the same side of the corresponding transistor along the second direction, which helps to reduce parasitic capacitance between adjacent memory structures and can optimize the electric field distribution.
[0185] In some embodiments, the semiconductor layer has an arcuate side surface on the third-direction side of the transistor, and the transistor is connected to the memory structure via the arcuate side surface. For example, as... Figure 24B As shown, the arc-shaped side surface of the second sub-semiconductor layer 133-2 of the semiconductor layer is connected to the first electrode 123 of the memory structure. The arc-shaped side surface of the semiconductor layer can effectively increase the contact area between the semiconductor layer and the memory structure, thereby improving device performance.
[0186] In some embodiments, the storage structure includes a first electrode, a dielectric layer, and a second electrode; wherein the first electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode connecting the first sub-electrode and the second sub-electrode, the third sub-electrode extending along a first direction and having opposing inner and outer sidewalls; the second electrode covers the inner sidewall of the dielectric layer; the dielectric layer covers the inner sidewall of the third sub-electrode and the entire surfaces of the first and second sub-electrodes; the outer sidewall of the third sub-electrode contacts an arcuate side surface.
[0187] like Figure 16B As shown, the storage structure includes a first electrode 123, a dielectric layer 125, and a second electrode 126. The first electrode 123 includes a first sub-electrode 123-1, a second sub-electrode 123-2, and a third sub-electrode 123-3 connecting the first sub-electrode 123-1 and the second sub-electrode 123-2. The third sub-electrode 123-3 extends along a first direction and has opposing inner and outer sidewalls. The second electrode 126 covers the inner sidewall of the dielectric layer 125. The dielectric layer 125 covers the inner sidewall of the third sub-electrode 123-3 and the entire surface of the first sub-electrode 123-1 and the second sub-electrode 123-2. The structural arrangement of the first electrode 123, dielectric layer 125, and second electrode in the above storage structure increases the contact area between the first electrode 123 and the dielectric layer 125, as well as between the dielectric layer 125 and the second electrode 126, thereby improving the capacitance of the storage structure.
[0188] Reference Figure 24BThe outer wall of the third sub-electrode of the first electrode 123 is in contact with the arc-shaped side surface.
[0189] In some embodiments, the first electrodes of a plurality of memory cells arranged along a first direction are spaced apart along the first direction; the dielectric layers of the plurality of memory cells arranged along the first direction are interconnected, and the second electrodes are interconnected. For example, as... Figure 16B As shown, the first electrodes 123 of a plurality of memory cells arranged along the first direction are spaced apart along the first direction, and the dielectric layers 125 of the plurality of memory cells arranged along the first direction are interconnected, and the second electrodes 126 are interconnected. In this way, the memory structure of different memory cells can be independently controlled by the spaced first electrodes.
[0190] In some embodiments, the semiconductor device further includes an isolation layer located between the semiconductor layer and the word line and between the memory structure and the word line, for preventing short circuits between the semiconductor layer and the word line and between the memory structure and the word line.
[0191] In some embodiments, the dimension of the memory structure along a third direction is smaller than the sum of the dimensions of the semiconductor layer and the isolation layer along the second direction. For example, as... Figure 24B As shown, W1 is the dimension of the memory structure along the second direction, and W2 is the sum of the dimensions of the semiconductor layer and the isolation layer along the second direction. W1 is smaller than W2 to effectively utilize the planar space, set up a memory structure with a larger capacitance, and at the same time ensure that the memory structure is not easily short-circuited with other structures (such as bit lines or word lines).
[0192] In some embodiments, the material of the semiconductor layer includes at least one of indium gallium zinc oxide, indium tin oxide, indium gallium zinc tin oxide, or indium tungsten oxide.
[0193] In some embodiments, such as Figure 24B and Figure 24C As shown, the transistor also includes a gate insulating layer 134, which is located at least between the gate electrode and the semiconductor layer.
[0194] The transistor in the semiconductor device provided in this disclosure includes a gate electrode extending along a second direction parallel to the substrate and a semiconductor layer covering a portion of the gate electrode; wherein the gate electrode includes a body and a first end and a second end opposite to each other along the second direction; the semiconductor layer covers the first end of the gate electrode and surrounds at least a portion of the sidewalls of the gate electrode. This increases the contact area between the semiconductor layer and the gate electrode, effectively increasing the channel width and thus the on-state current of the transistor, while also improving the gate electrode's control over the channel, effectively improving the performance of the semiconductor device within a limited space.
[0195] Based on the same inventive concept, this disclosure also provides an electronic device, which includes the semiconductor device provided in any of the above embodiments, or a semiconductor device prepared according to the method of the semiconductor device provided in any of the above embodiments. The electronic device may be: a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.
[0196] It should be understood that the phrases "some embodiments," "one embodiment," or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0197] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0198] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A plurality of memory cell layers are stacked at intervals along a first direction perpendicular to the substrate, each memory cell layer including a plurality of memory cells arranged in an array; each memory cell includes a transistor, the transistor including a gate electrode extending along a second direction parallel to the substrate and a semiconductor layer covering a portion of the gate electrode; The gate electrode includes a body and a first end and a second end opposite to each other along the second direction; the semiconductor layer covers the first end of the gate electrode and surrounds at least a portion of the sidewalls of the gate electrode; the first direction and the second direction are perpendicular.
2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: Multiple bit lines extending along the first direction, each bit line being connected to a semiconductor layer covering the first end of the gate electrode in a plurality of memory cells arranged along the first direction; Multiple word lines extending along a third direction parallel to the substrate, each word line being connected to the second end of the gate electrode of a plurality of memory cells arranged along the third direction in the same memory cell layer; Wherein, the first direction is perpendicular to the third direction, and the second direction intersects the third direction.
3. The semiconductor device according to claim 2, characterized in that, Along the second direction, two adjacent memory cells and the two bit lines between the memory cells are symmetrically distributed.
4. The semiconductor device according to claim 2 or 3, characterized in that, The storage unit also includes a storage structure; The semiconductor layer has an arcuate side surface on the portion of the transistor along the third direction, and the transistor is connected to the memory structure through the arcuate side surface.
5. The semiconductor device according to claim 4, characterized in that, The storage structure includes a first electrode, a dielectric layer, and a second electrode; wherein the first electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode connecting the first sub-electrode and the second sub-electrode, the third sub-electrode extending along the first direction and having opposing inner and outer sidewalls. The second electrode covers the inner wall of the dielectric layer; The dielectric layer covers the inner wall of the third sub-electrode and the entire surface of the first and second sub-electrodes; the outer wall of the third sub-electrode is in contact with the arcuate side surface.
6. The semiconductor device according to claim 5, characterized in that, The first electrodes of the plurality of memory cells arranged along the first direction are spaced apart along the first direction; The dielectric layers of the plurality of memory cells arranged along the first direction are interconnected, and the second electrodes are interconnected.
7. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes an isolation layer located between the semiconductor layer and the word line, and between the memory structure and the word line; The isolation layer surrounds a portion of the sidewall of the gate electrode.
8. The semiconductor device according to claim 7, characterized in that, The dimension of the storage structure along the second direction is smaller than the sum of the dimensions of the semiconductor layer and the isolation layer along the second direction.
9. The semiconductor device according to claim 1, characterized in that, The transistor further includes a gate insulating layer, which is located at least between the gate electrode and the semiconductor layer.
10. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A stacked layer is formed by alternately stacking a first insulating layer and a second insulating layer on the substrate along a first direction perpendicular to the substrate; A first hole and a first trench are formed through the stacked layers; wherein the first hole is located on opposite sides of the first trench along a second direction parallel to the substrate surface, and the first trench extends along a third direction parallel to the substrate surface; A bit line extending along the first direction is formed through the first trench; A storage structure is formed in the first hole; A second trench is formed that penetrates the stacked layer and extends along the third direction; wherein the second trench is located on opposite sides of the first hole along the second direction; The second insulating layer is removed along the second trench to expose the bit line and the memory structure, forming a plurality of first gaps spaced apart along the first direction and extending along the second direction; A semiconductor layer and a gate electrode are sequentially formed in the first gap to form a plurality of transistors stacked at intervals along the first direction; the gate electrode includes a body and a first end and a second end opposite to each other along the second direction; the semiconductor layer covers the first end of the gate electrode and surrounds at least a portion of the sidewalls of the gate electrode; Wherein, the first direction is perpendicular to the second direction and perpendicular to the third direction, and the second direction intersects the third direction.
11. The preparation method according to claim 10, characterized in that, The process of forming a bit line extending along the first direction through the first trench includes: A first sacrificial layer is formed in the first trench; A portion of the first sacrificial layer is removed to form a plurality of second holes spaced apart along the third direction; A first conductive layer is formed in the second hole; Remove the first conductive layer located at the bottom of the second hole; A third insulating layer covering the first conductive layer is formed in the second hole; Remove the first sacrificial layer between adjacent second holes to form a plurality of third holes spaced apart along the third direction, so as to expose the first conductive layer; A portion of the first conductive layer is removed along the third hole, and the remaining portion of the first conductive layer located on the two opposite sidewalls of the third insulating layer along the second direction constitutes the bit line.
12. The preparation method according to claim 10, characterized in that, The process of forming the storage structure in the first hole includes: Based on the removal of part of the second insulating layer through the first hole, a second gap is formed that is spaced apart along the first direction; A second conductive layer is formed in the first hole and the second void; Remove the second conductive layer located in the first hole, and the remaining second conductive layer located in the second gap constitutes the first electrode; Based on the first hole, the first insulating layer is etched to form a third gap that is spaced apart along the first direction; A dielectric layer and a second electrode are formed in the first hole, the second gap, and the third gap; wherein the second electrode covers the inner sidewall of the dielectric layer, and the dielectric layer covers the inner sidewall of the first electrode as well as the inner sidewall of the first hole and the third gap.
13. The preparation method according to claim 10, characterized in that, Forming a plurality of transistors stacked at intervals along the first direction, including: A fourth hole is formed through the stacked layer, the fourth hole being located between adjacent bit lines along the third direction; A fourth insulating layer is formed in the fourth hole; the material of the fourth insulating layer is different from the material of the second insulating layer. The second trench is formed, and the second insulating layer is removed along the second trench to form a first gap spaced apart along the first direction, so as to expose the fourth insulating layer. Semiconductor material, gate insulating material, and gate electrode material are sequentially deposited in the first gap; A portion of the semiconductor material, a portion of the gate insulating material, and a portion of the gate electrode material are removed along the second direction to form a semiconductor layer, a gate insulating layer, and a gate electrode, respectively; the gate insulating layer is located at least between the gate electrode and the semiconductor layer; the semiconductor layer has an arcuate side surface on one side of the transistor along the third direction.
14. The preparation method according to claim 13, characterized in that, The method further includes: A fifth insulating layer is formed at locations where a portion of the semiconductor material, a portion of the gate insulating material, and a portion of the gate electrode material are removed; Remove part of the fifth insulating layer to expose the gate electrode; Conductive material is deposited at least at the location where a portion of the fifth insulating layer is removed to form initial word lines, and the initial word lines located on the sidewalls of the first insulating layer are removed to form word lines extending along the third direction and spaced apart along the first direction.
15. An electronic device, characterized in that, This includes a semiconductor device according to any one of claims 1 to 9, or a semiconductor device manufactured by the method according to any one of claims 10 to 14.