Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The preparation method comprises the following steps: alternately forming a first dielectric layer and a second dielectric layer on a substrate to form a stacked structure; a first via hole is formed, the first via hole extends in the direction perpendicular to the plane where the substrate is located, and the stacked structure located in the first via hole is etched away; based on the first via hole, etching the stacked structure along a direction parallel to a plane where the substrate is located to form a first accommodating cavity, etching the first dielectric layer located in the first accommodating cavity, and communicating the first accommodating cavity with the first via hole; forming a barrier film in the first via hole and the first accommodating cavity, wherein the barrier film is used for forming a barrier layer; sequentially forming a semiconductor layer, an insulating layer and a word line based on the first via hole; the semiconductor layer is used for forming a channel layer of the transistor, the channel layer extends in the direction perpendicular to the plane where the substrate is located, the blocking layer surrounds the side wall of the channel layer, and the quality of the formed channel layer can be guaranteed.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily, while the types and number of devices contained in a single chip are increasing. This means that even minor differences in the manufacturing process can affect device performance. To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0003] This disclosure provides a semiconductor device, a method for fabricating the same, and an electronic device.

[0004] On one hand, this disclosure provides a method for fabricating a semiconductor device, the semiconductor device including a substrate and at least one transistor located on the substrate; the fabrication method includes:

[0005] A first dielectric layer and a second dielectric layer are alternately formed on the substrate to form a stacked structure;

[0006] A first via is formed, and the first via extends along a direction perpendicular to the plane of the substrate, and the stacked structure located within the first via is etched away;

[0007] Based on the first via, the stacked structure is etched along a direction parallel to the plane of the substrate to form a first receiving cavity. The first dielectric layer located within the first receiving cavity is etched away, and the first receiving cavity is connected to the first via.

[0008] A barrier film is formed within the first through hole and the first receiving cavity, and the barrier film is used to form a barrier layer;

[0009] A semiconductor layer, an insulating layer, and a word line are sequentially formed based on the first via; the semiconductor layer is used to form the channel layer of the transistor, the channel layer extends in a direction perpendicular to the plane of the substrate, and the barrier layer surrounds the sidewall of the channel layer.

[0010] In some exemplary embodiments, the sequential formation of a semiconductor layer, an insulating layer, and a word line based on the first via includes:

[0011] A sacrificial layer is formed based on the first via, and the barrier film and the sacrificial layer are sequentially located within the first receiving cavity; the sacrificial layer has a second receiving cavity, and the second receiving cavity is connected to the first via, and the semiconductor layer and the insulating layer fill the second receiving cavity.

[0012] In some exemplary embodiments, the barrier film forms a first receiving space; the formation of the sacrificial layer based on the first via includes:

[0013] A filling body is formed based on the first accommodating space, and the filling body fills the first accommodating space;

[0014] The filler and the barrier film located within the first via are etched away, so that the barrier film forms the initial pattern of the barrier layer.

[0015] Laterally etch the remaining filler exposed by the first via, so that the remaining filler forms the sacrificial layer.

[0016] In some exemplary embodiments, the semiconductor device further includes at least one capacitor and at least one bit line; prior to performing lateral etching on the stacked structure based on the first via to form a first receiving cavity, the fabrication method further includes:

[0017] First form the first plate of the capacitor, then form the bit lines; or...

[0018] First form the bit line, then form the first plate of the capacitor; or...

[0019] The position line is formed synchronously with the first plate of the capacitor.

[0020] In some exemplary embodiments, the step of first forming the first plate of the capacitor and then forming the bit line includes:

[0021] A second via is formed, and the second via extends along a direction perpendicular to the plane of the substrate, and the stacked structure located within the second via is etched away;

[0022] A first column is formed within the first through hole;

[0023] The stacked structure is laterally etched based on the second via to form a first receiving groove. The second dielectric layer located within the first receiving groove is etched away, and the first receiving groove is connected to the second via. The first receiving groove exposes part of the sidewall of the first column.

[0024] The first electrode plate is formed within the first receiving groove based on the second through hole.

[0025] In some exemplary embodiments, the process of first forming the first plate of the capacitor and then forming the bit line further includes:

[0026] After the first electrode plate is formed, a trench is formed, and the stacked structure located within the trench is etched away. The trench and the second via are located on both sides of the first via along a first direction, which is parallel to the plane of the substrate.

[0027] The stacked structure is laterally etched based on the trench to form a third receiving groove. The second dielectric layer located within the third receiving groove is etched away, and the third receiving groove is connected to the trench. The third receiving groove exposes part of the sidewall of the first column.

[0028] The bit line is formed within the third receiving groove based on the groove;

[0029] The first pillar located within the first via is etched away, and the first via exposes a portion of the first electrode plate and a portion of the bit line.

[0030] In some exemplary embodiments, after the semiconductor layer, insulating layer, and word line are formed sequentially, the fabrication method further includes:

[0031] Based on the second via and the trench, the initial pattern of the barrier layer is etched so that the initial pattern of the barrier layer forms a first barrier layer and a second barrier layer, and the first barrier layer and the second barrier layer are spaced apart along a direction perpendicular to the plane of the substrate.

[0032] The sacrificial layer is etched away based on the second via and the trench, exposing a portion of the semiconductor layer;

[0033] The exposed semiconductor layer is etched to form a plurality of channel layers spaced apart along a direction perpendicular to the plane of the substrate.

[0034] In some exemplary embodiments, the insulating layer located within the second receiving cavity forms a protrusion; after forming the plurality of channel layers, the fabrication method further includes:

[0035] Based on the second via and the trench, a protective layer is formed in the space formed after the sacrificial layer is etched. The protective layer is arranged in pairs with the protrusions, and the protective layer surrounds the outside of the corresponding protrusion.

[0036] On the other hand, embodiments of this disclosure provide a semiconductor device including a substrate and a plurality of memory cell layers located on the substrate. The memory cell layers include at least one memory cell, and the memory cell includes at least one transistor. The transistor includes a channel layer and a gate electrode, and the gate electrode extends along a direction perpendicular to the plane of the substrate. The channel layer surrounds the sidewall of the gate electrode. The memory cell layer further includes a barrier layer, which is disposed in pairs with the channel layers and surrounds the sidewall of the corresponding channel layer.

[0037] In some exemplary embodiments, the barrier layer includes at least one of a first barrier layer and a second barrier layer; the first barrier layer surrounds one end of the sidewall of the channel layer in a direction perpendicular to the plane of the substrate, and the second barrier layer surrounds the other end of the sidewall of the channel layer in a direction perpendicular to the plane of the substrate.

[0038] In some exemplary embodiments, the plurality of gate electrodes arranged along a direction perpendicular to the plane of the substrate are an interconnected integral structure and form a word line;

[0039] The character line includes multiple cross-sections parallel to the plane of the base, and the multiple cross-sections are identical.

[0040] In some exemplary embodiments, the semiconductor device further includes a plurality of bumps located between two adjacent channel layers disposed along a direction perpendicular to the plane of the substrate; the transistor further includes a gate insulating layer located between the channel layers and the gate electrode, and the plurality of bumps and the plurality of gate insulating layers are an integral structure interconnected with each other.

[0041] In some exemplary embodiments, the semiconductor device further includes a plurality of protective layers, wherein the protective layers are arranged in pairs with the protrusions, and the protective layers surround the outside of the corresponding protrusions.

[0042] In some exemplary embodiments, the storage unit further includes at least one capacitor, the capacitor including a first plate, a second plate, and a dielectric layer located between the first plate and the second plate, the first plate surrounding the sidewall of the second plate and in contact with the barrier layer.

[0043] On the other hand, embodiments of this disclosure provide an electronic device, including a semiconductor device formed by the preparation method described in any of the above embodiments, or a semiconductor device described in any of the above embodiments.

[0044] In this embodiment of the present disclosure, by forming a barrier film before forming a semiconductor layer, the barrier layer formed by the barrier film can protect the channel layer during the formation of the channel layer of the semiconductor layer, prevent excessive etching of the channel layer, and improve the quality of the semiconductor device.

[0045] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0046] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0047] Figure 1 This is a partial cross-sectional schematic diagram of a semiconductor device fabrication process;

[0048] Figure 2A This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure;

[0049] Figure 2B for Figure 2A A magnified view of a portion of the area marked A in the diagram;

[0050] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming a first receiving groove;

[0051] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device after bit lines have been formed according to an embodiment of the present disclosure;

[0052] Figure 5 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming a fourth receiving groove;

[0053] Figure 6 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming a barrier film;

[0054] Figure 7 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after the fourth pillar has been formed;

[0055] Figure 8 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after the formation of a sacrificial layer;

[0056] Figure 9 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after word lines have been formed;

[0057] Figure 10 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after the third accommodating space has been formed;

[0058] Figure 11 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after the fifth accommodating space has been formed;

[0059] Figure 12 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming the sixth receiving groove;

[0060] Figure 13 This is a cross-sectional schematic diagram of a semiconductor device after a channel layer has been formed, according to an embodiment of the present disclosure.

[0061] Figure 14 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after a protective thin film has been formed;

[0062] Figure 15 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming a sacrificial thin film;

[0063] Figure 16 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after the sixth pillar has been formed;

[0064] Figure 17 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure after the sacrificial portion has been formed;

[0065] Figure 18 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming a seventh receiving trench;

[0066] Figure 19 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after the second electrode plate has been formed. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0068] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0069] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0070] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0071] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0072] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0073] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0074] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0075] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0076] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0077] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0078] Figure 1 This is a partial cross-sectional schematic diagram of the fabrication process of a semiconductor device. Figure 1 As shown, the semiconductor device may include transistors 1, capacitors 2, and bit lines 8. Multiple transistors 1 and multiple capacitors 2 can be arranged along a third direction Z, which is the direction perpendicular to the plane containing the semiconductor device. The first direction X is parallel to the plane containing the semiconductor device. A groove 3 is formed between two adjacent bit lines 8. During the fabrication of the semiconductor device, a semiconductor layer 4, an insulating layer 5, and a conductive layer 6 are sequentially filled into the groove 3. Due to the presence of this groove 3, during the formation of the conductive layer 6 using atomic layer deposition, holes 7 are generated inside the conductive layer 6. Since the conductive layer 6 is used to form the gate electrode and word lines of the transistors, these holes affect the resistance of the transistors, reducing the performance of the semiconductor device.

[0079] During fabrication, the semiconductor layer 4 needs to be etched away to remove the semiconductor layer 4 located at the groove 3, so that the semiconductor layer 4 forms the channel layer for multiple transistors 1. Therefore, it is usually necessary to ensure that the bit line 8 extends beyond its contact point with the semiconductor layer 4 in the first direction X to meet the dimension L1, so as to prevent the etching material from damaging the final channel layer during the etching process of the semiconductor layer 4. Furthermore, it is usually necessary to ensure that the dimension of the bit line 8 along the first direction X meets L2, and that the protrusion dimension of the semiconductor layer 4 along the first direction X meets L3. However, existing semiconductor design structures and fabrication processes cannot meet the requirements of L1, L2, and L3.

[0080] This disclosure provides a method for fabricating a semiconductor device, the semiconductor device including a substrate and at least one transistor located on the substrate; the fabrication method includes:

[0081] A first dielectric layer and a second dielectric layer are alternately formed on the substrate to form a stacked structure;

[0082] A first via is formed, and the first via extends along a direction perpendicular to the plane of the substrate, and the stacked structure located within the first via is etched away;

[0083] Based on the first via, the stacked structure is etched along a direction parallel to the plane of the substrate to form a first receiving cavity. The first dielectric layer located within the first receiving cavity is etched away, and the first receiving cavity is connected to the first via.

[0084] A barrier film is formed within the first through hole and the first receiving cavity, and the barrier film is used to form a barrier layer;

[0085] A semiconductor layer, an insulating layer, and a word line are sequentially formed based on the first via; the semiconductor layer is used to form the channel layer of the transistor, the channel layer extends in a direction perpendicular to the plane of the substrate, and the barrier layer surrounds the sidewall of the channel layer.

[0086] In this embodiment of the present disclosure, by forming a barrier film before forming a semiconductor layer, the barrier layer formed by the barrier film can protect the channel layer during the formation of the channel layer of the semiconductor layer, prevent excessive etching of the channel layer, and improve the quality of the semiconductor device.

[0087] Figure 2A This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure. Figure 2B for Figure 2A A magnified view of a portion marked A in the diagram. (See diagram below.) Figure 2AAs shown, in this embodiment, three directions are defined: a first direction X, a second direction, and a third direction Z. The first direction X and the second direction are perpendicular to each other, and the plane containing the semiconductor device is parallel to the plane formed by the first direction X and the second direction. The third direction Z is perpendicular to the plane containing the semiconductor device. Because... Figure 2A , Figure 2B All are cross-sectional views along the plane formed by the first direction X and the third direction Z, therefore the second direction is not marked in the figure.

[0088] like Figure 2A As shown, a semiconductor device may include a substrate 10 and at least one memory cell layer 10a located on the substrate 10. For example, the semiconductor device may include two memory cell layers 10a, three memory cell layers 10a, or five memory cell layers 10a, etc., and multiple memory cell layers 10a may be stacked sequentially along a third direction Z. In this embodiment of the disclosure, a semiconductor device including five memory cell layers is taken as an example; however, this embodiment of the disclosure does not limit the number of memory cell layers included in the semiconductor device.

[0089] The storage cell layer 10a may include at least one storage cell. For example, the storage cell layer 10a may include one or two storage cells. In this embodiment of the disclosure, a storage cell layer including one storage cell is taken as an example. However, this embodiment of the disclosure does not limit the number of storage cells included in the storage cell layer. The storage cell may include at least one transistor 20 and at least one capacitor 30. For example, the storage cell may include one transistor 20 and one capacitor 30. The transistor 20 and the capacitor 30 may be arranged side by side and connected to each other.

[0090] The storage cell layer 10a may further include at least one bit line BL, and the bit line BL may extend along the second direction. For example, the storage cell layer 10a may include one bit line BL. Multiple storage cells located in the same storage cell layer 10a and arranged along the second direction may be connected to the same bit line BL.

[0091] The semiconductor device may further include at least one word line WL, which may extend along a third direction Z, and the gate electrodes of a plurality of transistors 20 stacked along the third direction Z may be connected to the same word line WL. Alternatively, the gate electrodes of the plurality of transistors 20 stacked along the third direction Z may be a single structure forming a word line WL.

[0092] In some exemplary embodiments, such as Figure 2BAs shown in the figure, transistor 20 is indicated by the dashed box. Transistor 20 may include a channel layer 21, a gate electrode 23, and a gate insulating layer 22 located between the channel layer 21 and the gate electrode 23. The gate electrode 23 may extend in a third direction Z, and the gate insulating layer 22 surrounds the sidewall of the gate electrode 23, while the channel layer 21 surrounds the sidewall of the gate insulating layer 22. In this embodiment, the transistor is a transistor with a vertical channel, which is beneficial for improving the integration density of semiconductor devices.

[0093] In some exemplary embodiments, such as Figure 2B As shown in the figure, capacitor 30 is indicated by the dashed box. Capacitor 30 may include a first plate 31, a second plate 32, and a dielectric layer 33 located between the first plate 31 and the second plate 32. The first plate 31 may surround the sidewall of the second plate 32. The first plate 31 of capacitor 30 may be in contact with the channel layer 21 of transistor 20.

[0094] In some exemplary embodiments, such as Figure 2B As shown, the memory cell layer 10a may include at least one barrier layer 40, which may be paired with transistors 20, and the barrier layer 40 surrounds the sidewall of the channel layer 21 of the corresponding transistor 20. The barrier layer 40 may include at least one of a first barrier layer 41 and a second barrier layer 42. The first barrier layer 41 surrounds one end of the sidewall of the channel layer 21 along a third direction Z, which may also be referred to as the first end. The second barrier layer 42 surrounds the other end of the sidewall of the channel layer 21 along a third direction Z, which may also be referred to as the second end. In embodiments of this disclosure, the end is not an endpoint, but a region near an endpoint. For example, along a third direction Z, the sidewall of the channel layer 21 can be divided into six equal parts, with one end occupying one-sixth of that part.

[0095] In some exemplary embodiments, the barrier layer 40 may include a first barrier layer 41 and a second barrier layer 42 disposed at a Z-distance along a third direction, with the first barrier layer 41 being closer to the substrate 10 than the second barrier layer 42. A portion of the bit line BL may be located between the first barrier layer 41 and the second barrier layer 42. A portion of the first electrode 31 of the capacitor 30 may be located between the first barrier layer 41 and the second barrier layer 42. During fabrication, the first barrier layer 41 and the second barrier layer 42 may be formed simultaneously. In embodiments of this disclosure, by providing barrier layers, over-etching of the channel layer during fabrication can be avoided, thus ensuring transistor performance.

[0096] The following example illustrates the structure of a semiconductor device through its fabrication process. The fabrication process of a semiconductor device may include the following steps:

[0097] (01) A first dielectric layer 11 and a second dielectric layer 12 are sequentially formed on one side of the substrate 10. Multiple first dielectric layers 11 and multiple second dielectric layers 12 are alternately arranged along the third direction Z to form an initial stacked structure. Subsequently, a third dielectric layer 13 and a fourth dielectric layer 14 are sequentially formed on the side of the initial stacked structure away from the substrate 10 to form a stacked structure, as shown below. Figure 3 As shown, five first dielectric layers 11 and five second dielectric layers 12 are arranged alternately along a third direction Z. In embodiments of this disclosure, the number of first and second dielectric layers included in the stacked structure is not limited. For example, the first and second dielectric layers can be prepared using a deposition process, which may include at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), evaporation, spin coating, or physical vapor deposition (PVD).

[0098] Subsequently, the stacked structure is etched to form multiple vias, which may include at least a first via K1 and a second via K2. The first via K1 and the second via K2 may be spaced apart along a first direction X. Both the first via K1 and the second via K2 may extend along a third direction Z, and the stacked structure within the first via K1 and the second via K2 is etched away, exposing a portion of the surface of the substrate 10. The orthographic projection of the via onto the plane of the substrate 10 may be circular or rectangular, etc. In embodiments of this disclosure, etching may include at least one of physical etching and chemical etching. The first via is used to accommodate portions of transistors formed in subsequent processes, and the second via is used to accommodate portions of capacitors formed in subsequent processes.

[0099] Subsequently, a first pillar 51 is formed, and the first pillar 51 fills the first through hole K1, as follows: Figure 3 As shown. For example, the surface of the first pillar 51 away from the substrate 10 may be flush with the surface of the stacked structure away from the substrate 10. For example, the surface of the first pillar 51 away from the substrate 10 may be treated with chemical mechanical polishing (CMP). For example, the first pillar 51 may be formed using a deposition process.

[0100] Subsequently, the stacked structure is laterally etched based on the second via K2 to form multiple first receiving grooves 61. The second dielectric layer 12 located within the first receiving grooves 61 is etched away, and the first receiving grooves 61 expose part of the sidewall of the first pillar 51. All the multiple first receiving grooves 61 are connected to the second via K2, such as... Figure 3 As shown. The first receiving tank is used to receive the first plate of the capacitor formed in a subsequent process.

[0101] In some exemplary embodiments, substrate 10 may include a single-crystal silicon substrate or a semiconductor-on-insulator (SOI) substrate, etc. For example, the SOI substrate may be a silicon-on-sapphire (SOS) substrate or a silicon-on-glass (SOG) substrate, etc. Substrate 10 may be a single-layer or composite-layer structure.

[0102] In some exemplary embodiments, the first dielectric layer 11 and the third dielectric layer 13 may both be silicon oxide layers, and the second dielectric layer 12 and the fourth dielectric layer 14 may both be silicon nitride layers.

[0103] (02) Based on the second via K2, multiple first plates 31 of multiple capacitors are formed within multiple first receiving slots 61, such as Figure 4 As shown. The first electrode plate 31 may include a top 31a, a bottom 31b, and a side portion 31c connected together. The top 31a and the bottom 31b are spaced apart along a third direction Z, with the bottom 31b closer to the substrate 10 than the top 31a. The side portion 31c is located between the top 31a and the bottom 31b. The top 31a, the bottom 31b, and the side portion 31c together form a second receiving groove 62, and the second receiving groove 62 is connected to the second through hole K2.

[0104] Subsequently, filling material is deposited within multiple second receiving grooves 62 based on the second via K2, filling the second receiving grooves 62 completely. Then, the filling material is oxidized, so that the filling material exposed by the second via K2 forms an oxide layer 34, and the remaining filling material, excluding the oxide layer 34, forms a filling layer 35, such as... Figure 4 As shown. For example, the filling material can be polycrystalline silicon, and the material of oxide layer 34 can be silicon oxide.

[0105] Subsequently, a trench 60 is formed. In the first direction X, the trench 60 and the second via K2 are located on opposite sides of the first via K1, and the trench 60 can extend along the second direction. The stacked structure within the trench 60 is etched away. Then, the second dielectric layer 12 is laterally etched based on the trench 60 to form a plurality of third receiving trenches 63, and the third receiving trenches 63 expose portions of the first pillar 51. The third receiving trenches 63 can extend along the second direction. All the plurality of third receiving trenches 63 are connected to the trench 60, such as... Figure 4 As shown. Subsequently, based on the trench 60, multiple bit lines BL are formed within multiple third receiving grooves 63, as follows. Figure 4 As shown.

[0106] Subsequently, a second pillar 52 and a third pillar 53 are formed. The second pillar 52 includes a second cladding layer 52b and a second body 52a. The second cladding layer 52b covers the sidewalls and bottom wall of the second body 52a, and together they fill the second via K2. The third pillar 53 includes a third cladding layer 53b and a third body 53a. The third cladding layer 53b covers the sidewalls and bottom wall of the third body 53a, and together they fill the trench 60. For example, the materials of the second body 52a and the third body 53a can both be polycrystalline silicon, and the materials of the second cladding layer 52b and the third cladding layer 53b can both be silicon nitride. For example, the second cladding layer 52b and the third cladding layer 53b can be formed simultaneously, and the second body 52a and the third body 53a can be formed simultaneously.

[0107] Subsequently, the first pillar 51 located within the first via K1 is etched away, exposing part of the side 31c of the first electrode plate 31 and part of the bit line BL.

[0108] In some possible embodiments, the bit line BL is formed first, and then the first electrode 31, oxide layer 34 and filler layer 35 are formed after the bit line BL is formed.

[0109] In some possible embodiments, the bit line BL is formed synchronously with the first electrode plate 31.

[0110] In some exemplary embodiments, the material of the first electrode 31 may include a metallic material. For example, the metallic material may include at least one of the following: tungsten (W), molybdenum (Mo), cobalt (Co), titanium (Ti), copper (Cu), aluminum (Al), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), silver (Ag), or gold (Au), or an alloy of the above metals. The first electrode 31 may be a single-layer or multi-layer structure. For example, the first electrode may be a multi-layer structure of titanium and titanium nitride.

[0111] In some exemplary embodiments, the material of the bit line BL may be the same as or different from the material of the first electrode plate 31.

[0112] (03) Based on the first via K1, multiple first dielectric layers 11 and third dielectric layers 13 are laterally etched to form multiple fourth receiving grooves 64 (first receiving cavities). All fourth receiving grooves 64 are connected to the first via K1, and the fourth receiving grooves 64 expose portions of the second pillar 52 and the third pillar 53, such as... Figure 5 As shown. The fourth receiving groove 64 can expose a portion of the top 31a of the first electrode plate 31, a portion of the bottom 31b, and portions of the bit line BL opposite each other along the third direction Z.

[0113] (04) A barrier film 43 is formed on the substrate 10 on which the aforementioned structure is formed, such as Figure 6 As shown, the barrier film 43 fills the first via K1 and the fourth receiving groove 64, and the barrier film 43 forms the first receiving space 68. For example, the barrier film 43 can be formed using an atomic layer deposition (ALD) process.

[0114] In some exemplary embodiments, the material of the barrier film 43 may include at least one of silicon carbide (SiCN), silicon nitride (SiN), or silicon carbide oxide (SiCO). For example, the material of the barrier film 43 may have a selection ratio of polysilicon greater than 2:1, or the material of the barrier film 43 may have a selection ratio of IGZO greater than 2:1.

[0115] (05) A fourth column 54 (filler) is formed based on the first accommodating space 68, such as Figure 7As shown, the fourth pillar 54 fills the first receiving space 68. The surface of the fourth pillar 54 away from the substrate 10 can be flush with the surface of the stacked structure away from the substrate 10, and the surface of the fourth pillar 54 away from the substrate 10 can be treated with chemical mechanical polishing (CMP). For example, the material of the fourth pillar 54 can be polycrystalline silicon.

[0116] (06) The fourth pillar 54 and the barrier film 43 located within the first via K1 are etched away, so that the barrier film 43 forms multiple initial barrier layer patterns 44. Subsequently, the fourth pillar 54 exposed by the first via K1 is laterally etched, so that the fourth pillar 54 forms multiple sacrificial layers 54a, such as... Figure 8 As shown. The initial pattern 44 of the barrier layer is used to form the first barrier layer and the second barrier layer in subsequent processes.

[0117] In some exemplary embodiments, the sacrificial layer 54a forms a fifth receiving groove 65 (second receiving cavity), and the fifth receiving groove 65 is connected to the first through hole K1.

[0118] In some exemplary embodiments, within the fourth receiving groove 64, the amount of etching of the fourth pillar 54 can be reduced by at least the thickness of a barrier film compared to a scheme without a barrier film, thereby increasing the size of the sacrificial layer.

[0119] (07) Based on the first via K1, a semiconductor layer 24, an insulating layer 25, and a word line WL are sequentially formed, such as Figure 9 As shown, the word line WL may include multiple gate electrodes 23. The semiconductor layer 24 and the insulating layer 25 together fill the fifth receiving groove 65. The word line WL has multiple cross-sections that are parallel to the plane formed by the first direction X and the second direction, and their shapes are substantially the same. The multiple cross-sections are arranged along the third direction Z. For example, the word line WL can be a cylinder or a rectangular pillar, etc. Since the etching amount of the fourth pillar 54 is reduced in the aforementioned steps, the semiconductor layer 24 and the insulating layer 25 can together fill the fifth receiving groove 65, so that the word line WL can form a pillar with a uniform cross-section, avoiding the formation of holes inside the word line WL and avoiding the adverse effects of holes on the resistance value of the word line WL.

[0120] In some exemplary embodiments, the insulating layer 25 may include a plurality of gate insulating layers 22 and protrusions 26. The protrusions 26 may be located within a fifth receiving groove 65. The gate insulating layers 22 are located between the gate electrode 23 and the subsequently formed channel layer.

[0121] In some exemplary embodiments, the material of the semiconductor layer 24 may include a metal oxide material, such as indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the transistor leakage current is relatively small (leakage current less than or equal to 10). -15 A), thus ensuring a low refresh rate for the dynamic memory. It should be noted that the metal oxide material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the transistor leakage current meets the requirements. Specific adjustments can be made according to the actual situation.

[0122] In some exemplary embodiments, the material of the insulating layer 25 may include a high dielectric constant material, which can improve the insulation between the subsequently formed channel layer and the gate electrode, thereby improving the performance of the semiconductor device. In embodiments of this disclosure, the high dielectric constant material may be a material with a dielectric constant equal to or greater than 3.9. The high dielectric constant material may include any one or more of hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), and strontium titanate (SrTiO3). The insulating layer 25 may be a multilayer or composite layer structure.

[0123] In some exemplary embodiments, the material of the word line WL may include a metallic material. For example, the metallic material may include at least one of the following: tungsten (W), molybdenum (Mo), cobalt (Co), titanium (Ti), copper (Cu), aluminum (Al), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), silver (Ag), or gold (Au), or an alloy of the above metals, or an oxide of the above metals. For example, the material of the word line WL may be ITO.

[0124] (08) Etch away the second body 52a and the third body 53a, such as Figure 10As shown. After the second body 52a is etched away, a second accommodating space 69 is formed, and after the third body 53a is etched away, a third accommodating space 70 is formed. The second accommodating space 69 and the third accommodating space 70 can be used as etching channels for etching the semiconductor layer in subsequent processes to form multiple channel layers.

[0125] (09) Based on the second accommodating space 69, the second covering layer 52b is etched away, and the initial pattern 44 of the barrier layer exposed by the second accommodating space 69 is etched to form the fourth accommodating space 71. Based on the third accommodating space 70, the third covering layer 53b is etched away, and the initial pattern 44 of the barrier layer exposed by the third accommodating space 70 is etched to form the fifth accommodating space 72, such as... Figure 11 As shown, the initial pattern 44 of the barrier layer is etched to form a first barrier layer 41 and a second barrier layer 42.

[0126] In some possible exemplary embodiments, the second coating layer 52b, the third coating layer 53b, and the initial pattern 44 of the barrier layer are etched using the same etching process.

[0127] (10) Based on the fourth accommodating space 71 and the fifth accommodating space 72, the sacrificial layer 54a is etched away to form the sixth accommodating groove 66, such as Figure 12 As shown, the sixth receiving trench 66 exposes a portion of the semiconductor layer 24. Because the material of the sacrificial layer 54a has a selectivity ratio with the materials of the first barrier layer 41 and the second barrier layer 42, the first barrier layer 41 and the second barrier layer 42 are not removed.

[0128] (11) The semiconductor layer 24 is etched based on the fourth accommodating space 71, the fifth accommodating space 72, and the sixth accommodating trench 66 to form multiple channel layers 21 in the semiconductor layer 24, such as Figure 13 As shown. The first barrier layer 41 and the second barrier layer 42 prevent the etching material from etching the semiconductor layer forming the channel layer. Therefore, the first barrier layer 41 and the second barrier layer 42 protect the channel layer and can improve the performance of the transistor.

[0129] (12) A protective film 55 is formed on the substrate 10 on which the aforementioned structure is formed. The protective film 55 fills the sixth receiving trench 66, the fourth receiving space 71, the fifth receiving space 72, and the space formed after the semiconductor layer 24 is etched. However, the protective film 55 does not completely fill the sixth receiving trench 66, the fourth receiving space 71, and the fifth receiving space 72. Figure 14 As shown, a protective film 55 surrounds the protrusion 26 exposed by the sixth receiving trench 66. The protective film 55 can protect the protrusion 26 and encapsulate the gap between the protrusion 26 and the channel layer 21, thereby improving the transistor's resistance to water and oxygen.

[0130] Since the sacrificial layer formed in the aforementioned steps has a large size in the first direction X, a sixth receiving groove with a large space is formed after the sacrificial layer is etched away. Therefore, a protective film with a large size in the first direction X can be formed in the sixth receiving groove, which can form a better encapsulation for the protrusion and the gap between the protrusion and the channel layer.

[0131] In some exemplary embodiments, the material of the protective film 55 may be silicon nitride.

[0132] (13) A sacrificial film 56 is formed on the substrate 10 on which the aforementioned structure is formed. The sacrificial film 56 fills the sixth receiving groove 66, the fourth receiving space 71, and the fifth receiving space 72, but the sacrificial film 56 does not completely fill the fourth receiving space 71 and the fifth receiving space 72. Figure 15 As shown. For example, the material of the sacrificial film 56 can be silicon dioxide.

[0133] In some possible embodiments, the sacrificial film 56 and the protective film 55 can together fill the fourth accommodating space 71 and the fifth accommodating space 72.

[0134] (14) A fifth pillar 57 and a sixth pillar 58 are formed on the base 10 that forms the aforementioned structure, as follows: Figure 16 As shown. The fifth pillar 57, the sacrificial film 56, and the protective film 55 together fill the fourth receiving space 71. The sixth pillar 58, the sacrificial film 56, and the protective film 55 together fill the fifth receiving space 72. For example, the material of the fifth pillar 57 and the material of the sixth pillar 58 can both be polycrystalline silicon.

[0135] (15) The fifth pillar 57, sacrificial film 56, and protective film 55 located within the second via K2 are etched away, such as... Figure 17 As shown, the sacrificial film 56 forms a plurality of sacrificial portions 56a, and the protective film 55 forms a plurality of protective layers 55a. For example, a self-aligned process can be used to remove the fifth pillar 57. For example, a physical etching process can be used to etch both the sacrificial film and the protective film.

[0136] (16) Based on the second via K2, the substrate 10 forming the aforementioned structure is laterally etched to form a plurality of seventh receiving grooves 67, and the plurality of seventh receiving grooves 67 are connected to the second via K2, such as Figure 18 As shown, the sacrificial portion 56a, the first dielectric layer 11, and the third dielectric layer 13 located within the seventh receiving tank 67 are all etched away, and simultaneously, the oxide layer 34 exposed by the second via K2 is etched away.

[0137] In some exemplary embodiments, the protective layer 55a can have a larger size in the first direction X, that is, the protective layer can have a thicker thickness along the first direction X. Since the protective layer has a larger size in the first direction X, the size of the sacrificial portion along the first direction X is reduced. Therefore, during the etching process of the sacrificial portion, the etching rate is reduced due to the size effect, resulting in greater resistance to over-etching, which is beneficial for increasing the process window of the capacitor. Compared with some technical solutions, the technical solution provided by the embodiments of this disclosure does not require improving the quality of the sacrificial portion to enhance its resistance to over-etching, thus reducing manufacturing complexity.

[0138] (17) On the substrate 10 where the aforementioned structure is formed, a dielectric thin film and a conductive thin film are sequentially formed based on the second via K2, such as Figure 19 As shown. The dielectric thin film includes multiple dielectric layers 33, and the conductive thin film includes multiple second electrode plates 32.

[0139] In some possible embodiments, based on the second via K2, the filling layer 35 can be etched away first, and then the dielectric film and the conductive film can be formed sequentially.

[0140] In some exemplary embodiments, the second electrode plate 32 and the first electrode plate 31 may be made of the same or different materials.

[0141] This disclosure provides a method for fabricating a semiconductor device, the semiconductor device including a substrate and at least one transistor located on the substrate; the fabrication method includes:

[0142] A first dielectric layer and a second dielectric layer are alternately formed on the substrate to form a stacked structure;

[0143] A first via is formed, and the first via extends along a direction perpendicular to the plane of the substrate, and the stacked structure located within the first via is etched away;

[0144] Based on the first via, the stacked structure is etched along a direction parallel to the plane of the substrate to form a first receiving cavity. The first dielectric layer located within the first receiving cavity is etched away, and the first receiving cavity is connected to the first via.

[0145] A barrier film is formed within the first through hole and the first receiving cavity, and the barrier film is used to form a barrier layer;

[0146] A semiconductor layer, an insulating layer, and a word line are sequentially formed based on the first via; the semiconductor layer is used to form the channel layer of the transistor, the channel layer extends in a direction perpendicular to the plane of the substrate, and the barrier layer surrounds the sidewall of the channel layer.

[0147] In some exemplary embodiments, the sequential formation of a semiconductor layer, an insulating layer, and a word line based on the first via includes:

[0148] A sacrificial layer is formed based on the first via, and the barrier film and the sacrificial layer are sequentially located within the first receiving cavity; the sacrificial layer has a second receiving cavity, and the second receiving cavity is connected to the first via, and the semiconductor layer and the insulating layer fill the second receiving cavity.

[0149] In some exemplary embodiments, the barrier film forms a first receiving space; the formation of the sacrificial layer based on the first via includes:

[0150] A filling body is formed based on the first accommodating space, and the filling body fills the first accommodating space;

[0151] The filler and the barrier film located within the first via are etched away, so that the barrier film forms the initial pattern of the barrier layer.

[0152] Laterally etch the remaining filler exposed by the first via, so that the remaining filler forms the sacrificial layer.

[0153] In some exemplary embodiments, the semiconductor device further includes at least one capacitor and at least one bit line; prior to performing lateral etching on the stacked structure based on the first via to form a first receiving cavity, the fabrication method further includes:

[0154] First form the first plate of the capacitor, then form the bit lines; or...

[0155] First form the bit line, then form the first plate of the capacitor; or...

[0156] The position line is formed synchronously with the first plate of the capacitor.

[0157] In some exemplary embodiments, the step of first forming the first plate of the capacitor and then forming the bit line includes:

[0158] A second via is formed, and the second via extends along a direction perpendicular to the plane of the substrate, and the stacked structure located within the second via is etched away;

[0159] A first column is formed within the first through hole;

[0160] The stacked structure is laterally etched based on the second via to form a first receiving groove. The second dielectric layer located within the first receiving groove is etched away, and the first receiving groove is connected to the second via. The first receiving groove exposes part of the sidewall of the first column.

[0161] The first electrode plate is formed within the first receiving groove based on the second through hole.

[0162] In some exemplary embodiments, the process of first forming the first plate of the capacitor and then forming the bit line further includes:

[0163] After the first electrode plate is formed, a trench is formed, and the stacked structure located within the trench is etched away. The trench and the second via are located on both sides of the first via along a first direction, which is parallel to the plane of the substrate.

[0164] The stacked structure is laterally etched based on the trench to form a third receiving groove. The second dielectric layer located within the third receiving groove is etched away, and the third receiving groove is connected to the trench. The third receiving groove exposes part of the sidewall of the first column.

[0165] The bit line is formed within the third receiving groove based on the groove;

[0166] The first pillar located within the first via is etched away, and the first via exposes a portion of the first electrode plate and a portion of the bit line.

[0167] In some exemplary embodiments, after the semiconductor layer, insulating layer, and word line are formed sequentially, the fabrication method further includes:

[0168] Based on the second via and the trench, the initial pattern of the barrier layer is etched so that the initial pattern of the barrier layer forms a first barrier layer and a second barrier layer, and the first barrier layer and the second barrier layer are spaced apart along a direction perpendicular to the plane of the substrate.

[0169] The sacrificial layer is etched away based on the second via and the trench, exposing a portion of the semiconductor layer;

[0170] The exposed semiconductor layer is etched to form a plurality of channel layers spaced apart along a direction perpendicular to the plane of the substrate.

[0171] In some exemplary embodiments, the insulating layer located within the second receiving cavity forms a protrusion; after forming the plurality of channel layers, the fabrication method further includes:

[0172] Based on the second via and the trench, a protective layer is formed in the space formed after the sacrificial layer is etched. The protective layer is arranged in pairs with the protrusions, and the protective layer surrounds the outside of the corresponding protrusion.

[0173] This disclosure also provides an electronic device, which includes the semiconductor device provided in any of the above embodiments. The electronic device can be any electronic product with storage function, such as a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0174] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes a substrate and at least one transistor located on the substrate; the fabrication method includes: A first dielectric layer and a second dielectric layer are alternately formed on the substrate to form a stacked structure; A first via is formed, and the first via extends along a direction perpendicular to the plane of the substrate, and the stacked structure located within the first via is etched away; Based on the first via, the stacked structure is etched along a direction parallel to the plane of the substrate to form a first receiving cavity. The first dielectric layer located within the first receiving cavity is etched away, and the first receiving cavity is connected to the first via. A barrier film is formed within the first through hole and the first receiving cavity, and the barrier film is used to form a barrier layer; A semiconductor layer, an insulating layer, and a word line are sequentially formed based on the first via; the semiconductor layer is used to form the channel layer of the transistor, the channel layer extends in a direction perpendicular to the plane of the substrate, and the barrier layer surrounds the sidewall of the channel layer.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of sequentially forming a semiconductor layer, an insulating layer, and a word line based on the first via includes: A sacrificial layer is formed based on the first via, and the barrier film and the sacrificial layer are sequentially located within the first receiving cavity; the sacrificial layer has a second receiving cavity, and the second receiving cavity is connected to the first via, and the semiconductor layer and the insulating layer fill the second receiving cavity.

3. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The barrier film forms a first accommodating space; The formation of the sacrificial layer based on the first via includes: A filling body is formed based on the first accommodating space, and the filling body fills the first accommodating space; The filler and the barrier film located within the first via are etched away, so that the barrier film forms an initial pattern of the barrier layer. Laterally etch the remaining filler exposed by the first via, so that the remaining filler forms the sacrificial layer.

4. The method for fabricating a semiconductor device as described in claim 3, characterized in that, The semiconductor device further includes at least one capacitor and at least one bit line; Before performing lateral etching on the stacked structure based on the first via to form the first receiving cavity, the fabrication method further includes: First form the first plate of the capacitor, then form the bit lines; or... First form the bit line, then form the first plate of the capacitor; or... The position line is formed synchronously with the first plate of the capacitor.

5. The method for fabricating a semiconductor device as described in claim 4, characterized in that, The process of first forming the first plate of the capacitor and then forming the bit line includes: A second via is formed, and the second via extends along a direction perpendicular to the plane of the substrate, and the stacked structure located within the second via is etched away; A first column is formed within the first through hole; The stacked structure is laterally etched based on the second via to form a first receiving groove. The second dielectric layer located within the first receiving groove is etched away, and the first receiving groove is connected to the second via. The first receiving groove exposes part of the sidewall of the first column. The first electrode plate is formed within the first receiving groove based on the second through hole.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The process of first forming the first plate of the capacitor and then forming the bit line also includes: After the first electrode plate is formed, a trench is formed, and the stacked structure located within the trench is etched away. The trench and the second via are located on both sides of the first via along a first direction, which is parallel to the plane of the substrate. The stacked structure is laterally etched based on the trench to form a third receiving groove. The second dielectric layer located within the third receiving groove is etched away, and the third receiving groove is connected to the trench. The third receiving groove exposes part of the sidewall of the first column. The bit line is formed within the third receiving groove based on the groove; The first pillar located within the first via is etched away, and the first via exposes a portion of the first electrode plate and a portion of the bit line.

7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, After the semiconductor layer, insulating layer, and word lines are formed sequentially, the fabrication method further includes: Based on the second via and the trench, the initial pattern of the barrier layer is etched so that the initial pattern of the barrier layer forms a first barrier layer and a second barrier layer, and the first barrier layer and the second barrier layer are spaced apart along a direction perpendicular to the plane of the substrate. The sacrificial layer is etched away based on the second via and the trench, exposing a portion of the semiconductor layer; The exposed semiconductor layer is etched to form a plurality of channel layers spaced apart along a direction perpendicular to the plane of the substrate.

8. The method for fabricating a semiconductor device as described in claim 7, characterized in that, The insulating layer located within the second receiving cavity forms a protrusion; After forming multiple channel layers, the fabrication method further includes: Based on the second via and the trench, a protective layer is formed in the space formed after the sacrificial layer is etched. The protective layer is arranged in pairs with the protrusions, and the protective layer surrounds the outside of the corresponding protrusion.

9. A semiconductor device, characterized in that, The system includes a substrate and a plurality of memory cell layers located on the substrate, each memory cell layer including at least one memory cell, and each memory cell including at least one transistor. The transistor includes a channel layer and a gate electrode, wherein the gate electrode extends in a direction perpendicular to the plane of the substrate, and the channel layer surrounds the sidewall of the gate electrode. The storage cell layer also includes a barrier layer, which is arranged in pairs with the channel layer, and the barrier layer surrounds the sidewall of the corresponding channel layer.

10. The semiconductor device as claimed in claim 9, characterized in that, The barrier layer includes at least one of a first barrier layer and a second barrier layer; The first barrier layer surrounds one end of the sidewall of the channel layer in a direction perpendicular to the plane of the substrate, and the second barrier layer surrounds the other end of the sidewall of the channel layer in a direction perpendicular to the plane of the substrate.

11. The semiconductor device as claimed in claim 9, characterized in that, The multiple gate electrodes arranged along a direction perpendicular to the plane of the substrate are interconnected as a single structure and form a word line; The character line includes multiple cross-sections parallel to the plane of the base, and the multiple cross-sections are identical.

12. The semiconductor device according to any one of claims 9 to 11, characterized in that, The semiconductor device further includes a plurality of bumps located between two adjacent channel layers arranged in a direction perpendicular to the plane of the substrate; the transistor further includes a gate insulating layer located between the channel layers and the gate electrode, and the plurality of bumps and the plurality of gate insulating layers are an integral structure interconnected with each other.

13. The semiconductor device as claimed in claim 12, characterized in that, The semiconductor device further includes multiple protective layers, and the protective layers are arranged in pairs with the protrusions, with the protective layers surrounding the outside of the corresponding protrusions.

14. The semiconductor device according to any one of claims 9 to 11, characterized in that, The storage unit further includes at least one capacitor, which includes a first plate, a second plate, and a dielectric layer located between the first plate and the second plate. The first plate surrounds the sidewall of the second plate and is in contact with the barrier layer.

15. An electronic device, characterized in that, This includes semiconductor devices formed by the method of fabricating a semiconductor device as described in any one of claims 1 to 8, or semiconductor devices as described in any one of claims 9 to 14.

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