Semiconductor device, manufacturing method thereof and electronic equipment
By forming a conformally covered protective layer on the surface of the sacrificial layer, the problem of the protective layer being unable to protect the sacrificial layer and the substrate is solved, thereby improving the performance and reliability of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2024-11-22
- Publication Date
- 2026-05-22
Smart Images
Figure CN122073799A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to, but is not limited to, the field of semiconductor manufacturing, specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology
[0002] With the development of integrated circuit technology, the size of semiconductor devices such as Dynamic Random Access Memory (DRAM) has been continuously miniaturized. Semiconductor devices have evolved from two-dimensional structures to three-dimensional stacked structures, which has significantly improved the integration of semiconductor devices. However, the complexity of semiconductor manufacturing processes has also increased. Since any tiny difference in the manufacturing process may affect the performance of semiconductor devices, this poses a challenge to the yield and reliability of semiconductor devices. Summary of the Invention
[0003] In view of the above, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, as well as an electronic device.
[0004] In a first aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor device, comprising:
[0005] Provide substrate;
[0006] A stacked layer is formed by alternately stacking a first insulating layer and a second insulating layer on the substrate along a first direction;
[0007] A first hole and a second hole are formed through the stacked layers; the first hole includes a first sub-hole extending along the first direction and a second sub-hole extending along a second direction parallel to the substrate surface into the second insulating layer;
[0008] A first electrode and a first sacrificial layer are sequentially formed in the second sub-hole;
[0009] A portion of the first insulating layer is removed along the first hole to form a third sub-hole extending into the first insulating layer along the second direction;
[0010] A protective layer is formed that at least covers the inner wall of the third sub-hole and the surface of the first sacrificial layer;
[0011] Multiple transistors are formed in the second hole and stacked at intervals along the first direction;
[0012] Remove the protective layer and the first sacrificial layer to expose the first electrode in the second sub-hole;
[0013] A dielectric layer and a second electrode are sequentially formed within the first hole to cover the surface of the first electrode, thereby forming a capacitor.
[0014] In some embodiments, the method further includes:
[0015] A second sacrificial layer and a third sacrificial layer are sequentially formed to cover the protective layer; a portion of the first insulating layer is removed along the second hole to form a fourth sub-hole extending into the first insulating layer along the second direction; the fourth sub-hole exposes a portion of the sidewall of the second sacrificial layer.
[0016] A fourth sacrificial layer is formed in the fourth sub-hole;
[0017] A semiconductor layer and a gate insulating layer are sequentially formed in the second hole, and a conductive material is filled in as a gate electrode layer.
[0018] The fourth sacrificial layer in the fourth sub-hole is removed to expose a portion of the sidewall of the semiconductor layer. The exposed semiconductor layer is then removed to form a plurality of transistors stacked at intervals along the first direction.
[0019] In some embodiments, removing the fourth sacrificial layer in the fourth sub-hole includes:
[0020] The second and third sacrificial layers are removed to form a third hole; the third hole exposes the sidewall of the fourth sacrificial layer.
[0021] The fourth sacrificial layer located in the fourth sub-hole is removed along the third hole.
[0022] In some embodiments, the material of the fourth sacrificial layer is the same as the material of the first sacrificial layer.
[0023] In some embodiments, the size of the third sub-hole in the second direction is less than or equal to the size of the second sub-hole in the second direction.
[0024] In some embodiments, the size of the fourth sub-hole in the second direction is less than or equal to the size of the first electrode in the second direction.
[0025] In some embodiments, the method further includes:
[0026] A first trench is formed through the stacked layers; a second hole is located between the first hole and the first trench; wherein the first trench extends along a third direction parallel to the surface of the substrate;
[0027] A fifth and a sixth sacrificial layer are formed within the second hole;
[0028] A portion of the second insulating layer is removed along the first trench to form a first sub-trench, the first sub-trench exposing at least a portion of the fifth sacrificial layer;
[0029] A conductive material is deposited in the first trench and the first sub-trench, and the conductive material is in contact with the fifth sacrificial layer;
[0030] The conductive material located outside the first sub-slot is removed, and the remaining conductive material located inside the first sub-slot forms multiple bit lines extending along the third direction;
[0031] Remove the fifth and sixth sacrificial layers from the second hole;
[0032] Multiple transistors are formed in the second hole and stacked at intervals along the first direction;
[0033] Wherein, the first direction is perpendicular to both the second direction and the third direction, and the second direction intersects with the third direction.
[0034] In some embodiments, the material of the protective layer includes at least one of silicon oxide, silicon carbonitride, or silicon carbonitride.
[0035] In some embodiments, the material of the protective layer is the same as the material of the first insulating layer.
[0036] In some embodiments, forming the first electrode and the first sacrificial layer in the second sub-hole includes:
[0037] A first electrode material and a first sacrificial material are sequentially formed to at least cover the sidewalls of the first sub-hole and the second sub-hole;
[0038] Remove the first electrode material and the first sacrificial material located outside the second sub-hole; the first electrode material located inside the second sub-hole constitutes the first electrode, and the first sacrificial material located inside the second sub-hole constitutes the first sacrificial layer.
[0039] In some embodiments, removing the exposed semiconductor layer to form a plurality of transistors stacked at intervals along the first direction includes:
[0040] The semiconductor layer, which is in the same layer as the first insulating layer, is removed by wet etching using an etching solution.
[0041] In a second aspect, embodiments of this disclosure provide a semiconductor device manufactured using any of the manufacturing methods described in the first aspect, comprising:
[0042] Substrate;
[0043] A plurality of memory cell layers are stacked at intervals along a first direction on the substrate, each memory cell layer including a plurality of memory cells arranged in an array; each memory cell includes a capacitor, and the capacitor includes a first electrode; the first electrodes of the plurality of memory cells arranged along the first direction in different memory cell layers are distributed at intervals along the first direction, each first electrode including a first sub-electrode, a second sub-electrode, and a third sub-electrode connecting the first sub-electrode and the second sub-electrode; the first sub-electrode and the second sub-electrode are both annular in cross-section perpendicular to the first direction; the third sub-electrode extends along the first direction;
[0044] The storage unit also includes a plurality of transistors stacked at intervals along the first direction.
[0045] In some embodiments, the capacitor further includes:
[0046] A dielectric layer that completely covers the surfaces of the first sub-electrode and the second sub-electrode and partially covers the surface of the third sub-electrode;
[0047] The second electrode covers the surface of the dielectric layer.
[0048] In some embodiments, the transistor includes a gate electrode layer, a semiconductor layer at least partially surrounding the gate electrode layer, and a gate insulating layer at least between the gate electrode layer and the semiconductor layer.
[0049] In some embodiments, the capacitor is located on one side of the transistor along a second direction parallel to the substrate surface; the first electrode of the capacitor is connected to the semiconductor layer of the transistor.
[0050] In some embodiments, the semiconductor device further includes:
[0051] Multiple bit lines extending along a third direction parallel to the substrate surface; each bit line is connected to a semiconductor layer of multiple memory cells arranged along the third direction in the same memory cell layer;
[0052] Wherein, the first direction is perpendicular to both the second direction and the third direction, and the second direction intersects with the third direction.
[0053] Thirdly, according to embodiments of the present disclosure, an electronic device includes a semiconductor device according to any of the second aspects.
[0054] The method for manufacturing a semiconductor device provided in this disclosure includes: providing a substrate; alternately stacking a first insulating layer and a second insulating layer on the substrate along a first direction to form a stacked layer; forming a first hole and a second hole through the stacked layer; the first hole includes a first sub-hole extending along the first direction and a second sub-hole extending into the second insulating layer along a second direction parallel to the surface of the substrate; sequentially forming a first electrode and a first sacrificial layer in the second sub-hole; removing a portion of the first insulating layer along the first hole to form a third sub-hole extending into the first insulating layer along the second direction; forming a protective layer that at least covers the inner wall of the third sub-hole and the surface of the first sacrificial layer; forming a plurality of transistors stacked at intervals along the first direction in the second hole; removing the protective layer and the first sacrificial layer to expose the first electrode in the second sub-hole; and sequentially forming a dielectric layer and a second electrode covering the surface of the first electrode in the first hole to form a capacitor. In this embodiment of the present disclosure, after the first sacrificial layer is formed in the second sub-hole of the first hole, the third sub-hole is formed by etching back a portion of the first insulating layer. The formed protective layer conformally covers the inner wall of the third sub-hole and the surface of the first sacrificial layer, effectively increasing the lateral etching distance required to expose the first sacrificial layer. At the same time, the protective layer also covers part of the substrate surface. Therefore, during the formation of other structures (such as transistors), the protective layer can effectively prevent the first sacrificial layer and the substrate from being damaged, thereby improving the performance and reliability of the semiconductor device. Attached Figure Description
[0055] Figure 1A A cross-sectional schematic diagram of the main process steps of a semiconductor device manufacturing method according to an embodiment of this disclosure;
[0056] Figure 1B for Figure 1A An enlarged view of the area indicated by the dashed box in the middle;
[0057] Figure 2A A second cross-sectional schematic diagram of the main process steps of a semiconductor device manufacturing method provided in an embodiment of this disclosure;
[0058] Figure 2B for Figure 2A An enlarged view of the area indicated by the dashed box in the middle;
[0059] Figure 3 A cross-sectional schematic diagram of the main process steps of a semiconductor device manufacturing method provided in an embodiment of this disclosure. Figure 3 ;
[0060] Figure 4 A cross-sectional schematic diagram of the main process steps of a semiconductor device manufacturing method provided in an embodiment of this disclosure. Figure 4 ;
[0061] Figure 5 A schematic diagram illustrating the specific implementation flow of a semiconductor device manufacturing method according to another embodiment of this disclosure;
[0062] Figure 6 A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure;
[0063] Figure 7 A second cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure;
[0064] Figure 8 A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure. Figure 3 ;
[0065] Figure 9 A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure. Figure 4 ;
[0066] Figure 10 A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure. Figure 5 ;
[0067] Figure 11A A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure. Figure 6 ;
[0068] Figure 11B for Figure 11A An enlarged view of the area indicated by the dashed box in the middle;
[0069] Figure 12A A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure. Figure 7 ;
[0070] Figure 12B for Figure 12A An enlarged view of the area indicated by the dashed box in the middle;
[0071] Figure 13 A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure. Figure 8 ;
[0072] Figure 14 A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure. Figure 9 ;
[0073] Figure 15A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure. Figure 10 ;
[0074] Figure 16 A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure. Figure 10 one;
[0075] Figure 17 A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to another embodiment of this disclosure. Figure 10 two;
[0076] Figure 18A A schematic cross-sectional view of a semiconductor device along a second insulating layer, provided for another embodiment of this disclosure;
[0077] Figure 18B A schematic cross-sectional view of a semiconductor device along a first insulating layer, provided for another embodiment of this disclosure;
[0078] Figure 19 This is a partial structural schematic diagram of a capacitor provided in an embodiment of the present disclosure. Detailed Implementation
[0079] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0080] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise scale, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0081] In this disclosure, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order, sequence, quantity, or importance.
[0082] In the embodiments of this disclosure, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" may be used to describe the positional relationships of the constituent elements with reference to the accompanying drawings. These terms are used solely for ease of description and simplification and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this disclosure. The positional relationships and orientations of the constituent elements may change depending on the placement direction of each constituent element.
[0083] In this embodiment of the disclosure, "parallel" means approximately parallel or nearly parallel, and the included angle between the two elements defined therein may be within the allowable range of process tolerance. Similarly, "perpendicular" means approximately perpendicular or nearly perpendicular, and the included angle between the two elements defined therein may be an error angle relative to a 90° right angle that is within the allowable range of process tolerance.
[0084] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict. In the methods involved in the embodiments of this disclosure, unless otherwise specified or described, the execution order of each step can be adjusted according to actual circumstances or needs. That is, different combinations of the sequences of steps involved in the embodiments of this disclosure all fall within the protection scope of this disclosure.
[0085] The transistor involved in the embodiments of this disclosure refers to a device that includes at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode). The gate can control the conductivity of the channel region, thereby enabling current to flow between the source, the channel region, and the drain based on gate control.
[0086] The deposition processes involved in the embodiments of this disclosure include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.
[0087] The growth processes described in this disclosure include, but are not limited to: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), ion beam epitaxy, solid phase epitaxy, and combinations thereof.
[0088] The etching processes described in this disclosure include, but are not limited to, dry etching, wet etching, and combinations thereof.
[0089] The semiconductor devices disclosed herein are at least a portion of those to be used in subsequent processes to form the final device structure. Here, the final device may be a memory, such as DRAM, or other memory chips or processing chips containing DRAM memory cells.
[0090] Figures 1A to 4 A cross-sectional schematic diagram of the main process steps of a method for manufacturing a semiconductor device according to an embodiment of this disclosure. (See reference...) Figures 1A to 4 The semiconductor device is formed as follows.
[0091] like Figure 1A As shown, a substrate 100 is provided, and a stacked layer 103 is formed by alternately stacking a first insulating layer 101 and a second insulating layer 102 along a first direction on the substrate 100. Exemplarily, the material of the first insulating layer 101 is silicon oxide, and the material of the second insulating layer 102 is silicon nitride.
[0092] A first through-hole, a second through-hole, and a first trench (not shown) are formed through the stacked layers, wherein the first and second through-holes extend along a first direction, and the first trench extends along a third direction. In a second direction, the second through-hole is located between the first through-hole and the first trench.
[0093] It should be noted that, here and below, both the second direction and the third direction are perpendicular to the first direction. The second direction and the third direction intersect each other; in some specific embodiments, the second direction is perpendicular to the third direction. For example, the first direction may be the extension direction of the z-axis shown in the figures, the second direction may be the extension direction of the x-axis shown in the figures, and the third direction may be the extension direction of the y-axis shown in the figures.
[0094] In some embodiments, before forming the bitline structure extending in a third direction through the first trench, a first sacrificial material layer 108 and a second sacrificial material layer 107 are sequentially formed in the second via to protect the second via. Exemplarily, the first sacrificial material layer 108 is made of silicon oxide, and the second sacrificial material layer 107 is made of polysilicon.
[0095] In some embodiments, before forming a bit line structure extending in a third direction through the first trench, the method further includes: removing a portion of the second insulating layer 102 along the first through-hole and forming a first electrode 104 and a third sacrificial material layer 105 at the location where the portion of the second insulating layer 102 has been removed.
[0096] In some embodiments, a protective layer 106 is formed on the third sacrificial material layer 105 exposed by the first through hole through in-situ oxidation.
[0097] It should be noted that, Figure 1A and Figure 1B This can be understood as the ideal situation for forming the protective layer 106. In this case, the protective layer 106 is uniform and defect-free, and can effectively cover the third sacrificial material layer 105. However, in the actual manufacturing process, during the formation of the protective layer 106 by in-situ oxidation, due to problems such as uneven diffusion of the oxidant, uneven temperature distribution, and stress concentration caused by the structure of the transverse grooves, the protective layer 106 is prone to cracking, peeling, and even failure to form a protective layer in some areas.
[0098] Figure 1B for Figure 1A A magnified view of area 111 shown in the dashed box, for reference. Figure 1A and Figure 1B The fourth sacrificial material layer 109 and the fifth sacrificial material layer 110 are formed to cover the protective layer 106.
[0099] For example, the third sacrificial material layer 105 and the fifth sacrificial material layer 110 are made of polycrystalline silicon, and the fourth sacrificial material layer 109 is made of silicon nitride.
[0100] exist Figure 1A After the steps shown are completed, a bitline structure extending in the third direction is formed through the first trench.
[0101] Figure 2B for Figure 2A A magnified view of area 112 shown in the dashed box, for reference. Figure 2A and Figure 2B Chemical mechanical polishing (CMP) is performed on the fifth sacrificial material layer 110 until the surface of the fourth sacrificial material layer 109 is exposed, and the second sacrificial material layer 107 and the first sacrificial material layer 108 in the second through hole are removed to form the third through hole.
[0102] A portion of the first insulating layer 101 is removed along the third through-hole to form a first lateral groove 113. Exemplarily, a portion of the first insulating layer 101 is removed along the third through-hole by wet etching to form the first lateral groove 113, which exposes the sidewall of the fourth sacrificial material layer 109.
[0103] like Figure 2B As shown, since wet etching is isotropic and the material of the protective layer 106 is the same as that of the first insulating layer 101, when the first transverse groove 113 is formed, the etching solution will also remove part of the protective layer 106 in the first direction (z direction), thereby damaging the third sacrificial material layer 105 covered by the protective layer 106.
[0104] refer to Figure 3 A sixth sacrificial material layer 114 is formed within the first transverse groove 113. Exemplarily, the material of the sixth sacrificial material layer 114 is polycrystalline silicon.
[0105] refer to Figure 4 A semiconductor layer 121 and a gate insulating layer 115 are sequentially formed within the second via, and a conductive material is filled to form a gate electrode layer 116. (Removal) Figure 3 The fourth sacrificial material layer 109 and the fifth sacrificial material layer 110 shown form a fourth via 117. The sixth sacrificial material layer 114 is removed along the fourth via 117 to form a second lateral groove 118, thereby exposing a portion of the sidewalls of the semiconductor layer 121.
[0106] Because in Figure 2A During the process steps, damage was caused to the third sacrificial material layer 105 covered by the protective layer 106, resulting in the exposure of part of the third sacrificial material layer 105. The third sacrificial material layer 105 and the sixth sacrificial material layer 114 are made of the same material; therefore, when the sixth sacrificial material layer 114 is removed, the third sacrificial material layer 105 is also damaged, forming a... Figure 4 Defects in the area indicated by the dashed box 119.
[0107] Furthermore, when removing the sixth sacrificial material layer 114 along the fourth via 117, the etching solution will damage the substrate 100 due to the isotropic nature of wet etching, forming conditions such as... Figure 4 Defects in the area indicated by the dashed box 120.
[0108] Continue to refer to Figure 4 The semiconductor layer co-layered with the first insulating layer 101 is removed, and a plurality of transistors are stacked at intervals along the first direction. In a subsequent process, the protective layer 106 and the third sacrificial material layer 105 are further removed to expose the first electrode 104, and a dielectric layer covering the first electrode 104 and a second electrode are sequentially formed along the fourth via 117 to form a capacitor structure.
[0109] In the formation of the aforementioned semiconductor devices, the protective layer is difficult to form or has defects, and it cannot effectively protect the third sacrificial material layer, which can also lead to damage to the substrate structure. On the one hand, because the third sacrificial material layer is damaged in advance, the area where the third sacrificial material layer is located (a part of the area used to form the capacitor structure) is contaminated or damaged in other process steps (such as the process steps for forming transistors), which reduces the performance of the final capacitor structure and thus reduces the reliability of the semiconductor device. On the other hand, substrate damage is prone to leakage, which will also affect the stability of the semiconductor device.
[0110] Based on this, another embodiment of this disclosure provides a method for manufacturing a semiconductor device. Figure 5 This is a schematic diagram illustrating a specific implementation flow of a semiconductor device manufacturing method according to another embodiment of this disclosure. For example... Figure 5 As shown, the specific steps of the manufacturing method of this semiconductor device include:
[0111] Step S10: Provide a substrate;
[0112] Step S20: Alternately stack a first insulating layer and a second insulating layer on the substrate along a first direction to form a stacked layer;
[0113] Step S30: Form a first hole and a second hole through the stacked layers; the first hole includes a first sub-hole extending along the first direction and a second sub-hole extending along a second direction parallel to the substrate surface into the second insulating layer;
[0114] Step S40: The first electrode and the first sacrificial layer are sequentially formed in the second sub-hole;
[0115] Step S50: Remove a portion of the first insulating layer along the first hole to form a third sub-hole extending into the first insulating layer along the second direction;
[0116] Step S60: Form a protective layer that at least covers the inner wall of the third sub-hole and the surface of the first sacrificial layer;
[0117] Step S70: Form a plurality of transistors stacked at intervals along the first direction within the second hole;
[0118] Step S80: Remove the protective layer and the first sacrificial layer to expose the first electrode in the second sub-hole;
[0119] Step S90: A dielectric layer and a second electrode are sequentially formed inside the first hole to cover the surface of the first electrode, thereby forming a capacitor.
[0120] Please refer to the following. Figures 6 to 17The present disclosure provides a more detailed description of the manufacturing process of the semiconductor device provided in the embodiments.
[0121] refer to Figure 6 A substrate 200 is provided; a first insulating layer 201 and a second insulating layer 202 are alternately stacked on the substrate 200 along a first direction to form a stacked layer 203; a first hole and a second hole are formed through the stacked layer; the first hole 204 includes a first sub-hole 205 extending along the first direction and a second sub-hole 206 extending into the second insulating layer 202 along a second direction parallel to the substrate surface.
[0122] It should be noted that, Figure 6 The dashed line shown is only used to indicate the location where the second sub-hole 206 is formed; in actual semiconductor devices, this dashed line does not exist.
[0123] In some implementations, the first hole is used to form a capacitor, and the second hole is used to form a transistor.
[0124] For example, the substrate 200 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., and can also be other epitaxial structures, such as silicon-germanium-on-insulator (SGOI), etc.
[0125] In some embodiments, the process of forming the first insulating layer 201 and the second insulating layer 202 may include any process known in the art, including but not limited to CVD, PVD, sputtering, and ALD.
[0126] Here, the first insulating layer 201 and the second insulating layer 202 may be partially retained or not retained in the final semiconductor device, for example, they may be replaced with other materials or formed into other specific structures. Exemplarily, the materials of the first insulating layer 201 and the second insulating layer 202 may be silicon oxide and silicon nitride, respectively.
[0127] In some embodiments, the method further includes: forming a first trench through the stacked layer; a second hole located between the first hole and the first trench; wherein the first trench extends along a third direction (y direction) parallel to the surface of the substrate.
[0128] Before forming the bit line extending along the third direction through the first trench, the first and second holes need to be protected to prevent the metal deposition, etching, high-temperature treatment and other process steps in the bit line fabrication process from contaminating or damaging the formation site of the transistor and capacitor.
[0129] In some implementations, such as Figure 6 As shown, a fifth sacrificial layer 208 and a sixth sacrificial layer 207 are formed within the second hole to protect it. Exemplarily, the fifth sacrificial layer 208 is made of silicon oxide, and the sixth sacrificial layer 207 is made of polycrystalline silicon.
[0130] refer to Figures 7 to 11B This achieves protection for the first hole.
[0131] like Figure 7 As shown, a first electrode and a first sacrificial layer are formed in the second sub-hole.
[0132] In some embodiments, a first electrode material and a first sacrificial material are sequentially formed to cover at least the sidewalls of the first sub-hole and the second sub-hole; the first electrode material and the first sacrificial material located outside the second sub-hole are removed; the first electrode material located inside the second sub-hole constitutes the first electrode 209, and the first sacrificial material located inside the second sub-hole constitutes the first sacrificial layer 210.
[0133] For example, the first electrode material can be a metallic material or an alloy material, such as a material containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal nitride material such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or titanium aluminum nitride (TiAlN).
[0134] like Figure 8 As shown, a portion of the first insulating layer is removed along the first hole to form a third sub-hole extending into the first insulating layer along the second direction.
[0135] In some embodiments, a portion of the first insulating layer 201 is removed along the first sub-hole 205 to form a third sub-hole 211 extending into the first insulating layer 201 in a second direction.
[0136] In some embodiments, the size of the third sub-hole in the second direction is less than or equal to the size of the second sub-hole in the second direction.
[0137] like Figure 9 As shown, a protective layer is formed that at least covers the inner wall of the third sub-hole and the surface of the first sacrificial layer.
[0138] In some embodiments, an ALD process is used to form a protective layer 212 along the first sub-hole 205, covering the inner wall of the third sub-hole and the surface of the first sacrificial layer. The protective layer 212 is conformal to both the third sub-hole and the first sacrificial layer.
[0139] In some embodiments, the material of the protective layer 212 includes at least one of silicon oxide, silicon carbonitride (SiOCN), or silicon carbonitride (SiCN).
[0140] In one embodiment, the protective layer is made of the same material as the first insulating layer. For example, both the protective layer 212 and the first insulating layer 201 are made of silicon oxide.
[0141] Figure 11B for Figure 11A An enlarged view of area 215 shown in the dashed box, as follows: Figure 10 , Figure 11A and Figure 11B As shown, a second sacrificial layer and a third sacrificial layer are formed sequentially to cover the protective layer.
[0142] In some embodiments, a second sacrificial layer 213 and a third sacrificial layer 214 are formed sequentially over the protective layer 212.
[0143] In some embodiments, the material of the second sacrificial layer 213 includes, but is not limited to, silicon nitride, and the material of the third sacrificial layer 214 includes, but is not limited to, polysilicon.
[0144] exist Figure 11A After the steps shown are completed, bit lines extending along a third direction are formed through the first trench. In some embodiments, a portion of the second insulating layer is removed along the first trench to form a first sub-trench, which exposes at least a portion of the fifth sacrificial layer 208; conductive material is deposited in the first trench and the first sub-trench, the conductive material contacting the fifth sacrificial layer 208. The conductive material outside the first sub-trench is removed, and the remaining conductive material inside the first sub-trench forms multiple bit lines extending along a third direction. The first direction is perpendicular to both the second and third directions, and the second direction intersects the third direction.
[0145] Continue to refer to Figures 12A to 16 Multiple transistors are formed in the second hole and stacked at intervals along the first direction.
[0146] Figure 12B for Figure 12A An enlarged view of area 215 shown in the dashed box, as follows: Figure 12A and Figure 12BAs shown, after removing the fifth sacrificial layer 208 and the sixth sacrificial layer 207 in the second hole, a portion of the first insulating layer 201 is removed along the second hole 217 to form a fourth sub-hole 216 extending in the first insulating layer 201 along the second direction; the fourth sub-hole 216 exposes a portion of the sidewall of the second sacrificial layer 213.
[0147] In some embodiments, the size of the fourth sub-hole in the second direction is less than or equal to the size of the first electrode in the second direction.
[0148] For example, such as Figure 12B As shown, the dimension W1 of the fourth sub-hole 216 in the second direction is equal to the dimension W2 of the first electrode 209 in the second direction. Figure 12B This illustrates the case where W1 equals W2.
[0149] In other embodiments, the dimension W1 of the fourth sub-hole 216 in the second direction is smaller than the dimension W2 of the first electrode 209 in the second direction.
[0150] In this embodiment of the disclosure, after forming a first sacrificial layer in the second sub-via, a third sub-via is formed by etching back a portion of the first insulating layer. The formed protective layer conformally covers the inner wall of the third sub-via and the surface of the first sacrificial layer. The protective layer effectively increases the lateral etch distance required to expose the first sacrificial layer. For example, as... Figure 12B As shown, when the first insulating layer 201 is partially removed to expose the second sacrificial layer 213, the lateral etching distance of the etching solution is W1, while the lateral etching distance to expose the first sacrificial layer 210 needs to reach at least W3, where W3 is greater than W1. Therefore, the etching solution can only remove the protective layer that is in the same layer as the first insulating layer, and the remaining part 212-1 of the protective layer can still cover the surface of the first sacrificial layer 210, thus preventing the first sacrificial layer 210 from being damaged.
[0151] like Figure 13 As shown, a fourth sacrificial layer is formed in the fourth sub-hole.
[0152] In some embodiments, a sacrificial material covering the fourth sub-via is formed, and the sacrificial material outside the fourth sub-via is removed to form a fourth sacrificial layer 219, exemplarily. The material of the fourth sacrificial layer 219 is polycrystalline silicon.
[0153] refer to Figures 14 to 16 A semiconductor layer and a gate insulating layer are sequentially formed in the second hole, and a conductive material is filled in as a gate electrode layer; the fourth sacrificial layer in the fourth sub-hole is removed to expose part of the sidewall of the semiconductor layer, and the exposed semiconductor layer is removed to form a plurality of transistors stacked at intervals along the first direction.
[0154] like Figure 14As shown, a semiconductor layer 220 and a gate insulating layer 221 are sequentially formed in the second hole, and a conductive material is filled in as a gate electrode layer 222.
[0155] In some embodiments, the semiconductor layer 220 is made of at least one of indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), and indium zinc oxide (IZO). When the semiconductor layer 220 is made of IGZO, the transistor has a smaller leakage current (leaking current less than or equal to 10). -15 A), thus ensuring a low refresh rate for the dynamic access memory.
[0156] In some embodiments, the gate insulating layer 221 can be made of a high-k dielectric (High-K, HK) insulating material, such as a dielectric material with a dielectric constant K greater than or equal to 3.9. Examples include, but are not limited to, high-k materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2).
[0157] In some embodiments, the gate electrode layer 222 can be made of a metallic material or an alloy material, such as a material containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it can be a metal nitride material such as titanium nitride, tantalum nitride, tungsten nitride, or titanium aluminum nitride.
[0158] like Figure 15 As shown, the second sacrificial layer 213 and the third sacrificial layer 214 are removed to form a third hole 223; the third hole 223 exposes the sidewall of the fourth sacrificial layer 219.
[0159] like Figure 16 As shown, the fourth sacrificial layer located in the fourth sub-hole is removed along the third hole.
[0160] In some embodiments, a fourth sacrificial layer located in a fourth sub-via is removed along the third via 223 to form a second sub-groove 224. The second sub-groove 224 exposes a portion of the sidewalls of the semiconductor layer 220.
[0161] Understandably, since the semiconductor layer 220 is arranged in a ring around the gate insulating layer 221 in the second hole, removing the fourth sacrificial layer located in the fourth sub-hole along the third hole exposes the semiconductor layer 220 for removal.
[0162] In some embodiments, when the fourth sacrificial layer located in the fourth sub-hole is removed along the third hole, the first sacrificial layer 210 and the substrate 200 are not damaged because the protective layer 212 completely covers the surface of the first sacrificial layer 210 and partially covers the substrate 200.
[0163] In some embodiments, the material of the fourth sacrificial layer 219 is the same as the material of the first sacrificial layer 210. Exemplarily, the material of the fourth sacrificial layer and the material of the first sacrificial layer are both polycrystalline silicon.
[0164] In some embodiments, removing the exposed semiconductor layer to form a plurality of transistors stacked at intervals along a first direction includes: performing wet etching on the semiconductor layer co-layered with the first insulating layer using an etching solution to remove the semiconductor layer co-layered with the first insulating layer.
[0165] like Figure 17 As shown, a wet etching process is used to etch the semiconductor layer 220, which is on the same layer as the first insulating layer 201, to remove the semiconductor layer 220. An isolation layer 225 is formed at the location where a portion of the semiconductor layer 220 has been removed, so that the semiconductor layers 220 are spaced apart from each other in a first direction. In some embodiments, the material of the isolation layer 225 includes, but is not limited to, silicon oxide or silicon nitride.
[0166] Specifically, the etching solution used to etch the semiconductor layer can include acid solutions such as hydrochloric acid (HCl), hydrofluoric acid (HF), and acetic acid at different concentrations and temperatures.
[0167] Here, the isolation layer 225 ensures that the semiconductor layer 220 will not be contaminated or damaged in subsequent processes.
[0168] In some embodiments, the protective layer 212 and the first sacrificial layer 210 are removed to expose the first electrode 209 in the second sub-hole; a dielectric layer covering the surface of the first electrode and a second electrode are sequentially formed within the first hole to form a capacitor. Figure 18A and Figure 18B As shown, the capacitor includes: a dielectric layer 226 that completely covers the surfaces of the first sub-electrode and the second sub-electrode and partially covers the surface of the third sub-electrode; and a second electrode 227 that covers the surface of the dielectric layer 226. This increases the contact area between the first electrode and the dielectric layer, thereby improving the capacitance of the capacitor.
[0169] In other embodiments, the protective layer 212 and the first sacrificial layer 210 are removed to expose the first electrode 209 in the second sub-via, and a fifth sub-via spaced apart along a first direction is formed based on the isolation layer 225 etched into the first via. A dielectric layer and a second electrode are formed in the first via, the second sub-via, and the fifth sub-via; wherein the second electrode covers the inner sidewall of the dielectric layer, and the dielectric layer covers the inner sidewall of the first electrode as well as the inner sidewalls of the first via and the fifth sub-via.
[0170] In some embodiments, the capacitor further includes a conductive layer 228, which can serve as a common electrode of the capacitor. Exemplarily, the material of the conductive layer 228 includes, but is not limited to, polycrystalline silicon.
[0171] In this embodiment of the present disclosure, after the first sacrificial layer is formed in the second sub-hole of the first hole, the third sub-hole is formed by etching back a portion of the first insulating layer. The formed protective layer conformally covers the inner wall of the third sub-hole and the surface of the first sacrificial layer, effectively increasing the lateral etching distance required to expose the first sacrificial layer. At the same time, the protective layer also covers part of the substrate surface. Therefore, during the formation of other structures (such as transistors), the protective layer can effectively prevent the first sacrificial layer and the substrate from being damaged, thereby improving the performance and reliability of the semiconductor device.
[0172] This disclosure also provides a semiconductor device manufactured using the manufacturing method provided in any of the above embodiments, comprising: a substrate; a plurality of memory cell layers stacked at intervals along a first direction on the substrate, each memory cell layer including a plurality of memory cells arranged in an array; each memory cell including a capacitor, the capacitor including a first electrode; first electrodes of the plurality of memory cells arranged along the first direction in different memory cell layers being distributed at intervals along the first direction, each first electrode including a first sub-electrode, a second sub-electrode, and a third sub-electrode connecting the first sub-electrode and the second sub-electrode; the first sub-electrode and the second sub-electrode both having annular cross-sections perpendicular to the first direction; the third sub-electrode extending along the first direction; and the memory cell further including a plurality of transistors stacked at intervals along the first direction.
[0173] In some embodiments, such as Figure 18A and Figure 18B As shown, the capacitor further includes: a dielectric layer 226, which completely covers the surfaces of the first sub-electrode and the second sub-electrode and partially covers the surface of the third sub-electrode; and a second electrode 227, which covers the surface of the dielectric layer 226.
[0174] Figure 19 This is a partial structural schematic diagram of a capacitor provided in an embodiment of this disclosure. Exemplarily, as shown... Figure 19As shown, the first electrode 209 includes a first sub-electrode 209-1, a second sub-electrode 209-2, and a third sub-electrode 209-3 connecting the first sub-electrode 209-1 and the second sub-electrode 209-2; the first sub-electrode 209-1 and the second sub-electrode 209-2 are both annular in cross-section perpendicular to the first direction (cross-section parallel to the XY plane); the third sub-electrode 209-3 extends along the first direction and has opposing inner and outer sidewalls. A dielectric layer 226 completely covers the surfaces of the first sub-electrode 209-1 and the second sub-electrode 209-2 and partially covers the surface of the third sub-electrode 209-3. Specifically, the dielectric layer 226 covers the inner sidewall of the third sub-electrode 209-3 and the entire surfaces of the first sub-electrode 209-1 and the second sub-electrode 209-2. The second electrode 227 covers the inner sidewall of the dielectric layer 226. In this way, the contact area between the first electrode 209 and the dielectric layer 226, and between the dielectric layer 226 and the second electrode 227, can be increased, thereby improving the capacitance of the capacitor.
[0175] In some embodiments, the capacitor further includes a conductive layer 228, which can serve as a common electrode of the capacitor. Exemplarily, the material of the conductive layer 228 includes, but is not limited to, polycrystalline silicon.
[0176] In some embodiments, such as Figure 18A and Figure 18B As shown, the transistor includes a gate electrode layer 222, a semiconductor layer 220 that at least partially surrounds the gate electrode layer 222, and a gate insulating layer 221 located at least between the gate electrode layer 222 and the semiconductor layer 220.
[0177] In some embodiments, such as Figure 18A As shown, the capacitor 229 is located on one side of the transistor along a second direction parallel to the substrate surface; the first electrode 209 of the capacitor 229 is connected to the semiconductor layer 220 of the transistor.
[0178] In some embodiments, such as Figure 18A As shown, the semiconductor device further includes: a plurality of bit lines 230 extending along a third direction parallel to the substrate surface; each bit line 230 is connected to a semiconductor layer 220 of a plurality of memory cells arranged along the third direction in the same memory cell layer; wherein the first direction is perpendicular to both the second direction and the third direction, and the second direction intersects the third direction.
[0179] In some embodiments, a dielectric layer 231 is provided between adjacent bit lines 230 in the second direction, and the material of the dielectric layer 231 includes, but is not limited to, silicon oxide.
[0180] The semiconductor device provided in this disclosure has the same technical effect as the manufacturing method of the semiconductor device provided in this disclosure, and will not be described again here.
[0181] Based on the same inventive concept, this disclosure also provides an electronic device, which includes the semiconductor device provided in any of the above embodiments, or a semiconductor device prepared according to the manufacturing method of the semiconductor device provided in any of the above embodiments. The electronic device may be: a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.
[0182] It should be understood that the phrases "some embodiments," "one embodiment," or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0183] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0184] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: Provide substrate; A stacked layer is formed by alternately stacking a first insulating layer and a second insulating layer on the substrate along a first direction; Forming a first hole and a second hole through the stacked layers; The first hole includes a first sub-hole extending along the first direction and a second sub-hole extending along a second direction parallel to the substrate surface into the second insulating layer; A first electrode and a first sacrificial layer are sequentially formed in the second sub-hole; A portion of the first insulating layer is removed along the first hole to form a third sub-hole extending into the first insulating layer along the second direction; A protective layer is formed that at least covers the inner wall of the third sub-hole and the surface of the first sacrificial layer; Multiple transistors are formed in the second hole and stacked at intervals along the first direction; Remove the protective layer and the first sacrificial layer to expose the first electrode in the second sub-hole; A dielectric layer and a second electrode are sequentially formed within the first hole to cover the surface of the first electrode, thereby forming a capacitor.
2. The manufacturing method according to claim 1, characterized in that, The method further includes: A second sacrificial layer and a third sacrificial layer are sequentially formed to cover the protective layer; a portion of the first insulating layer is removed along the second hole to form a fourth sub-hole extending into the first insulating layer along the second direction; the fourth sub-hole exposes a portion of the sidewall of the second sacrificial layer. A fourth sacrificial layer is formed in the fourth sub-hole; A semiconductor layer and a gate insulating layer are sequentially formed in the second hole, and a conductive material is filled in as a gate electrode layer. The fourth sacrificial layer in the fourth sub-hole is removed to expose a portion of the sidewall of the semiconductor layer. The exposed semiconductor layer is then removed to form a plurality of transistors stacked at intervals along the first direction.
3. The manufacturing method according to claim 2, characterized in that, The removal of the fourth sacrificial layer in the fourth sub-hole includes: The second and third sacrificial layers are removed to form a third hole; the third hole exposes the sidewall of the fourth sacrificial layer. The fourth sacrificial layer located in the fourth sub-hole is removed along the third hole.
4. The manufacturing method according to claim 2, characterized in that, The material of the fourth sacrificial layer is the same as that of the first sacrificial layer.
5. The manufacturing method according to claim 2, characterized in that, The dimension of the third sub-hole in the second direction is less than or equal to the dimension of the second sub-hole in the second direction.
6. The manufacturing method according to claim 2, characterized in that, The size of the fourth sub-hole in the second direction is less than or equal to the size of the first electrode in the second direction.
7. The manufacturing method according to claim 2, characterized in that, The method further includes: A first trench is formed through the stacked layers; a second hole is located between the first hole and the first trench; wherein the first trench extends along a third direction parallel to the surface of the substrate; A fifth and a sixth sacrificial layer are formed within the second hole; A portion of the second insulating layer is removed along the first trench to form a first sub-trench, the first sub-trench exposing at least a portion of the fifth sacrificial layer; A conductive material is deposited in the first trench and the first sub-trench, and the conductive material is in contact with the fifth sacrificial layer; The conductive material located outside the first sub-slot is removed, and the remaining conductive material located inside the first sub-slot forms multiple bit lines extending along the third direction; Remove the fifth and sixth sacrificial layers from the second hole; Multiple transistors are formed in the second hole and stacked at intervals along the first direction; Wherein, the first direction is perpendicular to both the second direction and the third direction, and the second direction intersects with the third direction.
8. The manufacturing method according to any one of claims 1-7, characterized in that, The material of the protective layer includes at least one of silicon oxide, silicon carbonitride, or silicon carbonitride.
9. The manufacturing method according to claim 8, characterized in that, The protective layer is made of the same material as the first insulating layer.
10. The manufacturing method according to claim 1, characterized in that, The formation of the first electrode and the first sacrificial layer in the second sub-hole includes: A first electrode material and a first sacrificial material are sequentially formed to at least cover the sidewalls of the first sub-hole and the second sub-hole; Remove the first electrode material and the first sacrificial material located outside the second sub-hole; the first electrode material located inside the second sub-hole constitutes the first electrode, and the first sacrificial material located inside the second sub-hole constitutes the first sacrificial layer.
11. The manufacturing method according to claim 2, characterized in that, The removal of the exposed semiconductor layer to form a plurality of transistors stacked at intervals along the first direction includes: The semiconductor layer, which is in the same layer as the first insulating layer, is removed by wet etching using an etching solution.
12. A semiconductor device, characterized in that, Manufactured using the manufacturing method of any one of claims 1-11, comprising: Substrate; A plurality of memory cell layers are stacked at intervals along a first direction on the substrate, each memory cell layer including a plurality of memory cells arranged in an array; each memory cell includes a capacitor, and the capacitor includes a first electrode; the first electrodes of the plurality of memory cells arranged along the first direction in different memory cell layers are distributed at intervals along the first direction, each first electrode including a first sub-electrode, a second sub-electrode, and a third sub-electrode connecting the first sub-electrode and the second sub-electrode; the first sub-electrode and the second sub-electrode are both annular in cross-section perpendicular to the first direction; the third sub-electrode extends along the first direction; The storage unit also includes a plurality of transistors stacked at intervals along the first direction.
13. The semiconductor device according to claim 12, characterized in that, The capacitor also includes: A dielectric layer that completely covers the surfaces of the first sub-electrode and the second sub-electrode and partially covers the surface of the third sub-electrode; The second electrode covers the surface of the dielectric layer.
14. The semiconductor device according to claim 12, characterized in that, The transistor includes a gate electrode layer, a semiconductor layer at least partially surrounding the gate electrode layer, and a gate insulating layer located at least between the gate electrode layer and the semiconductor layer.
15. The semiconductor device according to claim 14, characterized in that, The capacitor is located on one side of the transistor along a second direction parallel to the substrate surface; The first electrode of the capacitor is connected to the semiconductor layer of the transistor.
16. The semiconductor device according to claim 15, characterized in that, The semiconductor device further includes: Multiple bit lines extending along a third direction parallel to the substrate surface; each bit line is connected to a semiconductor layer of multiple memory cells arranged along the third direction in the same memory cell layer; Wherein, the first direction is perpendicular to both the second direction and the third direction, and the second direction intersects with the third direction.
17. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 12 to 16.