Semiconductor device including active pattern and gate electrode

Abstract

An example semiconductor device includes: a first cell active pattern and a first dummy active pattern arranged in a first horizontal direction; a first gate electrode adjacent to the first cell active pattern and the first dummy active pattern; a first cell gate dielectric layer between the first cell active pattern and the first gate electrode and a first dummy gate dielectric layer between the first dummy active pattern and the first gate electrode; a first gate contact plug contacting the first dummy active pattern and the first gate electrode; and a bit line disposed at a lower level than the first cell active pattern, connected to the first cell active pattern, and spaced apart from the first dummy active pattern.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0166104, filed on November 20, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including an active pattern and a gate electrode. Background Technology

[0003] Research is underway to reduce the size of the components that make up semiconductor devices and improve their performance. For example, in DRAM, research is being conducted to reliably and stably fabricate components with reduced dimensions. As component size decreases, the dispersion characteristics of semiconductor devices may deteriorate. Summary of the Invention

[0004] This disclosure relates to a semiconductor device capable of improving integration and performance, and a method for forming the semiconductor device.

[0005] In some embodiments, a semiconductor device includes: a first cell active pattern and a first dummy active pattern arranged along a first horizontal direction; a first gate electrode adjacent to the first cell active pattern and the first dummy active pattern; a first cell gate dielectric layer between the first cell active pattern and the first gate electrode and a first dummy gate dielectric layer between the first dummy active pattern and the first gate electrode; a first gate contact plug contacting the first dummy active pattern and the first gate electrode; and a bit line disposed at a level lower than the first cell active pattern, connected to the first cell active pattern, and spaced apart from the first dummy active pattern.

[0006] In some embodiments, a semiconductor device includes: a memory cell array region and an interface region, adjacent to each other in a first horizontal direction; a gate electrode extending in the first horizontal direction across the memory cell array region and into the interface region; an active pattern including a cell active pattern disposed in the memory cell array region and arranged in a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, and a dummy active pattern disposed in the interface region and arranged in the second horizontal direction; a gate dielectric layer between the gate electrode and the active pattern; a bit line extending in the second horizontal direction across the memory cell array region and connected to the cell active pattern below it; and a gate contact plug disposed in the interface region, wherein the active pattern penetrates the gate electrode in a vertical direction perpendicular to the first and second horizontal directions, a first gate electrode in the gate electrode is adjacent to a first dummy active pattern in the dummy active pattern, and a first gate contact plug in the gate contact plug vertically overlaps with the first dummy active pattern and contacts the first gate electrode.

[0007] In some embodiments, a semiconductor device includes: a memory cell array region and an interface region adjacent to each other in a first horizontal direction; a gate electrode extending in the first horizontal direction across the memory cell array region and into the interface region; a bit line extending in a second horizontal direction perpendicular to the first horizontal direction and across the memory cell array region; an active pattern penetrating the gate electrode in a vertical direction perpendicular to both the first and second horizontal directions, and including a cell active pattern disposed in the memory cell array region and a dummy active pattern disposed in the interface region; a gate dielectric layer between the active pattern and the gate electrode; and a gate contact plug connected to the gate electrode, wherein the dummy active pattern includes a first dummy active pattern and a second dummy active pattern adjacent to each other in the second horizontal direction, the length of the first dummy active pattern in the first horizontal direction being greater than the length of each cell active pattern in the first horizontal direction, the length of the first dummy active pattern in the first horizontal direction being greater than the length of the second dummy active pattern in the first horizontal direction, and the first gate contact plug in the gate contact plug contacts the first gate electrode in the gate electrode. Attached Figure Description

[0008] The aspects, features, and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 , Figure 2 and Figure 3 This is a diagram showing an example of a semiconductor device.

[0010] Figure 4 This is a schematic perspective view showing an example of a semiconductor device.

[0011] Figure 5A , Figure 5B , Figure 6A and Figure 6B This is a diagram showing an example of a semiconductor device.

[0012] Figure 7 This is a cross-sectional view showing an example of a semiconductor device.

[0013] Figure 8 This is a cross-sectional view showing an example of a semiconductor device.

[0014] Figure 9 This is a cross-sectional view showing an example of a semiconductor device.

[0015] Figure 10 This is a cross-sectional view showing an example of a semiconductor device.

[0016] Figure 11 This is a cross-sectional view showing an example of a semiconductor device.

[0017] Figure 12 This is a cross-sectional view showing an example of a semiconductor device.

[0018] Figure 13 This is a plan view showing an example of a semiconductor device.

[0019] Figure 14A and Figure 14B This is a diagram showing an example of a semiconductor device.

[0020] Figure 15 This is a plan view showing an example of a semiconductor device.

[0021] Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A and Figure 21B This is a cross-sectional view illustrating an example of a method for forming a semiconductor device. Detailed Implementation

[0022] In the following text, terms such as "upper part," "middle part," and "lower part" may be replaced by other terms (e.g., terms such as "first," "second," and "third") and may be used to describe elements in this specification. Terms such as "first," "second," and "third" may be used to describe various elements, but these elements are not limited by these terms, and a "first element" may be referred to as a "second element." In this specification, terms such as "lower part," "upper part," "upper end," and "lower end" may be terms used based on the accompanying drawings.

[0023] In this specification, among active patterns, an active pattern electrically connected to the bit line and the data storage structure can be defined as a cell active pattern, while an active pattern not electrically connected to the bit line and the data storage structure can be defined as a dummy active pattern.

[0024] refer to Figure 1 , Figure 2 and Figure 3 An example of semiconductor device 1 will be described below. Figure 1 , Figure 2 and Figure 3 middle, Figure 1 This is a conceptual perspective view of semiconductor device 1. Figure 2 It is a conceptual representation Figure 1 A perspective view of the electrical connection relationship between the first structure ST1 and the second structure ST2, and Figure 3 This is a circuit diagram showing a portion of the circuitry of the first structure ST1.

[0025] refer to Figure 1 , Figure 2 and Figure 3 The semiconductor device 1 may include a first structure ST1 and a second structure ST2 that vertically overlaps the first structure ST1. The second structure ST2 may be disposed on the first structure ST1. In some embodiments, the second structure ST2 may be disposed below the first structure ST1.

[0026] In some implementations, the first structure ST1 may include a storage unit MC ( Figure 3 The first chip structure is ST2, and the second chip structure ST2 may be a second chip structure including peripheral circuitry (e.g., a readout amplifier, a sub-word line driver, etc.) for the operation of the memory cell MC.

[0027] In some implementations, the first structure ST1 and the second structure ST2 can be formed by bonding through a bonding process (e.g., a wafer bonding process). For example, the first structure ST1 can contact and bond to the second structure ST2.

[0028] Semiconductor device 1 may include multiple memory banks BA and peripheral regions PERI.

[0029] The peripheral area PERI can include the first peripheral area PERI1 in the first structure ST1 and the second peripheral area PERI2 in the second structure ST2. The peripheral area PERI can be a peripheral area in which peripheral circuitry for inputting / outputting data or commands or inputting power / ground is provided.

[0030] Each of the multiple memory banks BA may include a first memory bank area BA1 in the first structure ST1 and a second memory bank area BA2 in the second structure ST2.

[0031] The first storage area BA1 in the first structure ST1 may include the storage cell array area MCA ( Figure 3 ) and Interface Area (IA) Figure 3 The storage cell array area MCA and the interface area IA can be adjacent to each other in the first horizontal direction X. For example, the storage cell array area MCA and the interface area IA can include a first interface area IA1, a first storage cell array area MCA1, a second interface area IA2, a second storage cell array area MCA2, and a third interface area IA3, which are sequentially arranged in the first horizontal direction.

[0032] The first storage area BA1 in the first structure ST1 may include storage cell MC ( Figure 3 ), Word line WL ( Figure 3 ) and bitline BL ( Figure 3 ).

[0033] A memory cell MC can be disposed within a memory cell array region MCA. Each word line WL can extend in a first horizontal direction X. A word line WL can cross the memory cell array region MCA, can be electrically connected to the memory cell MC, and can extend into an interface region IA adjacent to the memory cell array region MCA. For example, a first word line WL1 in the word line WL can cross the first memory cell array region MCA1 and can extend into a first interface region IA1 and a second interface region IA2. A second word line WL2 in the word line WL can cross the second memory cell array region MCA2 and can extend into a second interface region IA2 and a third interface region IA3.

[0034] The first structure ST1 may include a gate contact plug GC electrically connected to the word line WL in the interface region IA.

[0035] Bit line BL can cross the memory cell array region MCA in a second horizontal direction Y perpendicular to the first horizontal direction X, and can be electrically connected to the memory cell MC.

[0036] Each memory cell MC may include a data storage structure DS that can be used for data storage, and a cell transistor cTR that can be electrically connected to the data storage structure DS. In a memory such as DRAM, the data storage structure DS may be a cell capacitor that can store data.

[0037] The second memory bank region BA2 in the second structure ST2 may include peripheral circuitry, such as a sense amplifier electrically connected to the bit line BL in the memory cell array region MCA, and a sub-word line driver electrically connected to the word line WL in the memory cell array region MCA.

[0038] The first structure ST1 and the second structure ST2 may further include a routing interconnect structure RTa that electrically connects the first memory bank BA1 and the second memory bank BA2. For example, the routing interconnect structure RTa may include first routing interconnect structures RT_La and RT_Lb disposed in the first structure ST1, and second routing interconnect structures RT_Ua and RT_Ub disposed in the second structure ST2.

[0039] The first routing interconnect structures RT_La and RT_Lb may include a first interconnect structure RT_La electrically connected to the first memory bank region BA1 and a first bonding pad RT_Lb electrically connected to the first interconnect structure RT_La. The second routing interconnect structures RT_Ua and RT_Ub may include a second interconnect structure RT_Ua electrically connected to the second memory bank region BA2 and a second bonding pad RT_Ub electrically connected to the second interconnect structure RT_Ua.

[0040] The first bonding pad RT_Lb and the second bonding pad RT_Ub can contact and bond with each other. For example, the first bonding pad RT_Lb and the second bonding pad RT_Ub can include copper and can be bonded to each other by a metal-to-metal bonding process. Therefore, the bonding surface JN1 between the first structure ST1 and the second structure ST2 can include a metal-to-metal bonding area JNa where the first bonding pad RT_Lb of the first structure ST1 and the second bonding pad RT_Ub of the second structure ST2 bond with each other, and a dielectric bonding area JNb where the dielectric of the first structure ST1 and the dielectric of the second structure ST2 bond with each other.

[0041] Next, refer to Figure 4 An example describing the routing interconnect structure RTa and the bonding surface JN1. Figure 4 It shows Figure 2 A schematic perspective view of an example of the intermediate routing interconnect structure RTa and the bonding surface JN1.

[0042] In the example, refer to Figure 4 It can be replaced by the routing interconnection structure RTb. Figure 2In the routing interconnect structure RTa, the first bonding pad RT_Lb and the second bonding pad RT_Ub can be omitted, and can be replaced by bonding surface JN2. Figure 2 The bonding surface JN1 in the middle, wherein the metal indirect bonding region JNa can be omitted.

[0043] The routing interconnect structure RTb may include a first interconnect structure RT_Laa, a second interconnect structure RT_Uaa, and a connection structure RT_C. The first interconnect structure RT_Laa is included in the first structure ST1 and electrically connected to the first memory bank region BA1. The second interconnect structure RT_Uaa is included in the second structure ST2 and electrically connected to the second memory bank region BA2. The connection structure RT_C extends from the first structure ST1 to the second structure ST2 and electrically connects the first interconnect structure RT_Laa and the second interconnect structure RT_Uaa. The bonding surface JN2 between the first structure ST1 and the second structure ST2 may be formed as a dielectric bonding surface in which the dielectrics of the first structure ST1 and the second structure ST2 are bonded to each other. The connection structure RT_C may include a through-hole or a through-connection plug capable of penetrating the bonding surface JN2.

[0044] The following text will combine Figures 1 to 3 An example of the first structure ST1 of semiconductor device 1 is described below. Figures 1 to 3 The example of the first structure ST1 of the semiconductor device 1 described herein, but in the example implementation described below, Figure 3 The routing interconnect structure RTa and the bonding surface JN1 described herein can be replaced with... Figure 4 The routing interconnect structure RTb and the bonding surface JN2 described herein. Additionally, the example embodiments described below can be combined with each other to form example embodiments.

[0045] First, together with Figures 1 to 3 as well as Figure 5A , Figure 5B , Figure 6A and Figure 6B Let's describe an example of the semiconductor device 1 described above. Figure 5A , Figure 5B , Figure 6A and Figure 6B middle, Figure 5A This is a plan view showing an example of a semiconductor device. Figure 5B It shows Figure 5A A magnified view of a portion of the letter "A" in the image. Figure 6A It shows along Figure 5A A cross-sectional view of the region intercepted by lines I-I' and II-II' in the diagram, and Figure 6B It shows along Figure 5A A cross-sectional view of the region intercepted by line III-III' in the diagram.

[0046] refer to Figure 5A , Figure 5B , Figure 6A and Figure 6B Together Figures 1 to 3 As described above, the storage cell array area MCA and the interface area IA can be adjacent to each other in the first horizontal direction X. The storage cell array area MCA and the interface area IA can include a first interface area IA1, a first storage cell array area MCA1, a second interface area IA2, a second storage cell array area MCA2, and a third interface area IA3, which are sequentially arranged in the first horizontal direction X.

[0047] The following text will focus on describing one of the memory cell array areas (MCAs).

[0048] The semiconductor device 1 may further include an active pattern 9, a gate electrode 15, and a gate dielectric layer 12. The active pattern 9 may include a semiconductor material that can be used as a channel region of a transistor. For example, each active pattern 9 may include at least one of silicon, germanium, silicon-germanium, oxide semiconductor, or a two-dimensional material layer having semiconductor properties. For example, each active pattern 9 may include a semiconductor material such as single-crystal silicon.

[0049] The active pattern 9 may include a cell active pattern 9a and a dummy active pattern 9b. The cell active pattern 9a may be disposed in the memory cell array region MCA and may be arranged along a first horizontal direction X and a second horizontal direction Y. The dummy active pattern 9b may be disposed in each interface region IA along the second horizontal direction Y. The dummy active pattern 9b may be adjacent to the cell active pattern 9a in the first horizontal direction X.

[0050] Each unit active pattern 9a may include a first source / drain region SD1, a second source / drain region SD2 on the first source / drain region SD1, and a channel region CH between the first source / drain region SD1 and the second source / drain region SD2.

[0051] The active pattern 9 can have a cylindrical shape extending in a vertical direction Z perpendicular to the first horizontal direction X and the second horizontal direction Y. Therefore, the active pattern 9 can also be referred to as an active pillar, a semiconductor pillar, a semiconductor pattern, or a channel pattern.

[0052] Each active pattern 9a can be a strip shape extending in the first horizontal direction X. Each dummy active pattern 9b can be a strip shape extending in the first horizontal direction X. Each active pattern 9a can be a quadrilateral or elliptical shape elongated in the first horizontal direction X. The width of each active pattern 9a in the second horizontal direction Y can be substantially the same as the width of each dummy active pattern 9b in the second horizontal direction Y.

[0053] The active unit pattern 9a may include a first active unit pattern 9a_1 and a second active unit pattern 9a_2 that are adjacent to each other in the second horizontal direction Y. The dummy active pattern 9b may include a first dummy active pattern 9b_1 and a second dummy active pattern 9b_2 that are adjacent to each other in the second horizontal direction Y. The first active unit pattern 9a_1 and the first dummy active pattern 9b_1 may be arranged along the first horizontal direction X. The second active unit pattern 9a_2 and the second dummy active pattern 9b_2 may be arranged along the first horizontal direction X.

[0054] The length of the first dummy source pattern 9b_1 in the first horizontal direction X can be different from the length of the second dummy source pattern 9b_2 in the first horizontal direction X. For example, the length of the first dummy source pattern 9b_1 in the first horizontal direction X can be greater than the length of the second dummy source pattern 9b_2 in the first horizontal direction X. The length of the first dummy source pattern 9b_1 in the first horizontal direction X can be at least twice the length of the second dummy source pattern 9b_2 in the first horizontal direction X.

[0055] The length of the first dummy active pattern 9b_1 in the first horizontal direction X can be greater than the length of the active pattern 9a of each unit in the first horizontal direction X.

[0056] The length of the second dummy active pattern 9b_2 in the first horizontal direction X can be substantially equal to the length of each unit active pattern 9a in the first horizontal direction X.

[0057] Gate electrode 15 can be the word line WL described above ( Figure 3 Each gate electrode 15 may extend in a first horizontal direction X. The gate electrode 15 may extend across the memory cell array region MCA and into the interface region IA, and may be adjacent to the active pattern 9. The gate electrode 15 may face the side surface of the active pattern 9.

[0058] Each gate electrode 15 may be formed of, but is not limited to, doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof. Each gate electrode 15 may comprise a single layer or multiple layers of the aforementioned conductive materials.

[0059] The active pattern 9 can penetrate the gate electrode 15 in the vertical direction Z. The gate electrode 15 can surround the side surface of the active pattern 9. For example, the gate electrode 15 can surround the side surface of the channel region CH of the cell active pattern 9a.

[0060] The gate electrode 15 may include a first gate electrode 15_1 and a second gate electrode 15_2 that are adjacent to each other in the second horizontal direction Y. The first unit active pattern 9a_1 and the first dummy active pattern 9b_1 can penetrate the first gate electrode 15_1, and the second unit active pattern 9a_2 and the second dummy active pattern 9b_2 can penetrate the second gate electrode 15_2.

[0061] A gate dielectric layer 12 may be disposed on a side surface of the active pattern 9. Each gate dielectric layer 12 may surround the side surface of its corresponding active pattern 9 within the active pattern 9. The gate dielectric layer 12 may be disposed between the active pattern 9 and the gate electrode 15. The gate electrode 15 may be spaced apart from the active pattern 9 by the gate dielectric layer 12. The gate dielectric layer 12 may include a unit gate dielectric layer 12a between the unit active pattern 9a and the gate electrode 15, and a dummy gate dielectric layer 12b between the dummy active pattern 9b and the gate electrode 15.

[0062] Each of the above unit transistors cTR ( Figure 3 It may include a first source / drain region SD1, a second source / drain region SD2, a channel region CH, a gate electrode 15 facing the channel region CH, and a unit gate dielectric layer 12a between the gate electrode 15 and the channel region CH.

[0063] The channel region CH can extend in the vertical direction Z. Therefore, each unit transistor cTR can include a channel region CH extending in the vertical direction Z. Therefore, the integration density of the semiconductor device 1 can be improved because the arrangement density of the unit transistors cTR can be increased.

[0064] In the adjacent gate electrode 15 and cell active pattern 9a, the gate electrode 15 can surround the entire side surface of the channel region CH of the cell active pattern 9a. Therefore, the cell transistor cTR, which can be used as a vertical channel transistor, can be a gate all-around (GAA) structure transistor that can improve current control capability.

[0065] Therefore, semiconductor devices 1, including unit transistors cTRs that can function as vertical channel transistors and all-ring gate structure transistors, can improve integration and performance.

[0066] Semiconductor device 1 may include a conductive pattern 66, which may be the aforementioned gate contact plug GC. Figure 3 In the following text, conductive pattern 66 will be referred to as the gate contact plug and will be described.

[0067] Gate contact plug 66 can be connected to gate electrode 15 in interface region IA. Gate contact plug 66 can contact and be electrically connected to gate electrode 15. Each gate contact plug 66 may include at least one of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, or RuTiN.

[0068] The semiconductor device 1 may also include an insulating structure 64 and a unit contact structure 60.

[0069] The gate contact plug 66 may extend downward through the insulating structure 64 to contact and connect to the gate electrode 15. The gate contact plug 66 may extend downward from the portion penetrating the insulating structure 64, may penetrate the second gate cap pattern 42, and may extend into the insulating pattern 18. The upper surface of the gate contact plug 66 may be positioned at substantially the same level as the upper surface of the cell contact structure 60.

[0070] In the dummy active pattern 9b, the dummy active pattern that contacts the gate contact plug 66 can be the first dummy active pattern 9b_1, and the dummy active pattern that does not contact the gate contact plug 66 can be the second dummy active pattern 9b_2. The first dummy active pattern 9b_1 and the second dummy active pattern 9b_2 can be adjacent to each other in the second horizontal direction Y.

[0071] The gate contact plug 66 can contact the upper surface of the gate electrode 15 and the outer and inner surfaces of the upper region of the gate electrode 15. In this case, the inner surface of the gate electrode 15 can be the side surface of the gate electrode 15 facing the first dummy active pattern 9b_1, and the outer surface of the gate electrode 15 can be the side surface of the gate electrode 15 facing the inner surface of the gate electrode 15.

[0072] The gate contact plug 66 can contact the upper surface of the gate electrode 15, as well as the outer and inner surfaces of the upper region of the gate electrode 15, to reduce the contact resistance between the gate contact plug 66 and the gate electrode 15 that are in contact with each other. Therefore, the electrical characteristics of the semiconductor device 1 can be improved.

[0073] The gate contact plug 66 can be vertically overlapped with the first dummy active pattern 9b_1. For example, in the gate contact plug 66, the first gate contact plug 66_1 can be vertically overlapped with the first dummy active pattern 9b_1 and can be connected to the first gate electrode 15_1. The first gate contact plug 66_1 can contact the first dummy active pattern 9b_1, the first gate electrode 15_1, and the dummy gate dielectric layer 12b between the first dummy active pattern 9b_1 and the first gate electrode 15_1. The first gate contact plug 66_1 can contact the first dummy active pattern 9b_1 and can be spaced apart from the second dummy active pattern 9b_2.

[0074] Because of the first dummy active pattern 9b_1, the gate contact plug 66 connected to the gate electrode 15 can be formed stably and reliably. For example, the first dummy active pattern 9b_1 and the dummy gate dielectric layer 12b can be used as supports to stably support the gate electrode 15, and the gate contact plug 66 can stably contact the gate electrode 15.

[0075] In the region that vertically overlaps with the gate contact plug 66, the upper end of the dummy gate dielectric layer 12b can be positioned at a level lower than the upper end of the gate electrode 15 below the lower surface of the gate contact plug 66.

[0076] In the region that vertically overlaps with the gate contact plug 66, the lowermost end of the portion of the gate contact plug 66 that contacts the first dummy active pattern 9b_1 can be positioned at a level lower than the upper end of the gate electrode 15 below the lower surface of the gate contact plug 66.

[0077] In the region that vertically overlaps with the gate contact plug 66, the gate contact plug 66 may contact the two side surfaces of the upper region of the gate electrode 15.

[0078] In the gate contact plug 66, the first gate contact plug 66_1 connected to the first gate electrode 15_1 can be connected to the first gate electrode 15_1 in the second interface region IA2, and the gate contact plug connected to the second gate electrode 15_2 can be connected to the second gate electrode 15_2 in the first interface region IA1. The first gate electrode 15_1 may have an inner surface facing the first dummy active pattern 9b_1 and an outer surface opposite to the inner surface. The first gate contact plug 66_1 may contact the upper surface and the outer surface of the first gate electrode 15_1. The first gate contact plug 66_1 may extend between the inner surface of the first gate electrode 15_1 and the first dummy active pattern 9b_1, such that the first gate contact plug 66_1 may contact the inner surface of the first gate electrode 15_1 and the side surface of the first dummy active pattern 9b_1.

[0079] In the example, the upper surface of the gate contact plug 66 can be positioned at a higher level than the upper surface of the active pattern 9. For example, the first gate contact plug 66_1 ( Figure 5B The upper surface of ) can be set at a position greater than that of the first unit active pattern 9a_1 ( Figure 5B The upper surface of ) and the first dummy active pattern 9b_1 ( Figure 5B The upper surface of the surface is at a higher level.

[0080] Semiconductor device 1 may include a wire 24, which may be the aforementioned bit line BL ( Figure 3 In the following text, conductor 24 will be referred to as a bit line. Semiconductor device 1 may also include a bit line capping pattern 27 below bit line 24.

[0081] Each bit line 24 may extend in a second horizontal direction Y and may span the memory cell array region MCA. The bit line 24 may be connected to the cell active pattern 9a below the cell active pattern 9a. For example, the bit line 24 may be electrically connected to the first source / drain region SD1 of the cell active pattern 9a. The bit line 24 may be electrically connected to the first source / drain region SD1 of the cell transistor cTR. Each bit line 24 may include a first conductive layer 24a, a second conductive layer 24b below the first conductive layer 24a, and a third conductive layer 24c below the second conductive layer 24b. The first conductive layer 24a may include a doped semiconductor material layer. For example, the first conductive layer 24a may include at least one of a silicon layer or a silicon-germanium layer. For example, the first conductive layer 24a may include a polysilicon layer having an N-type conductivity type. The second conductive layer 24b may include at least one of a metal, a metal compound, or a metal-semiconductor compound. For example, the second conductive layer 24b may include at least one of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, CoSi, MoSi, TaSiN, RuTiN, or NiSi. For example, the second conductive layer 24b may include a metal semiconductor compound layer and a metal compound layer (e.g., a Ti layer, etc.) on top of the metal semiconductor compound layer (e.g., a Ti layer, etc.). The third conductive layer 24c may include a conductive material having a resistivity lower than that of the first conductive layer 24a. For example, the third conductive layer 24c may include a conductive material such as W, Mo, Ru, or Ni. The bit line capping pattern 27 may include an insulating material. For example, the bit line capping pattern 27 may include silicon nitride.

[0082] Semiconductor device 1 may also include a data storage structure DS.

[0083] Cell contact structure 60 can be connected to cell active pattern 9a. Cell contact structure 60 can be electrically connected to the second source / drain region SD2 of cell active pattern 9a. Cell contact structure 60 can be electrically connected to the second source / drain region SD2 of cell transistor cTR. Each cell contact structure 60 can be connected to its corresponding cell active pattern in cell active pattern 9a. Each cell contact structure 60 can contact the upper surface and upper side surface of its corresponding cell active pattern in cell active pattern 9a.

[0084] Each unit contact structure 60 may include a first conductive layer 48, a second conductive layer 51 on the first conductive layer 48, a third conductive layer 54 on the second conductive layer 51, and a fourth conductive layer 57 on the third conductive layer 54.

[0085] The first conductive layer 48 may be an N-type semiconductor layer with a first impurity concentration, and the second conductive layer 51 may be an N-type semiconductor layer with a second impurity concentration higher than that of the first conductive layer 48. For example, the first conductive layer 48 may be an N-type semiconductor layer with a first impurity concentration and may be a first doped silicon layer, and the second conductive layer 51 may be a second doped polysilicon layer with a higher impurity concentration than that of the first doped silicon layer of the first conductive layer 48. The third conductive layer 54 may include a metal semiconductor compound layer, and the fourth conductive layer 57 may include a metal nitride or a metal. For example, the third conductive layer 54 may include TiSi, TiSiN, TaSi, TaSiN, MoSi, NiSi, CoSi, etc. The fourth conductive layer 57 may include at least one of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, or RuTiN.

[0086] The maximum width of each gate contact plug 66 can be greater than the maximum width of each first conductive layer 48 of the unit contact structure 60.

[0087] The data storage structure DS may include a first electrode 72a connected to a cell contact structure 60, a second electrode 72c covering the first electrode 72a, and a dielectric layer 72b between the first electrode 72a and the second electrode 72c. Each first electrode 72a may have a cylindrical shape extending in the vertical direction Z. The data storage structure DS may be a cell capacitor of a memory such as DRAM.

[0088] The data storage structure DS can be positioned at a higher level than the active cell pattern 9a. The cell contact structure 60 can electrically connect the active cell pattern 9a and the data storage structure DS between the active cell pattern 9a and the first electrode 72a of the data storage structure DS.

[0089] The semiconductor device 1 may also include an insulating pattern 18. The insulating pattern 18 may be disposed between gate electrodes 15 in the memory cell array region MCA and may extend into the interface region IA. The insulating pattern 18 may have a lower surface disposed at a level lower than the level of the gate electrodes 15 and an upper surface disposed at a level higher than the level of the gate electrodes 15.

[0090] The semiconductor device 1 may further include a first gate capping pattern 21 disposed below the lower surface of the gate electrode 15, and a second gate capping pattern 42 disposed on the upper surface of the gate electrode 15 and extending to the upper surface of the insulating pattern 18. The first gate capping pattern 21 and the second gate capping pattern 42 may be formed of an insulating material.

[0091] The insulating structure 64 may be disposed on the side surfaces of the cell contact structure 60 and the gate contact plug 66. The insulating structure 64 may include a lower insulating layer 45 and an upper insulating layer 63 on the lower insulating layer 45.

[0092] The upper surface of the lower insulating layer 45 may be disposed at a level higher than the upper surface of the first conductive layer 48, but the implementation is not limited to this. For example, the upper surface of the lower insulating layer 45 may be disposed at a level substantially the same as the upper surface of the first conductive layer 48.

[0093] The semiconductor device 1 may also include an insulating etch stop layer 69. The etch stop layer 69 may be disposed on the cell contact structure 60 and the gate contact plug 66. The first electrode 72a of the data storage structure DS may penetrate the etch stop layer 69 and may be connected to the cell contact structure 60.

[0094] The semiconductor device 1 may also include a data storage structure DS and a first upper insulating layer 78 on the etch stop layer 69, and a second upper insulating layer 87 on the first upper insulating layer 78.

[0095] The semiconductor device 1 may also include a first contact plug 81, a second contact plug 82, a first upper interconnect 84, and a second upper interconnect 85.

[0096] The first contact plug 81 can penetrate the first upper insulating layer 78 and the etch stop layer 69, and can be connected to the gate contact plug 66. The second contact plug 82 can penetrate the first upper insulating layer 78 and can be connected to the second electrode 72c of the data storage structure DS. The first upper interconnect 84 can be connected to the first contact plug 81 on the first upper insulating layer 78, and the second upper interconnect 85 can be connected to the second contact plug 82 on the first upper insulating layer 78. The second upper insulating layer 87 can cover the first upper insulating layer 78, the first upper interconnect 84, and the second upper interconnect 85.

[0097] The semiconductor device 1 may also include an insulating pad 30 that covers the lower and side surfaces of the bit line 24, and covers the lower surface of the first gate cap pattern 21, the lower surface of the dummy active pattern 9b, the lower surface of the gate dielectric layer 12 and the lower surface of the insulating pattern 18.

[0098] The semiconductor device 1 may further include a bit line shielding pattern 33 disposed below the insulating pad 30 on the side surface of the bit line 24 and below the lower surface of the bit line 24. The bit line shielding pattern 33 may be formed of a conductive material. Since the portion of the bit line shielding pattern 33 disposed between the bit lines 24 can reduce the parasitic capacitance between the bit lines 24, the decrease in signal transmission speed of the bit lines 24 can be suppressed.

[0099] The semiconductor device 1 may also include a lower cover insulating layer 36 disposed below the bit line shielding pattern 33 and the insulating pad 30.

[0100] Next, various example embodiments that can improve the performance or productivity of semiconductor device 1 will be described. The various example embodiments described below and the previously described embodiments can be combined with each other to form example embodiments. Hereinafter, the above-described elements may be directly referenced without separate detailed description, or the description may be omitted. Furthermore, the following elements may be modified or replaced with reference to the accompanying drawings; however, elements that can be modified, replaced, or added may be combined with each other or with previously described elements to form a semiconductor device.

[0101] Figure 7 It shows that along Figure 5A The cross-sectional view of some elements in the area intercepted by lines I-I' and II-II' has been modified.

[0102] In some implementations, reference Figure 7 It can be used as follows Figure 7 The dummy gate dielectric layer 112b and gate contact plug 166 shown replace the aforementioned dummy gate dielectric layer 12b. Figure 6A ) and gate contact plug 66 ( Figure 6A For example, the gate contact plug 166 can contact the upper surface and the outer surface of the gate electrode 15, and the dummy gate dielectric layer 112b can extend between the gate contact plug 166 and the dummy active pattern 9b from the portion disposed between the inner surface of the gate electrode 15 and the dummy active pattern 9b. In the region that vertically overlaps with the gate contact plug 166, the upper end of the dummy gate dielectric layer 112b can be disposed at a level higher than the upper end of the gate electrode 15.

[0103] Figure 8 It shows that along Figure 5AThe cross-sectional view of some elements in the area intercepted by lines I-I' and II-II' has been modified.

[0104] In some implementations, reference Figure 8 It can be used as follows Figure 8 The gate contact plug 266 shown and the dummy active pattern 209b replace the gate contact plug 66 described above. Figure 6A ) and dummy source pattern 9b ( Figure 6A For example, in the region vertically overlapping with the gate contact plug 266, the lowermost end of the portion where the gate contact plug 266 and the dummy active pattern 209b contact each other can be positioned at a level lower than the upper end of the gate electrode 15 located below the lower surface of the gate contact plug 266. The overall volume of the gate contact plug 266 can be increased to improve its resistive characteristics.

[0105] Figure 9 It shows that along Figure 5A The cross-sectional view of some elements in the area intercepted by lines I-I' and II-II' has been modified.

[0106] In some implementations, reference Figure 9 It can be used as follows Figure 9 The dummy gate dielectric layer 312b, gate contact plug 366, and dummy active pattern 309b shown replace the aforementioned dummy gate dielectric layer 12b. Figure 6A ), gate contact plug 66 ( Figure 6A ) and dummy source pattern 9b.

[0107] The gate contact plug 66 described above can be replaced by a gate contact plug 366 covering the two side surfaces of the upper and middle regions of the gate electrode 15. Figure 6A This increases the contact area with the gate electrode 15. The gate contact plug 366 may extend downward to contact and connect with at least a portion of the two side surfaces of the lower region of the gate electrode 15.

[0108] In the region vertically overlapping with the gate contact plug 366, the gate contact plug 366 can contact the inner and outer surfaces of the upper region of the gate electrode 15. Therefore, due to the increased contact area between the gate contact plug 366 and the gate electrode 15, the contact resistance can be reduced, thereby improving the performance of the semiconductor device 1.

[0109] In the region that vertically overlaps with or is below the lower surface of the gate contact plug 366, the upper end of the dummy gate dielectric layer 312b may be positioned at a lower level than the middle region of the gate electrode 15.

[0110] In the region that vertically overlaps with or is below the lower surface of the gate contact plug 366, the lowest point of the portion where the gate contact plug 366 and the dummy active pattern 309b are in contact with each other can be positioned at a level lower than the level of the middle region of the gate electrode 15.

[0111] Figure 10 It shows that along Figure 5A The cross-sectional view of some elements in the area intercepted by lines I-I' and II-II' has been modified.

[0112] In some implementations, reference Figure 10 It can be used as follows Figure 10 The gate contact plug 466 shown replaces the gate contact plug 66 described above. Figure 6A The aforementioned dummy gate dielectric layer 12b can be replaced by a dummy gate dielectric layer 412b that contacts the gate contact plug 466. Figure 6A ).

[0113] The gate contact plug 466 may extend upward through the lower cover insulating layer 36 and may connect to and contact the gate electrode 15. The gate contact plug 466 may extend upward from the portion that penetrates the lower cover insulating layer 36, may penetrate the insulating pad 30, and may contact the dummy active pattern 9b, the insulating pattern 18, and the dummy gate dielectric layer 412b.

[0114] In the region that vertically overlaps with the gate contact plug 466, the lower surface of the dummy gate dielectric layer 412b can be positioned at a higher level than the lower surface of the gate electrode 15.

[0115] In the region that vertically overlaps with the gate contact plug 466, the gate contact plug 466 can be connected to and in contact with the lower surface of the gate electrode 15 and the inner and outer surfaces of the lower region of the gate electrode 15.

[0116] The lower surface of the gate contact plug 466 can be positioned at a level lower than that of the bit line 24. For example, the first gate electrode 15_1 connected to the gate electrode 15 in the gate contact plug 466. Figure 5B ) and the first dummy source pattern 9b_1 in the dummy source pattern 9b ( ) Figure 5B The lower surface of the gate contact plug 466 can be set at a level lower than that of the bit line 24.

[0117] Figure 11 It shows that along Figure 5A The cross-sectional view of some elements in the area intercepted by lines I-I' and II-II' has been modified.

[0118] In some implementations, reference Figure 11 It can be used Figure 10 The dummy gate dielectric layer 412b described herein replaces the aforementioned dummy gate dielectric layer 12b. Figure 6A ), can be used Figure 11 The gate contact plug 566 described herein replaces the gate contact plug 466 described above. Figure 10 ), and can be used Figure 11 The dummy active pattern 509b described in the text replaces the aforementioned dummy active pattern 9b. Figure 6A ).

[0119] In the region vertically overlapping with the gate contact plug 566, the gate contact plug 566 can contact and connect with the lower surface of the gate electrode 15, as well as the inner and outer surfaces of the gate electrode 15, such as... Figure 10 As stated above.

[0120] In the region vertically overlapping with the gate contact plug 566, the uppermost end of the portion where the gate contact plug 566 and the dummy active pattern 509b contact each other can be located at a level higher than the lower end of the gate electrode 15 located on the gate contact plug 566. The overall volume of the gate contact plug 566 can be increased to improve its resistive characteristics.

[0121] Figure 12 It shows that along Figure 5A The cross-sectional view of some elements in the area intercepted by lines I-I' and II-II' has been modified.

[0122] In some implementations, reference Figure 12 It can be used as follows Figure 12 The dummy gate dielectric layer 612b, gate contact plug 666, and dummy active pattern 609b shown are replaced. Figure 11 The dummy gate dielectric layer 412b described in the text ( Figure 11 ), gate contact plug 566 ( Figure 11 ) and dummy source pattern 509b ( Figure 11 ).

[0123] The gate contact plug described above can be replaced by a gate contact plug 666 covering the two side surfaces of the lower and middle regions of the gate electrode 15. Figure 11 The gate contact plug 666 extends upward from the portions covering the lower and middle regions of the gate electrode 15, and can connect to and contact at least a portion of the upper region of the gate electrode 15 on both side surfaces. Therefore, due to the increased contact area between the gate contact plug 666 and the gate electrode 15, the contact resistance can be reduced, thereby improving the performance of the semiconductor device 1.

[0124] In the region that vertically overlaps with or is on the gate contact plug 666, the lower end of the dummy gate dielectric layer (612b) may be positioned at a level higher than the level of the middle region of the gate electrode 15.

[0125] In the region that vertically overlaps with or is on the gate contact plug 666, the lowest point of the portion where the gate contact plug 666 and the dummy active pattern 609b are in contact with each other can be positioned at a level higher than the level of the middle region of the gate electrode 15.

[0126] Figure 13 It shows Figure 5A The dummy source pattern 9b in the plan view ( Figure 5A and Figure 5B A modified example floor plan.

[0127] In some implementations, reference Figure 13 The aforementioned dummy active pattern with different lengths in the first horizontal direction X can be replaced by a dummy active pattern 9b1 with the same length in the first horizontal direction X. Figure 5A (9b in the middle).

[0128] In some implementations, width and length can be used with Figure 5B The first dummy source pattern 9b_1 described in the text is... Figure 5B The second dummy pattern with equal width and length is replaced by the source pattern. Figure 5B The second dummy source pattern 9b_2 described in the text is... Figure 5B Therefore, each dummy source pattern 9b1 can be formed to have the same characteristics as... Figure 5B The first dummy source pattern 9b_1 described in the text is... Figure 5B (The shape and size are equal to the shape and size.)

[0129] In another example, the dummy active pattern 9b1 can be formed to have the same size as the unit active pattern 9a. For example, the dummy active pattern 9b1 and the unit active pattern 9a can have the same length in the first horizontal direction X. When the dummy active pattern 9b1 is set to have the same size as the unit active pattern 9a, the unit active pattern 9a ( Figure 13 The active pattern 9a of the cell adjacent to the interface region IA can be defined as a dummy active pattern, and bit line 24 ( Figure 13 The bit lines adjacent to the interface area IA in the ) can be omitted.

[0130] Figure 14A It is shown in Figure 13 The dummy source pattern 9b1 described in the plan view ( Figure 13The modified example floor plan, and Figure 14B It shows Figure 14A A magnified view of part "A1".

[0131] In some implementations, reference Figure 14A and Figure 14B It can be used as follows Figure 14A and Figure 14B The dummy source pattern 9b2 shown is replaced. Figure 13 The virtual source pattern 9b1 described in the text is... Figure 13 Each dummy active pattern 9b2 may include a first region 9b2a adjacent to the memory cell array region MCA, and a second region 9b2b extending from the first region 9b2a in a direction away from the memory cell array region MCA. In this case, the direction away from the memory cell array region MCA may be the direction away from the cell active pattern 9a adjacent to the dummy active pattern 9b2.

[0132] In each dummy active pattern 9b2, the width of the first region 9b2a in the second horizontal direction Y can be substantially equal to the width of each unit active pattern 9a in the second horizontal direction Y, and the width of the second region 9b2b in the second horizontal direction Y can be less than the width of the first region 9b2a in the second horizontal direction Y.

[0133] The dummy active pattern 9b2 may include a first dummy active pattern 9b2_1 connected to the gate contact plug 66 and a second dummy active pattern 9b2_2 not connected to the gate contact plug 66.

[0134] The gate contact plug 66 can be connected to and contact the second region 9b2b corresponding to the second region 9b2b of the first dummy active pattern 9b2_1, and can be spaced apart from the first region 9b2a of the first dummy active pattern 9b2_1.

[0135] The second dummy active pattern 9b2_2 may include a second region 9b2b to increase the distance between the gate contact plug 66 and the second dummy active pattern 9b2_2. Therefore, since the width of each gate contact plug 66 in the second horizontal direction Y can be increased within a range without causing an electrical short circuit with the second dummy active pattern 9b2_2, the electrical characteristics of the gate contact plug 66 can be improved.

[0136] Figure 15 It is shown in Figure 14A The dummy source pattern 9b2 described in the plan view ( Figure 14A and Figure 14B A modified example floor plan.

[0137] In some implementations, reference Figure 15It can be used as follows Figure 15 The dummy active pattern 9b3 shown is replaced. Figure 14A and Figure 14B The dummy active pattern 9b2 described herein. The dummy active pattern 9b3 may include patterns that can be used with... Figure 14A and Figure 14B The first dummy source pattern described in the text is 9b2_1 ( Figure 14A and Figure 14B The first dummy pattern, which is essentially the same as the source pattern 9b3a, and is similar to... Figure 5A and Figure 5B The second dummy active pattern 9b_2 shown can be disconnected to the gate contact plug 66. Figure 5A and Figure 5B The second dummy active pattern 9b3b is essentially identical. The first dummy active pattern 9b3a and the second dummy active pattern 9b3b can be spaced equidistant from the memory cell array region MCA. In the first horizontal direction X, the length of each first dummy active pattern 9b3a can be greater than the length of each second dummy active pattern 9b3b.

[0138] The second dummy active pattern 9b3b can be formed to have a shorter length than the first dummy active pattern 9b3a, thereby increasing the distance between the gate contact plug 66 and the second dummy active pattern 9b3b. Therefore, since the width of each gate contact plug 66 in the second horizontal direction Y can be increased within a range without causing an electrical short circuit with the second dummy active pattern 9b3b, the electrical characteristics of the gate contact plug 66 can be improved.

[0139] Next, refer to Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A and Figure 21B Together Figure 5A Examples of methods for forming semiconductor devices are described below. Figures 16A to 21B middle, Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A and Figure 21A It shows along Figure 5A A cross-sectional view of the region intercepted by lines I-I' and II-II', and Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B and Figure 21B It shows along Figure 5A A cross-sectional view of the region intercepted by line III-III'.

[0140] refer to Figure 5A , Figure 16A and Figure 16B A sacrificial substrate 3 and a sacrificial insulating layer 6 can be stacked sequentially. An active pattern 9 can be formed on the sacrificial insulating layer 6. The active pattern 9 can be formed from a semiconductor material such as single-crystal silicon.

[0141] The active pattern 9 may include a cell active pattern 9a formed in the memory cell array region MCA and a dummy active pattern 9b formed in the interface region IA. The cell active pattern 9a may be disposed along a first horizontal direction X and a second horizontal direction Y. The dummy active pattern 9b may be disposed along the second horizontal direction Y in each interface region IA. The dummy active pattern 9b may be adjacent to the cell active pattern 9a in the first horizontal direction X. A gate dielectric layer 12 may be formed to conformally cover the sacrificial insulating layer 6 and the active pattern 9.

[0142] refer to Figure 5A , Figure 17A and Figure 17B A conductive layer can be formed on the gate dielectric layer 12, an insulating pattern 18 can be formed on the conductive layer, and the conductive layer can be partially etched to form a gate conductive layer 14. The conductive layer used to form the gate conductive layer 14 can cover the side surfaces of the active patterns 9 and can fill the space between adjacent active patterns 9 in the first horizontal direction X. A portion of the gate conductive layer 14 can be formed between the lower surface of the insulating pattern 18 and the gate dielectric layer 12, and the upper surface of the gate conductive layer 14 can be formed at a level higher than the intermediate portion between the lower and upper surfaces of each active pattern 9.

[0143] refer to Figure 5A , Figure 18A and Figure 18B After forming the bit line conductive layer, the bit line conductive layer can be patterned to form bit lines 24. Each bit line 24 may include a first conductive layer 24a, a second conductive layer 24b, and a third conductive layer 24c stacked sequentially. While patterning the bit line conductive layer to form the bit line 24, areas that do not vertically overlap with the bit line 24 can be recessed. An insulating pad 30 can be formed to conformally cover the bit lines 24 and the areas other than the bit lines 24.

[0144] refer to Figure 5A , Figure 19A and Figure 19BA bit line shielding pattern 33 can be formed on the insulating pad 30 and filled between the bit lines 24. The bit line shielding pattern 33 can be formed of a conductive material. The bit line shielding pattern 33 can be formed in the memory cell array region MCA and can be formed in a portion of each interface region IA. The bit line shielding pattern 33 can vertically overlap with a portion of each dummy active pattern 9b. A lower cover insulating layer 36 can be formed covering the bit line shielding pattern 33 and the insulating pad 30.

[0145] refer to Figure 5A , Figure 20A and Figure 20B After positioning the lower capping insulating layer 36 in a downward orientation, the sacrificial substrate 3 and the sacrificial insulating layer 6 can be removed. The gate dielectric layer 12, exposed during the removal of the sacrificial insulating layer 6, can be partially etched to expose the gate conductive layer 14. Figure 19A and Figure 19B ), and can be used for exposed gate conductive layer 14 ( Figure 19A and Figure 19B Partial etching is performed to form the gate electrode 15. The upper surface of the gate electrode 15 may be formed at a level higher than the intermediate portion between the upper and lower surfaces of each active pattern 9.

[0146] refer to Figure 5A , Figure 21A and Figure 21B A second gate capping pattern 42 can be formed on the upper surface of the gate electrode 15 and covering the upper surface of the insulating pattern 18.

[0147] A cell contact structure 60 connected to the cell active pattern 9a, a gate contact plug 66 connected to the gate electrode 15, and an insulating structure 64 on the side surface of the cell contact structure 60 and the side surface of the gate contact plug 66 can be formed.

[0148] Each unit contact structure 60 may include a first conductive layer 48, a second conductive layer 51 on the first conductive layer 48, a third conductive layer 54 on the second conductive layer 51, and a fourth conductive layer 57 on the third conductive layer 54. A gate contact plug 66 may extend downward through the insulating structure 64 in the interface region IA to connect to the gate electrode 15. The gate contact plug 66 may be connected while vertically overlapping with a dummy active pattern 9b adjacent to the gate electrode 15 connected to the gate contact plug 66.

[0149] Refer again Figure 5A , Figure 5B , Figure 6A and Figure 6BAn insulating etch stop layer 69 may be formed on the cell contact structure 60, the gate contact plug 66, and the insulating structure 64. A data storage structure DS may be formed on the insulating etch stop layer 69. The data storage structure DS may include a first electrode 72a extending upward and connected to the cell contact structure 60 through the insulating etch stop layer 69, a dielectric layer 72b on the first electrode 72a and the insulating etch stop layer 69, and a second electrode 72c on the dielectric layer 72b.

[0150] A first upper insulating layer 78 can be formed to cover the data storage structure DS and the insulating etch stop layer 69. A first contact plug 81 and a second contact plug 82 can be formed. The first contact plug 81 can penetrate the first upper insulating layer 78 and the etch stop layer 69 and can be connected to the gate contact plug 66, and the second contact plug 82 can penetrate the first upper insulating layer 78 and can be connected to the second electrode 72c of the data storage structure DS.

[0151] A first upper interconnect 84 and a second upper interconnect 85 may be formed. The first upper interconnect 84 may be connected to a first contact plug 81 on a first upper insulating layer 78, and the second upper interconnect 85 may be connected to a second contact plug 82 on the first upper insulating layer 78. A second upper insulating layer 87 may be formed on the first upper insulating layer 78, the first upper interconnect 84, and the second upper interconnect 85.

[0152] In some implementations, the integration density of semiconductor devices can be improved because vertical channel transistors with channel regions extending in the vertical direction can be provided.

[0153] In some implementations, the performance of a vertical channel transistor can be improved because the gate electrode in the vertical channel transistor can surround the entire side surface of the channel region.

[0154] In some embodiments, active patterns may be provided, including cell active patterns electrically connected to bit lines and data storage structures, and dummy active patterns not electrically connected to bit lines and data storage structures. Gate electrodes, which can serve as word lines, may be adjacent to the cell active patterns and dummy active patterns, and gate contact plugs, which can be connected to the gate electrodes, may be connected to the gate electrodes while vertically overlapping with the gate electrodes and the adjacent dummy active patterns. Dummy active patterns adjacent to the gate electrodes and gate contact plugs may be provided to stably and reliably form the gate contact plugs. The gate contact plugs may contact at least one of the inner or outer surfaces of the gate electrodes. Therefore, since the contact area between the gate contact plugs and the gate electrodes can be increased, the contact resistance between the gate contact plugs and the gate electrodes can be reduced.

[0155] The various advantages and effects of this disclosure are not limited to those described above, and will be more readily understood in the process of describing some implementation methods.

[0156] Although this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to particular embodiments of the invention. Some features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, in some cases one or more features of a particular combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0157] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The first unit has an active pattern and the first dummy active pattern are positioned along the first horizontal direction; The first gate electrode is adjacent to the first cell active pattern and the first dummy active pattern; The first unit gate dielectric layer is located between the first unit active pattern and the first gate electrode; A first dummy gate dielectric layer is located between the first dummy source pattern and the first gate electrode; The first gate contact plug is in contact with the first dummy active pattern and the first gate electrode; as well as The bit line is set below the first cell active pattern, and the bit line is connected to the first cell active pattern and spaced apart from the first dummy active pattern.

2. The semiconductor device according to claim 1, wherein, In the first horizontal direction, the length of the first dummy active pattern is greater than the length of the first unit active pattern.

3. The semiconductor device according to claim 2, wherein, In a second horizontal direction perpendicular to the first horizontal direction, the width of the first dummy active pattern is the same as the width of the first unit active pattern.

4. The semiconductor device according to claim 2, wherein, The first dummy active pattern includes a first region and a second region, wherein the second region extends from the first region in a direction away from the first active pattern. Wherein, in the second horizontal direction perpendicular to the first horizontal direction, the width of the first region is the same as the width of the first unit active pattern, and In the second horizontal direction, the width of the second region is smaller than the width of the first region.

5. The semiconductor device according to claim 4, wherein, The first gate contact plug contacts the second region and is spaced apart from the first region.

6. The semiconductor device according to claim 1, further comprising: The data storage structure is configured to be higher than the active pattern of the first unit; as well as A unit contact structure electrically connects the data storage structure and the first unit active pattern, the unit contact structure being located between the data storage structure and the first unit active pattern.

7. The semiconductor device according to claim 6, wherein, The first unit active pattern includes a first source / drain region, a second source / drain region on the first source / drain region, and a channel region between the first source / drain region and the second source / drain region. Wherein, the bit line is connected to the first source / drain region of the first cell active pattern, and The unit contact structure is connected to the second source / drain region of the first unit active pattern.

8. The semiconductor device according to claim 7, wherein, The first gate electrode surrounds the side surface of the channel region of the first cell active pattern, and The first unit gate dielectric layer is located between the side surface of the channel region of the first unit active pattern and the first gate electrode.

9. The semiconductor device according to claim 1, wherein, The first gate electrode has an inner surface and an outer surface, the inner surface facing the first dummy source pattern, and the outer surface opposite the inner surface. Wherein, the upper surface of the first gate contact plug is configured to be higher than the upper surface of the first cell active pattern and the upper surface of the first dummy active pattern, and The first gate contact plug is in contact with the upper surface of the first gate electrode and the outer surface of the first gate electrode.

10. The semiconductor device according to claim 9, wherein, The first gate contact plug extends between the inner surface of the first gate electrode and the first dummy active pattern, and the first gate contact plug contacts the inner surface of the first gate electrode.

11. The semiconductor device according to claim 1, wherein, The first gate electrode has an inner surface and an outer surface, the inner surface facing the first dummy source pattern, and the outer surface opposite the inner surface. Wherein, the lower surface of the first gate contact plug is configured to be below the bit line, and The first gate contact plug is in contact with the lower surface of the first gate electrode and the outer surface of the first gate electrode.

12. The semiconductor device according to claim 11, wherein, The first gate contact plug extends between the inner surface of the first gate electrode and the first dummy active pattern, and the first gate contact plug contacts the inner surface of the first gate electrode.

13. The semiconductor device according to claim 1, further comprising: The second unit has an active pattern and the second dummy active pattern are positioned along the first horizontal direction; The second gate electrode is adjacent to the second cell active pattern and the second dummy active pattern; The second unit gate dielectric layer is located between the second unit active pattern and the second gate electrode; as well as A second dummy gate dielectric layer is disposed between the second dummy source pattern and the second gate electrode. The second active pattern and the first active pattern are adjacent to each other in a second horizontal direction perpendicular to the first horizontal direction. Wherein, the second dummy active pattern and the first dummy active pattern are adjacent to each other in the second horizontal direction, and The bit line extends from the first cell active pattern to the second cell active pattern in the second horizontal direction.

14. The semiconductor device according to claim 13, wherein, In the first horizontal direction, the length of the first dummy active pattern is greater than the length of the first unit active pattern, the length of the second unit active pattern, and the length of the second dummy active pattern.

15. The semiconductor device according to claim 13, wherein, In the first horizontal direction, the length of the first dummy active pattern is greater than the length of the first unit active pattern and the length of the second unit active pattern, and the length of the second dummy active pattern is greater than the length of the first unit active pattern and the length of the second unit active pattern.

16. A semiconductor device, comprising: The storage cell array area and the interface area are adjacent to each other in the first horizontal direction; Multiple gate electrodes extend in the first horizontal direction, across the memory cell array region, and into the interface region; Multiple active patterns, including multiple unit active patterns and multiple dummy active patterns, the multiple unit active patterns are disposed in the storage cell array area and positioned along the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the multiple dummy active patterns are disposed in the interface area and positioned along the second horizontal direction; Multiple gate dielectric layers are disposed between the multiple gate electrodes and the multiple active patterns; Multiple bit lines extend in the second horizontal direction, cross the memory cell array area, and connect to the multiple cell active patterns below the multiple cell active patterns; as well as Multiple gate contact plugs are disposed in the interface area. The plurality of active patterns extend into the plurality of gate electrodes in a vertical direction perpendicular to the first horizontal direction and the second horizontal direction. Wherein, the first gate electrode among the plurality of gate electrodes is adjacent to the first dummy active pattern among the plurality of dummy active patterns, and The first gate contact plug among the plurality of gate contact plugs vertically overlaps with the first dummy active pattern and contacts the first gate electrode.

17. The semiconductor device according to claim 16, wherein, The plurality of gate dielectric layers include a first dummy gate dielectric layer between the first dummy active pattern and the first gate electrode, and The first gate contact plug is in contact with the first dummy active pattern and the first dummy gate dielectric layer.

18. The semiconductor device according to claim 16, wherein, In the first horizontal direction, each of the plurality of unit active patterns has a first length, and the first dummy active pattern has a second length greater than the first length.

19. A semiconductor device, comprising: The storage cell array area and the interface area are adjacent to each other in the first horizontal direction; Multiple gate electrodes extend in the first horizontal direction, across the memory cell array region, and into the interface region; Multiple bit lines extend in a second horizontal direction perpendicular to the first horizontal direction and cross the memory cell array area; Multiple active patterns extend into the multiple gate electrodes in a vertical direction perpendicular to the first horizontal direction and the second horizontal direction. The multiple active patterns include multiple cell active patterns disposed in the memory cell array area and multiple dummy active patterns disposed in the interface area. Multiple gate dielectric layers are disposed between the multiple active patterns and the multiple gate electrodes; as well as Multiple gate contact plugs are connected to the multiple gate electrodes. The plurality of dummy active patterns include a first dummy active pattern and a second dummy active pattern that are adjacent to each other in the second horizontal direction. Wherein, the length of the first dummy active pattern in the first horizontal direction is greater than the length of each of the plurality of unit active patterns in the first horizontal direction. Wherein, the length of the first dummy active pattern in the first horizontal direction is greater than the length of the second dummy active pattern in the first horizontal direction, and The first gate contact plug among the plurality of gate contact plugs is in contact with the first gate electrode among the plurality of gate electrodes.

20. The semiconductor device according to claim 19, wherein, The first gate electrode is adjacent to the first dummy active pattern. The first gate electrode has an inner surface and an outer surface, the inner surface facing the first dummy source pattern, and the outer surface opposite the inner surface. Wherein, the first gate contact plug contacts at least one of the inner surface or the outer surface of the first gate electrode, and The first dummy active pattern contacts the first gate contact plug.

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