Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus

Abstract

A semiconductor device including a two-dimensional nanocrystal channel, a method of manufacturing the semiconductor device, and an electronic device including the semiconductor device are provided. The semiconductor device includes a channel layer, a gate electrode disposed to face the channel layer, a gate insulating film disposed between the channel layer and the gate electrode, and a source electrode and a drain electrode electrically connected to the channel layer. The channel layer includes a first transition metal dichalcogenide layer and a second transition metal dichalcogenide layer disposed on the first transition metal dichalcogenide layer. The first transition metal dichalcogenide layer includes a highly crystalline transition metal dichalcogenide material having a two-dimensional crystal structure. The second transition metal dichalcogenide layer includes a nanocrystalline transition metal dichalcogenide material having a two-dimensional crystal structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices including two-dimensional nanocrystal channels, methods for manufacturing semiconductor devices, and electronic devices including semiconductor devices. Background Technology

[0002] A field-effect transistor (FET) is a semiconductor device configured to perform electrical switching and is used in various integrated circuit (IC) devices, including memory and logic devices. With the increasing demand for higher integration in IC devices, the available space occupied by the transistors within them is rapidly decreasing. Therefore, attempts have been made to use two-dimensional materials instead of silicon-based three-dimensional materials to form transistors. However, two-dimensional materials are prone to peeling off during device fabrication. Furthermore, it is difficult to uniformly deposit insulators on two-dimensional materials. Summary of the Invention

[0003] A semiconductor device and an electronic device including the semiconductor device are provided, wherein a two-dimensional nanocrystalline material that is not easily peeled off during the manufacturing process is used as a channel in the semiconductor device.

[0004] A method for manufacturing semiconductor devices is provided.

[0005] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0006] According to one aspect of this disclosure, a semiconductor device includes: a channel layer including a first transition metal dichalcogenide layer and a second transition metal dichalcogenide layer on the first transition metal dichalcogenide layer; a gate electrode facing the channel layer; a gate insulating film between the channel layer and the gate electrode; and a source electrode and a drain electrode electrically connected to the channel layer, wherein the first transition metal dichalcogenide layer includes a highly crystalline transition metal dichalcogenide material having a two-dimensional crystal structure, and the second transition metal dichalcogenide layer includes a nanocrystalline transition metal dichalcogenide material having a two-dimensional crystal structure.

[0007] For example, the grain size of the second transition metal dichalcogenide layer can be 10 nm or smaller, and the grain size of the first transition metal dichalcogenide layer can be 50 nm or larger.

[0008] The distance between the first transition metal dichalcogenide layer and the second transition metal dichalcogenide layer can be 2 nm or less.

[0009] The first transition metal dichalcogenide layer may include highly crystalline transition metal dichalcogenide materials with a two-dimensional crystal structure stacked in 1 to 10 layers, and the second transition metal dichalcogenide layer may include nanocrystalline transition metal dichalcogenide materials with a two-dimensional crystal structure stacked in 1 to 10 layers.

[0010] The atomic ratio of chalcogens to transition metals in the second transition metal dichalcogenide layer can be within ±20% of the atomic ratio of chalcogens to transition metals in the first transition metal dichalcogenide layer.

[0011] The proportion of metals with an oxidation state of +4 among all metals in the first transition metal dichalcogenide layer may be 80% or greater, and the proportion of metals with an oxidation state of +4 among all metals in the second transition metal dichalcogenide layer may be 80% or greater.

[0012] The atomic ratio of chalcogens to transition metals in the first and second transition metal dichalcogenide layers can be 1.7 or greater.

[0013] The channel layer may further include a third transition metal disulfide layer disposed below the first transition metal disulfide layer. The first transition metal disulfide layer may be disposed between the third transition metal disulfide layer and the second transition metal disulfide layer. The third transition metal disulfide layer may include a nanocrystalline transition metal disulfide material with a two-dimensional crystal structure.

[0014] The first and second transition metal disulfide layers may include transition metal disulfide materials having the same conductivity type.

[0015] The first transition metal dichalcogenide layer and the second transition metal dichalcogenide layer may include the same transition metal and / or the same chalcogen element.

[0016] The second transition metal dichalcogenide layer may include a first transition metal and a second transition metal that are different from each other, and in the second transition metal dichalcogenide layer, the proportion of the first transition metal gradually increases and the proportion of the second transition metal gradually decreases along the thickness direction, or the second transition metal dichalcogenide layer includes a first chalcogenide element and a second chalcogenide element that are different from each other, and in the second transition metal dichalcogenide layer, the proportion of the first chalcogenide element gradually increases and the proportion of the second chalcogenide element gradually decreases along the thickness direction.

[0017] The semiconductor device may further include a substrate, wherein a channel layer may be on the substrate, a source electrode and a drain electrode may be spaced apart from each other on the channel layer, a gate insulating film may be on the channel layer between the source electrode and the drain electrode, and a gate electrode may be on the gate insulating film.

[0018] The second transition metal disulfide layer may include a first portion disposed between the first transition metal disulfide layer and the source electrode and between the first transition metal disulfide layer and the drain electrode, and a second portion disposed between the first transition metal disulfide layer and the gate insulating film, wherein the thickness of the first portion may be greater than the thickness of the second portion.

[0019] The semiconductor device may further include spacers between the gate electrode and the source electrode and between the gate electrode and the drain electrode, wherein the second transition metal disulfide layer may further include a third portion between the first transition metal disulfide layer and the spacers, and the absolute values ​​of the Fermi level difference between the first portion and the first transition metal disulfide layer, the absolute values ​​of the Fermi level difference between the second portion and the first transition metal disulfide layer, and the absolute values ​​of the Fermi level difference between the third portion and the first transition metal disulfide layer may all be greater than zero.

[0020] The semiconductor device may further include a substrate, wherein a channel layer may protrude from the substrate in a first direction, a gate insulating film surrounds an upper surface of the channel layer and two side surfaces of the channel layer in a second direction perpendicular to the first direction, and a gate electrode surrounds an upper surface of the gate insulating film and two side surfaces of the gate insulating film in the second direction.

[0021] The semiconductor device may further include a substrate, wherein the channel layers may include a plurality of channel layers spaced apart from the substrate along a first direction, the gate insulating film includes a plurality of gate insulating films surrounding a lower and upper surface of each of the plurality of channel layers and two side surfaces of each of the plurality of channel layers in a second direction perpendicular to the first direction, and the gate electrode may protrude from the substrate in the first direction to surround the plurality of gate insulating films.

[0022] According to another aspect of this disclosure, a method of manufacturing a semiconductor device includes: forming a channel layer comprising a first transition metal dichalcogenide layer and a second transition metal dichalcogenide layer on the first transition metal dichalcogenide layer; forming a source electrode and a drain electrode such that both the source electrode and the drain electrode are electrically connected to the channel layer; and forming a gate insulating film and a gate electrode on the gate insulating film such that the gate insulating film insulates the channel layer from the gate electrode, wherein the first transition metal dichalcogenide layer comprises a highly crystalline transition metal dichalcogenide material having a two-dimensional crystal structure, and the second transition metal dichalcogenide layer comprises a nanocrystalline transition metal dichalcogenide material having a two-dimensional crystal structure.

[0023] Forming the channel layer may include: depositing a highly crystalline transition metal dichalcogenide material at a first temperature; and depositing a nanocrystalline transition metal dichalcogenide material at a second temperature below the first temperature.

[0024] According to another aspect of this disclosure, an electronic device includes: a transistor including a channel layer, a gate electrode facing the channel layer, a gate insulating film between the channel layer and the gate electrode, and a source electrode and a drain electrode electrically connected to the channel layer; a word line electrically connected to the gate electrode of the transistor; a bit line electrically connected to the source electrode of the transistor; and a capacitor electrically connected to the drain electrode of the transistor, wherein the channel layer includes a first transition metal dichalcogenide layer and a second transition metal dichalcogenide layer on the first transition metal dichalcogenide layer, the first transition metal dichalcogenide layer including a highly crystalline transition metal dichalcogenide material having a two-dimensional crystal structure, and the second transition metal dichalcogenide layer including a nanocrystalline transition metal dichalcogenide material having a two-dimensional crystal structure. Attached Figure Description

[0025] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0026] Figure 1 It is a cross-sectional view schematically showing the structure of a semiconductor device according to at least one exemplary embodiment;

[0027] Figure 2 It is a cross-sectional view schematically showing the structure of a semiconductor device according to at least one exemplary embodiment;

[0028] Figures 3A to 3C This is a schematic cross-sectional view illustrating the process of forming a trench layer on a substrate;

[0029] Figure 4 This is a scanning electron microscope (SEM) image showing a nanocrystalline transition metal dichalcogenide layer grown on a highly crystalline transition metal dichalcogenide layer;

[0030] Figure 5 It is shown Figure 4 Transmission electron microscopy (TEM) image of a cross-section of a nanocrystalline transition metal dichalcogenide layer;

[0031] Figure 6 and Figure 7 This is an example diagram showing the EDS spectra of highly crystalline transition metal dichalcogenide layers and nanocrystalline transition metal dichalcogenide layers obtained by energy dispersive spectroscopy (EDS).

[0032] Figure 8 This is a diagram showing the Raman spectrum of a nanocrystalline transition metal dichalcogenide layer;

[0033] Figure 9 This is a diagram showing the Raman spectrum of a highly crystalline transition metal dichalcogenide layer;

[0034] Figure 10 An example of current distribution in multiple semiconductor devices, each including a channel layer, according to at least one exemplary embodiment;

[0035] Figure 11 Comparative examples of current distribution in multiple semiconductor devices, all of which include a channel layer formed by a transfer method, are shown;

[0036] Figures 12 to 14 It is a cross-sectional view schematically showing the structure of a semiconductor device according to at least some example embodiments;

[0037] Figure 15 It is a cross-sectional view schematically showing the structure of a semiconductor device according to at least one exemplary embodiment;

[0038] Figures 16 to 18 It is a cross-sectional view schematically showing the structure of a semiconductor device according to at least one exemplary embodiment;

[0039] Figure 19 It is a perspective view schematically illustrating the structure of a semiconductor device according to at least some example embodiments;

[0040] Figure 20 It is a schematic representation of the path along Figure 19 The line A-A' intercepts Figure 19 Cross-sectional views of the channel layer and gate electrode of a semiconductor device;

[0041] Figure 21 This is a TEM image showing the stacked structure in which aluminum oxide and MoS2 layers are grown alternately;

[0042] Figures 22 to 25 They are shown respectively Figure 21 An elemental mapping image showing the elemental distribution of molybdenum (Mo), sulfur (S), aluminum (Al), and oxygen (O) in the stacked structure shown.

[0043] Figure 26 This is a graph showing the grain size of highly crystalline MoS2 based on the thickness of the aluminum oxide layer;

[0044] Figure 27 It is a schematic cross-sectional view of the channel layer and gate electrode of a semiconductor device according to at least some example embodiments;

[0045] Figure 28 It is a schematic cross-sectional view of the channel layer and gate electrode of a semiconductor device according to at least some example embodiments;

[0046] Figure 29 This is a circuit diagram of a complementary metal-oxide-semiconductor (CMOS) inverter according to at least one exemplary embodiment;

[0047] Figure 30 It is a circuit diagram of a CMOS static random access memory (SRAM) device according to at least one example embodiment;

[0048] Figure 31 It is a circuit diagram of a CMOS dynamic random access memory (DRAM) device according to at least one exemplary embodiment;

[0049] Figure 32 It is a block diagram of an electronic device according to at least one example embodiment; and

[0050] Figure 33 It is a block diagram of an electronic device according to at least one example implementation. Detailed Implementation

[0051] Reference will now be made in detail to some embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, the presented embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only by reference to the accompanying drawings to illustrate various aspects. Additionally, when the terms “about” or “substantially” are used in conjunction with numerical and / or geometric terms in this specification, the numerical values ​​intended to be associated include manufacturing tolerances (e.g., ±10%) around said numerical values. Furthermore, regardless of whether numerical and / or geometric terms are modified to “about” or “substantially,” it will be understood that these values ​​should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around said numerical values ​​and / or geometry. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire column of elements when following a column of elements, but not individual elements within that column.

[0052] The following describes in detail a semiconductor device including a two-dimensional nanocrystal channel, a method for manufacturing the semiconductor device, and an electronic device including the semiconductor device. In the following figures, the same reference numerals denote the same elements, and the dimensions of each element in the figures may be exaggerated for clarity and ease of explanation. Furthermore, the embodiments described herein are merely examples, and various modifications can be made to them.

[0053] In the following text, the terms “above,” “on,” “below,” or “under” will include not only those directly above, below, to the left, or to the right in a contact manner, but also those in a non-contact manner. For example, such spatial relation terms are used here based on the orientation shown in the accompanying drawings and may be used in other ways when the orientation of the corresponding object changes. In other words, in addition to the orientation depicted in the accompanying drawings, such spatial relation terms are intended to cover other different orientations of the device in use or operation, such that the device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relation terms used herein are interpreted accordingly. Unless the context clearly indicates otherwise, the singular form used herein is also intended to include the plural form. It will be understood that the terms “comprising,” “including,” or “having” as used herein indicate the presence of the stated element, but do not exclude the presence or addition of one or more other elements.

[0054] The use of the term "the" and similar indicator words can correspond to both the singular and plural. The operations constituting a method can be performed in any suitable order, unless otherwise stated herein or obviously contradicted by the context, and are not necessarily limited to the stated order.

[0055] Furthermore, terms such as “unit” and “module” described in the specification refer to a unit that performs at least one function or operation and can be implemented as processing circuitry, such as hardware, software, or a combination of hardware and software. For example, processing circuitry may include, but is not limited to, a central processing unit (CPU), application processor (AP), arithmetic logic unit (ALU), graphics processing unit (GPU), digital signal processor, microcomputer, field-programmable gate array (FPGA), system-on-a-chip (SoC), programmable logic unit, microprocessor, or application-specific integrated circuit (ASIC), unless otherwise explicitly stated.

[0056] The connecting lines or connecting components shown in the accompanying drawings are intended to illustrate example functional relationships and / or physical or logical connections between various elements. It should be noted that many alternative or additional functional relationships, physical connections, or logical connections may exist in actual devices.

[0057] All illustrations or exemplary terms used in the embodiments are merely for the purpose of describing the technical ideas in detail, and the scope of this disclosure is not limited by the illustrations or exemplary terms unless it is limited by the claims.

[0058] Figure 1 This is a schematic cross-sectional view illustrating the structure of a semiconductor device 100 according to at least one exemplary embodiment. (Refer to...) Figure 1A semiconductor device 100 according to at least one example embodiment includes a channel layer 110, a gate insulating film 121 disposed on the channel layer 110, a gate electrode 122 disposed on the gate insulating film 121, and a source electrode 123 and a drain electrode 124 electrically connected through the channel layer 110 when the semiconductor device 100 is turned on. In other words, the channel layer 110 may be provided between the source electrode 123 and the drain electrode 124 to electrically connect both the source electrode 123 and the drain electrode 124. The gate electrode 122 may be configured to face the channel layer 110, and the gate insulating film 121 may be disposed between the channel layer 110 and the gate electrode 122 and insulate the channel layer 110 from the gate electrode 122.

[0059] Semiconductor device 100 may be, for example, a field-effect transistor (FET). Specifically, semiconductor device 100 may be a FET with a top-gate structure, wherein the gate electrode 122 is disposed above the channel layer 110. In this case, the gate electrode 122, source electrode 123, and drain electrode 124 may be disposed on the same side relative to the substrate 101. For example, the gate electrode 122, source electrode 123, and drain electrode 124 may all be disposed facing the upper surface of the substrate 101.

[0060] The semiconductor device 100 may further include a substrate 101. The substrate 101 may be an insulating substrate, including at least one of, for example, glass, plastic, dielectric, and / or the like. A channel layer 110, a source electrode 123, and a drain electrode 124 may be disposed on the substrate 101. The source electrode 123 and the drain electrode 124 may respectively contact two sides of the channel layer 110 on the substrate 101. For example, the source electrode 123 may be electrically connected to a first side surface of the channel layer 110, and the drain electrode 124 may be electrically connected to a second side surface of the channel layer 110 opposite to the first side surface.

[0061] The gate insulating film 121 may comprise an insulating material having a high dielectric constant of about 10 or greater. For example, the gate insulating film 121 may comprise at least one of hafnium oxide (HfO), aluminum oxide (AlO), tantalum oxide (TaO), and / or the like. Although Figure 1 It is shown that the width of the gate insulating film 121 is smaller than the width of the channel layer 110, but the width of the gate insulating film 121 can be equal to the width of the channel layer 110.

[0062] The channel layer 110 may comprise a semiconductor material having a two-dimensional crystal structure. For example, the channel layer 110 may comprise a transition metal dichalcogenide material. According to at least some example embodiments, a transition metal dichalcogenide is a compound of a transition metal and a chalcogenide. In other words, the channel layer 110 may comprise an MX2 semiconductor, where M is a transition metal and X is a chalcogenide. The transition metal M may comprise at least one of molybdenum (Mo), tungsten (W), hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti), rhenium (Re), niobium (Nb), tin (Sn), and platinum (Pt). The chalcogenide X may comprise at least one of sulfur (S), selenium (Se), and tellurium (Te). The channel layer 110 may include, for example, MoS2, MoSe2, MoTe2, WS2, WSe2, TiS2, ZrS2, ZrSe2, HfS2, PtSe2, PtS2, SnS2, TaS2, ReS2, NbS2, TaSe2, HfSe2, ReSe2, TiSe2, NbSe2, SnSe2, WTe2, TaTe2, HfTe2, ReTe2, TiTe2, NbTe2, SnTe2, etc.

[0063] Transition metal dichalcogenides (TMDs) exhibit excellent properties even at relatively small thicknesses, such as 1 nm or less, and their properties are easily controllable. Therefore, a channel layer 110 comprising a TMD material is beneficial for miniaturization of the semiconductor device 100. On the other hand, the channel layer 110 according to at least one exemplary embodiment may comprise at least two layers with different grain sizes to prevent or mitigate degradation caused by damage resulting from the stripping of the channel layer 110 from the substrate 101 during the manufacturing process due to low bonding strength between the substrate 101 and the channel layer 110. For example, the channel layer 110 may comprise a first TMD layer 111 and a second TMD layer 112. The first TMD layer 111 may be disposed on the substrate 101. The second TMD layer 112 may be disposed on the first TMD layer 111 and may be in direct contact with the first TMD layer 111. The gate insulating film 121 can be disposed on the second transition metal disulfide layer 112. Therefore, the first transition metal disulfide layer 111 can be disposed between the substrate 101 and the second transition metal disulfide layer 112, and the second transition metal disulfide layer 112 can be disposed between the first transition metal disulfide layer 111 and the gate insulating film 121.

[0064] The first transition metal dichalcogenide layer 111 may include a highly crystalline transition metal dichalcogenide material with a two-dimensional crystal structure, and the second transition metal dichalcogenide layer 112 may include a nanocrystalline transition metal dichalcogenide material with a two-dimensional crystal structure. For example, the grain size (L) of the second transition metal dichalcogenide layer 112 may be... G2 It can be greater than 0 nanometers (nm) and less than or equal to about 10 nm (e.g., 0 nm). <L G2 ≤ Approximately 10 nm), the grain size of the first transition metal dichalcogenide layer 111 (L G1 The first transition metal dichalcogenide layer 111 can be greater than or equal to about 5 times the grain size of the second transition metal dichalcogenide layer 112. For example, the grain size of the first transition metal dichalcogenide layer 111 can be 50 nm or larger, about 100 nm or larger and / or about 200 nm or larger, and about 1,000 nm or smaller.

[0065] The first transition metal dichalcogenide layer 111 can be provided by stacking highly crystalline transition metal dichalcogenide material with a two-dimensional structure into one to ten layers and / or one to three layers. The second transition metal dichalcogenide layer 112 can be provided by stacking nanocrystalline transition metal dichalcogenide material with a two-dimensional structure into one to ten layers and / or one to three layers. For example, the thickness of each of the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112 can be from about 0.7 nm to about 7 nm, and / or from about 0.7 nm to about 2.5 nm.

[0066] The first transition metal disulfide layer 111 and the second transition metal disulfide layer 112 may contain the same transition metal disulfide material but have different grain sizes. Optionally, the first transition metal disulfide layer 111 and the second transition metal disulfide layer 112 may contain different transition metal disulfide materials and have different grain sizes. In other words, the first transition metal disulfide layer 111 and the second transition metal disulfide layer 112 may contain the same transition metal and the same chalcogenide element but have different grain sizes, or they may contain the same transition metal and different chalcogenide elements but have different grain sizes, or they may contain different transition metals and different chalcogenide elements but have different grain sizes. The threshold voltage of the semiconductor device 100 can be determined based on the band gap of the first transition metal disulfide layer 111 and the second transition metal disulfide layer 112. The threshold voltage of the semiconductor device 100 can be controlled to a desired value by selecting the materials of the first transition metal disulfide layer 111 and the second transition metal disulfide layer 112.

[0067] When the material of the first transition metal disulfide layer 111 is different from the material of the second transition metal disulfide layer 112, materials with the same conductivity type (or polarity) can be selected as the materials of the first transition metal disulfide layer 111 and the second transition metal disulfide layer 112. For example, when the first transition metal disulfide layer 111 includes an n-type transition metal disulfide material, the second transition metal disulfide layer 112 may also include an n-type transition metal disulfide material. Optionally, when the first transition metal disulfide layer 111 includes a p-type transition metal disulfide material, the second transition metal disulfide layer 112 may also include a p-type transition metal disulfide material. Examples of n-type transition metal dichalcogenide materials may include MoS2, MoSe2, WS2, HfS2, ZrS2 and / or similar materials, and examples of p-type transition metal dichalcogenide materials may include WSe2, MoTe2, WTe2, HfTe2 and / or similar materials.

[0068] Furthermore, when the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112 comprise different transition metal dichalcogenide materials, it may be advantageous during the manufacturing process if the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112 comprise the same chalcogenide element. Moreover, the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112 comprising the same chalcogenide element can have electrically similar properties. For example, the transition metal dichalcogenide materials of the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112 can both comprise sulfur (S), both comprise selenium (Se), or both comprise tellurium (Te).

[0069] According to at least one exemplary embodiment, the crystal orientation of the first transition metal disulfide layer 111 may be the same as or different from the crystal orientation of the second transition metal disulfide layer 112. For example, in at least one exemplary embodiment, one of the first transition metal disulfide layer 111 and the second transition metal disulfide layer 112 may have a zigzag crystal orientation as the primary crystal orientation, while the other may have an armchair-shaped crystal orientation as the primary crystal orientation, for example, oriented in the direction between the source electrode 123 and the drain electrode 124. When the crystal orientation of the first transition metal disulfide layer 111 is different from that of the second transition metal disulfide layer 112, the effect of reducing the band gap as the stacking amount of the second transition metal disulfide layer 112 increases may be reduced. Therefore, leakage current can be reduced or suppressed by controlling the crystal orientation of the first transition metal disulfide layer 111 and the second transition metal disulfide layer 112, as well as the stacking amount of the first transition metal disulfide layer 111 and the second transition metal disulfide layer 112.

[0070] Figure 2 This is a schematic cross-sectional view illustrating the structure of a semiconductor device 100a according to at least one example embodiment. Although Figure 1 The diagram shows that the channel layer 110 comprises two layers with different grain sizes, but this disclosure is not limited thereto. (See also...) Figure 2 The channel layer 110a of the semiconductor device 100a may further include a third transition metal dichalcogenide layer 113 disposed below the first transition metal dichalcogenide layer 111. The remaining components of the semiconductor device 100a may be connected to... Figure 1 The remaining components of the semiconductor device 100 shown are the same.

[0071] A third transition metal disulfide layer 113 can be disposed between the substrate 101 and the first transition metal disulfide layer 111. In other words, the third transition metal disulfide layer 113 can be disposed on the substrate 101, the first transition metal disulfide layer 111 can be disposed on the third transition metal disulfide layer 113, and the second transition metal disulfide layer 112 can be disposed on the first transition metal disulfide layer 111. In these cases, the first transition metal disulfide layer 111 can be disposed between the third transition metal disulfide layer 113 and the second transition metal disulfide layer 112. Like the second transition metal disulfide layer 112, the third transition metal disulfide layer 113 can comprise a nanocrystalline transition metal disulfide material with a two-dimensional crystal structure. For example, the grain size of the third transition metal disulfide layer 113 can be about 10 nm or smaller. The third transition metal dichalcogenide layer 113 can be provided by stacking one to ten layers or one to three layers of nanocrystalline transition metal dichalcogenide material with a two-dimensional structure. For example, the thickness of the third transition metal dichalcogenide layer 113 can be from about 0.7 nm to about 7 nm, or from about 0.7 nm to about 2.5 nm. The third transition metal dichalcogenide layer 113 can include materials that are the same as or different from the materials of each of the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112. Even when the third transition metal dichalcogenide layer 113 includes materials that are different from the materials of each of the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112, materials having the same conductivity type can be selected as the materials of the first to third transition metal dichalcogenide layers 111, 112 and 113.

[0072] According to at least one example embodiment, the channel layer 110 can be provided by growing it directly on the substrate 101. Figures 3A to 3C This is a cross-sectional view schematically illustrating the process of forming a channel layer 110 on a substrate 101.

[0073] Reference Figure 3A A highly crystalline transition metal dichalcogenide material 111' can be grown on substrate 101. The highly crystalline transition metal dichalcogenide material 111' can be deposited and grown by chemical vapor deposition (CVD), plasma-enhanced CVD (PE-CVD), or inductively coupled plasma chemical vapor deposition (ICP-CVD) at a first temperature of about 400 degrees Celsius (°C) or higher (e.g., about 600°C).

[0074] Reference Figure 3B Nanocrystalline transition metal dichalcogenide material 112' can be grown on highly crystalline transition metal dichalcogenide material 111'. The nanocrystalline transition metal dichalcogenide material 112' can be grown at a second temperature below the first temperature. For example, in at least some example embodiments, the second temperature can be about 127°C or higher and below about 400°C, which is lower than the first temperature. For example, the nanocrystalline transition metal dichalcogenide material 112' can be deposited and grown at a temperature of 350°C by CVD, PE-CVD, or ICP-CVD.

[0075] Reference Figure 3C A channel layer 110 comprising a first transition metal dichalcogenide layer 111 and a second transition metal dichalcogenide layer 112 can be formed by patterning highly crystalline transition metal dichalcogenide material 111' and nanocrystalline transition metal dichalcogenide material 112'. Although Figure 3C Simultaneous patterning of highly crystalline transition metal dichalcogenide material 111' and nanocrystalline transition metal dichalcogenide material 112' is shown, but this disclosure is not limited thereto. For example, by patterning in Figure 3A After forming the first transition metal dichalcogenide layer 111 with the highly crystalline transition metal dichalcogenide material 111' shown in the operation, a nanocrystalline transition metal dichalcogenide material 112' can be grown to cover the substrate 101 and the first transition metal dichalcogenide layer 111. Then, the nanocrystalline transition metal dichalcogenide material 112' can be patterned.

[0076] After forming the channel layer 110, a gate insulating film material can be deposited to a uniform thickness to cover the substrate 101 and the channel layer 110. Then, a gate insulating film 121 can be formed on the channel layer 110 by patterning the gate insulating film material via an etching process. Conductive material can be deposited to a uniform thickness over the substrate 101, the channel layer 110, and the gate insulating film 121. Then, a gate electrode 122, a source electrode 123, and a drain electrode 124 can be formed by patterning the conductive material via an etching process. In this way, a semiconductor device 100 can be manufactured. For example, the conductive material retained on both sides of the channel layer 110 can become the source electrode 123 and the drain electrode 124, and the conductive material retained on the gate insulating film 121 can become the gate electrode 122.

[0077] According to at least one example embodiment, a second transition metal dichalcogenide layer 112 comprising nanocrystalline transition metal dichalcogenide material can reduce or prevent the first transition metal dichalcogenide layer 111 from peeling off from the substrate 101, for example by protecting the first transition metal dichalcogenide layer 111 from chemical materials (e.g., developers), which might otherwise be affected during the fabrication of the semiconductor device 100 in the process of patterning the channel layer 110 (e.g., during the manufacturing of the semiconductor device 100). Figure 3C The second transition metal dichalcogenide layer 112 (as shown in the diagram) penetrates into the first transition metal dichalcogenide layer 111. Furthermore, the second transition metal dichalcogenide layer 112 can reduce or prevent damage, oxidation, or contamination of the first transition metal dichalcogenide layer 111 during the manufacturing process of the semiconductor device 100 due to exposure to heat, oxygen, or various other chemicals. Moreover, because a high-density grain boundary exists in the nanocrystalline transition metal dichalcogenide material of the second transition metal dichalcogenide layer 112, an insulator can be uniformly deposited on the second transition metal dichalcogenide layer 112 by using the high-density grain boundaries as seed points. Therefore, the gate insulating film 121 and the gate electrode 122 can be deposited on the channel layer 110 with high quality.

[0078] During the process of growing the channel layer 110, the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112 are protected from oxidation and are not doped or replaced by other heterogeneous elements. Therefore, the atomic ratio of chalcogenide element X to transition metal M in the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112 can be maintained, for example, at about 1.7 or greater. In at least some example embodiments, the atomic ratio of chalcogenide element X to transition metal M is 2, and even when minor defects occur in the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112, the atomic ratio of chalcogenide element X to transition metal M may not fall below 1.7. Furthermore, the proportion of metals with an oxidation number of +4 among all metals in the first transition metal dichalcogenide layer 111 can be 80% or greater. Similarly, the proportion of metals with an oxidation number of +4 among all metals in the second transition metal dichalcogenide layer 112 can be 80% or greater.

[0079] Furthermore, the atomic ratio of chalcogenide X to transition metal M in the first transition metal dichalcogenide layer 111 can be equal to and / or substantially similar to the atomic ratio of chalcogenide X to transition metal M in the second transition metal dichalcogenide layer 112. For example, the atomic ratio of chalcogenide X to transition metal M in the second transition metal dichalcogenide layer 112 can be within approximately ±20% of the atomic ratio of chalcogenide X to transition metal M in the first transition metal dichalcogenide layer 111.

[0080] Figure 4 This is a scanning electron microscope (SEM) image showing a nanocrystalline transition metal dichalcogenide layer grown on a highly crystalline transition metal dichalcogenide layer. Additionally, Figure 5 It is shown Figure 4 The image shows a cross-sectional transmission electron microscope (TEM) image of a nanocrystalline transition metal dichalcogenide layer. A highly crystalline transition metal dichalcogenide layer containing MoS2 was grown directly on a catalyst at approximately 600 °C, followed by the growth of a MoS2-containing nanocrystalline transition metal dichalcogenide layer on top of the highly crystalline transition metal dichalcogenide layer at approximately 350 °C. (Refer to...) Figure 4 It can be confirmed that the nanocrystalline transition metal dichalcogenide layer has a relatively uniform surface. Furthermore, referring to... Figure 5 It can be confirmed that the nanocrystalline transition metal dichalcogenide layer has grown to a relatively uniform thickness.

[0081] The grain size and elemental composition of the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112 of the channel layer 110 can be confirmed by, for example, cross-sectional TEM analysis, energy dispersive spectroscopy (EDS), electron energy loss spectroscopy (EELS), Raman spectroscopy, etc. Figure 6 and Figure 7 This is an example EDS spectrum showing the highly crystalline transition metal dichalcogenide layer and the nanocrystalline transition metal dichalcogenide layer obtained by EDS analysis. The highly crystalline transition metal dichalcogenide layer comprises MoS2 grown at 600 °C, and the nanocrystalline transition metal dichalcogenide layer comprises MoS2 grown at 350 °C. Figure 6 The EDS analysis results of the 3d orbitals of molybdenum (Mo) are shown. Figure 7 The EDS analysis results for the 2p orbital of sulfur (S) are shown. (Refer to...) Figure 6 and Figure 7 It can be confirmed that the highly crystalline transition metal dichalcogenide layer and the nanocrystalline transition metal dichalcogenide layer have the same composition because the spectral peaks appear at the same energy. Furthermore, since the full width at half maximum (FWHM) of the spectrum of the nanocrystalline transition metal dichalcogenide layer is greater than that of the highly crystalline transition metal dichalcogenide layer, it can be confirmed that the grain size of the nanocrystalline transition metal dichalcogenide layer is smaller than that of the highly crystalline transition metal dichalcogenide layer.

[0082] Figure 8 This is a diagram showing the Raman spectrum of a nanocrystalline transition metal dichalcogenide layer. Figure 9 This is a Raman spectrum showing the layer of highly crystalline transition metal dichalcogenides. (Refer to...) Figure 8 and Figure 9 It can be confirmed that even when the highly crystalline transition metal dichalcogenide layer and the nanocrystalline transition metal dichalcogenide layer contain the same material (MoS2), different peaks appear depending on the grain size. Through the above analysis, the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112 of the channel layer 110 can be distinguished from each other.

[0083] On the other hand, such as Figures 3A to 3C As shown, because the channel layer 110 is formed by a direct growth method rather than a transfer method, the quality of the channel layer 110 is relatively insensitive to the surface condition of the substrate 101. Therefore, the channel layer 110 can be formed relatively uniformly over the entire area of ​​the substrate 101 or the wafer. Figure 10 Examples of current distributions in multiple semiconductor devices, each including a channel layer, according to at least one exemplary embodiment, are shown. Figure 11 Comparative examples of current distributions in multiple semiconductor devices, all including channel layers formed by a transfer method, are shown. In particular, Figure 10 and Figure 11 The results show the measurement of the source-drain currents of multiple semiconductor devices arranged in a local square region of the wafer after multiple semiconductor devices have been formed on the wafer. For example, Figure 10The results of measuring the source-drain currents of 600 semiconductor devices arranged in a partially square region of a wafer are shown. Figure 11 The results of measuring the source-drain currents of 135 semiconductor devices arranged in a partially square region of a wafer are shown. (Refer to...) Figure 10 and Figure 11 It can be confirmed that the current deviation between multiple semiconductor devices according to the embodiment is relatively small, while the current deviation between multiple semiconductor devices including the channel layer formed by the transfer method is relatively large.

[0084] The method of forming the channel layer 110 can be distinguished by the distance between the layers. For example, when the first transition metal dichalcogenide layer 111 is grown directly on the substrate 101 and the second transition metal dichalcogenide layer 112 is grown directly on the first transition metal dichalcogenide layer 111, there are almost no empty spaces between the layers. For example, the distance between the substrate 101 and the first transition metal dichalcogenide layer 111 can be 2 nm or less, and the distance between the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112 can be 2 nm or less. On the other hand, when the first transition metal dichalcogenide layer 111 and the second transition metal dichalcogenide layer 112 are formed by a transfer method, empty spaces are formed between the layers, and therefore, the distance between the layers can be greater than 2 nm.

[0085] Figure 12 This is a schematic cross-sectional view illustrating the structure of a semiconductor device 100b according to at least some example embodiments. Figure 1 and Figure 2 In the semiconductor devices 100 and 100a shown, the source electrode 123 and the drain electrode 124 are directly disposed on the substrate 101, and the channel layer 110 is disposed between the source electrode 123 and the drain electrode 124; however, this disclosure is not limited thereto. (See also...) Figure 12 Semiconductor device 100b may include a substrate 101, a channel layer 110 on the substrate 101, a source electrode 123 and a drain electrode 124 spaced apart from each other on the channel layer 110, a gate insulating film 121 on the channel layer 110 between the source electrode 123 and the drain electrode 124, and a gate electrode 122 on the gate insulating film 121. The gate electrode 122, source electrode 123, and drain electrode 124 may all be disposed above the channel layer 110. The source electrode 123 and drain electrode 124 may be configured to face each other on opposite sides of the gate insulating film 121 on the upper surface of the channel layer 110. The source electrode 123 and drain electrode 124 may be spaced apart from the substrate 101 and not in direct contact with the substrate 101. In other words, the channel layer 110 may be disposed between the source electrode 123 and the substrate 101, and between the drain electrode 124 and the substrate 101.

[0086] The channel layer 110 may include a first transition metal disulfide layer 111 on the substrate 101 and a second transition metal disulfide layer 112 on the first transition metal disulfide layer 111. The source electrode 123, the drain electrode 124 and the gate insulating film 121 may be disposed on the second transition metal disulfide layer 112.

[0087] In at least some example embodiments, the channel layer 110 of the semiconductor device 100b may further include Figure 2 The third transition metal disulfide layer 113 is shown. For example, the channel layer 110 may further include a third transition metal disulfide layer 113 disposed below the first transition metal disulfide layer 111. In these cases, the third transition metal disulfide layer 113 may be disposed on the substrate 101, the first transition metal disulfide layer 111 may be disposed on the third transition metal disulfide layer 113, and the second transition metal disulfide layer 112 may be disposed on the first transition metal disulfide layer 111.

[0088] Additionally, the semiconductor device 100b may further include spacers 125 that electrically separate the gate electrode 122 from the source electrode 123 and from the drain electrode 124. The spacers 125 may be disposed on the channel layer 110, particularly on the second transition metal dichalcogenide layer 112, between the gate electrode 122 and the source electrode 123, and between the gate electrode 122 and the drain electrode 124. The spacers 125 may include an insulating dielectric. For example, the spacers 125 may include materials selected from silicon oxide (SiO2) and silicon nitride (SiN). x At least one of the following materials: silicon nitride oxide (SiON). However, in at least some example embodiments, the spacer 125 may be omitted when the gate electrode 122 and the source electrode 123 are sufficiently electrically separated from each other and the gate electrode 122 and the drain electrode 124 are sufficiently electrically separated from each other.

[0089] Figure 13 This is a schematic cross-sectional view illustrating the structure of a semiconductor device 100c according to at least some exemplary embodiments. By considering the characteristics of the gate insulating film 121, source electrode 123, drain electrode 124, and spacer 125 on the second transition metal dichalcogenide layer 112, the second transition metal dichalcogenide layer 112 can be divided into portions with different materials. (Refer to...) Figure 13The channel layer 110b of the semiconductor device 100c may include a first transition metal disulfide layer 111 and a second transition metal disulfide layer 112 disposed on the first transition metal disulfide layer 111. The second transition metal disulfide layer 112 may be divided into multiple portions. For example, the second transition metal disulfide layer 112 may include a first portion 112a, a second portion 112b, and a third portion 112c. The first portion 112a may be disposed between the first transition metal disulfide layer 111 and the source electrode 123, and between the first transition metal disulfide layer 111 and the drain electrode 124. The second portion 112b may be disposed between the first transition metal disulfide layer 111 and the gate insulating film 121. The third portion 112c may be disposed between the first transition metal disulfide layer 111 and the spacer 125. The first part 112a, the second part 112b and the third part 112c may be spaced apart from each other on the first transition metal dichalcogenide layer 111.

[0090] In at least one example embodiment, the first portion 112a, the second portion 112b, and the third portion 112c may comprise the same nanocrystalline transition metal dichalcogenide material. In at least one example embodiment, by taking into account the function of the layers disposed on the first portion 112a, the second portion 112b, and the third portion 112c respectively, the first portion 112a, the second portion 112b, and the third portion 112c may comprise different nanocrystalline transition metal dichalcogenide materials.

[0091] The first portion 112a disposed below the source electrode 123 or drain electrode 124 may include a transition metal dichalcogenide material having semiconductor or metallic properties selected to reduce contact resistance. For example, the first portion 112a may include a transition metal dichalcogenide material based on a noble metal (such as platinum (Pt)) or a transition metal dichalcogenide material having a 1T or 1T' crystalline phase. Furthermore, the first portion 112a may include a transition metal dichalcogenide material selected to provide a doping effect to the first transition metal dichalcogenide layer 111 below it. For example, when the channel layer 110 is n-type, the first portion 112a may include a transition metal dichalcogenide material having a higher Fermi level than the transition metal dichalcogenide material of the first transition metal dichalcogenide layer 111. When the channel layer 110 is p-type, the first portion 112a may include a transition metal dichalcogenide material having a Fermi level lower than that of the transition metal dichalcogenide material of the first transition metal dichalcogenide layer 111. Therefore, the absolute value of the Fermi level difference between the first transition metal dichalcogenide layer 111 and the first portion 112a can be greater than zero. For example, the first portion 112a may include PtSe2, PtS2, 1T-phase-MoS2, 1T'-phase-MoTe2, etc. In the contact region between the source electrode 123 and the first portion 112a, and in the contact region between the drain electrode 124 and the first portion 112a, conductivity can be improved and contact resistance can be reduced.

[0092] The third portion 112c, disposed below the spacer 125, may include a transition metal dichalcogenide (TMD) material having the same conductivity type (or polarity) as the first TMD layer 111 below it, and may have semiconductor properties capable of providing a doping effect to the first TMD layer 111. For example, when the channel layer 110 is n-type, the third portion 112c may include a TMD material having a higher Fermi level than the TMD material of the first TMD layer 111. When the channel layer 110 is p-type, the third portion 112c may include a TMD material having a lower Fermi level than the TMD material of the first TMD layer 111. Therefore, the absolute value of the Fermi level difference between the first TMD layer 111 and the third portion 112c may be greater than zero. The doping effect of the third part 112c on the first transition metal disulfide layer 111 can be the same as the doping effect of the first part 112a on the first transition metal disulfide layer 111. However, this disclosure is not limited thereto. The doping effect of the third part 112c on the first transition metal disulfide layer 111 can be slightly greater or less than the doping effect of the first part 112a on the first transition metal disulfide layer 111.

[0093] The second portion 112b disposed beneath the gate insulating film 121 may include a transition metal dichalcogenide material with semiconductor properties, having the same conductivity type (or polarity) as the first transition metal dichalcogenide layer 111 beneath it. Furthermore, the second portion 112b may include a different transition metal dichalcogenide material than the first transition metal dichalcogenide layer 111 to provide a doping effect to the first transition metal dichalcogenide layer 111. Therefore, in the case of the second portion 112b, the absolute value of the Fermi level difference between the first transition metal dichalcogenide layer 111 and the second portion 112b can be greater than zero. The threshold voltage of the semiconductor device 100c can be controlled based on the Fermi level of the second portion 112b. Because the doping effect of the second portion 112b on the first transition metal dichalcogenide layer 111 controls the threshold voltage, the Fermi level of the second portion 112b can be higher or lower than the Fermi level of the first transition metal dichalcogenide layer 111, regardless of the conductivity type of the channel layer 110.

[0094] Figure 14 This is a schematic cross-sectional view illustrating the structure of a semiconductor device 100d according to at least some example embodiments. By taking into account the characteristics of the gate insulating film 121, the source electrode 123, and the drain electrode 124 on the second transition metal dichalcogenide layer 112, the second transition metal dichalcogenide layer 112 can be divided into layers with different thicknesses. (Refer to...) Figure 14 The channel layer 110c of the semiconductor device 100d may include a first transition metal disulfide layer 111 and a second transition metal disulfide layer 112 disposed on the first transition metal disulfide layer 111. The second transition metal disulfide layer 112 may be divided into multiple portions. For example, the second transition metal disulfide layer 112 may include a first portion 112a disposed between the first transition metal disulfide layer 111 and the source electrode 123 and between the first transition metal disulfide layer 111 and the drain electrode 124, and a second portion 112b disposed between the first transition metal disulfide layer 111 and the gate insulating film 121. The first portion 112a and the second portion 112b may be spaced apart from each other on the first transition metal disulfide layer 111. The semiconductor device 100d may further include Figure 13 The spacer 125 and channel layer 110c shown may further include Figure 13 The third part, 112c, is shown.

[0095] Generally, as the amount of transition metal dichalcogenide material stacked increases, that is, as the thickness increases, the band gap can decrease and the conductivity can increase. Therefore, the first portion 112a disposed below the source electrode 123 and / or the drain electrode 124 can have a relatively thick thickness (e.g., a relatively large amount of stacking) to reduce contact resistance, and the second portion 112b disposed below the gate insulating film 121 can have a relatively thin thickness (e.g., a relatively small amount of stacking). Therefore, the thickness of the first portion 112a can be greater than the thickness of the second portion 112b. In other words, the amount of transition metal dichalcogenide material stacked in the first portion 112a can be greater than the amount of transition metal dichalcogenide material stacked in the second portion 112b. For example, when both the first portion 112a and the second portion 112b include PtSe2, the first portion 112a can include three or more layers of PtSe2, and the second portion 112b can include two or fewer layers of PtSe2.

[0096] It has been described that the interior of a second transition metal dichalcogenide layer 112 disposed on a first transition metal dichalcogenide layer 111 has a single composition, but the composition can gradually change in a second transition metal dichalcogenide layer 112. Figure 15 This is a schematic cross-sectional view illustrating the structure of a semiconductor device according to at least one exemplary embodiment. (Refer to...) Figure 15The second transition metal dichalcogenide layer 112 of the channel layer 110e may include at least two different transition metal dichalcogenide materials. The ratio between the different transition metal dichalcogenide materials in the second transition metal dichalcogenide layer 112 may gradually and continuously change along the thickness direction. In other words, the second transition metal dichalcogenide layer 112 may include two or more different transition metals or two or more different chalcogen elements, and the ratio between the two or more different transition metals or the ratio between the two or more different chalcogen elements may gradually and continuously change along the thickness direction of the second transition metal dichalcogenide layer 112.

[0097] For example, the second transition metal dichalcogenide layer 112 may include a first region 112A on the first transition metal dichalcogenide layer 111, a second region 112B on the first region 112A, and a third region 112C on the second region 112B. The first region 112A may include a first transition metal and a first chalcogenide element. The third region 112C may include the first transition metal and a second chalcogenide element different from the first chalcogenide element. The second region 112B may include the first transition metal, the first chalcogenide element, and the second chalcogenide element. In the second region 112B, the proportion of the first chalcogenide element may gradually and continuously decrease along the thickness direction from the first region 112A to the third region 112C, while the proportion of the second chalcogenide element may gradually and continuously increase. Optionally, the third region 112C may include a second transition metal different from the first transition metal, and the first chalcogenide element. The second region 112B may include the first transition metal, the second transition metal, and the first chalcogenide element. In the second region 112B, the proportion of the first transition metal can gradually and continuously decrease along the thickness direction from the first region 112A to the third region 112C, while the proportion of the second transition metal can gradually and continuously increase. The bandgap of the channel layer 110e can be finely controlled to a desired value through the gradient distribution of heterogeneous transition metals or heterogeneous chalcogenides. Therefore, the threshold voltage of the semiconductor device can be controlled.

[0098] Figure 16 This is a schematic cross-sectional view illustrating the structure of a semiconductor device according to at least one exemplary embodiment. The semiconductor device described above is a FET with a top-gate structure, wherein the gate electrode is disposed on the upper side; however, this disclosure is not necessarily limited to this. The semiconductor device may have a bottom-gate structure, wherein the gate electrode is disposed on the lower side. (Refer to...) Figure 16 The semiconductor device 200 may include a gate electrode 201, a gate insulating film 202 surrounding two side surfaces and a top surface of the gate electrode 201, a channel layer 210 on the top surface of the gate insulating film 202, and a source electrode 221 and a drain electrode 222 electrically connected to the channel layer 210.

[0099] In the bottom-gate structure, the source electrode 221 and drain electrode 222 can be disposed on the opposite side of the channel layer 210 from the gate electrode 201. For example, the source electrode 221 and drain electrode 222 can be disposed above the channel layer 210, and the gate electrode 201 can be disposed below the channel layer 210. The source electrode 221 and drain electrode 222 can be spaced apart from each other on the upper surface of the channel layer 210. In other words, the channel layer 210 can include a first surface and a second surface opposite to each other, the source electrode 221 and drain electrode 222 can be spaced apart from each other on the first surface of the channel layer 210, and the gate electrode 201 can be configured to face the second surface of the channel layer 210.

[0100] The channel layer 210 may include a first transition metal disulfide layer 211 on the gate insulating film 202 and a second transition metal disulfide layer 212 on the first transition metal disulfide layer 211. The first transition metal disulfide layer 211 can be provided by direct growth on the gate insulating film 202, and the second transition metal disulfide layer 212 can be provided by direct growth on the first transition metal disulfide layer 211. The first transition metal disulfide layer 211 may be referenced to... Figure 1 The first transition metal dichalcogenide layer 111 described is the same as that described above, and the second transition metal dichalcogenide layer 212 may be the same as that described above. Figure 1 The second transition metal dichalcogenide layer 112 described is the same.

[0101] Figure 17 This is a schematic cross-sectional view illustrating the structure of a semiconductor device according to at least one exemplary embodiment. (Refer to...) Figure 17 The channel layer 210a of the semiconductor device 200a may further include a third transition metal dichalcogenide layer 213 disposed below the first transition metal dichalcogenide layer 211. The remaining components of the semiconductor device 200a may be connected to... Figure 16 The remaining components of the semiconductor device 200 shown are the same. A third transition metal disulfide layer 213 may be disposed between the gate insulating film 202 and the first transition metal disulfide layer 211. In other words, the third transition metal disulfide layer 213 may be disposed on the gate insulating film 202, the first transition metal disulfide layer 211 may be disposed on the third transition metal disulfide layer 213, and the second transition metal disulfide layer 212 may be disposed on the first transition metal disulfide layer 211. The third transition metal disulfide layer 213 may be connected to a reference... Figure 2 The third transition metal dichalcogenide layer 113 described is the same.

[0102] Figure 18 This is a schematic cross-sectional view illustrating the structure of a semiconductor device according to at least one exemplary embodiment. (Refer to...) Figure 18 Semiconductor device 200b can be a FET with a dual-gate structure. (And...) Figure 16 Compared to the semiconductor device 200 shown in the figure, Figure 18 The semiconductor device 200b shown may further include an upper gate insulating film 203 disposed on the upper surface of the channel layer 210 between the source electrode 221 and the drain electrode 222, and an upper gate 204 disposed on the upper gate insulating film 203. In this case, the gate electrode 201 may be a "lower gate electrode" and the gate insulating film 202 may be a "lower gate insulating film".

[0103] The case of a FET having a planar channel has been described, but this disclosure is not limited thereto. For example, the technical aspects of the embodiments described above can be applied to FinFETs, gate-all-around FETs (GAAFETs), or multi-bridge channel FETs (MBCFETs) having a three-dimensional channel structure.

[0104] Figure 19 This is a perspective view schematically illustrating the structure of a semiconductor device 300 according to at least some exemplary embodiments. Figure 20 It is a schematic representation of the path along Figure 19 The line A-A' intercepts Figure 19 A cross-sectional view of the channel layer 310 and gate electrode 305 of the semiconductor device 300. Figure 19 and Figure 20 The semiconductor device 300 shown may be a FinFET. (See reference...) Figure 19 and Figure 20 The semiconductor device 300 may include a substrate 301 having insulating properties, a channel layer 310 protruding from the substrate 301 in a first direction (Z-axis direction), a gate insulating film 304 surrounding two side surfaces of the channel layer 310 in a second direction (X-axis direction) perpendicular to the first direction and the upper surface of the channel layer 310, a gate electrode 305 surrounding two side surfaces of the gate insulating film 304 in the second direction and the upper surface of the gate insulating film 304, a source electrode 302 protruding from the substrate 301 in the first direction and electrically connected to a first side surface of the channel layer 310 in a third direction (Y-axis direction) perpendicular to the first and second directions, and a drain electrode 303 protruding from the substrate 301 in the first direction and electrically connected to a second side surface of the channel layer 310 in a third direction opposite to the first side surface.

[0105] The channel layer 310 may include a first transition metal disulfide layer 311 and a second transition metal disulfide layer 312. The second transition metal disulfide layer 312 may surround the two side surfaces of the first transition metal disulfide layer 311 in a second direction and the upper surface of the first transition metal disulfide layer 311. In other aspects, the first transition metal disulfide layer 311 may be connected to... Figure 1 The first transition metal dichalcogenide layer 111 shown is the same as (or substantially similar to) that of the second transition metal dichalcogenide layer 312. Figure 1 The second transition metal dichalcogenide layer 112 shown is the same as (or substantially similar to) the second transition metal dichalcogenide layer shown in the figure.

[0106] Although not shown, the channel layer 310 may further include a third transition metal dichalcogenide layer. In this case, the first transition metal dichalcogenide layer 311 may surround the two side surfaces of the third transition metal dichalcogenide layer in the second direction and the upper surface of the third transition metal dichalcogenide layer. The third transition metal dichalcogenide layer may be connected with... Figure 2 The third transition metal dichalcogenide layer 113 shown is the same.

[0107] Additionally, the semiconductor device 300 may further include a support 320 supporting the channel layer 310. The support 320 may protrude from the substrate 301 in a first direction. The channel layer 310 may surround three sides of the support 320. For example, a first transition metal dichalcogenide layer 311 may surround two side surfaces of the support 320 in a second direction and the top surface of the support 320. When the channel layer 310 includes a third transition metal dichalcogenide layer, the third transition metal dichalcogenide layer may surround two side surfaces of the support 320 in the second direction and the top surface of the support 320.

[0108] As described above, the gate insulating film and gate electrode can be directly grown with high quality on nanocrystalline transition metal dichalcogenide materials. Therefore, the channel layer and gate structure can be stacked vertically. Furthermore, there is no need to insert a separate intermediate layer, such as a seed layer, between the channel layer and the gate structure. For example, Figure 21 This is a TEM image showing a stacked structure with alternating growth of aluminum oxide and MoS2 layers. (See reference) Figure 21 The first MoS2 layer, the first aluminum oxide layer, the second MoS2 layer, the second aluminum oxide layer, the third MoS2 layer, and the third aluminum oxide layer can be sequentially and directly grown on the aluminum oxide substrate. The first MoS2 layer, the first aluminum oxide layer, the second MoS2 layer, the second aluminum oxide layer, the third MoS2 layer, and the third aluminum oxide layer grown as described above can have relatively uniform thicknesses. Although in Figure 21Not visible in the image, but the first, second, and third MoS2 layers each comprise highly crystalline MoS2 grown at 600°C and nanocrystalline MoS2 grown at 350°C. For example, after growing highly crystalline MoS2 on an aluminum oxide layer at 600°C, nanocrystalline MoS2 can be directly grown on the highly crystalline MoS2 at 350°C, and then an aluminum oxide layer can be directly grown on the nanocrystalline MoS2.

[0109] Figures 22 to 25 They are shown respectively Figure 21 An elemental mapping image showing the elemental distribution of molybdenum (Mo), sulfur (S), aluminum (Al), and oxygen (O) in the stacked structure shown. (Refer to...) Figure 22 and Figure 23 It can be confirmed that, apart from molybdenum (Mo) and sulfur (S), other elements are almost entirely absent from the first to third MoS2 layers. (See reference...) Figure 24 and Figure 25 It can be confirmed that, apart from aluminum (Al) and oxygen (O), almost no other elements are distributed in the first to third aluminum oxide layers. Therefore, it can be confirmed that during the repeated and direct growth of the MoS2 and aluminum oxide layers, the MoS2 layer was not oxidized or contaminated by other elements, and the aluminum oxide layer was not contaminated by other elements. Furthermore, it can be confirmed that almost no undesirable interface layer forms between the MoS2 and aluminum oxide layers.

[0110] Figure 26 This is a graph showing the grain size of highly crystalline MoS2 based on the thickness of the aluminum oxide layer. (Refer to...) Figure 26 When the thickness of the aluminum oxide layer is 5 nm or greater, the deviation between the grain size of the highly crystalline MoS2 in the second MoS2 layer and the grain size of the highly crystalline MoS2 in the third MoS2 layer can be relatively small. In other words, even when the insulating film and transition metal dichalcogenide layer are repeatedly stacked, the quality deviation between layers can be small and the layers can be grown uniformly. Therefore, GAAFETs or MBCFETs comprising multiple channel layers disposed in the thickness direction or vertical direction can be manufactured with high quality.

[0111] Figure 27 This is a schematic cross-sectional view of the channel layer and gate electrode of a semiconductor device according to at least some example embodiments. Figure 27 The structures of the source and drain electrodes in the semiconductor device shown can be compared with those in the reference. Figure 19 The source electrode 302 and the drain electrode 303 described have the same structure. Figure 27 Showing in with Figure 20 The structure of the channel layer and gate electrode in a cross-section along the same direction. (Refer to...) Figure 27The semiconductor device may include a plurality of channel layers 310 disposed at intervals from the substrate 301 along a first direction (Z-axis direction). Although Figure 27 Three channel layers 310 are shown as an example, but this is not a limitation; a semiconductor device may include more than three channel layers.

[0112] The semiconductor device may further include a plurality of gate insulating films 304 surrounding two side surfaces of each of the plurality of channel layers 310 in a second direction (X-axis direction) and a lower and upper surface of each of the plurality of channel layers 310, and a gate electrode 305 surrounding two side surfaces of each of the plurality of gate insulating films 304 in the second direction and a lower and upper surface of the plurality of gate insulating films 304. In other words, each of the plurality of gate insulating films 304 may surround four sides of a corresponding channel layer among the plurality of channel layers 310. The gate electrode 305 may protrude from the substrate 301 in a first direction to surround the four sides of each of the plurality of gate insulating films 304. The plurality of gate insulating films 304 may be spaced apart from the substrate 301 along the first direction, and the gate electrode 305 may be disposed between the plurality of gate insulating films 304.

[0113] The channel layer 310 may include a first transition metal disulfide layer 311 and a second transition metal disulfide layer 312. The second transition metal disulfide layer 312 may be disposed on the first transition metal disulfide layer 311 in a first direction. In other words, the second transition metal disulfide layer 312 may be disposed on the upper surface of the first transition metal disulfide layer 311. The lower surface and two side surfaces of the first transition metal disulfide layer 311, as well as the two side surfaces and the upper surface of the second transition metal disulfide layer 312, may be surrounded by a gate insulating film 304.

[0114] Although not shown, the channel layer 310 may further include a third transition metal disulfide layer disposed below the first transition metal disulfide layer 311. The first transition metal disulfide layer 311 may be disposed between the third transition metal disulfide layer and the second transition metal disulfide layer 312. In this case, the lower surface and two side surfaces of the third transition metal disulfide layer, the two side surfaces of the first transition metal disulfide layer 311, and the two side surfaces and upper surface of the second transition metal disulfide layer 312 may be surrounded by the gate insulating film 304.

[0115] Figure 28 This is a schematic cross-sectional view illustrating the channel layer and gate electrode of a semiconductor device according to at least some example embodiments. (Refer to...) Figure 28Two channel layers 310 can be surrounded by a gate insulating film 304. Accordingly, the number of channel layers 310 can be twice the number of gate insulating films 304. An insulator bridge 306 can be disposed between the two channel layers 310 surrounded by a gate insulating film 304. Therefore, the first transition metal disulfide layer 311, the second transition metal disulfide layer 312, the insulator bridge 306, the first transition metal disulfide layer 311, and the second transition metal disulfide layer 312 can be sequentially stacked in a gate insulating film 304 along a first direction. Furthermore, when the channel layer 310 further includes a third transition metal disulfide layer, the third transition metal disulfide layer, the first transition metal disulfide layer 311, the second transition metal disulfide layer 312, the insulator bridge 306, the third transition metal disulfide layer, the first transition metal disulfide layer 311, and the second transition metal disulfide layer 312 can be sequentially stacked in a gate insulating film 304 along a first direction.

[0116] The aforementioned semiconductor devices can be used in, for example, display driver integrated circuits, complementary metal-oxide-semiconductor (CMOS) inverters, CMOS static random access memory (SRAM) devices, CMOS NAND circuits, CMOS dynamic random access memory (DRAM) and / or various other electronic devices.

[0117] Figure 29 This is a circuit diagram of a CMOS inverter 400 according to at least one exemplary embodiment. (Refer to...) Figure 29 The CMOS inverter 400 includes a CMOS transistor 410. The CMOS transistor 410 includes a p-channel metal-oxide-semiconductor (PMOS) transistor 420 and an n-channel metal-oxide-semiconductor (NMOS) transistor 430 connected between a power supply terminal Vdd and a ground terminal. The CMOS transistor 410 may include the semiconductor device according to the above embodiment.

[0118] Figure 30 This is a circuit diagram of a CMOS SRAM device 500 according to at least one exemplary embodiment. (Refer to...) Figure 30The CMOS SRAM device 500 includes a pair of driving transistors 510. Each of the driving transistors 510 includes a PMOS transistor 520 and an NMOS transistor 530 connected between a power supply terminal Vdd and a ground terminal. The CMOS SRAM device 500 may further include a pair of transfer transistors 540. The source of the transfer transistor 540 is cross-connected to a common node of the PMOS transistor 520 and the NMOS transistor 530 constituting the driving transistor 510. The power supply terminal Vdd is connected to the source of the PMOS transistor 520, and the ground terminal is connected to the source of the NMOS transistor 530. A word line WL may be connected to the gate of the pair of transfer transistors 540, and a bit line BL and an anti-phase line may be connected to the drain of each of the pair of transfer transistors 540, respectively. At least one of the driving transistors 510 and the transfer transistors 540 of the CMOS SRAM device 500 may include a semiconductor device according to the above embodiment.

[0119] Figure 31 This is a circuit diagram of a CMOS DRAM device 600 according to at least one exemplary embodiment. (Refer to...) Figure 31 The CMOS DRAM device 600 includes a transistor TR, a capacitor CA, a word line WL, and a bit line BL. The word line WL can be electrically connected to the gate of the transistor TR, and the bit line BL can be electrically connected to the source of the transistor TR. The first electrode of the capacitor CA can be connected to the drain of the transistor TR, and the second electrode of the capacitor CA can be grounded. The transistor TR of the CMOS DRAM device 600 can include the semiconductor device according to the above embodiment.

[0120] Figure 32 This is a block diagram illustrating an electronic device 700 according to at least one example embodiment. (Refer to...) Figure 32 The electronic device 700 includes a memory 710 and a memory controller 720. The memory controller 720 can control the memory 710 to read data from and / or write data to the memory 710 in response to a request from the host 730. At least one of the memory 710 or the memory controller 720 may include, according to... Figures 1 to 11 The semiconductor device described in the embodiments.

[0121] Figure 33 This is a block diagram of an electronic device 800 according to at least one example embodiment. (See also...) Figure 33 The electronic device 800 can be configured as a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. The electronic device 800 includes a controller 810, an input / output (I / O) device 820, a memory 830, and a wireless interface 840, and these components are interconnected with each other via a bus 850.

[0122] The controller 810 may include at least one of a microprocessor, a digital signal processor, and a similar processing device. The I / O device 820 may include at least one of a keypad, a keyboard, and a display. The memory 830 may be used to store instructions executed by the controller 810. For example, the memory 830 may be used to store user data. The electronic device 800 may use a wireless interface 840 to send / receive data over a wireless communication network. The wireless interface 840 may include an antenna and / or a wireless transceiver. In some embodiments, the electronic device 800 may be used in the communication interface protocols of third-generation communication systems, such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Digital Cellular (NADC), Extended Time Division Multiple Access (E-TDMA), and / or Wideband Code Division Multiple Access (WCDMA).

[0123] Electronic device 800 may include a semiconductor device according to the above embodiments.

[0124] According to at least one example embodiment, the channel layer of a semiconductor device includes a highly crystalline transition metal dichalcogenide layer and a nanocrystalline transition metal dichalcogenide layer thereon. The nanocrystalline transition metal dichalcogenide layer can reduce or prevent the highly crystalline transition metal dichalcogenide layer from peeling off from the underlying layer when chemical materials (such as developers) penetrate into the highly crystalline transition metal dichalcogenide layer during the process of manufacturing the semiconductor device.

[0125] In addition, nanocrystalline transition metal dichalcogenide layers can reduce or prevent highly crystalline transition metal dichalcogenide layers from being damaged, oxidized, or contaminated during the manufacturing process of semiconductor devices due to exposure to heat, oxygen, or various other chemicals.

[0126] Furthermore, the insulator can be uniformly deposited on the nanocrystalline transition metal dichalcogenide layer. Therefore, the gate insulating film and gate electrode can be deposited on the channel layer with high quality.

[0127] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in at least some of the example embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0128] Cross-references to related applications

[0129] This application is based on and claims priority to Korean Patent Application No. 10-2024-0167757, filed on November 21, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: The channel layer includes a first transition metal disulfide layer and a second transition metal disulfide layer on the first transition metal disulfide layer; The gate electrode faces the channel layer; A gate insulating film is disposed between the channel layer and the gate electrode; and The source and drain electrodes are electrically connected to the channel layer. The first transition metal dichalcogenide layer comprises a highly crystalline transition metal dichalcogenide material with a two-dimensional crystal structure, and the second transition metal dichalcogenide layer comprises a nanocrystalline transition metal dichalcogenide material with a two-dimensional crystal structure.

2. The semiconductor device according to claim 1, wherein, The grain size of the second transition metal dichalcogenide layer is 10 nm or smaller, and The grain size of the first transition metal dichalcogenide layer is 50 nm or larger.

3. The semiconductor device according to claim 1, wherein, The distance between the first transition metal dichalcogenide layer and the second transition metal dichalcogenide layer is 2 nm or less.

4. The semiconductor device according to claim 1, wherein, The first transition metal dichalcogenide layer comprises 1 to 10 layers of the highly crystalline transition metal dichalcogenide material having the two-dimensional crystal structure, and The second transition metal dichalcogenide layer comprises nanocrystalline transition metal dichalcogenide material having the two-dimensional crystal structure, stacked in 1 to 10 layers.

5. The semiconductor device according to claim 1, wherein, The atomic ratio of chalcogenide to transition metal in the second transition metal dichalcogenide layer is within ±20% of the atomic ratio of chalcogenide to transition metal in the first transition metal dichalcogenide layer.

6. The semiconductor device according to claim 1, wherein The proportion of metals with an oxidation state of +4 among all metals in the first transition metal dichalcogenide layer is 80% or greater, and The proportion of metals with an oxidation state of +4 among all metals in the second transition metal dichalcogenide layer is 80% or greater.

7. The semiconductor device according to claim 1, wherein, The ratio of chalcogen elements to transition metals in the first and second transition metal dichalcogenide layers is 1.7 or greater.

8. The semiconductor device according to claim 1, wherein, The channel layer further includes a third transition metal disulfide layer disposed below the first transition metal disulfide layer, the first transition metal disulfide layer being disposed between the third transition metal disulfide layer and the second transition metal disulfide layer, and The third transition metal dichalcogenide layer comprises a nanocrystalline transition metal dichalcogenide material with a two-dimensional crystal structure.

9. The semiconductor device according to claim 1, wherein, The first transition metal dichalcogenide layer and the second transition metal dichalcogenide layer comprise transition metal dichalcogenide materials having the same conductivity type.

10. The semiconductor device according to claim 1, wherein, The first transition metal dichalcogenide layer and the second transition metal dichalcogenide layer comprise the same transition metal and / or the same chalcogenide element.

11. The semiconductor device according to claim 1, wherein, The second transition metal dichalcogenide layer comprises a first transition metal and a second transition metal that are different from each other, and in the second transition metal dichalcogenide layer, along the thickness direction, the proportion of the first transition metal gradually increases and the proportion of the second transition metal gradually decreases, or The second transition metal dichalcogenide layer includes a first chalcogenide element and a second chalcogenide element that are different from each other, and in the second transition metal dichalcogenide layer, along the thickness direction, the proportion of the first chalcogenide element gradually increases and the proportion of the second chalcogenide element gradually decreases.

12. The semiconductor device according to claim 1, further comprising: Substrate, The channel layer is located on the substrate. The source electrode and the drain electrode are spaced apart from each other on the channel layer. The gate insulating film is located on the channel layer between the source electrode and the drain electrode, and The gate electrode is on the gate insulating film.

13. The semiconductor device according to claim 12, wherein The second transition metal disulfide layer includes a first portion between the first transition metal disulfide layer and the source electrode, and between the first transition metal disulfide layer and the drain electrode, and a second portion between the first transition metal disulfide layer and the gate insulating film. The thickness of the first part is greater than the thickness of the second part.

14. The semiconductor device of claim 13, further comprising: The spacers between the gate electrode and the source electrode, and between the gate electrode and the drain electrode. The second transition metal dichalcogenide layer further includes a third portion between the first transition metal dichalcogenide layer and the spacer, and The absolute values ​​of the Fermi level difference between the first part and the first transition metal disulfide layer, the absolute values ​​of the Fermi level difference between the second part and the first transition metal disulfide layer, and the absolute values ​​of the Fermi level difference between the third part and the first transition metal disulfide layer are all greater than zero.

15. The semiconductor device according to claim 1, further comprising: Substrate, The channel layer protrudes from the substrate in a first direction. The gate insulating film surrounds the upper surface of the channel layer and the two side surfaces of the channel layer in a second direction perpendicular to the first direction, and The gate electrode surrounds the upper surface of the gate insulating film and the two side surfaces of the gate insulating film in the second direction.

16. The semiconductor device of claim 1, further comprising: Substrate, The channel layer includes a plurality of channel layers spaced apart from the substrate in a first direction. The gate insulating film includes a plurality of gate insulating films surrounding the lower and upper surfaces of each of the plurality of channel layers and two side surfaces of each of the plurality of channel layers in a second direction perpendicular to the first direction. The gate electrode protrudes from the substrate in the first direction to surround the plurality of gate insulating films.

17. A method for manufacturing a semiconductor device, the method comprising: A channel layer is formed, the channel layer comprising a first transition metal disulfide layer and a second transition metal disulfide layer on the first transition metal disulfide layer; A source electrode and a drain electrode are formed such that both the source electrode and the drain electrode are electrically connected to the channel layer; as well as A gate insulating film and a gate electrode are formed on the gate insulating film, such that the gate insulating film insulates the channel layer from the gate electrode. The first transition metal dichalcogenide layer comprises a highly crystalline transition metal dichalcogenide material with a two-dimensional crystal structure, and the second transition metal dichalcogenide layer comprises a nanocrystalline transition metal dichalcogenide material with a two-dimensional crystal structure.

18. The method according to claim 17, wherein, The formation of the trench layer includes: Depositing the highly crystalline transition metal dichalcogenide material at a first temperature; and The nanocrystalline transition metal dichalcogenide material is deposited at a second temperature lower than the first temperature.

19. The method of claim 17, wherein, The grain size of the second transition metal dichalcogenide layer is 10 nm or smaller, and The grain size of the first transition metal dichalcogenide layer is 50 nm or larger.

20. An electronic device, comprising: A transistor includes a channel layer, a gate electrode facing the channel layer, a gate insulating film between the channel layer and the gate electrode, and a source electrode and a drain electrode electrically connected to the channel layer; The word line is electrically connected to the gate electrode of the transistor; Bit lines are electrically connected to the source electrode of the transistor; as well as A capacitor, electrically connected to the drain electrode of the transistor. The channel layer comprises a first transition metal dichalcogenide layer and a second transition metal dichalcogenide layer on the first transition metal dichalcogenide layer. The first transition metal dichalcogenide layer comprises a highly crystalline transition metal dichalcogenide material with a two-dimensional crystal structure, and The second transition metal dichalcogenide layer comprises a nanocrystalline transition metal dichalcogenide material having a two-dimensional crystal structure.

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