Laminated structure and manufacturing method thereof, semiconductor structure and electronic equipment

Abstract

The invention relates to a laminated structure and a manufacturing method thereof, a semiconductor structure and electronic equipment, relates to the technical field of semiconductors, and aims to improve the uniformity of device performance in the semiconductor structure. The laminated structure comprises a plurality of functional layers and a plurality of dielectric layers which are alternately laminated on a substrate, wherein the functional layer is used for forming a target structure or an accommodating groove of the target structure after patterning; the thickness difference of different functional layers is related to the distance difference between the corresponding target structure and the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a stacked structure and its manufacturing method, a semiconductor structure, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in semiconductor structures are increasing, making it possible for even the slightest differences in the manufacturing process to affect device performance.

[0003] Currently, semiconductor structures employ three-dimensional stacking, which facilitates higher density and lower cost integration. However, as the number of stacked layers continues to increase, limitations in process capabilities mean that process differences between different layers can severely impact the performance of devices at different layers. Summary of the Invention

[0004] Based on this, the present disclosure provides a stacked structure and its manufacturing method, a semiconductor structure, and an electronic device, which can improve the uniformity of device performance in the semiconductor structure, thereby effectively improving the electrical performance of the electronic device.

[0005] According to some embodiments, this disclosure provides a stacked structure, including: multiple functional layers and multiple dielectric layers alternately stacked on a substrate; wherein, the functional layers are used to form a target structure or a receiving groove of the target structure after patterning; the thickness difference of different functional layers is related to the distance difference between their corresponding target structures and the substrate.

[0006] According to some embodiments, functional layers are used to form the target structure after patterning; wherein the thickness of each functional layer gradually decreases along the direction away from the substrate.

[0007] According to some embodiments, functional layers are used to form receiving grooves of the target structure after patterning; wherein the thickness of each functional layer gradually increases along the direction away from the substrate.

[0008] According to some embodiments, the thickness of different functional layers is different.

[0009] According to other embodiments, the multi-layer functional layer includes multiple functional layer groups, and each functional layer group includes at least two functional layers; wherein the functional layers in the same functional layer group have the same thickness, and the functional layers in different functional layer groups have different thicknesses.

[0010] According to some embodiments, the functional layer includes a semiconductor layer; wherein the difference in in-situ doping concentration of different functional layers is related to the difference in distance between their corresponding target structures and the substrate.

[0011] According to some embodiments, this disclosure also provides a method for manufacturing a laminated structure, used to prepare the laminated structure in any of the above embodiments. The method for manufacturing the laminated structure includes the following steps.

[0012] Obtain the number of functional layers to be stacked. The functional layers are used to form the target structure or the receiving slot of the target structure after patterning.

[0013] By matching the distance differences between the target structure and the substrate corresponding to different functional layers, the formation thickness of each functional layer is determined.

[0014] Based on the thickness, multiple functional layers and multiple dielectric layers are alternately stacked on the substrate to obtain a stacked structure.

[0015] According to some embodiments, the functional layer includes a semiconductor layer. The method for manufacturing the stacked structure further includes the following steps.

[0016] By matching the distance differences between the target structure and the substrate corresponding to different functional layers, the in-situ doping concentration of each functional layer is determined.

[0017] Accordingly, the functional layer is formed based on the corresponding formation thickness and the in-situ doping concentration.

[0018] According to some embodiments, this disclosure further provides a semiconductor structure, including: a substrate and a plurality of devices arrayed on the substrate and stacked along a direction perpendicular to the substrate. The devices include semiconductor layers. The size differences between different semiconductor layers are related to the differences in distance between their corresponding devices and the substrate.

[0019] According to some embodiments, the semiconductor layers extend in a direction parallel to the substrate; wherein, in a direction away from the substrate, the thickness of each semiconductor layer gradually decreases in the direction perpendicular to the substrate.

[0020] According to some embodiments, the device further includes a gate and a gate dielectric layer located between the gate and the semiconductor layer.

[0021] According to some embodiments, a gate, a gate dielectric layer, and a semiconductor layer are stacked sequentially, with the gate located on the side of the semiconductor layer close to and / or away from the substrate.

[0022] According to other embodiments, the gate surrounds the semiconductor layer in a plane perpendicular to the substrate.

[0023] According to some embodiments, the semiconductor structure further includes: multiple functional layers and multiple dielectric layers alternately stacked on a substrate, and vias penetrating each functional layer and corresponding dielectric layer along a direction perpendicular to the substrate. Each functional layer has a receiving groove surrounding the via. Semiconductor layers cover the inner walls of the receiving grooves, and the width of each semiconductor layer gradually increases along the direction perpendicular to the substrate in a direction away from the substrate. The thickness of each functional layer is equal to the width of the corresponding semiconductor layer.

[0024] According to some embodiments, the functional layer includes: a first source / drain and a second source / drain located on both sides of the semiconductor layer along the direction parallel to the substrate and respectively connected to the semiconductor layer.

[0025] According to some embodiments, the device further includes: a gate dielectric layer located on the side of the semiconductor layer opposite to the functional layer, and a gate located on the side of the gate dielectric layer opposite to the semiconductor layer. The semiconductor structure further includes: a word line located within the via and connected to the gate.

[0026] According to some embodiments, the difference in in-situ doping concentration between different semiconductor layers is related to the difference in their distance from the substrate.

[0027] According to some embodiments, this disclosure provides another aspect of an electronic device, including: a semiconductor structure as described in any of the preceding embodiments.

[0028] The embodiments disclosed herein may have, or at least have, the following advantages:

[0029] In this embodiment, multiple functional layers and multiple dielectric layers are alternately stacked on a substrate. Patterning the functional layers can form a accommodating trench for the target structure (e.g., a semiconductor layer of a device). Based on this, this embodiment sets the thickness difference of different functional layers to be related to the distance difference between their corresponding target structures and the substrate. This thickness difference can effectively compensate for the adverse effects of process differences on the performance of different device layers, ensuring improved uniformity of device performance within the semiconductor structure, thereby effectively improving the electrical performance of electronic devices. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0031] Figure 1 Figure (a) is a schematic diagram of a stacked structure provided in some embodiments of this disclosure; Figure 1 Figure (b) in the figure illustrates some embodiments of this disclosure based on Figure 1 Figure (a) shows a schematic diagram of a semiconductor structure fabricated using a stacked structure;

[0032] Figure 2 Figure (a) is a schematic diagram of another stacked structure provided in some embodiments of this disclosure; Figure 2 Figure (b) in the figure illustrates some embodiments of this disclosure based on Figure 2 A schematic diagram of another semiconductor structure fabricated using the stacked structure shown in Figure (a);

[0033] Figure 3 This is a schematic diagram comparing the thickness variations of each functional layer in different stacked structures provided in some embodiments of this disclosure;

[0034] Figure 4 This is a flowchart illustrating a method for manufacturing a laminated structure provided in some embodiments of this disclosure;

[0035] Figure 5 This is a flowchart illustrating another method for manufacturing a laminated structure provided in some embodiments of this disclosure;

[0036] Figure 6 This is a schematic diagram of the equivalent circuit of a 2T0C memory cell provided in some embodiments of this disclosure;

[0037] Figure 7 This is a schematic diagram of an equivalent circuit for another 2T0C memory cell provided in some embodiments of this disclosure;

[0038] Figure 8 This is a schematic diagram illustrating the changes in the bit line current of each storage cell during multi-bit storage in some embodiments of this disclosure.

[0039] Figure label:

[0040] 1-Substrate, 2-Layered structure, 21-Functional layer, 22-Dielectric layer, U-Functional layer group;

[0041] 3-Device, 31-Semiconductor layer, 32-Gate dielectric layer, 33-Gate, 34-First source / drain, 35-Second source / drain;

[0042] H - Hole, G - Receiving groove, WL - Letter mark. Detailed Implementation

[0043] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0045] The term "embodiment" in this document means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0046] It is understood that the terms “first,” “second,” “third,” “fourth,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0047] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0048] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0049] Semiconductor structures employ three-dimensional stacking, facilitating higher density and lower cost integration. However, as the number of stacked layers increases, limitations in process capabilities mean that process differences between different layers (e.g., morphological differences due to varying vertical etching depths) can severely impact the performance of devices on different layers. Therefore, this disclosure provides a stacked structure and its manufacturing method, a semiconductor structure, and an electronic device, which can improve the uniformity of device performance within the semiconductor structure, thereby effectively enhancing the electrical performance of the electronic device.

[0050] In some embodiments of this disclosure, please refer to Figure 1 and Figure 2The stacked structure provided in this embodiment includes: multiple functional layers 21 and multiple dielectric layers 22 alternately stacked on a substrate 1. The functional layers 21 are used to form a target structure or a receiving groove for the target structure after patterning. The thickness difference of different functional layers 21 is related to the difference in distance from their corresponding target structures to the substrate 1.

[0051] Here, the thickness difference of different functional layers 21 is related to the distance difference between their corresponding target structures and the substrate 1. Specifically, the thickness of each functional layer 21 varies with the distance between its corresponding target structure and the substrate 1. Furthermore, the thickness difference of different functional layers 21 and the distance between their corresponding target structures and the substrate 1 can be positively or negatively correlated.

[0052] In some embodiments, please combine Figure 1 As can be understood from Figures (a) and (b), functional layer 21 is used to form the target structure after patterning, and the target structure is, for example, Figure 1 The semiconductor layer 31 of device 3 is shown in Figure (b); correspondingly, the thickness of each functional layer 21 gradually decreases along the direction away from the substrate 1.

[0053] For example, Figure 1 Figure (a) illustrates the three-layer functional layer 21 as an example. In the direction away from the substrate 1, the thickness T1 of the first functional layer 21 is greater than the thickness T2 of the second functional layer 21, and the thickness T2 of the second functional layer 21 is greater than the thickness T3 of the third functional layer 21, that is: T1 > T2 > T3.

[0054] In other embodiments, please refer to Figure 2 As can be understood from Figures (a) and (b), functional layer 21 is used to form a receiving slot for the target structure after patterning. The target structure is, for example, Figure 2 The semiconductor layer 31 of device 3 is shown in Figure (b); correspondingly, the thickness of each functional layer 21 gradually increases along the direction away from the substrate 1.

[0055] For example, Figure 2 Figure (a) illustrates the three-layer functional layer 21 as an example. In the direction away from the substrate 1, the thickness D1 of the first functional layer 21 is less than the thickness D2 of the second functional layer 21, and the thickness D2 of the second functional layer 21 is less than the thickness D3 of the third functional layer 21, that is: D1 < D2 < D3.

[0056] In this embodiment, multiple functional layers 21 and multiple dielectric layers 22 are alternately stacked on the substrate 1. Patterning the functional layers 21 can form a accommodating trench for the target structure (e.g., the semiconductor layer 31 of device 3). Based on this, the thickness difference of different functional layers 21 is related to the distance difference between their corresponding target structures and the substrate 1. This thickness difference can effectively compensate for the adverse effects on the performance of different device layers 3 caused by process differences, ensuring improved uniformity of device performance in the semiconductor structure and thus effectively improving the electrical performance of the electronic device.

[0057] It is worth mentioning that the thickness variation of different functional layers 21 can be achieved using a variety of implementation methods.

[0058] In some possible implementations, please refer to Figure 1 , Figure 2 and Figure 3 As can be understood from Figure (a), the thicknesses of different functional layers 21 are different. That is, the thickness of each functional layer 21 can be varied layer by layer to facilitate precise control of the performance of each device and ensure high accuracy.

[0059] Optionally, the thickness of each functional layer 21 can vary linearly.

[0060] In some other possible implementations, please refer to Figure 1 , Figure 2 and Figure 3 As illustrated in Figure (b), the multilayer functional layer 21 comprises multiple functional layer groups U, each functional layer group U including at least two functional layers 21; wherein, the functional layers 21 within the same functional layer group U have the same thickness, while the functional layers 21 in different functional layer groups U have different thicknesses. That is, the thickness of each functional layer 21 can vary group by group according to the division of functional layer groups U. This facilitates matching process capabilities, making it easier to control the thickness of each functional layer, thereby achieving performance control of each device.

[0061] It should be noted that in some of the above embodiments, the number of stacked layers and the corresponding materials of the functional layer 21 and the dielectric layer 22 can be selected and set according to requirements, and this disclosure does not limit this. However, it is understood that the stacked structure provided by this disclosure is more advantageous in large-scale applications of devices with a large number of stacked layers.

[0062] In some examples, the material of functional layer 21 includes, but is not limited to, semiconductor materials, metallic materials, insulating materials, or sacrificial materials. Correspondingly, the material of dielectric layer 22 is different from that of functional layer 21, and both preferably have a high etching selectivity. The material of dielectric layer 22 can be matched with the material of functional layer 21 by using insulating materials or sacrificial materials.

[0063] In some embodiments of this disclosure, the functional layer 21 includes a semiconductor layer, meaning that the functional layer 21 is formed using a semiconductor material. The functional layer 21 is, for example, a silicon layer, a polycrystalline silicon layer, or a metal-oxide-semiconductor layer. Accordingly, the difference in in-situ doping concentration of different functional layers 21 is related to the difference in distance between their corresponding target structures and the substrate 1.

[0064] Here, in-situ doping refers to the process of introducing dopant atoms into the thin film lattice by introducing a dopant gas into the reaction chamber during deposition. That is, the in-situ doping process occurs simultaneously with the thin film growth process. Compared to post-deposition processes such as ion implantation or diffusion doping, in-situ doping is convenient and inexpensive, and can effectively avoid introducing potential lattice defects.

[0065] In addition, similar to the principle of thickness variation of different functional layers 21, the in-situ doping concentration variation of different functional layers 21 can also be achieved by various implementation methods.

[0066] In some possible implementations, the in-situ doping concentration of different functional layers 21 is different. That is, the in-situ doping concentration of each functional layer 21 can be changed layer by layer.

[0067] Optionally, the in-situ doping concentration of each functional layer 21 can vary linearly.

[0068] In other possible implementations, the multilayer functional layer 21 includes multiple functional layer groups U, each functional layer group U including at least two functional layers 21; wherein, the in-situ doping concentration of the functional layers 21 in the same functional layer group U is the same, and the in-situ doping concentration of the functional layers 21 in different functional layer groups U is different. That is, the in-situ doping concentration of each functional layer 21 can be changed group by group according to the divided functional layer groups U.

[0069] This disclosure also provides a method for manufacturing a laminated structure in some embodiments, used to prepare the laminated structure in any of the above embodiments. This manufacturing method also possesses all the technical advantages of the aforementioned laminated structures, and will not be elaborated upon here.

[0070] Please see Figure 4 The manufacturing method of the laminated structure provided in this embodiment may include the following steps S100~S300.

[0071] S100, obtain the number of functional layers to be stacked. The functional layers are used to form the target structure or the receiving slot of the target structure after patterning.

[0072] S200: Match the distance differences between the target structure and the substrate corresponding to different functional layers to determine the formation thickness of each functional layer.

[0073] S300, according to the thickness, multiple functional layers and multiple dielectric layers are alternately stacked on the substrate to obtain a stacked structure.

[0074] For example, the thickness difference between different functional layers can be achieved by modulating the process time. Thus, the manufacturing method provided in this disclosure is easy to implement and requires no additional process steps.

[0075] In some embodiments of this disclosure, the functional layer includes a semiconductor layer. Please refer to... Figure 5 The method for manufacturing the stacked structure further includes: in step S200', matching the distance differences between the target structure and the substrate corresponding to different functional layers to determine the in-situ doping concentration of each functional layer. Accordingly, in step S300', the functional layers are formed based on the corresponding formation thickness and the in-situ doping concentration.

[0076] Based on the above, some embodiments of this disclosure also provide a semiconductor structure that can be fabricated based on the stacked structure in some of the above embodiments.

[0077] Please see Figure 1 Figure (b) in the middle and Figure 2 Figure (b) shows a semiconductor structure comprising a substrate 1 and a plurality of devices 3 arrayed on the substrate 1 and stacked along a direction perpendicular to the substrate 1. Each device 3 includes a semiconductor layer 31. The size difference between different semiconductor layers 31 is related to the difference in distance between their corresponding devices 3 and the substrate 1.

[0078] For example, device 3 includes, but is not limited to, a gate-all-around transistor, a dual-gate transistor, or a channel-all-around transistor.

[0079] In some embodiments, such as Figure 1 As shown in Figure (b), the semiconductor layer 31 extends in a direction parallel to the substrate 1; wherein, in the direction away from the substrate 1, the thickness of each semiconductor layer 31 gradually decreases in the direction perpendicular to the substrate.

[0080] For example, the semiconductor layer 31 is formed based on the patterning of the functional layer 21 in the stacked structure 2.

[0081] For example, the thicknesses of different semiconductor layers 31 are different; that is, the thickness of each semiconductor layer 31 can decrease layer by layer along the direction away from the substrate 1. Alternatively, the multilayer semiconductor layer 31 includes multiple semiconductor layer groups, each semiconductor layer group including at least two semiconductor layers 31; wherein the semiconductor layers 31 in the same semiconductor layer group have the same thickness, and the semiconductor layers 31 in different semiconductor layer groups have different thicknesses. That is, the thickness of each semiconductor layer 31 can decrease layer by layer along the direction away from the substrate 1 according to the divided semiconductor layers.

[0082] For example, Figure 1Figure (b) illustrates the three-layer semiconductor layer 31 as an example. In the direction away from the substrate 1, the thickness T1 of the first semiconductor layer 31 is greater than the thickness T2 of the second semiconductor layer 31, and the thickness T2 of the second semiconductor layer 31 is greater than the thickness T3 of the third semiconductor layer 31, that is: T1 > T2 > T3.

[0083] Based on this, in some embodiments, please refer to Figure 1 In Figure (b), device 3 further includes: gate 33 and gate dielectric layer 32 located between gate 33 and semiconductor layer 31.

[0084] Here, it can be understood that the gate 33 and the gate dielectric layer 32 can be formed in the region where the dielectric layer has been removed after the dielectric layer in the corresponding region of the stacked structure has been removed.

[0085] In some possible implementations, the gate 33, the gate dielectric layer 32, and the semiconductor layer 31 are stacked sequentially, with the gate 33 located on the side of the semiconductor layer 31 close to and / or away from the substrate 1.

[0086] In some other possible implementations, device 3 is a dual-gate transistor, that is, gate 33 can be provided on both the side of semiconductor layer 31 near substrate 1 and the side away from substrate 1.

[0087] In some other possible implementations, device 3 is a fully surround gate transistor, that is, the gate 33 surrounds the semiconductor layer 31 in a plane perpendicular to the substrate 1.

[0088] It should be added that, in some of the above embodiments, such as Figure 1 As shown in Figure (b), the device 3 also includes a first source / drain 34 and a second source / drain 35 located on both sides of the semiconductor layer 31 and respectively connected to the semiconductor layer 31.

[0089] Optionally, the first source / drain 34 and the second source / drain 35 can be patterned based on the functional layer 21 in the stacked structure 2, or they can be independently fabricated in the region where the functional layer has been removed after the corresponding region of the stacked structure has been removed.

[0090] In other embodiments, please refer to Figure 2 The semiconductor structure further includes: multiple functional layers 21 and multiple dielectric layers 22 alternately stacked on the substrate 1, and holes H penetrating each functional layer 21 and the corresponding dielectric layer 22 along the direction perpendicular to the substrate. Each functional layer 21 has a receiving groove G surrounding the hole H. Semiconductor layers 31 cover the inner wall of the receiving groove G, and along the direction away from the substrate 1, the width of each semiconductor layer 31 gradually increases along the direction perpendicular to the substrate 1.

[0091] For example, such as Figure 2As shown in Figure (b), device 3 further includes a first source / drain 34 and a second source / drain 35 located on both sides of semiconductor layer 31 and respectively connected to semiconductor layer 31. Furthermore, the first source / drain 34 and the second source / drain 35 can be patterned based on the functional layer 21 in the stacked structure 2; that is, the functional layer 21 includes: a first source / drain 34 and a second source / drain 35 located on both sides of semiconductor layer 31 along the direction parallel to substrate 1 and respectively connected to semiconductor layer 31.

[0092] Furthermore, it can be understood that the receiving trench G is formed by removing the functional layer 21 of the corresponding region, while the semiconductor layer 31 is formed on the inner wall of the receiving trench G. Therefore, the thickness of the functional layer 21 can be expressed as the width of the corresponding semiconductor layer 31. That is, the thickness of each functional layer 21 is equal to the width of the corresponding semiconductor layer 31.

[0093] For example, Figure 2 Figure (b) illustrates the three-layer semiconductor layer 31 as an example. In the direction away from the substrate 1, the thickness D1 of the first semiconductor layer 31 is less than the thickness D2 of the second semiconductor layer 31, and the thickness D2 of the second semiconductor layer 31 is greater than the thickness D3 of the third semiconductor layer 31, that is: D1 < D2 < D3.

[0094] For example, the widths of different semiconductor layers 31 are different; that is, the width of each semiconductor layer 31 can increase layer by layer in the direction away from the substrate 1. Alternatively, the multilayer semiconductor layers 31 include multiple semiconductor layer groups, each semiconductor layer group including at least two semiconductor layers 31; wherein the semiconductor layers 31 in the same semiconductor layer group have the same width, and the semiconductor layers 31 in different semiconductor layer groups have different widths. That is, the width of each semiconductor layer 31 can increase layer by layer in the direction away from the substrate 1 according to the divided semiconductor layers.

[0095] Based on this, in some embodiments, please refer to Figure 2 In Figure (b), device 3 further includes: a gate dielectric layer 32 located on the side of semiconductor layer 31 away from functional layer 21 (e.g., first source / drain 34 and second source / drain 35), and a gate 33 located on the side of gate dielectric layer 32 away from semiconductor layer 31.

[0096] Optionally, such as Figure 2 As shown in Figure (b), device 3 is a fully surround channel transistor, that is, the semiconductor layer 31 surrounds the gate 33 in a plane parallel to the substrate 1.

[0097] Optionally, such as Figure 2 As shown in Figure (b), the semiconductor structure also includes a word line WL located within the hole H and connected to the gate 33.

[0098] In some examples, the word line WL and the connected gate 33 are an integral structure, that is, the word line WL and the connected gate 33 can be formed using the same material and the same deposition process.

[0099] It is worth mentioning that, in some embodiments, the difference in in-situ doping concentration of different semiconductor layers 31 is related to the difference in their distance from the substrate 1.

[0100] Here, the semiconductor layer 31 can be formed based on the functional layer 21 in the stacked structure, for example... Figure 1 As shown in Figure (b); or, the semiconductor layer 31 can also be formed within the accommodating trench G of the corresponding functional layer 21, for example... Figure 2 As shown in Figure (b). Furthermore, in the example where the first source / drain 34 and the second source / drain 35 of device 3 are formed based on the corresponding functional layer 21 and the functional layer 21 is made of semiconductor material, the difference in in-situ doping concentration of the first source / drain 34 and the second source / drain 35 in different layer devices 3 is also related to the difference in their distance from the substrate 1.

[0101] Furthermore, the in-situ doping concentration changes of the semiconductor layer 31 and the first source / drain 34 and the second source / drain 35 in each device 3 can be implemented with reference to the in-situ doping concentration changes of each functional layer 21 in some of the aforementioned embodiments.

[0102] In summary, to more clearly illustrate the advantages of the stacked structure and semiconductor structure in the embodiments of this disclosure, the following description uses a semiconductor structure as an example of a memory.

[0103] It is understandable that three-dimensional stacking of memory cells in a memory can achieve higher density and lower cost integration. However, although the device (e.g., transistor) dimensions of each memory cell are designed to be the same, in actual fabrication, due to limitations in process capabilities, the actual contours of the deep holes or trenches used to fabricate each device vary from top to bottom with their distance from the substrate. This causes the device dimensions and performance parameters (e.g., threshold voltage Vth) of each device to also vary regularly from top to bottom with their distance from the substrate, which can easily lead to significant performance differences between devices located at the top and bottom of the memory.

[0104] For example, such as Figure 6 and Figure 7 As shown, the memory cell in the memory adopts a 2T0C architecture, meaning that the memory cell includes two transistors and zero capacitors; wherein, at least one transistor can be fabricated using the aforementioned stacked structure, and this transistor is device 3 in the aforementioned semiconductor structure, which can serve as a read / write transistor. This transistor is, for example, Figure 6 The fully surround gate transistor shown or Figure 7 The dual-gate transistor shown.

[0105] In some embodiments, the memory cell in the memory may also adopt a 2T1C architecture, that is, the memory cell includes two transistors and one capacitor. Similarly, at least one transistor in the memory cell can be formed using the aforementioned stacked structure, and this transistor is device 3 in the aforementioned semiconductor structure, which can serve as a read / write transistor. Alternatively, the memory cell in the memory may also adopt a 1T1C architecture, that is, the memory cell includes one transistor and one capacitor, and this transistor can be formed using the aforementioned stacked structure, and this transistor is device 3 in the aforementioned semiconductor structure, which can serve as an access transistor. The embodiments of this disclosure do not limit the architecture of the memory cell.

[0106] Based on this, please refer to Figure 8 For memory, I R = k× (V SN -V th ) = k× (V DATA -V th ); where I R To read the current, k is the correlation coefficient, V SN V is the storage node voltage. th V is the threshold voltage for reading and writing transistors. DATA The voltage is used to store data. Therefore, in order to reliably read data, the bit line current change ΔI caused by the read / write transistors in the memory cell is required. BL It should be less than the bit current variation ΔI between adjacent memory cells. bit Furthermore, for multi-bit storage, the bit line current change ΔI in the storage cell caused by the read / write transistors... BL The smaller the better. That is, reduce the bit line current variation ΔI corresponding to each memory cell in the memory. BL It is of utmost importance.

[0107] The stacked structure and semiconductor structure provided in the foregoing embodiments of this disclosure can effectively compensate for the impact of process differences on the performance of different layer devices 3 (e.g., transistors) by controlling the thickness difference of different functional layers 21. Specifically, by controlling the thickness of the functional layer 21 to correspond to the dimension of the semiconductor layer 31 in the device 3 along the direction perpendicular to the substrate 1, the channel dimension of the device 3 is controlled to compensate for the performance of different layer devices 3. For example, the sensing margin of read / write transistors in 2T0C or 2T1C memory cells can be improved, especially for each memory cell used for multi-bit storage; or, for example, the uniformity of access transistors in 1T1C memory cells can be improved.

[0108] Furthermore, in some embodiments, the stacked structure and semiconductor structure provided in the foregoing embodiments of this disclosure can effectively compensate for the impact of process differences on the performance of different layer devices 3 (e.g., transistors) by controlling the in-situ doping concentration difference of different functional layers 21. Specifically, by controlling the in-situ doping concentration of the functional layer 21 to correspond to the in-situ doping concentration of the semiconductor layer 31 or the first source / drain 34 and the second source / drain 35 in the device 3, the threshold voltage Vth or electron mobility of the device 3 is controlled to compensate for the performance of different layer devices 3.

[0109] This disclosure also provides an electronic device, such as a data storage device, a photocopier, a network device, a home appliance, an instrument, a mobile phone, a computer, or other devices with data storage capabilities. The electronic device may include a housing and a circuit board disposed within the housing, and a semiconductor structure integrated on the circuit board. The semiconductor structure can be referred to the relevant descriptions in the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in this disclosure.

[0110] In some embodiments, the semiconductor structure is a memory, which can be coupled to an external control device such as a processor or actuator. The processor is coupled to the memory and is able to control the read and write operations of the memory.

[0111] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A layered structure, characterized in that, include: Multiple functional layers and multiple dielectric layers are alternately stacked on a substrate; The functional layer is used to form the target structure or the receiving groove of the target structure after patterning; The thickness difference of the functional layers in different layers is related to the difference in distance between the corresponding target structure and the substrate.

2. The stacked structure as described in claim 1, characterized in that, The functional layers are used to form the target structure after patterning; wherein the thickness of each functional layer gradually decreases along the direction away from the substrate.

3. The stacked structure as described in claim 1, characterized in that, The functional layers are used to form receiving grooves of the target structure after patterning; wherein the thickness of each functional layer gradually increases along the direction away from the substrate.

4. The stacked structure as described in claim 1, characterized in that, The thickness of the functional layers varies in different layers; Alternatively, the multi-layered functional layers may include multiple functional layer groups, each functional layer group including at least two functional layers; wherein the functional layers in the same functional layer group have the same thickness, and the functional layers in different functional layer groups have different thicknesses.

5. The laminated structure as described in any one of claims 1 to 4, characterized in that, The functional layer includes a semiconductor layer; wherein the difference in in-situ doping concentration of different functional layers is related to the difference in distance from the corresponding target structure to the substrate.

6. A method for manufacturing a laminated structure, characterized in that, include: Obtain the number of functional layers to be stacked; the functional layers are used to form the target structure or the receiving slot of the target structure after patterning; By matching the distance differences between the target structure and the substrate corresponding to the functional layers of different layers, the formation thickness of each functional layer is determined; Based on the thickness, multiple functional layers and multiple dielectric layers are alternately stacked on the substrate to obtain a stacked structure.

7. The method for manufacturing the laminated structure as described in claim 6, characterized in that, The functional layer includes a semiconductor layer; The manufacturing method further includes: By matching the distance differences between the target structure and the substrate corresponding to the functional layers of different layers, the in-situ doping concentration of each functional layer is determined; The functional layer is formed based on the corresponding formation thickness and the in-situ doping concentration.

8. A semiconductor structure, characterized in that, include: A substrate and an array of devices disposed on the substrate and stacked along a direction perpendicular to the substrate; the devices include a semiconductor layer; The size difference of the semiconductor layers in different layers is related to the difference in distance between the corresponding device and the substrate.

9. The semiconductor structure as described in claim 8, characterized in that, The semiconductor layers extend in a direction parallel to the substrate; wherein, in a direction away from the substrate, the thickness of each semiconductor layer gradually decreases in a direction perpendicular to the substrate.

10. The semiconductor structure as described in claim 9, characterized in that, The device further includes: a gate and a gate dielectric layer located between the gate and the semiconductor layer; wherein... The gate, the gate dielectric layer, and the semiconductor layer are stacked sequentially, with the gate located on the side of the semiconductor layer close to and / or away from the substrate; Alternatively, the gate surrounds the semiconductor layer in a plane perpendicular to the substrate.

11. The semiconductor structure as described in claim 8, characterized in that, Also includes: Multiple functional layers and multiple dielectric layers are alternately stacked on the substrate, and holes penetrate each of the functional layers and the corresponding dielectric layers along the direction perpendicular to the substrate; The functional layer has a receiving groove surrounding the hole; the semiconductor layer covers the inner wall of the receiving groove, and the width of each semiconductor layer gradually increases in the direction perpendicular to the substrate, away from the substrate. The thickness of each functional layer is equal to the width of the corresponding semiconductor layer.

12. The semiconductor structure as claimed in claim 11, characterized in that, The functional layer includes: a first source / drain and a second source / drain located on both sides of the semiconductor layer along a direction parallel to the substrate and respectively connected to the semiconductor layer.

13. The semiconductor structure as described in claim 11, characterized in that, The device further includes: a gate dielectric layer located on the side of the semiconductor layer opposite to the functional layer, and a gate located on the side of the gate dielectric layer opposite to the semiconductor layer; The semiconductor structure further includes a word line located within the hole and connected to the gate.

14. The semiconductor structure according to any one of claims 8 to 13, characterized in that, The difference in in-situ doping concentration of different semiconductor layers is related to the difference in their distance from the substrate.

15. An electronic device, characterized in that, include: The semiconductor structure as described in any one of claims 8 to 14.

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