Semiconductor device

Abstract

A semiconductor device includes an active layer including a core region and a dummy region, the active layer including an active region disposed on the core region and the dummy region and a gate structure disposed on the active region, a front interconnect layer disposed on the active layer and including a front interconnect structure, and a back interconnect layer disposed under the active layer and including a back interconnect structure. The gate structure includes a first gate structure disposed on the core region and electrically connected to the front interconnect structure and a dummy gate structure disposed on the dummy region and electrically floating. The front interconnect structure includes a first front transmission line disposed on the core region and a first front connection line disposed on the core region and the dummy region. The first front connection line is electrically connected to the first front transmission line and extends from the core region to the dummy region.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and semiconductor chips that include semiconductor devices. Background Technology

[0002] With the increasing demand for high performance, high speed, and / or multifunctionality in semiconductor devices, the integration density of semiconductor devices has increased. Based on this trend towards higher integration, semiconductor devices with BackSide Power Delivery Network (BSPDN) structures have been developed, in which power rails are located on the back side of the wafer. Furthermore, research continues on the structures and methods for fault analysis (FA) of semiconductor devices with BSPDN structures. Summary of the Invention

[0003] One aspect of this disclosure is to provide a semiconductor device that can improve reliability without degrading electrical characteristics, and a semiconductor chip including said semiconductor device.

[0004] According to one aspect of this disclosure, a semiconductor device includes: an active layer comprising a core region and a dummy region surrounding the core region, the active layer including an active region, a plurality of gate structures, and a plurality of source / drain regions, the active region extending in a first direction and disposed on both the core region and the dummy region, the plurality of gate structures disposed on the active region, each of the plurality of gate structures extending in a second direction and intersecting the active region, the plurality of source / drain regions disposed on side surfaces of the plurality of gate structures and disposed on the active region; a front interconnect layer disposed on the active layer and including a front interconnect structure and a front insulating layer covering the front interconnect structure; and a rear interconnect layer disposed below the active layer and including a rear interconnect structure and a rear insulating layer covering the rear interconnect structure. The plurality of gate structures includes a plurality of first gate structures disposed on the core region and electrically connected to the front interconnect structure, and a plurality of dummy gate structures disposed on the dummy region and electrically floating. The front interconnect structure includes a first front transmission line disposed on the core region and a first front connection line disposed on the core region and the dummy region. The first front connection line is electrically connected to the first front transmission line and extends from the core region to the dummy region.

[0005] According to one aspect of this disclosure, a semiconductor device includes: an active layer including a core region and a dummy region surrounding the core region; a plurality of transmission lines stacked on the core region in a vertical direction perpendicular to an upper surface of the active layer, the plurality of transmission lines including a plurality of first transmission lines and a plurality of second transmission lines, the plurality of first transmission lines extending in a first horizontal direction parallel to the upper surface of the active layer, the plurality of second transmission lines alternately stacked with the plurality of first transmission lines and extending in a second horizontal direction parallel to the upper surface of the active layer and intersecting the first horizontal direction; a plurality of inspection lines stacked on the dummy region in the vertical direction, the plurality of inspection lines including a plurality of first inspection lines extending in the first horizontal direction and a plurality of second inspection lines alternately stacked with the plurality of first inspection lines and extending in the second horizontal direction; and a plurality of connecting lines extending from the core region to the dummy region and electrically connecting the plurality of transmission lines to the plurality of inspection lines. The plurality of connecting lines includes a plurality of first connecting lines extending in the first horizontal direction and a plurality of second connecting lines extending in the second horizontal direction.

[0006] According to one aspect of this disclosure, a semiconductor device includes: a plurality of gate structures spaced apart from each other in a first direction and each of the plurality of gate structures extending in a second direction intersecting the first direction; a plurality of dummy gate structures spaced apart from each other in the first direction and each of the plurality of dummy gate structures extending in the second direction; an interlayer insulating layer covering the plurality of gate structures and the plurality of dummy gate structures; a front interconnect structure disposed on the interlayer insulating layer; a plurality of gate contacts penetrating the interlayer insulating layer to electrically connect the plurality of gate structures to the front interconnect structure; and a rear interconnect structure disposed below the plurality of gate structures. The front interconnect structure includes: a plurality of front transmission lines, each of which includes a portion overlapping the plurality of gate structures in a third direction perpendicular to the first direction and the second direction; a plurality of front inspection lines, each of which includes a portion overlapping the plurality of dummy gate structures in the third direction; and a plurality of front connection lines connecting the plurality of front transmission lines to the plurality of front inspection lines. Each of the plurality of front connection lines includes a portion overlapping the plurality of gate structures in the third direction and a portion overlapping the plurality of dummy gate structures in the third direction. The front interconnect structure is electrically isolated from the plurality of dummy gate structures.

[0007] In a semiconductor device with a BSPDN structure, a portion of the metal interconnect in the core region can extend into a dummy region to enable fault analysis (FA) and the extended metal interconnect can be cut after the fault analysis (FA), thereby providing a semiconductor device and a semiconductor chip including the semiconductor device that can improve reliability without degrading electrical characteristics.

[0008] The advantages and effects of this disclosure are not limited to those described above, and can be more easily understood in the process of describing specific exemplary embodiments of this disclosure. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic top view showing a semiconductor chip according to an example embodiment; Figure 2A This is a schematic top view illustrating a semiconductor device according to an example embodiment; Figure 2B This is a schematic cross-sectional view illustrating a semiconductor device according to an example embodiment; Figure 2C This is a schematic partial enlarged view illustrating a semiconductor device according to an example embodiment; Figure 3A This is a schematic top view illustrating a semiconductor device according to an example embodiment; Figure 3B This is a schematic cross-sectional view illustrating a semiconductor device according to an example embodiment; Figures 4 to 12 This is a cross-sectional view showing a semiconductor device according to an example embodiment; Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20 , Figure 21 , Figure 22A , Figure 23 and Figure 24 This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 22BThis is a partially enlarged view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0010] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. It will be understood that, unless otherwise stated, expressions such as “on,” “above,” “above,” “below,” “under,” “below,” and “side” are used solely for indication purposes based on the drawings. Expressions such as “first,” “second,” etc., as used herein may refer to various different elements regardless of their order and / or priority, and are used only to distinguish one element from another, not to limit the elements. In the drawings, similar reference numerals may denote similar elements. Unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms as well.

[0011] Figure 1 This is a schematic top view illustrating a semiconductor chip according to an example embodiment. For ease of description, only... Figure 1 The image shows some components of a semiconductor chip.

[0012] Figure 2A This is a schematic top view illustrating a semiconductor device according to an example embodiment. Figure 2A Show Figure 1 An enlarged view of region "A" is provided, showing the semiconductor device located in the corresponding region. For ease of description, Figure 2A Only some components of the semiconductor device are shown. Figure 2A This illustrates a portion of an interconnect layer that may be included in a component of a semiconductor device.

[0013] Figure 2B This is a schematic cross-sectional view illustrating a semiconductor device according to an example embodiment. Figure 2B It is along Figure 2A A schematic cross-sectional view of line II′ of a semiconductor device.

[0014] Figure 2C This is a schematic partial enlarged view illustrating a semiconductor device according to an example embodiment. Figure 2C Show Figure 2B A magnified view of region "B".

[0015] refer to Figure 1 The semiconductor chip 10 may include multiple core regions CR, dummy regions DR surrounding the multiple core regions, and remaining slicing tracks SL surrounding the dummy regions DR.

[0016] Multiple core regions (CRs) can be arranged in a grid shape with the same or different sizes, and can be regions in which transistors are set.

[0017] A dummy region DR can surround multiple core regions CR and can be disposed between multiple core regions CR. Multiple core regions CR can be separated from each other by the dummy region DR. Within the dummy region DR, components identical or similar to those disposed in the multiple core regions CR can be disposed, but such components can be dummy components that do not transmit electrical signals or power. In embodiments, dummy components can include dummy transistors having dummy gate structures and dummy source / drain regions. In embodiments, core regions CR can refer to the region where functional logic circuitry, such as processors, memory blocks, signal processors, caches, and interconnect structures, is located. For example, core regions CR can include standard cell logic, custom logic, or intellectual property (IP) cores. In embodiments, the semiconductor chip also includes a peripheral region in which input / output (I / O) pads, power loops, and test circuitry are implemented. In embodiments, the dummy region DR can be disposed in the space between the peripheral region and the core region CR to improve process consistency in the manufacture of the semiconductor chip 10.

[0018] The remaining scribe line SL can surround the dummy region DR and can form the edge of the semiconductor chip 10. The remaining scribe line SL can be the scribe line remaining after the semiconductor chip is diced into individual chip units along the scribe line in the wafer, which includes semiconductor chips arranged in a grid pattern and scribe lines extending between the semiconductor chips. Unlike semiconductor devices that can be disposed in the core region CR and the dummy region DR, semiconductor devices may not be disposed in the remaining scribe line SL.

[0019] refer to Figures 2A to 2C The semiconductor device 100 may include a core region CR and a dummy region DR surrounding the core region CR, and may include an active layer ACL, a front interconnect layer FML disposed on the active layer ACL, and a rear interconnect layer BML disposed below the active layer ACL.

[0020] In structures including a front interconnect layer (FML) and a back interconnect layer (BML) covering the upper and lower portions of an active layer ACL, fault analysis (FA) using optical measurement methods to detect defects in transistors included in the active layer ACL may be impossible, and therefore, an alternative method is required for defect detection. As a method, the structures of the front interconnect structure 210 of the front interconnect layer FML and the back interconnect structure 250 of the back interconnect layer BML can be modified to detect defects in transistors via back-end (BEOL) wiring, which refers to the formation of metal interconnects and pathways in the BEOL process where transistors formed in the front-end (FEOL) process are electrically connected to functional logic, memory, or analog circuitry. If necessary, extended metal lines formed through the BEOL process for detecting defects in transistors can be cut to prevent or minimize speed degradation of the semiconductor device. This disclosure provides a semiconductor device capable of improving reliability without degrading electrical characteristics by achieving defect detection without degrading the performance of the semiconductor device or by minimizing performance degradation. In addition to semiconductor devices included in logic chips, this disclosure can also be applied to semiconductor devices included in the peripheral regions of memory chips such as SRAM.

[0021] The active layer ACL may include components formed by a front-end (FEOL) process, such as transistors including gate structures. The front interconnect layer (FML) may be disposed on the active layer ACL and may include components formed by a back-end (BEOL) process, and such components may transmit electrical signals to components formed in the active layer ACL. The back interconnect layer (BML) may be disposed below the active layer ACL and may include components that transmit power to components formed in the active layer ACL. Each of the active layer ACL, the front interconnect layer (FML), and the back interconnect layer (BML) may include a core region CR and a dummy region DR surrounding the core region. With respect to each core region CR, the dummy region DR may be a ring shape surrounding the core region CR. Depending on the description method, the core region CR and the dummy region DR may be defined by the active layer ACL. For example, the core region CR may be a region in which a transistor of a semiconductor device is disposed, and the dummy region DR may be a region in which a dummy transistor is disposed.

[0022] The active layer ACL may include: an active region 105; a channel structure 140 including a first channel layer 141, a second channel layer 142, and a third channel layer 143 perpendicularly spaced apart from each other on the active region 105; a gate structure 160 extending by intersecting the active region 105 and including a gate electrode 165; a source / drain region 130 connected to the channel structure 140; a front contact 181 and a back contact 191 connected to the source / drain region 130; a lower barrier structure 195 penetrating the active region 105 below the gate structure 160; and a rear power rail 193 connected to the back contact 191 below the active region 105. The active layer ACL of the semiconductor device 100 may also include an interlayer insulating layer 170.

[0023] In the semiconductor device 100, the active region 105 may have a fin structure, and the gate electrode 165 may be disposed between the active region 105 and the channel structure 140, and may be disposed between the first channel layer 141, the second channel layer 142 and the third channel layer 143 of the channel structure 140, and may also be disposed on the channel structure 140. Therefore, the semiconductor device 100 may include a transistor having an MBCFET™ (Multi-Bridge Channel FET) structure as a gate-all-around field-effect transistor.

[0024] The active region 105 may have an upper surface extending in a first direction (e.g., the X direction). The active region 105 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. (See also...) Figure 13A and Figure 13BThe active region 105 may be a component included in a substrate 101 having upper surfaces extending in the X and Y directions, and as the manufacturing process proceeds, at least a portion of the substrate 101 may be removed, such that the active region 105, as part of the substrate 101, may remain in the semiconductor device 100. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. The substrate 101 may include semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. The active region 105 may be defined by a device isolation layer formed by a shallow trench isolation (STI) process and may be configured to extend in one direction (e.g., the X direction). The X direction may be defined as a first direction or a second direction. The active region 105 may partially protrude onto the device isolation layer, such that the upper surface of the active region 105 may be disposed at a height higher than the upper surface of the device isolation layer. On both sides of the gate structure 160, the active region 105 can be partially recessed to form a recessed region, and the source / drain region 130 can be disposed in the recessed region.

[0025] In an example embodiment, the active region 105 may or may not include a well region containing impurities. For example, in the case of a P-type transistor (pFET), the well region may include N-type impurities such as phosphorus (P), arsenic (As), and antimony (Sb), and in the case of an N-type transistor (nFET), the well region may include P-type impurities such as boron (B), gallium (Ga), and indium (In). The well region may, for example, be located at a predetermined depth from the upper surface of the active region 105.

[0026] The device isolation layer defining the active region 105 may be formed of an insulating material (e.g., oxide, nitride, or a combination thereof).

[0027] In the example embodiment, the active region 105 can be completely removed during the process and can be replaced with an insulating layer. For example, in the following... Figure 22A In this process, not only the substrate 101 but also the active region 105 can be removed, and the space from which the active region 105 is removed can be filled with an insulating material and can be replaced with an insulating layer.

[0028] In the region where the active region 105 intersects with the gate structure 160, a channel structure 140 may be disposed on the active region 105. Each channel structure 140 may include a plurality of channel layers spaced apart from each other in a third direction (e.g., the Z direction), namely a first channel layer 141, a second channel layer 142, and a third channel layer 143. The third direction may also be referred to as the vertical direction. The first channel layer 141, the second channel layer 142, and the third channel layer 143 may be sequentially disposed from the lower part of the channel structure 140. The channel structure 140 may be connected to the source / drain region 130. The channel structure 140 may have the same or similar width in the X direction as the gate structure 160. In the example embodiment, the number and shape of the channel layers included in a channel structure 140 may vary. For example, a channel structure 140 may include four channel layers, and may include two or three channel layers, or five or more channel layers.

[0029] The channel structure 140 may be formed of a semiconductor material (e.g., at least one of silicon (Si), silicon-germanium (SiGe), and germanium (Ge). The channel structure 140 may be formed of, for example, the same material as the active region 105. In some example embodiments, the channel structure 140 may include an impurity region disposed in a region adjacent to the source / drain region 130.

[0030] The gate structure 160 can be configured to extend in a direction (e.g., the Y direction) intersecting the active region 105 and the channel structure 140. The Y direction can be defined as a second direction or a first direction. When the active region 105 is defined to extend in the first direction, the gate structure 160 can be defined to extend in the second direction intersecting the first direction. Conversely, when the gate structure 160 is defined to extend in the first direction, the active region 105 can be defined to extend in the second direction intersecting the first direction. The first direction and the second direction can also be referred to as a first horizontal direction and a second horizontal direction, respectively. The active region 105 and / or the channel structure 140 intersecting the gate electrode 165 of the gate structure 160 can form the functional channel region of the transistor.

[0031] Gate structure 160 may include a first gate structure 160a electrically connected to the front interconnect structure 210 via gate contact 185 and a second gate structure 160b not electrically connected to the front interconnect structure 210. In an embodiment, the second gate structure 160b may be an electrically floating dummy gate structure electrically isolated from or not connected to other elements including the front interconnect structure 210. The first gate structure 160a may be disposed in the core region CR and may not be disposed in the dummy region DR. According to an example embodiment, the second gate structure 160b may be disposed in the dummy region DR and may also be disposed between the first gate structures 160a located in the core region CR. In an embodiment, some gate structures located in the core region CR may appear not to be connected to the gate contact 185, but these gate structures are connected to the gate contact 185 at different locations along the second direction (Y-axis). Since the gate contact 185 is not disposed on the second gate structure 160b, which is a dummy component, the entire upper surface of each second gate structure 160b may be covered by the interlayer insulating layer 170. In other words, the entire upper surface of each second gate structure 160b can contact the interlayer insulating layer 170.

[0032] Each gate structure 160 may include a gate electrode 165, a gate dielectric layer 162, and a gate spacer 164.

[0033] A gate dielectric layer 162 may be disposed between the active region 105 and the gate electrode 165, and between the channel structure 140 and the gate electrode 165, and may be configured to cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may be configured to surround all surfaces except the uppermost surface of the gate electrode 165. The gate dielectric layer 162 may extend between the gate electrode 165 and the gate spacer 164, but this disclosure is not limited thereto. The gate dielectric layer 162 may include oxides, nitrides, or high-k materials. High-k materials may refer to dielectric materials having a higher dielectric constant than silicon oxide (SiO2) films. High-k materials may be, for example, alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2) and hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y Hafnium aluminum oxide (HfAl) x O yIt is one of praseodymium oxide (Pr₂O₃) and praseodymium oxide (Pr₂O₃). According to an example embodiment, the gate dielectric layer 162 may be formed of a multilayer film.

[0034] The gate electrode 165 may be configured to fill the gap between the first channel layer 141, the second channel layer 142, and the third channel layer 143 located on the active region 105 and may extend onto the channel structure 140. The gate electrode 165 may be separated from the first channel layer 141, the second channel layer 142, and the third channel layer 143 by a gate dielectric layer 162. The gate electrode 165 may include a conductive material and may include metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN) and / or metallic materials such as aluminum (Al), tungsten (W), and molybdenum (Mo), or semiconductor materials such as doped polycrystalline silicon. According to an example embodiment, the gate electrode 165 may be formed from two or more multilayers.

[0035] Gate spacer 164 may be disposed on the opposite side surface of gate electrode 165 located on channel structure 140 in a first direction (X-axis). Gate spacer 164 may insulate source / drain region 130 from gate electrode 165. According to an example embodiment, gate spacer 164 may be formed of a multilayer structure. Gate spacer 164 may be formed of at least one of oxide, nitride, and oxynitride, and may be formed of, for example, a low-k film.

[0036] In an example embodiment, a gate capping layer comprising an insulating material may be disposed on the gate structure 160. The gate capping layer may include at least one of, for example, oxides, nitrides, and oxynitrides.

[0037] The source / drain region 130 may be disposed in a recessed region obtained by partially recessing the upper portion of the active region 105 on opposite sides of the gate structure 160. The recessed region may extend along the side surface of the channel structure 140 and the side surface of the gate dielectric layer 162. The source / drain region 130 may be disposed to cover the X-direction side surface of each of the first channel layer 141, the second channel layer 142, and the third channel layer 143 of the channel structure 140. The upper surface of the source / drain region 130 may be disposed at a height equal to or higher than the height of the lower surface of the gate electrode 165 located on the channel structure 140, and the height may vary in the example embodiment. In the example embodiment, the side surface of the source / drain region 130 may have a curvature according to the first channel layer 141, the second channel layer 142, and the third channel layer 143. In an example embodiment, internal spacers comprising insulating material may be further provided between the side surface of the source / drain region 130 and the gate structure 160. In an example embodiment, the specific shape of the side surface of the source / drain region 130 may vary. The source / drain region 130 may be an epitaxial growth region and may include multiple epitaxial layers. The epitaxial growth surface of the source / drain region 130 may contact the channel structure 140 and the interlayer insulating layer 170.

[0038] The source / drain region 130 may include a semiconductor material (e.g., at least one of silicon (Si) and germanium (Ge)) and may also include a dopant. For example, for an nFET, the dopant may be an n-type dopant including at least one of phosphorus (P), arsenic (As), and antimony (Sb). For example, for a pFET, the dopant may be a p-type dopant including at least one of boron (B), gallium (Ga), and indium (In).

[0039] The interlayer insulating layer 170 may be configured to cover the source / drain region 130 and the gate structure 160. In an example embodiment, the interlayer insulating layer 170 may include multiple insulating layers. The interlayer insulating layer 170 may include at least one of oxides, nitrides, and oxynitrides, and may include, for example, a low-k material.

[0040] The front contact 181 can be connected to the source / drain region 130 and can transmit power to the source / drain region 130. The front contact 181 can be configured to penetrate the interlayer insulation layer 170 and be recessed from the top into or extend into the source / drain region 130. The front contact can have a side surface that is inclined towards the active region 105 due to the aspect ratio (i.e., such that its width decreases with decreasing height), but this disclosure is not limited thereto. The front contact 181 can be as follows: Figure 2CThis example embodiment shows an extension from the upper portion of the channel structure 140 to below the lower surface of the third channel layer 143, which serves as the third channel layer. This disclosure is not limited thereto. In an embodiment, the front contact 181 may extend below the lower surface of the second channel layer 142. Although not specifically shown, the front contact 181 may include a metal semiconductor compound layer disposed along a surface recessed along the source / drain region 130 and a conductive layer situated on the metal semiconductor compound layer. The metal semiconductor compound layer may include metal elements and semiconductor elements, and may include, for example, a metal silicide comprising at least one of TiSi, CoSi, MoSi, LaSi, NiSi, TaSi, and WSi. The conductive layer included in the front contact 181 may include, for example, a metallic material such as tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), ruthenium (Ru), and aluminum (Al).

[0041] The back contact 191 can be connected to the source / drain region 130 and can transmit power to the source / drain region 130. The back contact 191 can be configured to penetrate the active region 105 and be recessed from the bottom into or extend into the source / drain region 130. The back contact 191 can have a sloped side surface such that its width decreases with increasing height due to aspect ratio, but this disclosure is not limited thereto. The back contact 191 can be as follows: Figure 2C This example embodiment shows an extension from the lower portion of the channel structure 140 to above the upper surface of the first channel layer 141, which serves as the first channel layer. This disclosure is not limited thereto. In an embodiment, the back contact 191 may extend above the lower surface of the second channel layer 142. Although not specifically shown, the back contact 191 may include a metal semiconductor compound layer in which the source / drain regions 130 are disposed along a recessed surface, and a conductive layer located below the metal semiconductor compound layer. The metal semiconductor compound layer may include metal elements and semiconductor elements, and may include, for example, a metal silicide comprising at least one of TiSi, CoSi, MoSi, LaSi, NiSi, TaSi, and WSi. The conductive layer included in the back contact 191 may include, for example, a metallic material such as tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), ruthenium (Ru), and aluminum (Al).

[0042] The rear power rail 193 may be disposed below and electrically connected to the back contact 191. In an example embodiment, the rear power rail 193 may be disposed below the active region 105 and extend in a first direction (e.g., the X direction) in which the active region 105 extends. In an example embodiment, the rear power rail 193 may be formed simultaneously with the back contact 191, such that the rear power rail 193 and the back contact 191 may be integrally formed. The rear power rail 193 may, together with the back contact 191, form a BSPDN for applying power or ground voltage. In an example embodiment, the rear power rail 193 may include a pass region and / or a line region. The rear power rail 193 may include a conductive material and may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), and molybdenum (Mo).

[0043] A lower blocking structure 195 may be disposed below the gate structure 160 and penetrate the active region 105. The lower blocking structure 195 may separate the active region 105. The lower blocking structure 195 may block leakage current that may occur in the active region 105 located below the gate structure 160. The lower blocking structure 195 may contact the lower surface of the gate structure 160. In an example embodiment, the lower blocking structure 195 may penetrate the rear power rail 193. In an example embodiment, the lower blocking structure 195 may separate the rear power rail 193, depending on the design intent. The lower blocking structure 195 may have a shape in which its width decreases with increasing height, but this disclosure is not limited thereto. For example, in some example embodiments, the lower blocking structure 195 may have a shape in which its width increases with increasing height and then decreases again. In a second direction (e.g., the Y direction), the width of each lower blocking structure 195 may be equal to or greater than the width of the active region 105. The lower blocking structure 195 may include an insulating material and may include at least one of, for example, oxides, nitrides, and oxynitrides. The lower blocking structure 195 may be disposed within the core region CR or may not be disposed within the dummy region DR. In the example embodiment, when the active region 105 is removed and replaced with an insulating layer, the lower blocking structure 195 may not be disposed.

[0044] Gate contact 185 may be disposed on and electrically connected to gate structure 160. Gate contact 185 may be disposed on gate structure 160 by penetrating interlayer insulating layer 170. Gate contact 185 may electrically connect front interconnect structure 210 of front interconnect layer FML and gate structure 160, and may transmit electrical signals to gate structure 160. Gate contact 185 may be disposed on first gate structure 160a disposed in core region CR, and may not be disposed on second gate structure 160b.

[0045] The upper path 183 can be disposed on and electrically connected to the front contact 181. The upper path 183 can electrically connect the front interconnect structure 210 of the front interconnect layer FML to the front contact 181 and can transfer power to the source / drain region 130. The upper path 183 may not be disposed within the dummy region DR.

[0046] The front interconnect layer (FML) may include components formed by the BEOL process, such as front interconnect structure 210 and front insulating layer 225 covering front interconnect structure 210.

[0047] The front interconnect structure 210 can be located within the front interconnect layer FML on the active layer ACL, and can include front transmission lines 215 stacked sequentially in the core region CR and front connection lines 217 connected to the front transmission lines 215 and extending from the core region CR to the dummy region DR.

[0048] Although not specifically shown, pathways can be provided between lines at different heights, and lines at different heights can be connected to each other through pathways provided between them.

[0049] The front transmission line 215 may include a first front transmission line 215a extending in a first direction (e.g., in the X direction) and a second front transmission line 215b alternately stacked with the first front transmission line 215a and extending in a second direction (e.g., in the Y direction). The line disposed at the lowest height among the front transmission lines 215 and connected to the upper pass 183 or gate contact 185 in the active layer ACL may be the first front transmission line 215a extending in the first direction. Each front transmission line 215 may be a power transmission line or a signal transmission line. The power transmission line may supply different power supply voltages (e.g., VDD and VSS) to the semiconductor device and may be electrically connected to the source / drain region 130 within the active layer ACL. The signal transmission line may supply electrical signals to the semiconductor device and may be electrically connected to the gate structure 160. The front transmission lines 215 may be disposed in the core region CR and may not be disposed in the dummy region DR. The front transmission line 215 can be electrically connected to the first gate structure 160a or the source / drain region 130 disposed in the core region CR of the active layer ACL, but it can be decoupled from the second gate structure 160b or the source / drain region 130 disposed in the dummy region DR of the active layer ACL, and can be electrically isolated from the second gate structure 160b or the source / drain region 130 disposed in the dummy region DR. In other words, the second gate structure 160b and the source / drain region 130 disposed in the dummy region DR can be electrically floated.

[0050] The front connection line 217 can extend from the front transmission line 215 within the core region CR and can extend into the dummy region DR. The front connection line 217 may include a first front connection line 217a extending in a first direction (e.g., in the X direction) and a second front connection line 217b extending in a second direction (e.g., in the Y direction). In an embodiment, the first front connection line 217a may be positioned at the same height as the first front transmission line 215a. For example, the first front connection line 217a may be positioned at the same height as the uppermost first front transmission line 215a. In an embodiment, the second front connection line 217b may be positioned at the same height as the second front transmission line 215b.

[0051] The front check line 219 may be disposed within the dummy region DR and may be electrically connected to the front transmission line 215 via the front interconnect line 217. The front check line 219 may include a first front check line 219a extending in a first direction (e.g., in the X direction) and a second front check line 219b extending in a second direction (e.g., in the Y direction). The first front check line 219a may be disposed at the same height as the first front transmission line 215a, and the second front check line 219b may be disposed at the same height as the second front transmission line 215b. In an example embodiment, the first front check line 219a and the second front check line 219b may be alternately stacked and extended such that the front check line 219 may extend to the upper surface of the front interconnect layer FML. For example, the front interconnect layer FML can be a multi-level structure including a first front transmission line 215a and a second front transmission line 215b that are alternately stacked in the vertical direction, and the front check line 219 can also be formed in a multi-level structure, wherein each level of the front check line 219 corresponds to and is aligned with the corresponding level of the front interconnect layer FML.

[0052] The front interconnect structure 210 may include a conductive material, such as at least one of aluminum (Al), copper (Cu), tungsten (W), and ruthenium (Ru).

[0053] The front insulating layer 225 may cover the front interconnect structure 210 and may include multiple insulating layers. For example, the front insulating layer 225 may include multiple insulating layers stacked and disposed at a height corresponding to a corresponding height of the front interconnect structure 210. The front insulating layer 225 may include an insulating material and may include, for example, oxides, nitrides, or oxynitrides.

[0054] By performing routing tests on the front inspection line 219 disposed in the dummy region DR, defect detection can be performed on components located at least near the edge (i.e., outer boundary) of the core region CR. According to an example embodiment, defect detection can also be performed on components located inside the core region CR. The front inspection line 219 can be connected to the front transmission line 215 via the front connection line 217, and the front inspection line 219 can be disposed in a dummy region DR in which the front transmission line 215 is not disposed, allowing defects to be detected in components in the active layer ACL without altering the arrangement of the front transmission line 215 in the core region CR. Furthermore, because the interconnects extend only to the minimum required for routing tests, performance degradation of semiconductor devices due to increased interconnect lengths can be minimized, thereby enabling improved electrical characteristics. In embodiments, routing tests may include: scan chain tests for detecting logic or memory cell faults; IDDQ tests for measuring abnormal quiescent currents to detect leakage paths or short circuits; or parameter tests for measuring the electrical characteristics of transistors.

[0055] The rear interconnect layer BML may include a rear interconnect structure 250 that applies power to the rear power rail 193 and the back contact 191, and a rear insulating layer 265 covering the rear interconnect structure 250.

[0056] Although not specifically shown, pathways can be provided between lines positioned at different heights, and lines positioned at different heights can be connected to each other via pathways provided between them. For example, a pathway can be provided in the space between two adjacent first front transmission lines in the first front transmission line 215a and one of the second front transmission lines 215b, thereby connecting the first front transmission line 215a to the second front transmission line 215b. Similarly, a pathway can be provided in the space between two adjacent first front inspection lines in the first front inspection line 219a and one of the second front inspection lines 219b, thereby connecting the first front inspection line 219a to the second front inspection line 219b.

[0057] The rear interconnect structure 250 may include a first rear transmission line 255a extending in a first direction (e.g., the X direction) and a second rear transmission line 255b alternately stacked with the first rear transmission line 255a and extending in a second direction (e.g., the Y direction). Although not specifically shown, the first rear transmission line 255a and the second rear transmission line 255b, disposed at different heights, may be connected by a rear path disposed between them. The rear transmission line 255 may be electrically connected to the source / drain region 130 in the active layer ACL and may supply different power supply voltages (e.g., VDD and VSS) to the source / drain region 130 respectively. The rear transmission line 255 may be disposed in the core region CR and may not be disposed in the dummy region DR. The rear transmission line 255 may be electrically connected to the source / drain region 130 in the core region CR and may not be electrically connected to the source / drain region 130 in the dummy region DR.

[0058] The rear insulating layer 265 may cover the rear interconnect structure 250 and may include multiple insulating layers. For example, the rear insulating layer 265 may include multiple insulating layers stacked and disposed at a height corresponding to a corresponding height of the rear interconnect structure 250. The rear insulating layer 265 may include an insulating material, such as an oxide, nitride, or oxynitride.

[0059] Semiconductor device 100 can be used to... Figure 2B The structure is reversed for packaging, so that the back interconnect layer BML is placed in the upper part, but the packaging form of the semiconductor device 100 is not limited to this.

[0060] In the description of the following example embodiments, references to the above will be omitted. Figure 1 and Figures 2A to 2C The descriptions overlap.

[0061] Figure 3A This is a schematic top view illustrating a semiconductor device according to an example embodiment. Figure 3A Showing with Figure 2A The corresponding area. For ease of description, Figure 3A Only some components of the semiconductor device are shown. Figure 3A This shows a portion of the interconnect layer and front partition structure 220 that can be included in a component of a semiconductor device.

[0062] Figure 3B This is a schematic cross-sectional view illustrating a semiconductor device according to an example embodiment. Figure 3B schematically showing along Figure 3A The cross section cut by the cutting line Ⅱ-Ⅱ' of the semiconductor device.

[0063] refer to Figure 3A and Figure 3B ,and Figures 2A to 2CUnlike semiconductor device 100, semiconductor device 100A may also include a front partition structure 220. The front partition structure 220 can penetrate the front interconnect lines 217 within the front interconnect layer FML and can isolate the front interconnect lines 217 from each other. Therefore, the front transmission line 215 within the core region CR and the front check line 219 within the dummy region DR can be electrically isolated from each other. For example, the front partition structure 220 can divide each front interconnect line 217 into two parts. One part can remain connected to the front transmission line 215 in the core region CR, and the other part can be disconnected from the front transmission line 215. The front partition structure 220 can extend in a vertical direction (e.g., along the Z direction) within the front interconnect layer FML. The lower end of the front partition structure 220 can be disposed within the front interconnect layer FML, and the front partition structure 220 can be spaced apart from the active layer ACL. The front partition structure 220 may be disposed in the dummy region DR and may extend to surround at least a portion of the edge (i.e., outer boundary) of the core region CR, and may penetrate all front connecting lines 217 and may separate the front connecting lines 217 from each other. In an example embodiment, the front partition structure 220 may not be disposed in the portion in which the front connecting lines 217 are not disposed, and may not surround the portion surrounding the edge of the core region CR.

[0064] The semiconductor device 100A can form a front partition structure 220 by cutting and separating the front interconnect 217 after utilizing the front interconnect 217 and the front inspection line 219 provided for defect detection, so that it is possible to provide a semiconductor device that can prevent the performance of the semiconductor device from being degraded due to the extension of the interconnect and can improve reliability without degrading the electrical characteristics.

[0065] Figures 4 to 12 This is a cross-sectional view of a semiconductor device according to an example embodiment. Figures 4 to 12 All show with Figure 2B The corresponding area.

[0066] refer to Figure 4 ,and Figures 2A to 2C Unlike semiconductor device 100, semiconductor device 100B may include front interconnect structures 210 disposed at different heights. Front connection line 217 may include a first front connection line 217a extending in a first direction and disposed at different heights, and front check line 219 may at least partially contact the front connection line 217 and may be connected to the front transmission line 215.

[0067] refer to Figure 5 ,and Figure 4 Unlike semiconductor device 100B, semiconductor device 100C can be configured such that the front transmission line 215 and the front inspection line 219 can be spaced apart from each other in a first direction. In this case, also refer to… Figure 2A The front transmission line 215 and the front inspection line 219 can be electrically connected to each other via a first front connection line 217a extending in a first direction and a second front connection line 217b extending in a second direction.

[0068] refer to Figure 6 ,and Figures 2A to 2C Unlike semiconductor device 100, semiconductor device 100D can be configured such that the back interconnect structure 250 may include a back connection line 257 extending from the core region CR to the dummy region DR. In an example embodiment, the back interconnect structure 250 may include a first back connection line 257a extending in a first direction. The first back connection line 257a may include lines disposed at different heights. Figures 2A to 2C Unlike semiconductor device 100, front interconnect structure 210 may not include front connection line 217 and front check line 219.

[0069] refer to Figure 7 Semiconductor device 100E may include a post-inspection line 259 extending from the dummy region DR. See also... Figure 2A Similar to Figure 5 The semiconductor device 100C may include a rear interconnect structure 250 that may include a rear connection line 257 extending in a second direction.

[0070] refer to Figure 8 Unlike the previous example embodiments, semiconductor device 100F may include both front interconnect line 217 and rear interconnect line 257. Rear interconnect structure 250 may include a rear transmission line 255 disposed within a core region CR, a rear interconnect line 257 extending from the core region CR into a dummy region DR, and a rear check line 259 connected to the rear transmission line 255 via the rear interconnect line 257 within the dummy region DR. The front transmission line 215 and rear transmission line 255 may be collectively referred to as "transmission lines," the front interconnect line 217 and rear interconnect line 257 may be collectively referred to as "connection lines," and the front check line 219 and rear check line 259 may be collectively referred to as "check lines." The front interconnect structure 210 and rear interconnect structure 250 may be collectively referred to as "interconnect structure." For example, "interconnect structure" may refer to either the front interconnect structure 210 or the rear interconnect structure 250 according to the example embodiment.

[0071] refer to Figure 9 ,and Figure 8Unlike semiconductor device 100F, semiconductor device 100G may also include a front partition structure 220 and a rear partition structure 260. The front partition structure 220 may partition the front interconnect line 217 within the front interconnect layer FML, and the rear partition structure 260 may partition the rear interconnect line 257 within the rear interconnect layer BML. The rear partition structure 260 may extend in the vertical direction, and its upper end may be positioned at a height lower than the height of the active layer ACL, and may be spaced apart from the active layer ACL. In a third direction (e.g., the Z direction), the rear partition structure 260 may include a portion overlapping with the front partition structure 220. Except for the location where components are disposed, the rear partition structure 260 may have the same or similar features as the front partition structure 220. For example, similar to... Figure 3A The front partition structure 220 and the rear partition structure 260 shown can extend along the edge of the core region CR within the dummy region DR and can surround at least a portion of the edge of the core region CR.

[0072] refer to Figure 10 ,and Figure 9 Unlike semiconductor device 100G, semiconductor device 100H can be configured such that the front partition structure 220 and the rear partition structure 260 can extend into the active layer ACL. The front partition structure 220 and the rear partition structure 260 can contact each other. For example, the front partition structure 220 and the rear partition structure 260 can overlap and contact a portion of the second gate structure 160b in a third direction (e.g., the Z direction). Because the front partition structure 220 and the rear partition structure 260 extend within the dummy region DR, even if the front partition structure 220 and the rear partition structure 260 extend into the active layer ACL, the transistors and other components within the core region CR will not be damaged.

[0073] refer to Figure 11 ,and Figure 9 Unlike semiconductor device 100G, semiconductor device 100I may not include the rear partition structure 260 and may be configured such that the front partition structure 220 extends through the active layer ACL into the rear interconnect layer BML. The front partition structure 220 may penetrate and separate the front interconnect line 217 and the rear interconnect line 257.

[0074] refer to Figure 12 ,and Figure 11 Unlike semiconductor device 100I, semiconductor device 100J may not include the front separator structure 220 and may be configured such that the rear separator structure 260 can penetrate the active layer ACL and extend into the front interconnect layer FML. The rear separator structure 260 can penetrate and separate the front interconnect line 217 and the rear interconnect line 257.

[0075] Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20 , Figure 21 , Figure 22A , Figure 23 and Figure 24 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment, following a process sequence. Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20 , Figure 21 , Figure 22A , Figure 23 and Figure 24 Showing with Figure 2B The corresponding area.

[0076] Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 22B This is a partially enlarged view illustrating a method for manufacturing a semiconductor device according to an example embodiment, following a process sequence. Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 22B Showing with Figure 2C The corresponding area.

[0077] refer to Figure 13A and Figure 13B Multiple sacrificial layers 120 and multiple channel layers 141, 142 and 143 may be alternately stacked on substrate 101, and multiple channel layers 141, 142 and 143 and substrate 101 may be partially removed to form an active structure including active region 105.

[0078] Substrate 101 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Substrate 101 may include a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0079] Multiple channel layers 141, 142, and 143 may include a first channel layer 141, a second channel layer 142, and a third channel layer 143, and multiple sacrificial layers 120 may be stacked alternately with the multiple channel layers 141, 142, and 143. Figure 2B and Figure 2C As shown, the multiple sacrificial layers 120 may be layers that replace the gate dielectric layer 162 and gate electrode 165 beneath the first channel layer 141, second channel layer 142, and third channel layer 143 by subsequent processes. The sacrificial layers 120 may be formed of a material having etch selectivity relative to the first channel layer 141, second channel layer 142, and third channel layer 143. The first channel layer 141, second channel layer 142, and third channel layer 143 may include materials different from those of the sacrificial layers 120. The sacrificial layers 120, as well as the first channel layer 141, second channel layer 142, and third channel layer 143, comprise semiconductor materials including, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may include different materials and may or may not include impurities. For example, the sacrificial layer 120 may include silicon germanium (SiGe), and the first channel layer 141, second channel layer 142, and third channel layer 143 may include silicon (Si).

[0080] The sacrificial layer 120, as well as the first trench layer 141, the second trench layer 142, and the third trench layer 143, can be formed to create a stacked structure by performing an epitaxial growth process. In an example embodiment, the number of trench layers stacked alternately with the sacrificial layer 120 can vary.

[0081] The active structure may include an active region 105, multiple sacrificial layers 120, and a first channel layer 141, a second channel layer 142, and a third channel layer 143. The active structure may be formed in a linear shape extending in one direction (e.g., the X direction) and may be spaced apart from adjacent active structures in the Y direction. The side surfaces of the active structures in the Y direction may be coplanar with each other and may be arranged in a straight line.

[0082] Insulating material can be filled in a region from which portions of the active region 105, the plurality of sacrificial layers 120, and each of the first channel layer 141, the second channel layer 142, and the third channel layer 143 have been removed. A device isolation layer can be formed by removing portions of the insulating material such that the active region 105 protrudes beyond the upper surface of the remaining insulating material. The active region 105 can be formed as part of the substrate 101 and can include an epitaxial layer grown from the substrate 101.

[0083] refer to Figure 14A and Figure 14B A sacrificial gate structure 200 and a gate spacer 164 can be formed on the active structure.

[0084] As in Figure 2B and Figure 2C Similarly, each sacrificial gate structure 200 can be a sacrificial structure formed by subsequent processes in a region on the channel structure 140 where the gate dielectric layer 162 and gate electrode 165 are disposed. The sacrificial gate structure 200 can have a line shape extending in one direction when intersecting with an active structure. The sacrificial gate structure 200 can extend, for example, in the Y direction. Each sacrificial gate structure 200 can include a first sacrificial gate layer 202 and a second sacrificial gate layer 205 sequentially stacked, and a mask patterning layer 206. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 can be patterned using the mask patterning layer 206.

[0085] The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be an insulating layer and a conductive layer, respectively, but this disclosure is not limited thereto, and the first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be formed as a single layer. For example, the first sacrificial gate layer 202 may include silicon oxide, and the second sacrificial gate layer 205 may include polysilicon. The mask pattern layer 206 may include silicon oxide and / or silicon nitride.

[0086] Gate spacers 164 may be formed on opposite sidewalls of the sacrificial gate structure 200. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may have the same width, and the gate spacers 164 may be formed along the side surfaces of the first sacrificial gate layer 202 and the second sacrificial gate layer 205. This disclosure is not limited thereto. In embodiments, the first sacrificial gate layer 202 may be formed with a smaller width than the second sacrificial gate layer 205, and the gate spacers 164 may be formed along the side surfaces of the first sacrificial gate layer 202 and the second sacrificial gate layer 205. The gate spacers 164 may be formed of a low-k dielectric material and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0087] refer to Figure 15A and Figure 15B An etching process using the sacrificial gate structure 200 as an etching mask can be performed to form a recessed region RC that penetrates the active structure and exposes the active region 105.

[0088] The sacrificial layer 120 exposed from the sacrificial gate structure 200, as well as the first channel layer 141, the second channel layer 142, and the third channel layer 143, can be partially removed to form a recessed region, and multiple sacrificial layers 120 can be partially removed. Therefore, the first channel layer 141, the second channel layer 142, and the third channel layer 143 can form a channel structure 140 with a finite length in the X direction.

[0089] refer to Figure 16A and Figure 16B Multiple source / drain regions 130 can be formed in the recessed region RC.

[0090] The source / drain region 130 can be formed in the recessed region RC, and can be grown and formed, for example, from the side surface of the active region 105 and the side surface of the channel structure 140 by a selective epitaxial process.

[0091] The source / drain region 130 may include multiple epitaxial layers, and the epitaxial layers may have different non-silicon concentrations. The source / drain region 130 may include impurities through in-situ doping and may include multiple layers with different dopant elements and / or doping concentrations. In some example embodiments, the source / drain region 130 may have P-type conductivity and may be formed with at least one dopant selected from boron (B), gallium (Ga), and indium (In). In some example embodiments, the source / drain region 130 may have N-type conductivity and may be formed with at least one dopant selected from phosphorus (P), arsenic (As), and antimony (Sb).

[0092] refer to Figure 17A and Figure 17B It can partially form an interlayer insulating layer 170 and remove the sacrificial gate structure 200 and multiple sacrificial layers 120.

[0093] An interlayer insulating layer 170 can be formed by forming an insulating film covering the sacrificial gate structure 200 and the source / drain region 130 and performing a planarization process.

[0094] The sacrificial gate structure 200 and the plurality of sacrificial layers 120 can be selectively removed relative to the gate spacer 164 and the channel structure 140. First, the sacrificial gate structure 200 can be removed to form an upper gap region UR, and then the plurality of sacrificial layers 120 exposed through the upper gap region UR can be removed to form a lower gap region LR. For example, when the plurality of sacrificial layers 120 comprise silicon germanium (SiGe) and the channel structure 140 comprises silicon (Si), the plurality of sacrificial layers 120 can be selectively removed relative to the channel structure 140 by performing a wet etching process.

[0095] refer to Figure 18A and Figure 18B A gate dielectric layer 162 and a gate electrode 165 can be formed to form a gate structure 160.

[0096] The gate structure 160 can be formed to fill the upper gap region UR and the lower gap region LR. The gate dielectric layer 162 can be formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. The gate electrode 165 can be formed to completely fill the upper gap region UR and the lower gap region LR, and can then be removed from the upper gap region UR to a predetermined depth together with the gate dielectric layer 162 and the gate spacer 164. Therefore, a gate structure 160 comprising the gate dielectric layer 162 and the gate electrode 165 can be formed.

[0097] refer to Figure 19A and Figure 19B This can form a front contact 181, an upper passage 183, and a gate contact 185.

[0098] The front contact 181 can be formed by forming a contact hole that penetrates the interlayer insulating layer 170 and extends into the interior of the source / drain region 130, and then forming a metal semiconductor compound layer and a conductive layer.

[0099] Gate contact 185 can be formed on gate structure 160 through interlayer insulating layer 170. Gate contact 185 can be electrically connected to gate electrode 165 of gate structure 160.

[0100] The upper passage 183 can be formed on the front contact 181 through the interlayer insulation layer 170 and can be electrically connected to the front contact 181.

[0101] refer to Figure 20 A front transmission line 215 and a front insulating layer 225 may be partially formed on the interlayer insulating layer 170, the upper passage 183 and the gate contact 185.

[0102] The front transmission lines 215 can be sequentially formed from the bottom, can be formed within the core region CR, and can be electrically connected to the upper pass 183 or the gate contact 185. The front transmission lines 215 can be stacked by alternately forming a first front transmission line 215a extending in a first direction and a second front transmission line 215b extending in a second direction. The front insulating layer 225 can be sequentially stacked at the same height as the front transmission lines 215 and can be formed from multiple layers.

[0103] refer to Figure 21 Front interconnect lines 217 and front inspection lines 219 can be formed to form a front interconnect structure 210, and a front interconnect layer FML can be formed.

[0104] The front connection line 217 can be connected to the front transmission line 215 within the core region CR and can extend to the dummy region DR, and the front check line 219 can be formed in the dummy region DR and can be connected to the front transmission line 215.

[0105] refer to Figure 22A and Figure 22B At least a portion of the substrate 101 can be removed.

[0106] In order to Figure 21 Processing is performed on the lower surface of substrate 101, which may form a separate carrier substrate on the front interconnect layer (FML) and the entire structure may be flipped over to perform the following processes. Substrate 101 may be thinned by removing portions of it (e.g., through grinding, milling, and / or polishing processes). In some example embodiments, the active region 105 and the device isolation layer may also be partially removed. In some example embodiments, substrate 101 and the active region 105 may be completely removed.

[0107] refer to Figure 23 It can form a back contact 191, a rear power rail 193 and a lower blocking structure 195 as components included in the active layer ACL.

[0108] A lower barrier structure 195 penetrating the active region 105 can be formed, and a back contact 191 and a rear power rail 193 can be formed. The lower barrier structure 195 can be formed by forming a hole penetrating the active region 105 and exposing the gate structure 160, and then depositing an insulating material inside the hole. The back contact 191 can be formed by forming a hole penetrating the active region 105 and partially recessed into the source / drain region 130, and then filling the hole with a conductive material. The back contact 191 can be formed in the same or a similar process as the front contact 181. The rear power rail 193 can be formed together with the back contact 191, and can be based on... Figure 23 It is formed by methods such as depositing a conductive material covering the upper surface of the active region 105. Based on Figure 23 The upper surface of the lower blocking structure 195 and the upper surface of the rear electric rail 193 can be formed to form coplanar surfaces through planarization processes such as chemical mechanical polishing (CMP).

[0109] refer to Figure 24 as well as Figure 2B A rear interconnect structure 250 and a rear insulation layer 265 (i.e., back-side insulation layer) can be formed on the rear power rail 193 to form the components included in the rear interconnect layer BML.

[0110] The rear interconnect structure 250 and the rear insulating layer 265 can be formed in the same or similar process as the front interconnect structure 210 and the front insulating layer 225.

[0111] This disclosure is not limited to the embodiments and drawings described above, but is defined by the appended claims. Therefore, those skilled in the art can make various substitutions, modifications, or changes without departing from the scope of this disclosure as defined by the appended claims, and such substitutions, modifications, or changes should be construed as being included within the scope of this disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: An active layer includes a core region and a dummy region surrounding the core region. The active layer includes an active region, a plurality of gate structures, and a plurality of source / drain regions. The active region extends in a first direction and is disposed on both the core region and the dummy region. The plurality of gate structures are disposed on the active region. Each of the plurality of gate structures extends in a second direction and intersects with the active region. The plurality of source / drain regions are disposed on the side surfaces of the plurality of gate structures and are disposed on the active region. A front interconnect layer, the front interconnect layer being disposed on the active layer and including a front interconnect structure and a front insulating layer covering the front interconnect structure; as well as A rear interconnect layer is disposed below the active layer and includes a rear interconnect structure and a rear insulating layer covering the rear interconnect structure. The plurality of gate structures include a plurality of first gate structures disposed on the core region and electrically connected to the front interconnect structure, and a plurality of dummy gate structures disposed on the dummy region and electrically floating. The front interconnect structure includes a first front transmission line disposed on the core region and a first front connection line disposed on the core region and the dummy region. The first front connection line is electrically connected to the first front transmission line and extends from the core region to the dummy region.

2. The semiconductor device according to claim 1, further comprising: A front partition structure is disposed on the dummy area, and the first front connection line is cut into a first front connection line portion connected to the first front transmission line and a second front connection line portion disconnected from the first front transmission line.

3. The semiconductor device according to claim 2, in, When viewed from above, the front partition structure extends along the outer boundary of the core region and surrounds at least a portion of the outer boundary of the core region.

4. The semiconductor device according to claim 1, in, The post-interconnection structure includes a post-transmission line disposed on the core region and a post-connection line disposed on the core region and the dummy region, and The rear connection line is electrically connected to the rear transmission line and extends from the core region to the dummy region.

5. The semiconductor device according to claim 4, further comprising: A front partition structure extends upward in a third direction perpendicular to the first and second directions, and penetrates the front insulating layer and the active layer. The front partition structure divides the first front connector into a first front connector portion connected to the first front transmission line and a second front connector portion disconnected from the first front transmission line. The front partition structure further divides the rear connection line into a first rear connection line portion connected to the rear transmission line and a second rear connection line portion disconnected from the rear transmission line.

6. The semiconductor device according to claim 4, further comprising: A rear partition structure that divides the rear connector into a first rear connector portion connected to the rear transmission line and a second rear connector portion disconnected from the rear transmission line.

7. The semiconductor device according to claim 6, in, The rear partition structure is disposed on the dummy area, and When viewed in a top view, the rear partition structure extends along the outer boundary of the core region and surrounds at least a portion of the outer boundary of the core region.

8. The semiconductor device according to claim 4, further comprising: A front partition structure extends upward in a third direction perpendicular to the first direction and the second direction, and cuts the first front connection line into a first front connection line portion connected to the first front transmission line and a second front connection line portion disconnected from the first front transmission line. as well as A rear partition structure that extends upward on the third party and cuts the rear connection line into a first rear connection line portion connected to the rear transmission line and a second rear connection line portion disconnected from the rear transmission line.

9. The semiconductor device according to claim 8, in, The front partition structure extends into the interior of the active layer by penetrating the front insulating layer, and The rear separation structure extends into the interior of the active layer by penetrating the rear insulating layer.

10. The semiconductor device according to claim 9, in, The rear partition structure contacts the front partition structure and the active layer.

11. The semiconductor device according to claim 1, in, The front interconnect structure also includes: A second front transmission line extends in the second direction and is disposed below the first front transmission line extending in the first direction; and The second front connecting line extends in the second direction. Wherein, the first front connection line extending in the first direction is positioned at the same height as the first front transmission line, and The second front connection line extending in the second direction is positioned at the same height as the second front transmission line.

12. The semiconductor device according to claim 1, in, The active layer further includes: Multiple gate contacts are disposed on the multiple first gate structures and electrically connected to the front interconnect structure; An interlayer insulating layer covering the plurality of source / drain regions, the plurality of gate structures, and the plurality of gate contacts; Multiple back-side contacts, the multiple back-side contacts extending from the bottom surface of the active region through the active region and extending into multiple first source / drain regions disposed on the core region among the multiple source / drain regions; and A rear power rail is disposed below the active area and electrically connects the plurality of back-side contacts to the rear interconnect structure.

13. The semiconductor device according to claim 1, in, The plurality of second source / drain regions disposed in the dummy region among the plurality of source / drain regions are electrically floated.

14. A semiconductor device, the semiconductor device comprising: An active layer, comprising a core region and a virtual region surrounding the core region; Multiple transmission lines are stacked on the core region in a vertical direction perpendicular to the upper surface of the active layer. The multiple transmission lines include multiple first transmission lines and multiple second transmission lines. The multiple first transmission lines extend in a first horizontal direction parallel to the upper surface of the active layer. The multiple second transmission lines are alternately stacked with the multiple first transmission lines and extend in a second horizontal direction parallel to the upper surface of the active layer and intersecting the first horizontal direction. Multiple inspection lines are stacked on the dummy area in the vertical direction. The multiple inspection lines include multiple first inspection lines extending in the first horizontal direction and multiple second inspection lines that are stacked alternately with the multiple first inspection lines and extend in the second horizontal direction. as well as Multiple connecting lines extend from the core area to the dummy area and electrically connect the multiple transmission lines to the multiple inspection lines. The plurality of connecting lines include a plurality of first connecting lines extending in the first horizontal direction and a plurality of second connecting lines extending in the second horizontal direction.

15. The semiconductor device according to claim 14, in, The plurality of first connection lines are connected to the plurality of first transmission lines in the core area, and The plurality of second connecting lines are connected to the plurality of second transmission lines in the core area.

16. The semiconductor device according to claim 14, in, The plurality of first connecting lines are connected to the plurality of first inspection lines in the dummy area, and The plurality of second connecting lines are connected to the plurality of second inspection lines in the dummy area.

17. The semiconductor device of claim 14, further comprising: A partition structure is disposed on the dummy region and extends along the outer boundary of the core region. The separating structure divides each of the plurality of connecting lines into a first portion connected to the corresponding transmission line in the plurality of transmission lines and a second portion disconnected from the corresponding transmission line.

18. A semiconductor device, the semiconductor device comprising: A plurality of gate structures, the plurality of gate structures being spaced apart from each other in a first direction and each of the plurality of gate structures extending in a second direction intersecting the first direction; A plurality of dummy gate structures, the plurality of dummy gate structures being spaced apart from each other in a first direction and each of the plurality of dummy gate structures extending in a second direction; An interlayer insulating layer, the interlayer insulating layer covering the plurality of gate structures and the plurality of dummy gate structures; A front interconnect structure, wherein the front interconnect structure is disposed on the interlayer insulating layer; Multiple gate contacts that penetrate the interlayer insulating layer to electrically connect the multiple gate structures to the front interconnect structure; as well as A rear interconnect structure is disposed below the plurality of gate structures. The front interconnect structure includes: Multiple front transmission lines, each of the multiple front transmission lines including a portion that overlaps with the multiple gate structures in a third upward direction perpendicular to the first direction and the second direction; Multiple front inspection lines, each of the multiple front inspection lines including a portion overlapping with the multiple dummy gate structures in the third direction; and Multiple front connectors connect the multiple front transmission lines to the multiple front inspection lines. Each of the plurality of front connection lines includes a portion overlapping with the plurality of gate structures in the third direction and a portion overlapping with the plurality of dummy gate structures in the third direction. The front interconnect structure is electrically isolated from the plurality of dummy gate structures.

19. The semiconductor device of claim 18, further comprising: A front partition structure that extends upward on the third party and cuts each of the plurality of front connection lines into a first portion connected to a corresponding front transmission line among the plurality of front transmission lines and a second portion disconnected from the corresponding front transmission line.

20. The semiconductor device according to claim 19, in, The front partition structure overlaps with and contacts a portion of the plurality of dummy gate structures in the third direction.

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