Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the method comprises: providing an SOI wafer, the SOI wafer comprising a bottom substrate layer, a buried oxygen layer and a top device layer, the buried oxygen layer being located between the surface of the bottom substrate layer and the surface of the top device layer, and at least exposing the sidewall of the bottom substrate layer; forming a first dielectric layer on the sidewall of the bottom substrate layer, the thermal conductivity of the first dielectric layer being less than that of the bottom substrate layer, which is conducive to improving the pattern alignment accuracy when the top device layer is used to prepare a device, improving the device performance and improving the product yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Silicon on insulator (SOI) is a novel semiconductor silicon material formed by embedding a layer of silicon dioxide, which serves as an insulating layer, within a conventional single-crystal silicon wafer. SOI materials are widely recognized in the industry as one of the solutions to replace existing single-crystal silicon materials in the era of nanotechnology and are a major tool for maintaining Moore's Law.

[0003] Existing SOI wafers are suitable for a wide range of applications in industries such as MEMS, power devices, pressure sensors, and CMOS integrated circuit manufacturing. SOI wafers offer excellent solutions for high-speed and low-power devices and are widely considered a new solution for high-voltage and radio frequency devices. An SOI wafer has a sandwich-like structure with three layers: a top layer (device layer), a middle buried oxide layer (an insulating SiO2 layer), and a bottom substrate (bulk silicon).

[0004] However, the performance of existing SOI wafers still needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: an SOI wafer, the SOI wafer comprising a substrate layer, a buried oxide layer, and a top device layer, the buried oxide layer being located between the substrate layer and the top device layer, and at least exposing the sidewalls of the substrate layer; and a first dielectric layer located on the sidewalls of the substrate layer, the first dielectric layer having a thermal conductivity less than that of the substrate layer.

[0007] Optionally, the first dielectric layer is also formed on the sidewall of the top device layer.

[0008] Optionally, the material of the first dielectric layer includes one or more of silicon oxide, silicon nitride, silicon carbide nitride, silicon carbide nitride, silicon carbide, silicon carbide, and silicon carbide nitride.

[0009] Optionally, the buried oxide layer is located on a first surface of the substrate layer; the substrate layer includes a central region and an edge region surrounding the central region; the buried oxide layer covers the first surface of the central region and also exposes the first surface of the edge region.

[0010] Optionally, the first dielectric layer is also located on the first surface of the edge region.

[0011] Optionally, the substrate layer further includes a second surface opposite to the first surface, and the SOI wafer further includes a back oxide layer located on the second surface; the back oxide layer covers the second surface of the central region and also exposes the second surface of the edge region.

[0012] Optionally, the first dielectric layer is also located on the second surface of the edge region.

[0013] Optionally, it further includes: a second dielectric layer located on the second surface of the edge region, the thermal conductivity of the second dielectric layer being lower than that of the substrate layer; the material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0014] Optionally, the thermal conductivity of the buried oxide layer is less than that of the substrate layer; the thermal conductivity of the first dielectric layer is less than or equal to 100 W / cm·K.

[0015] Accordingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing an SOI wafer, the SOI wafer comprising a substrate layer, a buried oxide layer and a top device layer, the buried oxide layer being located between the surface of the substrate layer and the surface of the top device layer, and exposing at least the sidewalls of the substrate layer; forming a first dielectric layer on the sidewalls of the substrate layer, the thermal conductivity of the first dielectric layer being less than the thermal conductivity of the substrate layer.

[0016] Optionally, the formation process of the first dielectric layer includes a modification process or a chemical vapor deposition process; the modification process includes a thermal oxidation process, a nitriding process, or an ion implantation process.

[0017] Optionally, the formation process of the first dielectric layer includes an ion implantation process. The process parameters of the ion implantation process include: implanted ions include one or more of nitrogen ions, oxygen ions, and carbon ions; the implantation direction is towards the surface of the top device layer, and the angle between the implanted ion and the sidewall of the bottom substrate layer ranges from 1° to 80°; the implantation dose ranges from greater than 1E12 atom / cm. 2 .

[0018] Optionally, a protective layer is formed on the surface of the top device layer before the first dielectric layer is formed; and the protective layer is removed after the first dielectric layer is formed.

[0019] Optionally, the material of the protective layer includes a photoresist material.

[0020] Optionally, it also includes annealing the first dielectric layer.

[0021] Optionally, the process parameters of the annealing process include: a process temperature range of 600℃ to 1300℃ and an annealing time range of 1ms to 60min.

[0022] Optionally, the first dielectric layer is also formed on the sidewall of the top device layer.

[0023] Optionally, the buried oxide layer is located on a first surface of the substrate layer; the substrate layer includes a central region and an edge region surrounding the central region; the buried oxide layer is located on the first surface of the central region and also exposes the first surface of the edge region.

[0024] Optionally, the first dielectric layer is also formed on the first surface of the edge region.

[0025] Optionally, the substrate layer further includes a second surface opposite to the first surface, and the SOI wafer further includes a back oxide layer located on the second surface of the central region and also exposing the second surface of the edge region.

[0026] Optionally, the first dielectric layer is also formed on the second surface of the edge region.

[0027] Optionally, the method further includes: forming a second dielectric layer on the second surface of the edge region, wherein the thermal conductivity of the second dielectric layer is lower than that of the substrate layer.

[0028] Optionally, the process for forming the second dielectric layer includes a modification process or a chemical vapor deposition process; the modification process includes a thermal oxidation process, a nitriding process, or an ion implantation process.

[0029] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0030] In the semiconductor structure formation method provided by the present invention, a first dielectric layer is formed on the sidewall of the substrate layer. The thermal conductivity of the first dielectric layer is less than that of the substrate layer, which reduces the difference in thermal conductivity between the sidewall of the substrate layer and the surface of the substrate layer covered by the buried oxide layer. During the heating and cooling process of high-temperature processing, this helps to reduce the temperature gradient of the substrate layer in the horizontal direction caused by the difference in heat dissipation rate, thereby reducing the probability of defects such as grain boundaries and dislocations at the edge of the substrate layer. This also reduces the problem of distortion and deformation of the top device layer caused by the upward transmission of stress due to such defects, which helps to improve the pattern alignment accuracy when fabricating the device with the top device layer, improve device performance, and improve product yield.

[0031] In the semiconductor structure provided by the present invention, a first dielectric layer located on the sidewall of the substrate has a lower thermal conductivity than the substrate. This reduces the difference in thermal conductivity between the sidewall of the substrate and the surface of the substrate covered by the buried oxide layer. During the heating and cooling process of high-temperature manufacturing, this helps to reduce the temperature gradient of the substrate in the horizontal direction caused by the difference in heat dissipation rate. This reduces the probability of defects such as grain boundaries and dislocations at the edge of the substrate, and reduces the problem of distortion and deformation of the top device layer caused by the upward transmission of stress due to these defects. This also helps to improve the pattern alignment accuracy when fabricating devices using the top device layer, improve device performance, and increase product yield. Attached Figure Description

[0032] Figure 1 and Figure 2 This is a schematic diagram of the structure of an SOI wafer;

[0033] Figures 3 to 6 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0034] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0035] As described in the background section, the performance of SOI wafers produced using existing technologies still needs improvement. This section will now illustrate and analyze this using an SOI wafer as an example.

[0036] Figure 1 and Figure 2 This is a schematic diagram of the structure of an SOI wafer.

[0037] Please refer to Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the three-dimensional structure. Figure 2 for Figure 1 A cross-sectional view along the EE1 direction is shown in the figure. The SOI wafer includes: a bottom substrate layer 100 having a first surface 10a and a second surface 10b opposite to each other; a buried oxide layer 101 located on the first surface 10a; a back oxide layer 102 located on the second surface 10b; and a top silicon layer 103 located on the surface of the buried oxide layer 101.

[0038] In the aforementioned SOI wafer structure, the buried oxide layer 101 and the back oxide layer 102 are made of silicon oxide, while the bottom substrate layer 100 and the top silicon layer 103 are made of silicon. Since silicon oxide has a thermal conductivity of approximately 7.6 W / cm·K, and silicon has a thermal conductivity of approximately 150 W / cm·K, there is a significant difference in their thermal conductivity. During the subsequent high-temperature process's heating and cooling, areas on the surface of the bottom substrate layer 100 covered by the buried oxide layer 101 and areas not covered by the buried oxide layer 101 (e.g.,...) Figure 2 The area marked by the dashed line includes the sidewalls of the substrate layer 100, and the first exposed surface 10a of the buried oxide layer 101 and the second exposed surface 10b of the back oxide layer 102. These areas exhibit differences in heat dissipation rates, resulting in a temperature gradient in the horizontal direction of the substrate layer 100. When this temperature gradient exceeds a certain critical value, defects such as grain boundaries and dislocations will appear at the edge region of the substrate layer 100. The stress caused by these defects propagates upwards, leading to distortion and deformation of the top silicon layer 103. This results in poor pattern overlay performance during subsequent device fabrication on the top silicon layer 103, thus reducing device performance.

[0039] To address the aforementioned issues, this invention provides a semiconductor structure and its formation method, in which a first dielectric layer is formed on the sidewall of the substrate layer. The thermal conductivity of the first dielectric layer is lower than that of the substrate layer, reducing the difference in thermal conductivity between the sidewall of the substrate layer and the surface of the substrate layer covered by the buried oxide layer. During the heating and cooling process of high-temperature manufacturing, this helps to reduce the temperature gradient of the substrate layer in the horizontal direction caused by differences in heat dissipation rates, thereby reducing the probability of defects such as grain boundaries and dislocations at the edges of the substrate layer. This also reduces the problem of stress upward transmission caused by these defects, leading to distortion and deformation of the top device layer. This improves the pattern alignment accuracy when fabricating devices using the top device layer, enhances device performance, and increases product yield.

[0040] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 3 to 6 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0042] Please refer to Figure 3 The SOI wafer is provided, the SOI wafer including a bottom substrate layer 200, a buried oxide layer 201 and a top device layer 202, the buried oxide layer 201 being located between the surface of the bottom substrate layer 200 and the surface of the top device layer 202, and exposing at least the sidewalls of the bottom substrate layer 200.

[0043] In this embodiment, the thermal conductivity of the buried oxide layer 201 is less than that of the substrate layer 200.

[0044] Specifically, the buried oxide layer 201 is located on the first surface 20a of the substrate layer 200.

[0045] In this embodiment, the substrate layer 200 includes a central region (not shown in the figure) and an edge region (not shown in the figure) surrounding the central region; the buried oxide layer 201 covers the first surface 20a of the central region and also exposes the first surface 20a of the edge region. That is, the SOI wafer has a step at the edge of the substrate layer 200.

[0046] In this embodiment, the width d of the edge region is 0.5mm to 3mm.

[0047] In another embodiment, the buried oxide layer 201 may cover the entire first surface 20a.

[0048] In this embodiment, the substrate layer 200 further includes a second surface 20b opposite to the first surface 20a, and the SOI wafer further includes a back oxide layer 203 located on the second surface 20b.

[0049] In this embodiment, the material of the back oxide layer 203 includes silicon oxide.

[0050] Specifically, the back oxide layer 203 covers the second surface 20b of the central region and also exposes the second surface 20b of the edge region.

[0051] In another embodiment, the back oxide layer 203 may cover the entire second surface 20b.

[0052] The buried oxide layer 201 and the substrate layer 200 are subject to stress caused by lattice mismatch, and the back oxide layer 203 is used to balance this stress.

[0053] In other embodiments, the SOI wafer may also not have the back oxide layer 203.

[0054] In this embodiment, the substrate layer 200 is made of silicon, the buried oxide layer 201 is made of silicon oxide, and the top device layer 202 is made of silicon. The device layer is subsequently used to fabricate several devices, such as transistors.

[0055] In this embodiment, the sidewall of the substrate layer 200 is perpendicular to the first surface 20 of the substrate layer 200.

[0056] In another embodiment, the sidewall of the substrate layer and the first surface may have a certain angle, such as an angle ranging from 80 degrees to 110 degrees, that is, the sidewall of the substrate layer and the first surface are nearly perpendicular.

[0057] Subsequently, a first dielectric layer is formed on the sidewall of the substrate 200, wherein the thermal conductivity of the first dielectric layer is lower than that of the substrate.

[0058] In this embodiment, please also refer to Figure 4 Before forming the first dielectric layer, a protective layer 204 is formed on the surface of the top device layer 202.

[0059] In this embodiment, the protective layer 204 is made of photoresist. The protective layer 204 is used to prevent ion implantation onto the surface of the top device layer 202 during the subsequent formation of the first dielectric layer, thus avoiding impact on the performance of subsequent devices. Photoresist is chosen as the protective layer 204 because it is easy to remove later and has minimal impact on the performance of the top device layer 202.

[0060] Please refer to Figure 5 A first dielectric layer 205 is formed on the sidewall of the substrate layer 200, and the thermal conductivity of the first dielectric layer 205 is lower than that of the substrate layer 200.

[0061] Thus, the sidewalls of the substrate layer 200 are covered by the first dielectric layer 205. Since the thermal conductivity of the first dielectric layer 205 is lower than that of the substrate layer 200, the difference in thermal conductivity between the sidewalls of the substrate layer 200 and the surface of the substrate layer 200 covered by the buried oxide layer 201 is reduced. During the heating and cooling process of high-temperature manufacturing, this helps to reduce the temperature gradient of the substrate layer 200 in the horizontal direction caused by the difference in heat dissipation rate. This reduces the probability of defects such as grain boundaries and dislocations appearing at the edges of the substrate layer 200, and reduces the problem of distortion and deformation of the top device layer 202 caused by the upward transmission of stress due to these defects. This helps to improve the pattern alignment accuracy when fabricating devices using the top device layer 202, improve device performance, and increase product yield.

[0062] Preferably, the thermal conductivity of the first dielectric layer 205 is less than or equal to 100 W / cm·K. By selecting this thermal conductivity, a smaller thickness of the first dielectric layer 205 can be used to balance the difference in heat dissipation rate.

[0063] It should be noted that the thickness of the first dielectric layer 205 can be selected based on the difference between its thermal conductivity and that of the substrate 200 and the buried oxide layer 201, thereby reducing the difference in thermal conductivity of the surface coverings of the substrate 200. For example, if the selected thermal conductivity of the first dielectric layer 205 is the same as that of the buried oxide layer 201, the thickness of the first dielectric layer 205 can be the same as the thickness of the buried oxide layer 201. If the selected thermal conductivity of the first dielectric layer 205 is greater than that of the buried oxide layer 201, the thickness of the first dielectric layer 205 can be greater than that of the buried oxide layer 201. Conversely, if the selected thermal conductivity of the first dielectric layer 205 is less than that of the buried oxide layer 201, the thickness of the first dielectric layer 205 can be less than that of the buried oxide layer 201.

[0064] In this embodiment, the first dielectric layer 205 is also formed on the sidewall of the top device layer 202. This further reduces the difference in thermal conductivity of the top device layer 202 due to the surface covering, reduces the difference in heat dissipation during the temperature rise and fall process of high-temperature processes, and further reduces the deformation problems caused to the top device layer 202.

[0065] In another embodiment, the first dielectric layer 205 may not be formed on the sidewall of the top device layer 202.

[0066] In this embodiment, the first dielectric layer 205 is also formed on the first surface 20a of the edge region. This further reduces the difference in thermal conductivity between the exposed surface of the substrate layer 200 and the surface of the substrate layer 200 covered by the buried oxide layer 201, reduces the difference in heat dissipation during the heating and cooling process of high-temperature processes, and further reduces the deformation problem caused to the top device layer 202.

[0067] In another embodiment, the first dielectric layer 205 may not be formed on the first surface 20a in the edge region.

[0068] In this embodiment, the first dielectric layer 205 is also formed on the second surface 20b of the edge region. This further reduces the difference in thermal conductivity between the exposed surface of the substrate layer 200 and the surface of the substrate layer 200 covered by the buried oxide layer 201, reduces the difference in heat dissipation during the heating and cooling process of high-temperature processes, and further reduces the deformation problem caused to the top device layer 202.

[0069] In another embodiment, the first dielectric layer 205 may not be formed on the second surface 20b of the edge region.

[0070] It should be noted that during the process of forming the first dielectric layer, the injection direction is towards the surface of the top device layer 202, that is, the first surface 20a is towards the ion source or reaction source. Since the second surface 20b is opposite to the first surface 20a, the first dielectric layer 205 on the second surface 20b is opposite to the first dielectric layer 205 on the first surface 20a, and its film formation quality is poor.

[0071] In another embodiment, after forming the first dielectric layer, the second surface can be oriented towards an ion source or reaction source to form a second dielectric layer on the second surface in the edge region. The thermal conductivity of the second dielectric layer is lower than that of the substrate layer. The formation process of the second dielectric layer includes a modification process or a chemical vapor deposition process. The modification process includes a thermal oxidation process, a nitriding process, or an ion implantation process. The second dielectric layer is used to reduce the heat dissipation difference on the surface of the substrate layer 200 during the temperature rise and fall processes of high-temperature processes, further reducing the deformation problem caused to the top device layer 202.

[0072] The material of the first dielectric layer 205 includes one or more of silicon oxide, silicon nitride, silicon carbide nitride, silicon carbide nitride, silicon carbide, silicon carbide, and silicon carbide nitride. In this embodiment, the material of the first dielectric layer 205 is silicon oxide.

[0073] The formation process of the first dielectric layer 205 includes a modification process or a chemical vapor deposition process; the modification process includes a thermal oxidation process, a nitriding process or an ion implantation process.

[0074] In this embodiment, the modification process includes an ion implantation process. The process parameters of the ion implantation process include: the implanted ions include one or more of nitrogen ions, oxygen ions, and carbon ions; the implantation direction is towards the surface of the top device layer; the included angle α between the implanted ions and the sidewall of the bottom substrate layer 200 ranges from 1° to 80°; and the implantation dose is greater than 1E12 atom / cm. 2 The reason for choosing the implantation direction here is to ensure that the sidewalls of the substrate layer 200 can be adequately implanted with ions.

[0075] In another embodiment, the process for forming the first dielectric layer 205 includes a thermal oxidation process, and the material of the first dielectric layer 205 formed includes silicon oxide.

[0076] In another embodiment, the process for forming the first dielectric layer 205 includes a nitriding process, and the material of the first dielectric layer 205 includes silicon nitride.

[0077] In another embodiment, the formation process of the first dielectric layer 205 includes a chemical vapor deposition process.

[0078] Please refer to this embodiment as well. Figure 6 After the first dielectric layer 205 is formed, the protective layer 204 is removed (e.g., Figure 5 (As shown).

[0079] In this embodiment, after removing the protective layer 204, the first dielectric layer 205 is further annealed. Here, the annealing process is used to activate oxygen ions.

[0080] In this embodiment, the process parameters of the annealing process include: a process temperature range of 600℃ to 1300℃ and an annealing time range of 1ms to 60min.

[0081] The annealing process can be achieved using either Rapid Thermal Processing (RTP) or furnace tube processing.

[0082] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 6 The semiconductor structure includes: an SOI wafer, the SOI wafer including a bottom substrate layer 200, a buried oxide layer 201 and a top device layer 202, the buried oxide layer 201 being located between the bottom substrate layer 200 and the top device layer 202, and exposing at least the sidewall of the bottom substrate layer 200; and a first dielectric layer 205 located on the sidewall of the bottom substrate layer 200, the first dielectric layer 205 having a lower thermal conductivity than the bottom substrate layer 200.

[0083] Thus, the sidewalls of the substrate layer 200 are covered by the first dielectric layer 205. Since the thermal conductivity of the first dielectric layer 205 is lower than that of the substrate layer 200, the difference in thermal conductivity between the sidewalls of the substrate layer 200 and the surface of the substrate layer 200 covered by the buried oxide layer 201 is reduced. During the heating and cooling process of high-temperature manufacturing, this helps to reduce the temperature gradient of the substrate layer 200 in the horizontal direction caused by the difference in heat dissipation rate. This reduces the probability of defects such as grain boundaries and dislocations appearing at the edges of the substrate layer 200, and reduces the problem of distortion and deformation of the top device layer 202 caused by the upward transmission of stress due to these defects. This helps to improve the pattern alignment accuracy when fabricating devices using the top device layer 202, improve device performance, and increase product yield.

[0084] In this embodiment, the thermal conductivity of the buried oxide layer 201 is less than that of the substrate layer 200.

[0085] In this embodiment, the first dielectric layer 205 is also formed on the sidewall of the top device layer.

[0086] The material of the first dielectric layer 205 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the first dielectric layer 205 is silicon oxide.

[0087] In this embodiment, the buried oxide layer 201 is located on the first surface 20a of the substrate layer 200.

[0088] In this embodiment, the substrate layer 200 includes a central region (not shown in the figure) and an edge region (not shown in the figure) surrounding the central region.

[0089] In this embodiment, the buried oxygen layer 201 covers the first surface 20a of the central region and also exposes the first surface 20a of the edge region.

[0090] In this embodiment, the first dielectric layer 205 is also located on the first surface 20a of the edge region.

[0091] In this embodiment, the substrate layer 200 further includes a second surface 20b opposite to the first surface 20a, and the SOI wafer further includes a back oxide layer 203 located on the second surface 20b.

[0092] In this embodiment, the back oxide layer 203 covers the second surface 20b of the central region and also exposes the second surface 20b of the edge region.

[0093] In another embodiment, the semiconductor structure further includes: a second dielectric layer located on the second surface of the edge region, the thermal conductivity of the second dielectric layer being lower than that of the substrate layer; the material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0094] In this embodiment, the thermal conductivity of the first dielectric layer 205 is less than or equal to 100 W / cm·K.

[0095] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: SOI wafer, the SOI wafer including a bottom substrate layer, a buried oxide layer and a top device layer, the buried oxide layer being located between the bottom substrate layer and the top device layer, and exposing at least the sidewalls of the bottom substrate layer; A first dielectric layer located on the sidewall of the substrate layer, wherein the thermal conductivity of the first dielectric layer is less than that of the substrate layer.

2. The semiconductor structure as described in claim 1, characterized in that, The first dielectric layer is also formed on the sidewall of the top device layer.

3. The semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric layer includes one or more of silicon oxide, silicon nitride, silicon carbide nitride, silicon carbide nitride, silicon carbide, silicon carbide, and silicon carbide nitride.

4. The semiconductor structure as described in claim 1, characterized in that, The buried oxide layer is located on a first surface of the substrate layer; the substrate layer includes a central region and an edge region surrounding the central region; the buried oxide layer covers the first surface of the central region and also exposes the first surface of the edge region.

5. The semiconductor structure as described in claim 4, characterized in that, The first dielectric layer is also located on the first surface of the edge region.

6. The semiconductor structure as described in claim 4, characterized in that, The substrate layer also includes a second surface opposite to the first surface, and the SOI wafer also includes a back oxide layer located on the second surface; the back oxide layer covers the second surface of the central region and also exposes the second surface of the edge region.

7. The semiconductor structure as described in claim 6, characterized in that, The first dielectric layer is also located on the second surface of the edge region.

8. The semiconductor structure as described in claim 6, characterized in that, Also includes: A second dielectric layer located on the second surface of the edge region, wherein the thermal conductivity of the second dielectric layer is lower than that of the substrate layer; The material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

9. The semiconductor structure as described in claim 1, characterized in that, The thermal conductivity of the buried oxide layer is less than that of the substrate layer; the thermal conductivity of the first dielectric layer is less than or equal to 100 W / cm·K.

10. A method for forming a semiconductor structure, characterized in that, include: An SOI wafer is provided, the SOI wafer comprising a substrate layer, a buried oxide layer and a top device layer, the buried oxide layer being located between the surface of the substrate layer and the surface of the top device layer, and exposing at least the sidewalls of the substrate layer; A first dielectric layer is formed on the sidewall of the substrate layer, and the thermal conductivity of the first dielectric layer is less than that of the substrate layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The formation process of the first dielectric layer includes a modification process or a chemical vapor deposition process; the modification process includes a thermal oxidation process, a nitriding process, or an ion implantation process.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The formation process of the first dielectric layer includes an ion implantation process. The process parameters of the ion implantation process include: implanted ions include one or more of nitrogen ions, oxygen ions, and carbon ions; the implantation direction is towards the surface of the top device layer, and the angle between the implanted ion and the sidewall of the bottom substrate layer is in the range of 1° to 80°; the implantation dose is greater than 1E12 atom / cm. 2 .

13. The method for forming a semiconductor structure as described in claim 10, characterized in that, Before forming the first dielectric layer, a protective layer is formed on the surface of the top device layer; after forming the first dielectric layer, the protective layer is removed.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The protective layer is made of photoresist.

15. The method for forming a semiconductor structure as described in claim 10, characterized in that, Also includes: The first dielectric layer is annealed.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The process parameters of the annealing process include: a process temperature range of 600℃ to 1300℃ and an annealing time range of 1ms to 60min.

17. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first dielectric layer is also formed on the sidewall of the top device layer.

18. The method for forming a semiconductor structure as described in claim 10, characterized in that, The buried oxide layer is located on a first surface of the substrate layer; the substrate layer includes a central region and an edge region surrounding the central region; the buried oxide layer is located on the first surface of the central region and also exposes the first surface of the edge region.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The first dielectric layer is also formed on the first surface of the edge region.

20. The method for forming a semiconductor structure as described in claim 18, characterized in that, The substrate layer also includes a second surface opposite to the first surface, and the SOI wafer also includes a back oxide layer located on the second surface of the central region and exposing the second surface of the edge region.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The first dielectric layer is also formed on the second surface of the edge region.

22. The method for forming a semiconductor structure as described in claim 20, characterized in that, The method further includes forming a second dielectric layer on the second surface of the edge region, wherein the thermal conductivity of the second dielectric layer is lower than that of the substrate layer.

23. The method for forming a semiconductor structure as described in claim 22, characterized in that, The process for forming the second dielectric layer includes a modification process or a chemical vapor deposition process; the modification process includes a thermal oxidation process, a nitriding process, or an ion implantation process.

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