Back contact battery and preparation method thereof, photovoltaic module and photovoltaic system

Abstract

The invention relates to the technical field of solar cells, in particular to a back contact cell and a preparation method thereof, a photovoltaic module and a photovoltaic system. The preparation method of the back contact battery comprises the following steps: providing a semiconductor substrate which is provided with a front surface and a back surface which are oppositely arranged; wherein the back surface is provided with first regions and second regions which are alternately distributed, and the first regions are provided with N-type doped silicon layers; a nucleation induction layer and a P-type doped silicon main body layer are sequentially laminated on the second region along a first direction from the front surface to the back surface; and processing the P-type doped silicon main body layer by laser so as to crystallize the P-type doped silicon main body layer. According to the invention, the P-type doped silicon main body layer can be crystallized by adopting relatively low energy, and meanwhile, the damage to a functional layer (a passivation layer) below can be avoided.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a back contact cell and its preparation method, a photovoltaic module, and a photovoltaic system. Background Technology

[0002] Back-contact (BC) solar cells, due to their unobstructed front side grid structure, can achieve ultra-high short-circuit current density, combining aesthetics and high efficiency. They have become a rapidly developing and important technology direction in the field of crystalline silicon solar cells and have received widespread attention from the industry.

[0003] In existing processes, P-type amorphous silicon is commonly used as the hole-selective transport layer. However, this structure leads to a high equivalent series resistance (Rs) in the battery, which is detrimental to improving the fill factor (FF) and conversion efficiency. To reduce Rs, an improved approach can be adopted: first, a thicker P-type doped amorphous silicon layer is deposited, and then it is transformed into microcrystalline silicon with better conductivity using a laser-assisted crystallization process. However, this process faces significant challenges: the laser crystallization process window is extremely narrow, the phase transition from P-type amorphous silicon to microcrystalline silicon is difficult, and the requirements for film quality control are extremely high. Crucially, in hybrid BC battery structures, the intrinsic passivation layer, prepared at low temperatures (180℃~250℃), lies beneath the P-type doped layer. Strict control of process parameters is necessary during laser crystallization to avoid high-temperature damage to the underlying passivation structure. Therefore, in practice, laser energy and scanning conditions are often conservatively set, resulting in the P-type amorphous silicon approximately 5 nm to 10 nm above the intrinsic passivation layer not being fully crystallized and remaining in an amorphous state. The residual amorphous layer has poor conductivity, which limits the further reduction of the overall Rs of the battery, thus becoming an important bottleneck affecting the FF and efficiency improvement.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the Invention

[0005] This application provides a back contact battery and its preparation method, a photovoltaic module, and a photovoltaic system to solve or alleviate one or more of the technical problems mentioned above.

[0006] The first aspect of this application provides a method for preparing a back contact battery, comprising the following steps: A semiconductor substrate is provided, the semiconductor substrate having a front side and a back side disposed opposite to each other; The back side has an alternating first region and a second region. The first region is provided with an N-type doped silicon layer. Along the first direction from the front side to the back side, the second region includes a nucleation induction layer and a P-type doped silicon host layer stacked sequentially. The P-type doped silicon host layer is treated with a laser to crystallize it, thereby forming a crystallized region including microcrystalline silicon.

[0007] In a first aspect of the embodiments of this application, due to the presence of the nucleation induction layer, a lower energy is required to crystallize the P-type doped silicon host layer during laser crystallization, while also avoiding damage to the passivation layer.

[0008] A second aspect of this application provides a back contact battery, including a semiconductor substrate having a front side and a back side disposed opposite to each other; The back side has an alternating first region and a second region. The first region is provided with an N-type doped silicon layer. Along the first direction from the front side to the back side, the second region includes a nucleation induction layer and a P-type doped silicon host layer stacked sequentially. The region of the P-type doped silicon host layer near the nucleation induction layer is a crystallization region, which includes microcrystalline silicon.

[0009] In a second aspect of the embodiments of this application, in this back contact battery, due to the presence of a nucleation induction layer on the passivation layer, the region of the P-type doped silicon main layer near the passivation layer can be a crystallized region that contacts the grains in the nucleation induction layer, further reducing the series resistance R. s .

[0010] A third aspect of this application provides a photovoltaic module, which includes the back-contact cell described in the second aspect. The photovoltaic module provided by this application achieves higher output power, conversion efficiency, and operational reliability by integrating the back-contact cell with low series resistance and high fill factor.

[0011] A fourth aspect of this application discloses a photovoltaic system, which includes the photovoltaic modules described in the third aspect. The photovoltaic system constructed based on these modules has higher power generation, lower levelized cost of electricity (LCOE), and optimized system investment costs, resulting in significantly improved overall performance and economic efficiency. Attached Figure Description

[0012] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0013] Figure 1 This is a schematic diagram of the structure of the back contact battery provided in the embodiments of this application; Figure 2 This is a partial structural diagram of the back side of the back contact battery provided in an embodiment of this application; Figure 3 This is a partial structural diagram of the back side of a back-contact battery provided in another embodiment of this application; Figure 4 yes Figure 3 A magnified view of a portion of the image; Figure 5 This is an energy band diagram at the top of the tower in an embodiment of this application; Figure 6 This is an energy band diagram at the tower base of an embodiment of this application; Figure 7 This is a transmission electron microscope (TEM) image of the tower base location after TCO deposition in step 6 of Example 1. Figure 8 This is a TEM image of the tip edge location of the sample after TCO deposition in step 6 of Example 1.

[0014] Explanation of reference numerals in the attached figures: 100 - Semiconductor substrate; 201 - Tunneling oxide layer; 202 - N-type doped silicon layer; 301 - First passivation layer on the front side; 302 - Second passivation layer on the front side; 303 - Anti-reflection layer on the front side; 401 - Passivation layer; 402 - P-type amorphous layer; 403 - Seed layer; 404 - P-type microcrystalline layer; 405 - P-type doped silicon host layer; 501 - Transparent conductive oxide (TCO) layer; 601 - N-region gate electrode; 602 - P-region gate electrode; A - First region; B - Second region. Detailed Implementation

[0015] The embodiments of this application are described in detail below, with examples of the embodiments illustrated in the accompanying drawings. In the drawings, for clarity, the dimensions of layers, regions, and elements, as well as their relative dimensions, may be exaggerated. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0016] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0017] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0018] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] In this application, when numerical intervals (i.e., numerical ranges) are involved, unless otherwise specified, the distribution of selectable numerical values ​​within the numerical interval is considered continuous, and includes the two endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed in this application should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include percentage intervals, ratio intervals, proportion intervals, etc.

[0020] The following provides a definition of the terminology used in this application.

[0021] In this embodiment, microcrystals refer to the microstructure of the thin film material. It is a mixed phase structure between amorphous silicon (a-Si) and monocrystalline silicon (c-Si). This P-type microcrystalline silicon is composed of countless tiny "silicon grains" with regular crystal structures embedded in the "network framework" of amorphous silicon.

[0022] This application provides a back-contact solar cell and its fabrication method, as well as a photovoltaic module and photovoltaic system technical solution. Based on this, it solves the problem of incomplete crystallization or damage to the underlying passivation layer during laser crystallization of the P-type amorphous silicon in the back-contact solar cell. See below for details.

[0023] Exemplary embodiments according to this application will now be described in more detail with reference to the accompanying drawings. It should be understood that these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0024] The first aspect of this application provides a method for preparing a back contact battery.

[0025] In some embodiments, the preparation method includes the following steps: S1, see also Figure 1 A semiconductor substrate 1 is provided, which has a front side and a back side disposed opposite to each other; in this embodiment, the direction from the front side to the back side is taken as the first direction.

[0026] In some embodiments, a first passivation layer 301, a second passivation layer 302, and an antireflection layer 303 are sequentially stacked on the front side of the semiconductor substrate 1.

[0027] The positive and negative electrodes of the back-contact battery are both located on the back side. In some embodiments, the back side of the semiconductor substrate 1 has an alternately distributed first region A and a second region B, and the first region A is provided with an N-type doped silicon layer; optionally, see [reference needed]. Figure 2 The N-type doped silicon layer includes a tunneling oxide layer 201 and an N-type doped silicon layer 202 sequentially stacked on the first region A, thereby forming a passivated contact structure to achieve selective electron transport.

[0028] In some embodiments, see continue to see Figure 2 Along the first direction, a passivation layer 401, a nucleation induction layer, and a P-type doped silicon host layer 405 are sequentially stacked on the second region B. Thus, due to the presence of the nucleation induction layer, a lower energy is required to crystallize the P-type doped silicon host layer 405 by laser crystallization. At the same time, the reduction in laser energy can avoid damage to the passivation layer 401.

[0029] In some embodiments, along a first direction, at least a portion of the surface of the second region B is lower than the surface of the first region A, forming a groove structure. The groove structure includes a groove bottom surface and groove sides. A laser is used to process the P-type doped silicon host layer 405 located in the groove bottom region to crystallize the P-type doped silicon host layer 405. Thus, while transforming most of the P-type doped silicon host layer 405 from amorphous silicon to microcrystalline silicon, the P-type doped silicon host layer 405 near the first region A remains amorphous silicon. This avoids the leakage problem caused by the high lateral conductivity of the microcrystalline silicon located there, which would rapidly transport holes to the N-type doped silicon layer in the first region A for recombination.

[0030] In some embodiments, see Figure 2 A transparent conductive oxide (TCO) layer 501 is provided on the N-type doped silicon layer 202, and an N-region gate electrode 601 is provided on the transparent conductive oxide layer 501; a transparent conductive oxide layer 501 is provided on the P-type doped silicon body layer 405, and a P-region gate electrode 602 is provided on the transparent conductive oxide layer 501. Thus, both the positive and negative electrodes are located on the back side.

[0031] Optionally, the transparent conductive oxide layer 501 on the P-type doped silicon host layer 405 can be extended to the first region A. In this case, the length of the region to be crystallized in the P-type doped silicon host layer 405 is less than the length of the corresponding transparent conductive oxide layer 501.

[0032] Optionally, the transparent conductive oxide layer 501 on the P-type doped silicon host layer 405 may exist only at the bottom of the groove. In this case, the length of the crystallization region of the P-type doped silicon host layer 405 is equal to the length of the corresponding transparent conductive oxide layer 501.

[0033] In some embodiments, the nucleation-inducing layer includes a seed layer 403 and a P-type microcrystalline layer 404 sequentially stacked along a first aspect. Thus, existing grains can serve as nucleation sites when the P-type doped silicon host layer 405 transforms from amorphous to crystalline, reducing the energy required for crystallization and controlling the energy required for crystallization within a range that does not damage the passivation layer 401. In this way, a highly crystallized P-type doped silicon host layer 405 can be obtained without damaging the passivation layer 401. Specifically, the side of the P-type doped silicon host layer 405 closest to the P-type microcrystalline layer 404 can be crystallized.

[0034] In other embodiments, the nucleation-inducing layer further includes a p-type amorphous layer 402, which is located on the side of the seed layer 403 near the passivation layer 401. Thus, it can serve as a hole-selective transport layer, which can bend the energy bands through heavy doping with boron to block electrons; it can also block subsequent high-energy plasma bombardment, protecting the passivation layer 401 from damage.

[0035] Optionally, the second region B can be a pyramidal textured structure. Laser crystallization of amorphous silicon on a pyramidal textured structure is more difficult than on a planar structure. This is because laser energy is more easily concentrated at the pyramid tip, which may result in the pyramid tip being crystallized while the pyramid base is not fully crystallized or not crystallized at all. Therefore, in this case, the crystallization rate in the P-doped layer at the pyramid tip of the pyramidal textured structure is higher, resulting in larger grains. Meanwhile, smaller grains in the seed layer still exist at the pyramid base in the 3nm to 10nm thickness range adjacent to the passivation layer. The embodiments of this application can optimize the above problems and make the grains more uniform.

[0036] Optionally, PECVD can be used to deposit a P-type amorphous layer, with the ratio of hydrogen to silane during the deposition process being (5-100):1, for example, 5:1, 10:1, 30:1, 50:1, 80:1, 100:1, etc.

[0037] Optionally, the atomic ratio of B to Si in the P-type amorphous 402 thin film is (0.03 to 0.1):1. For example, the atomic ratio of B to Si in the P-type amorphous 402 thin film can be 0.03:1, 0.05:1, 0.08:1, 0.1:1, etc.

[0038] Optionally, the thickness of the p-type amorphous layer 402 is 0.5 nm to 2 nm. For example, it can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, etc.

[0039] In some embodiments, the passivation layer comprises intrinsic amorphous silicon or intrinsic silicon oxide, which has a good passivation effect. However, if high-energy laser crystallization is used, the passivation performance of intrinsic amorphous silicon or intrinsic silicon oxide will be affected. Optionally, the thickness of the passivation layer is 6 nm, 8 nm, 12 nm, 15 nm, etc.

[0040] Optionally, the seed layer is deposited using plasma-enhanced chemical vapor deposition (PECVD) with a hydrogen to silane flow rate ratio of 300–600:1. This extremely high hydrogen to silane flow rate ratio allows for the deposition of a very dense thin layer with an initial microcrystalline structure. The high density effectively prevents the outward diffusion of boron from the p-type doped silicon host layer 405, thus maintaining a high level of band bending. Furthermore, the density of this seed layer promotes the subsequent crystallization of the p-type microcrystalline layer 404. For example, hydrogen to silane flow rate ratios of 300:1, 400:1, 500:1, and 600:1 can be used.

[0041] Optionally, the deposition thickness of the seed layer 403 is precisely controlled between 0.5 nm and 2 nm. For example, it can be 0.5 nm, 0.7 nm, 2 nm, etc.

[0042] Optionally, the P-type microcrystalline layer 404 is formed by plasma-enhanced chemical vapor deposition, with a hydrogen to silane flow rate ratio of (300–500):1 during the deposition process. This facilitates the formation of microcrystalline silicon. For example, the hydrogen to silane flow rate ratio used in the deposition process can be 300:1, 400:1, 500:1, etc.

[0043] Optionally, the thickness of the P-type microcrystalline layer 404 is 5 nm to 10 nm. For example, it can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc.

[0044] Optionally, the seed layer 403 is doped with a P-type element (e.g., B element), and the doping concentration of the P-type element in the seed layer 403 is lower than the doping concentration of the P-type element in the P-type doped silicon host layer 405. The doping concentration of the P-type element in the P-type microcrystalline layer 404 is lower than the doping concentration of the P-type element in the P-type doped silicon host layer 405. That is, the P-type element concentration gradually increases from the seed layer 403 to the P-type microcrystalline layer 404 and then to the P-type doped silicon host layer 405, which can make the upper band bending continuous and gradual, which is beneficial to enhancing carrier transport. For example, the above doping concentration requirements can be achieved by controlling the B source flow rate during the deposition process.

[0045] For example, the B to Si atomic ratio in the seed layer 403 is (0.002 to 0.01):1; the B / Si atomic ratio in the P-type microcrystalline layer 404 is (0.01 to 0.015):1; and the B / Si atomic ratio in the P-type doped silicon host layer 405 is (0.03 to 0.2):1.

[0046] Furthermore, in the first direction, the B-type element in the P-type doped silicon host layer 405 gradually increases in size. Consequently, the bending of the energy band in the valence band is gradual and continuous, which is more conducive to carrier transport.

[0047] S2. The P-type doped silicon host layer is treated with a laser to crystallize the P-type doped silicon host layer 405, thereby forming a crystallization region including microcrystalline silicon. This achieves crystallization of the P-type doped silicon host layer 405 at a lower energy level without damaging the passivation layer 401.

[0048] Optionally, laser processing of the p-type doped silicon host layer 405 includes: The laser used is a short-wavelength pulsed laser with an energy density of 60 mJ / cm². 2 ~300 mJ / cm 2 Therefore, the crystallization degree of the P-type doped silicon host layer 405 can be improved, especially the P-type doped silicon host layer 405 near the passivation layer 401 can also be crystallized, while the passivation performance of the passivation layer 401 will not be damaged by heat.

[0049] It is understood that the crystallization region in this application embodiment is formed by crystallization of the P-type doped silicon host layer 405. Due to the presence of the nucleation induction layer in this application embodiment, nucleation and crystal growth can be induced under laser. When the laser energy is low, the P-type doped silicon host layer 405 near the nucleation induction layer can form a crystallization region.

[0050] Optionally, the wavelength of the short-wavelength laser can be 355nm, 450nm, or 532nm. Therefore, using a short-wavelength laser results in higher photon energy and a very shallow absorption depth, with almost all the energy being absorbed by the surface amorphous silicon, leading to high efficiency and protection of the underlying layer.

[0051] Optionally, the laser spot can be a continuously distributed energy spot. This is beneficial for creating uniform illumination.

[0052] Optionally, the continuous energy distribution spot can be a flat-top spot or a Gaussian spot.

[0053] Preferably, the continuous energy distribution spot is a flat-topped spot. This results in uniform energy distribution, consistent performance across the entire scanned region, and enables uniform crystallization.

[0054] Optionally, the laser scanning speed is 0.1 m / s to 10 m / s; the laser scanning overlap rate is 50% to 95%. Thus, crystallization can be performed while maintaining the scanning speed.

[0055] For example, the scanning speed of the laser can be 0.1 m / s, 1 m / s, 3 m / s, 5 m / s, 8 m / s, 9 m / s, 10 m / s, etc.

[0056] For example, the scanning overlap rate of the laser can be 50%, 60%, 70%, 80%, 95%, etc.

[0057] Optionally, the laser treatment is performed in an inert atmosphere, which is an atmosphere that will not react with the various functional layers of the back-contact battery. For example, it can be a nitrogen atmosphere or a vacuum environment.

[0058] Optionally, the laser pulse width is in the picosecond range. This allows laser energy to be injected and cut off in an extremely short time, resulting in a very shallow thermal diffusion depth. This effectively confines the energy within the P-type layer, greatly protecting the passivation layer. For example, the laser pulse width can range from 1 picosecond to 500 picoseconds. Specifically, it can be 10 picoseconds, 100 picoseconds, 200 picoseconds, 300 picoseconds, 400 picoseconds, 500 picoseconds, etc.

[0059] A second aspect of this application provides a back contact battery, including a semiconductor substrate 100, the semiconductor substrate 100 having a front side and a back side disposed opposite to each other; The back side has an alternating first region A and a second region B. The first region A is provided with an N-type doped silicon layer. Along the first direction from the front side to the back side, the second region includes a nucleation induction layer and a P-type doped silicon host layer 405 stacked sequentially. The region near the nucleation-inducing layer of the P-type doped silicon host layer 405 is a crystallization region, which includes microcrystalline silicon.

[0060] In a second aspect of this application's embodiments, in a back-contact battery, due to the presence of a nucleation induction layer, a crystalline layer containing microcrystalline silicon can be formed in the region of the P-type doped silicon host layer 405 near the passivation layer, and this microcrystalline silicon can connect with the grains within the nucleation induction layer, further reducing the battery's series resistance (R). s ).

[0061] The crystallization region in this application refers to the crystalline silicon layer formed by laser processing of the P-type doped silicon host layer 405, and the crystalline silicon layer is structurally connected to the P-type microcrystalline silicon layer in the nucleation induction layer at the interface.

[0062] In some embodiments, in the back contact battery, the semiconductor substrate 100 corresponding to the second region B has a textured structure. Accordingly, each functional layer (nucleation induction layer and p-type doped silicon host layer 405) deposited on the textured structure of the semiconductor substrate 100 also has a textured structure.

[0063] It is worth noting that in the embodiments of this application, the crystallization region is necessarily located on the side of the P-type doped silicon host layer 405 close to the semiconductor substrate 100, and the thickness h of the crystallization region can be less than or equal to the thickness H of the P-type doped silicon host layer 405.

[0064] Optionally, (H-5nm)≦h≦H. This allows the vast majority of the p-type doped silicon host layer 405 to be a crystallized region.

[0065] Furthermore, the thickness of the p-type doped silicon host layer 405 is 20 nm to 30 nm. For example, the thickness of the p-type doped silicon host layer 405 can be 20 nm, 22 nm, 25 nm, 28 nm, 30 nm, etc. Correspondingly, the thickness h of the crystallized region can be 15 nm, 18 nm, 20 nm, 22 nm, 25 nm, 28 nm, 30 nm, etc.

[0066] Optionally, the textured structure includes a pyramidal textured structure; the crystallized region of the P-type doped silicon host layer 405 covers the apex and at least part of the base of the pyramidal textured structure. This is because laser crystallization is more difficult on pyramidal textured structures than on planar structures within the laser crystallization region. During laser processing, the pyramid apex is more likely to concentrate laser energy, so laser crystallization may only crystallize the pyramid apex on the textured surface, while the base remains uncrystallized. In this embodiment, due to the presence of the nucleation induction layer, the bottom of the base of the P-type doped silicon host layer 405 can also be crystallized, forming a crystallized region of a certain thickness. For example, the thickness of this crystallized region can be 3nm to 8nm. It is understood that crystallized regions of varying thicknesses are also formed on the slope between the base and the apex.

[0067] In some embodiments, in the back contact battery, the nucleation induction layer includes a seed crystal layer 403 and a P-type microcrystalline layer 404 stacked sequentially along a first aspect; thereby, the existing grains can serve as nucleation sites when the P-type doped silicon host layer 405 transforms from amorphous to crystalline, reducing the energy required for crystallization and controlling the energy required for crystallization within a range that does not damage the passivation layer 401, which allows the bottom of the P-type doped silicon host layer 405 to crystallize without damaging the passivation layer 401.

[0068] Optionally, the thickness of the seed layer 403 is 0.5 nm to 2 nm. For example, the thickness of the seed layer 403 can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, etc. Therefore, the presence of the seed layer 403 is beneficial to promoting the rapid crystallization of the subsequent P-type microcrystalline layer.

[0069] Optionally, the thickness of the P-type microcrystalline layer 404 is 5 nm to 10 nm. For example, the thickness of the P-type microcrystalline layer 404 can be 5 nm, 7 nm, 8 nm, 10 nm, etc.

[0070] In other embodiments, the nucleation-inducing layer further includes a p-type amorphous layer 402, which is located on the side of the seed layer 403 near the passivation layer 401. Thus, the p-type amorphous layer 402 can selectively transport holes, bend the energy band by heavy doping with p-type elements (e.g., boron), and block electrons; it can also block subsequent high-energy plasma bombardment, protecting the passivation layer 401 from damage.

[0071] Optionally, the thickness of the seed layer 403 is 0.5 nm to 2 nm. For example, the thickness of the seed layer 403 can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, etc.

[0072] Optionally, the thickness of the P-type microcrystalline layer 404 is 5 nm to 10 nm. For example, the thickness of the P-type microcrystalline layer 404 can be 5 nm, 7 nm, 8 nm, 10 nm, etc.

[0073] Optionally, the thickness of the p-type amorphous layer 402 is 0.5 nm to 2 nm. For example, the p-type amorphous layer 402 can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, etc.

[0074] Furthermore, the seed layer 403 is doped with P-type elements, and the doping concentration of P-type elements in the seed layer 403 is lower than that in the P-type doped silicon host layer 405. The doping concentration of P-type elements in the P-type microcrystalline layer 404 is also lower than that in the P-type doped silicon host layer 405. That is, the P-type element concentration gradually increases from the seed layer 403 to the P-type microcrystalline layer 404 and then to the P-type doped silicon host layer 405, which makes the energy band bending in the valence band continuous and gradual, which is beneficial to enhancing the transport of holes in the valence band.

[0075] In some embodiments, most of the P-type doped silicon host layer 405 has a crystalline region, while the P-type doped silicon host layer 405 near the first region A remains in an amorphous silicon state, that is, the P-type doped silicon host layer 405 near the first region A does not have a crystalline region. While reducing cell series resistance, improving fill factor and conversion efficiency, keeping the P-type doped silicon host layer 405 near the first region A in an amorphous silicon state can prevent short circuits at the contact between the first region A and the second region B.

[0076] For example, see Figure 1 In some embodiments, in the back contact battery, along a first direction, at least a portion of the surface of the second region B is lower than the surface of the first region A, forming a groove structure, the groove structure including a groove bottom surface; the first region A is provided with an N-type doped silicon layer 202; along a first direction from the front to the back of the semiconductor substrate 100, the second region B includes a passivation layer 401, a nucleation induction layer, and a P-type doped silicon host layer 405 stacked sequentially; the passivation layer 401, the nucleation induction layer, and the P-type doped silicon host layer 405 located in the second region B extend to the first region A and cover a portion of the N-type doped silicon layer 202; wherein, the P-type doped silicon host layer 405 located at the bottom surface of the groove is a P-type doped microcrystalline silicon layer, and the remaining P-type doped silicon host layer 405 is a P-type doped amorphous silicon layer.

[0077] In some embodiments, a passivation layer 401 is further provided between the nucleation induction layer and the semiconductor substrate 100 in this back contact battery. Thanks to the inducing effect of the nucleation induction layer on laser crystallization, complete crystallization of the P-type doped silicon host layer 405 can be achieved at significantly reduced laser energy. This protects the passivation layer 401 from high-temperature damage and maintains excellent interface passivation performance.

[0078] Optionally, the passivation layer 401 may include intrinsic amorphous silicon or intrinsic silicon oxide.

[0079] Optionally, the thickness of the passivation layer 401 is 6 nm to 15 nm. For example, the thickness of the passivation layer 401 can be 6 nm, 8 nm, 12 nm, 15 nm, etc.

[0080] See also some examples. Figure 3 and Figure 4As can be seen from the textured structure of the P-type doped silicon host layer 405 in this embodiment, there are crystallized regions on the tip, base, and inclined surface between the tip and base. These crystallized regions are distributed near the nucleation induction layers (seed layer 403 and P-type microcrystalline layer 404). It can also be seen that the crystallized region at the tip almost completely covers the corresponding P-type doped silicon host layer 405, while the crystallized region at the base is thinner, and the thickness of the crystallized region increases from the base to the tip. At the tip, from the first direction, the layers are sequentially: silicon substrate, intrinsic amorphous silicon, P-type microcrystalline silicon (seed layer 403, P-type microcrystalline layer 404, and crystallized region). Figure 5 As shown, the introduction of microcrystals into contact with intrinsic amorphous silicon and the silicon substrate results in greater band bending in the conduction band, which facilitates the bounce of electrons and their passage through holes. At the base of the tower, the layers are sequentially: silicon substrate, intrinsic amorphous silicon, P-type microcrystalline silicon (seed layer 403, P-type microcrystalline layer 404), and a P-type doped amorphous silicon layer, as shown. Figure 6 This study introduces microcrystals that contact the passivation layer 401 and the silicon substrate to form conduction band bends on the conduction band, and analyzes how this facilitates carrier transport.

[0081] In some embodiments, the series resistance R of the back contact battery s The resistance should not exceed 2.0mΩ to 2.6mΩ. This allows for maintaining a low level of series resistance.

[0082] A third aspect of this application provides a photovoltaic module, which includes a back-contact cell as described in the second aspect. The photovoltaic module provided by this application achieves higher output power, conversion efficiency, and operational reliability by integrating a back-contact cell with low series resistance and a high fill factor.

[0083] A fourth aspect of this application discloses a photovoltaic system, which includes the photovoltaic module described in the third aspect. The photovoltaic system constructed based on this module has higher power generation, lower levelized cost of electricity (LCOE), and optimized system investment costs, resulting in significantly improved overall performance and economic efficiency.

[0084] The following section will conduct performance tests on the back contact battery or manufacturing method provided in the embodiments of this application, as well as related comparative examples.

[0085]

Example 1

[0086] 2. Deposition and patterning of the electron transport functional layer on the back side: A tunneling oxide layer 201 with a thickness of approximately 1.2 nm was grown on the back side of an N-type silicon substrate using thermal oxidation. Subsequently, a phosphorus-doped in-situ polycrystalline silicon layer (N-type doped silicon layer 202) with a thickness of 200 nm was deposited at 580 °C using low-pressure chemical vapor deposition (LPCVD). The phosphorus doping concentration was approximately 1 × 10⁻⁶. 19 cm -3 A silicon nitride layer is deposited on the surface of the N-type doped silicon layer 202 as a mask. Then, a laser is used to remove the silicon nitride, N-type polysilicon and tunneling oxide layer in a certain area, thereby forming the P-region. Laser processing residues were cleaned using a diluted hydrofluoric acid solution (HF:H2O = 1:10).

[0087] 3. The front texturing and the back P-area light-trapping structure are formed: Anisotropic etching of the exposed P-regions on the front and back sides of the silicon wafer was performed using a 2% sodium hydroxide (NaOH) solution at 80℃ to form a pyramidal textured structure with a size of 3-5 μm.

[0088] 4. Deposition of front passivation layer and antireflection layer: A 20 nm thick layer of aluminum oxide was first deposited on the front side of the silicon wafer using atomic layer deposition (ALD) as the first passivation layer 301. Then, a 20 nm thick silicon nitride (SiN) layer was prepared using plasma-enhanced chemical vapor deposition (PECVD). x ) as the second passivation layer 302 on the front side and silicon oxynitride (SiN) with a thickness of 70nm x O y ) as the front anti-reflective layer 303.

[0089] 5. Deposition of hole-selective transport layer in the P-region on the back side: 501. Use a 2% hydrofluoric acid (HF) solution at 30°C to clean and remove the front film coated on the back side; 502. P-type functional thin films are sequentially deposited and stacked on the P-region of the back side of the silicon wafer using PECVD technology: a. Deposited passivation layer 401: An intrinsic hydrogenated amorphous silicon layer with a thickness of 8 nm was deposited at 180 °C as passivation layer 401. The reaction gases were silane (SiH4) and hydrogen (H2), and the pressure was 200 Pa. b. Deposition of a P-type amorphous layer 402: A 1 nm thick P-type amorphous layer 402 was deposited. The process gas had a silane flow rate of 1000 sccm, a hydrogen flow rate of 30000 sccm, and a diborane (B2H6, concentration 1% in H2) flow rate of 800 sccm. The deposition pressure was 180 Pa. At this time, the hydrogen to silane flow rate ratio in the gas was 30:1. c. Seed layer 403: A seed crystal layer of 403 with a thickness of about 1.5 nm was deposited. The deposition parameters were as follows: silane 100 sccm, hydrogen 50000 sccm, carbon dioxide (CO2) 10 sccm and methane (CH4) 3 sccm, diborane flow rate 10 sccm, and pressure 250 Pa; at this time, the hydrogen to silane flow rate ratio was 500:1. d. Deposition of P-type microcrystalline layer 404: A 10 nm thick boron-doped microcrystalline silicon layer (P-type microcrystalline layer 404) was deposited with the following parameters: gas composition of silane 100 sccm, hydrogen 40000 sccm, diborane (B2H6, concentration 1% in H2) 30 sccm, and pressure of 300 Pa; at this time, the hydrogen to silane flow ratio was 400:1. e. Deposit P-type doped silicon host layer 405: A 25 nm thick boron-doped amorphous silicon layer, namely the P-type doped silicon host layer 405, was deposited. The initial deposition stage gas composition was 1000 sccm of silane, 50000 sccm of hydrogen, and 1500 sccm of diborane. During the deposition process, the diborane flow rate was linearly increased to 3000 sccm, while the hydrogen flow rate was linearly decreased to 20000 sccm, and the pressure was maintained at 200 Pa.

[0090] 6. Laser crystallization process: Laser scanning was performed on the P-region film stack to achieve crystallization of the P-type doped silicon host layer 405 and its mixing modification with other layers. The laser crystallization parameters were as follows: a 355 nm wavelength ultraviolet laser with a pulse width of 500 ps was used to crystallize the P-region film stack, and the laser energy density was 150 mJ / cm². 2 A flat-top light spot was used, the scanning speed was 2 m / s, and the scanning overlap rate was 85%.

[0091] 7. Backside N-zone opening and TCO deposition: A laser is used to create grooves on the surface of the N-region functional layer on the back side, removing the P-type film stack (P-type amorphous layer 402, seed layer 403, P-type microcrystalline layer 404 and P-type doped silicon host layer 405) and passivation layer 401 covering it, exposing the N-region functional layer, and then removing the residue by wet process.

[0092] A transparent conductive film of indium tin oxide (ITO) with a thickness of 80 nm was deposited on the entire back side at room temperature using physical vapor deposition (PVD) technology.

[0093] 8. Electrode preparation and contact formation: A third patterning process is performed, in which the TCO film at the gate line positions of the N and P regions is removed by laser to form an isolation layer. Then, wet cleaning is performed to remove laser damage.

[0094] Silver paste grid electrodes were printed on the exposed N and P regions by screen printing, and ohmic contacts were formed by sintering at 180°C for 15 minutes.

[0095] 9. Testing Photoinjection annealing was performed, followed by electrical performance testing.

[0096]

Example 2

[0097]

Example 3

[0098]

Example 4

[0099]

Example 5

[0100]

Example 6

[0101]

Example 7

[0102] d. Deposition of P-type doped silicon host layer 405: A 25 nm thick boron-doped amorphous silicon layer was deposited. The initial deposition phase consisted of 1000 sccm of silane, 50000 sccm of hydrogen, and 1500 sccm of diborane. During the deposition process, the diborane flow rate was linearly increased to 3000 sccm while the hydrogen flow rate was linearly decreased to 20000 sccm, and the pressure was maintained at 200 Pa.

[0103]

Example 8

[0104] Comparative Example 1 Everything else is the same as in Example 1, except that step 5 does not deposit the P-type amorphous layer 402, the seed crystal layer 403, or the P-type microcrystalline layer 404, as detailed below: 5. Deposition of hole-selective transport layer in the P-region on the back side 501. Use a 5% potassium hydroxide (KOH) solution at 30°C to clean and remove the front film coated on the back side; 502. P-type functional thin films are sequentially deposited and stacked on the P-region of the back side of the silicon wafer using PECVD technology: a. Deposited passivation layer 401: An intrinsic hydrogenated amorphous silicon layer with a thickness of 8 nm was deposited at 180 °C, with silane (SiH4) and hydrogen (H2) as the reacting gases and a pressure of 200 Pa. b. Depositing the P-type doped silicon host layer 405: A 35 nm thick boron-doped amorphous silicon layer was deposited. The initial deposition phase consisted of 1000 sccm of silane, 50000 sccm of hydrogen, and 1500 sccm of diborane. During the deposition process, the diborane flow rate was linearly increased to 3000 sccm while the hydrogen flow rate was linearly decreased to 20000 sccm, and the pressure was maintained at 200 Pa.

[0105] 6. Laser crystallization process Laser scanning was performed on the P-region film stack to achieve crystallization of the P-type doped silicon host layer 405 and its mixing modification with other layers. The laser crystallization parameters were as follows: a 355 nm wavelength ultraviolet laser with a pulse width of 500 ps was used to crystallize the P-region film stack, and the laser energy density was 150 mJ / cm². 2 A flat-top light spot was used, the scanning speed was 1.5 m / s, and the scanning overlap rate was 85%.

[0106] Comparative Example 2 Everything else is the same as in Example 2, except that step 5 does not involve depositing the P-type amorphous layer 402, the seed crystal layer 403, or the P-type microcrystalline layer 404, and step 6 is as follows: 5. Deposition of hole-selective transport layer in the P-region on the back side 501. Use a 5% potassium hydroxide (KOH) solution at 30°C to clean and remove the front film coated on the back side; 502. P-type functional thin films are sequentially deposited and stacked on the P-region of the back side of the silicon wafer using PECVD technology: a. Deposited passivation layer 401: An intrinsic hydrogenated amorphous silicon layer with a thickness of 8 nm was deposited at 180 °C, with silane (SiH4) and hydrogen (H2) as the reacting gases and a pressure of 200 Pa. b. Depositing the P-type doped silicon host layer 405: A 35 nm thick boron-doped amorphous silicon layer was deposited. The initial deposition phase consisted of 1000 sccm of silane, 50000 sccm of hydrogen, and 1500 sccm of diborane. During the deposition process, the diborane flow rate was linearly increased to 3000 sccm while the hydrogen flow rate was linearly decreased to 20000 sccm, and the pressure was maintained at 200 Pa.

[0107] 6. Laser crystallization process Laser scanning was performed on the p-region film stack to achieve crystallization of the p-type doped silicon host layer 405 and its mixing modification with other layers. The laser crystallization parameters were as follows: a 355 nm ultraviolet laser with a pulse width of 500 ps was used to crystallize the p-region film stack, and the laser energy density was 800 mJ / cm². 2 A flat-top light spot was used, the scanning speed was 1.5 m / s, and the scanning overlap rate was 85%.

[0108] Comparative Example 3 Everything else is the same as in Example 2, except that step 5 does not involve depositing the P-type amorphous layer 402, the seed crystal layer 403, or the P-type microcrystalline layer 404, and crystallization does not occur. Step 6 is also omitted. The details are as follows: 5. Deposition of hole-selective transport layer in the P-region on the back side 501. Use a 5% potassium hydroxide (KOH) solution at 30°C to clean and remove the front film coated on the back side; 502. P-type functional thin films are sequentially deposited and stacked on the P-region of the back side of the silicon wafer using PECVD technology: a. Deposited passivation layer 401: An intrinsic hydrogenated amorphous silicon layer with a thickness of 8 nm was deposited at 180 °C, with silane (SiH4) and hydrogen (H2) as the reacting gases and a pressure of 200 Pa. b. Depositing the P-type doped silicon host layer 405: A 35 nm thick boron-doped amorphous silicon layer was deposited. The initial deposition phase consisted of 1000 sccm of silane, 50000 sccm of hydrogen, and 1500 sccm of diborane. During the deposition process, the diborane flow rate was linearly increased to 3000 sccm while the hydrogen flow rate was linearly decreased to 20000 sccm, and the pressure was maintained at 200 Pa.

[0109] [Test Example] I. The back contact batteries of Examples 1 to 8 and Comparative Examples 1 to 2 were subjected to IV tests under STC conditions, and the data obtained are shown in Table 1.

[0110] The fill factor (FF) used in this article refers to the actual maximum available power (P). m or V mp ×J mp ) and theoretical (not practically obtainable) power (J) sc ×V oc The ratio of FF to V. Therefore, FF can be determined by the following formula: FF = (V mp ×J mp ) / (J sc ×V oc ), where J mp and V mp These represent the points at maximum power (P0) and maximum power (P0). m The current density and voltage at point J were obtained by changing the resistance in the circuit until J×V reached its maximum value; J sc and V oc These represent the short-circuit current and open-circuit voltage, respectively. The fill factor is a key parameter for evaluating solar cells. Commercial solar cells typically have a fill factor of approximately 60% or higher.

[0111] The open-circuit voltage (V) used in this article oc ( ) is the potential difference between the anode and cathode of a device under conditions of no external load connection.

[0112] The short-circuit current (I) used in this article sc) represents the maximum current flowing through a photovoltaic cell or module when the output terminal is short-circuited (voltage V=0) under STC conditions.

[0113] The power conversion efficiency (PCE) of solar cells used in this article refers to the percentage of power converted from absorbed light into electrical energy. The PCE of a solar cell can be measured under standard test conditions (STC) based on incident light irradiance (E: W / m²). 2 ) and the surface area of ​​solar cells (Ac:m 2 The STC is calculated by dividing by the point of maximum power (Pm). STC typically refers to the value at a temperature of 25°C and an irradiance of 1000 W / m². 2 The spectrum of air quality 1.5 (AM1.5).

[0114] 2. Under no light conditions, a forward bias was applied to the back contact batteries of Examples 1-8 and Comparative Examples 1-2, and the current and voltage were measured. Then, the measured dark-state IV curves were fitted, and an ideal diode equation model including series resistance was used to obtain the series resistance (Rs) and parallel resistance (Rsh) of each battery. The series resistance (Rs) and parallel resistance (Rsh) of each battery are also shown in Table 1.

[0115] III. TEM testing was performed on the samples from step 5 of Example 1 after TCO deposition, and on the samples from step 6 of Example 1 after TCO deposition. The results are shown in […]. Figure 3 and Figure 4 .

[0116] Table 1:

[0117] As shown in Table 1 above, Examples 1-5 demonstrate that the series resistance (Rs) is relatively low. This is because the crystallinity within the P-type doped silicon host layer 405 increases with the increase in laser energy. Example 6 shows that when the laser energy is too high, the passivation effect of the passivation layer is affected, resulting in a significant decrease in Rs, but also a decrease in Voc. Comparative Example 1, without a seed layer and a P-type microcrystalline layer, uses the same laser energy as in Example 1. The P-type doped silicon host layer 405 near the passivation layer 401 cannot crystallize, resulting in a higher Rs in the battery, leading to a lower FF and lower conversion efficiency. In Comparative Example 2, increasing the laser energy significantly reduces Rs, but because the passivation layer is damaged, the Voc significantly decreases.

[0118] The data in Table 1 also show that the changes in Voc, Isc, and pseudo-fill factor (pFF) after laser crystallization in Comparative Example 1 are relatively small, basically the same as those in Comparative Example 3 without laser crystallization. Compared with Comparative Example 3, Comparative Example 1 shows a significant decrease in Rs, which is reduced by nearly 40%. This is because laser crystallization affects the P-type doped silicon host layer 405, causing partial crystallization of the P-type doped silicon host layer 405, thus significantly reducing Rs, thereby increasing FF by 0.8% and improving conversion efficiency by 0.2%. In contrast, after laser crystallization of the microcrystalline + amorphous material in Example 1, the changes in Voc, Isc, and pseudo-fill factor (pFF) are relatively small, basically the same as those in Comparative Example 3 without laser crystallization. Compared to the amorphous silicon substrate in Example 1 after laser crystallization, Voc and Isc remained essentially unchanged, while Rs decreased by 0.5 mΩ, leading to further improvements in FF and conversion efficiency. Furthermore, compared to Comparative Example 1 (amorphous silicon without laser crystallization) and Comparative Example 3 (amorphous silicon with laser crystallization), the cell with the superimposed microcrystalline layer in Example 1 exhibited a relatively higher pFF. This is mainly due to the higher hydrogen dilution ratio during nucleation-inducing layer deposition, which injects hydrogen into the passivation layer, resulting in improved passivation performance. Additionally, the stronger band bending between the P-type microcrystalline layer and the n-type silicon substrate in the conduction band facilitates electron bounce and hole passage, thereby reducing interfacial recombination. Moreover, Table 1 shows that the Rsh of the cells in all examples with the superimposed microcrystalline layer decreased to some extent, thus effectively mitigating the hot spot effect of the module.

[0119] See Figure 7 and Figure 8 , Figure 7 This is a TEM image of the pyramid base location after laser crystallization in Example 1. Figure 8 This is a TEM image of the edge of the pyramid tip after laser crystallization in Example 1. Figure 3 It can be seen that after laser crystallization, only microcrystalline grains near the passivation layer still exist at the base of the pyramid. These microcrystalline grains are small in size and distributed closer to the passivation layer, indicating that this structure is formed during thin film deposition. Figure 8 It can be seen that after laser crystallization, microcrystals begin to appear near the TCO position due to the heating effect of the laser, and the microcrystals continue to grow towards the silicon substrate. Therefore, the TEM image shows that the microcrystals are present in the entire P-type doped layer between the passivation layer and the TCO layer. Figure 7 and Figure 8 In comparison, it can be seen that laser crystallization can further increase the number of microcrystals in the P-type doped layer at the top of the tower, thereby increasing the crystallization rate of the P-type doped silicon main layer. There are also grains near the silicon substrate at the base of the tower.

[0120] This application embodiment can also provide a photovoltaic module (not shown), which includes the back contact cell as described above. The back contact cell can be connected in series and / or in parallel with one or more other solar cells in a predetermined manner. Multiple cells can form a cell string, and adjacent cells can be connected together by string welding.

[0121] This application provides a photovoltaic system including the photovoltaic modules described in any of the above embodiments. The advantages of the aforementioned photovoltaic modules are also present in this photovoltaic system, and will not be repeated here. The application fields of the aforementioned photovoltaic system are wide, not limited to photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants, but also including various devices and apparatuses that utilize solar energy for power generation, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy for power generation. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic modules; for example, multiple photovoltaic modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0122] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The directional terms "inner" and "outer" refer to the inside or outside relative to the outline of the component itself. For example, if a device in the drawings is inverted, a device described as "above" or "on top of" other devices or structures will subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0123] It should also be noted that the terms "one embodiment," "another embodiment," and "embodiment" used in this application refer to specific features, structures, or characteristics described in connection with that embodiment, which are included in at least one embodiment described in the general description of this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in connection with any embodiment, the intention is to suggest that implementing such a feature, structure, or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0124] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0125] It should also be noted that the above are merely preferred embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A method for preparing a back contact battery, characterized in that, Includes the following steps: A semiconductor substrate is provided, the semiconductor substrate having a front side and a back side disposed opposite to each other; The back side has an alternating first region and a second region. The first region is provided with an N-type doped silicon layer. Along the first direction from the front side to the back side, the second region includes a nucleation induction layer and a P-type doped silicon host layer stacked sequentially. The P-type doped silicon host layer is treated with a laser to crystallize it, thereby forming a crystallized region including microcrystalline silicon.

2. The method for preparing a back contact battery according to claim 1, characterized in that, Along the first direction, at least a portion of the surface of the second region is lower than the surface of the first region, forming a groove structure, the groove structure including a groove bottom surface; The P-type doped silicon host layer located in the bottom region of the groove is treated with a laser to crystallize the P-type doped silicon host layer.

3. The method for preparing a back contact battery according to claim 1 or 2, characterized in that, The nucleation induction layer includes a seed crystal layer and a P-type microcrystal layer stacked sequentially along the first aspect; The seed crystal layer is formed by plasma-enhanced chemical vapor deposition, and the flow rate ratio of hydrogen to silane used in the deposition process is (300-600):1; and / or The thickness of the seed crystal layer is 0.5 nm to 2 nm; and / or The P-type microcrystalline layer is formed by plasma-enhanced chemical vapor deposition, and the flow rate ratio of hydrogen to silane used in the deposition process is (300-500):1; and / or The thickness of the P-type microcrystalline layer is 5 nm to 10 nm.

4. The method for preparing a back contact battery according to claim 3, characterized in that, The seed layer is doped with P-type elements, and the doping concentration of the P-type elements in the seed layer is less than the doping concentration of the P-type elements in the P-type doped silicon host layer; and / or The doping concentration of P-type elements in the P-type microcrystalline layer is less than that in the P-type doped silicon host layer.

5. The method for preparing a back contact battery according to claim 3, characterized in that, The nucleation induction layer includes a P-type amorphous layer, a seed crystal layer, and a P-type microcrystalline layer sequentially stacked in a first direction; The thickness of the P-type amorphous layer is 0.5 nm to 2 nm.

6. The method for preparing a back contact battery according to claim 1 or 2, characterized in that, The laser processing of the P-type doped silicon host layer includes: The laser used is a short-wavelength pulsed laser with an energy density of 60 mJ / cm². 2 ~300 mJ / cm 2 .

7. The method for preparing a back contact battery according to claim 6, characterized in that, The laser processing satisfies at least one of the following conditions (1) to (3): (1) The laser spot is a continuous energy distribution spot, and the scanning overlap rate of the laser is 50% to 95%; (2) The laser treatment is performed in an inert atmosphere; (3) The scanning speed of the laser is 0.1 m / s to 10 m / s.

8. The method for preparing a back contact battery according to claim 7, characterized in that, The continuous energy distribution light spot is a flat-top light spot or a Gaussian light spot; The short-wavelength laser has a wavelength of 355nm, 450nm, or 532nm; The pulse width of the laser is in the picosecond to nanosecond range; The pulse width of the laser is 1 picosecond to 500 picoseconds.

9. The method for preparing a back contact battery according to claim 1 or 2, characterized in that, A passivation layer is further provided between the nucleation induction layer and the semiconductor substrate; The passivation layer comprises intrinsic amorphous silicon or intrinsic silicon oxide; The thickness of the passivation layer is 6 nm to 15 nm.

10. The method for preparing a back contact battery according to claim 1 or 2, characterized in that, The second area has a pyramid-shaped velvet surface structure.

11. A back-contact battery, characterized in that, Includes a semiconductor substrate having a front side and a back side disposed opposite to each other; The back side has an alternating first region and a second region. The first region is provided with an N-type doped silicon layer. Along the first direction from the front side to the back side, the second region includes a nucleation induction layer and a P-type doped silicon host layer stacked sequentially. The region of the P-type doped silicon host layer near the nucleation induction layer is a crystallization region, which includes microcrystalline silicon.

12. The back contact battery according to claim 11, characterized in that, The semiconductor substrate, the nucleation induction layer, and the P-type doped silicon host layer corresponding to the second region all have a textured structure.

13. The back contact battery according to claim 12, characterized in that, The velvet structure includes a pyramid-shaped velvet structure; The crystallized region of the P-type doped silicon host layer covers the apex and at least part of the base of the pyramid-shaped textured structure.

14. The back contact battery according to claim 11, 12 or 13, characterized in that, The thickness of the crystallized region is h, and the thickness of the P-type doped silicon host layer is H. The thickness of the crystallized region h satisfies: (H-5nm)≦h≦H.

15. The back contact battery according to claim 11, characterized in that, The nucleation induction layer includes a seed crystal layer and a P-type microcrystal layer stacked sequentially along the first direction; The thickness of the seed crystal layer is 0.5 nm to 2 nm; and / or The thickness of the P-type microcrystalline layer is 5 nm to 10 nm.

16. The back contact battery according to claim 11, characterized in that, The nucleation induction layer includes a P-type amorphous layer, a seed crystal layer, and a P-type microcrystalline layer that are sequentially stacked along the first direction; The thickness of the seed crystal layer is 0.5 nm to 2 nm; and / or The thickness of the P-type microcrystalline layer is 5 nm to 10 nm; and / or The thickness of the P-type amorphous layer is 0.5 nm to 2 nm.

17. The back contact battery according to claim 15 or 16, characterized in that, The seed layer is doped with P-type elements, and the doping concentration of the P-type elements in the seed layer is less than the doping concentration of the P-type elements in the P-type doped silicon host layer; and / or The doping concentration of P-type elements in the P-type microcrystalline layer is less than that in the P-type doped silicon host layer.

18. The back contact battery according to claim 11, 12, 13, 15 or 16, characterized in that, Along the first direction, at least a portion of the surface of the second region is lower than the surface of the first region, forming a groove structure, the groove structure including a groove bottom surface; The nucleation induction layer and the P-type doped silicon host layer located in the second region extend to the first region and cover a portion of the N-type doped silicon layer; The P-type doped silicon host layer located in the bottom region of the groove has the crystallization region, and the remaining P-type doped silicon host layer is a P-type doped amorphous silicon layer.

19. The back contact battery according to claim 11, 12, 13, 15 or 16, characterized in that, A passivation layer is further provided between the nucleation induction layer and the semiconductor substrate; The passivation layer comprises intrinsic amorphous silicon or intrinsic silicon oxide; The thickness of the passivation layer is 6 nm to 15 nm.

20. The back contact battery according to claim 11, 12, 13, 15 or 16, characterized in that, The series resistance R of the battery s Not higher than 2.0mΩ~2.6mΩ.

21. A photovoltaic module, characterized in that, The photovoltaic module includes a back contact cell prepared by the preparation method according to any one of claims 1 to 10 or a back contact cell according to any one of claims 11 to 20.

22. A photovoltaic system, characterized in that, The photovoltaic system includes the photovoltaic module as described in claim 21.

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