Semiconductor device with deterioration detection capability

Abstract

The invention relates to a semiconductor device with degradation detection capability. A semiconductor device having a power transistor is described herein. In one embodiment, a power transistor is composed of a plurality of transistor cells arranged in a cell array, where the plurality of transistor cells includes a first transistor cell arranged in a first portion of the cell array and a second transistor cell arranged in a second portion of the cell array. The semiconductor device also includes: a metallization layer forming a source electrode of the power transistor; a first bonding wire having an end piece bonded to a first portion of the metallization layer covering the first portion of the cell array; and a second bonding wire having an end piece bonded to a second portion of the metallization layer covering the second portion of the cell array. The end piece of the second bonding wire has a larger volume than the end piece of the first bonding wire.

Description

Technical Field

[0001] This specification relates to semiconductor devices with power transistors and degradation detection capabilities. Background Technology

[0002] One concept frequently associated with current measurement in power transistors involves the use of so-called sensing transistors. Power transistors (such as DMOS transistors) typically consist of multiple transistor cells (transistor cell arrays) connected in parallel. However, some transistor cells in the cell array form separate transistors (sensing transistors). Sensing transistors can operate at approximately the same operating point as power transistors, but have a much smaller effective area. Therefore, the current flowing through the power transistor and the sensing transistor is approximately proportional in this arrangement, where the scaling factor K (at least theoretically) corresponds to the ratio of the effective areas of the two transistors. That is, the effective area of ​​the sensing transistor is K times smaller than the effective area of ​​the power transistor.

[0003] During operation, semiconductor chips, including power transistors, can be exposed to varying thermal loads, which can lead to degradation and eventually failure over time. There are concepts of performing so-called "health checks" on semiconductor chips using integrated circuit devices. However, these concepts are often limited to specific applications or problems are not identified until it is too late to ensure reliable continuation of operation (failed operation). Summary of the Invention

[0004] This document describes a semiconductor device having a power transistor. In one embodiment, the power transistor comprises a plurality of transistor cells arranged in a cell array, wherein the plurality of transistor cells include a first transistor cell and a second transistor cell, the first transistor cell being arranged in a first portion of the cell array and the second transistor cell being arranged in a second portion of the cell array. The semiconductor device further includes: a metallization layer forming the source electrode of the power transistor; a first bonding wire having a terminal attached to the first portion of the metallization layer, the first portion of the metallization layer covering the first portion of the cell array; and a second bonding wire having a terminal attached to the second portion of the metallization layer, the second portion of the metallization layer covering the second portion of the cell array. The terminal of the second bonding wire has a larger volume than the terminal of the first bonding wire.

[0005] Furthermore, a method for operating a wireless device is described herein. In one embodiment, the method includes: detecting whether a resistor formed by a portion of a metallization layer and arranged in series with the load current path of a power transistor has changed by a specific amount; and deactivating at least a portion of a second transistor cell when the resistance has been detected to have changed by the specific amount. Attached Figure Description

[0006] The exemplary embodiments will now be explained in more detail with reference to the accompanying drawings. The drawings are not necessarily drawn to scale, and the exemplary embodiments are not limited to the aspects illustrated only. Rather, it is important to explain the principles upon which the exemplary embodiments are based. Regarding the drawings:

[0007] Figure 1 The illustration shows an example of a current measurement circuit that uses a sensing transistor to measure current.

[0008] Figure 2 An additional diagram illustrating the resistance of the chip's metallization is shown. Figure 1 Examples;

[0009] Figure 3 These are images of the semiconductor chip surface recorded using a microscope. Figure 2 The circuitry is integrated into the semiconductor chip;

[0010] Figure 4 It is a schematic cross-sectional diagram of a semiconductor chip;

[0011] Figure 5 The diagram illustrates a circuit according to a first exemplary embodiment, wherein different bonding lines are used to contact different locations of the chip metallization layer.

[0012] Figure 6 An example of a wire bonding interconnect is illustrated, wherein the bonding lead has an end piece with an enlarged volume and therefore an enlarged heat capacity to better cool adjacent portions of the metallization layer.

[0013] Figure 7 The diagram illustrates the relationship between... Figure 6 An alternative to the traditional joint line design, offering a similar effect.

[0014] Figure 8 The illustration shows a conventional wire bonding interconnect formed, for example, by a wedge bonding process.

[0015] Figure 9 The diagram illustrates a circuit with additional detection. Figure 2 The additional detection circuit is configured to detect degradation of the chip metallization layer by detecting an increased voltage across a specific portion of the chip metallization layer.

[0016] Figure 10 The diagram illustrates a circuit included in a semiconductor device for deactivating some transistor cells that form a cell array of power transistors.

[0017] Figure 11 An example of a system including a microcontroller and semiconductor devices according to one of the embodiments described herein is illustrated.

[0018] Figure 12 A flowchart illustrating an embodiment of a method for operating a semiconductor device is shown. Detailed Implementation

[0019] Figure 1 An exemplary embodiment of a current measurement circuit including a sensing transistor is shown. In the depicted example, the electrical load R LOAD Through power transistor T L Switching is performed in a manner that allows current to flow through power transistor T. L And therefore, it also flows through the load R LOAD The current is from i LOAD Indicator. Power transistor T L It can be like Figure 1 The high-side switch is shown. That is, the power transistor T... L The main current path (drain-source current path in the case of a MOS transistor) is connected between the power supply terminal VS and the output (output pin OUT), and the load R LOAD It can be connected to this output. It should be understood that this disclosure is not limited to high-side transistors. The concepts described herein can be readily applied to circuits with low-side switches.

[0020] Including sensing transistor T S The current sensing circuit is coupled to the power transistor T L The current sensing circuit is configured to provide a measurement current i0, which represents the current through the power transistor T. L Load current i LOAD As described in the invention, the sensing current i0 and the load current i LOAD Approximately proportional, i.e., i0 = i LOAD / K (scale factor K). For current measurement, transistor T S and T L They must have the same (or at least similar) characteristics and operate (approximately) at the same operating point. Therefore, two transistors T... L and T S The gate electrodes are connected to each other. The drain electrodes are connected in the same way. Furthermore, in a high-side arrangement, transistor T... L and T S The drain electrode is connected to the power supply terminal VS, at which a power supply voltage V exists during operation. S .

[0021] In order to make transistor T L and T S They all operate at the same operating point, transistor T L and T SThe drain-source voltages at the point should be the same. In the depicted embodiment, this is achieved by means of an operational amplifier OA and an additional transistor T0, which together ensure that the sensing transistor T0... S The source voltage at point T is adjusted to match that of the power transistor T. L The source voltage at that point is the same value. It should be noted that an operational amplifier is not necessary. This is to ensure that the measured current i0 is the same as the load current i. LOAD The approximate ratio between these values, as well as other concepts, exist. Specific implementation methods will depend on the application requirements.

[0022] exist Figure 1 In the example, sensing transistor T S It is connected in series with another transistor T0 (i.e., their main current path) so that the same measuring current i0 flows through both transistors (T0 and T0). S (and T0). In the depicted example, transistor T0 is a p-channel MOS transistor, while transistor T... S and T L It is an n-channel MOS transistor. The gate of transistor T0 is driven by the output signal of operational amplifier OA, where the input of operational amplifier OA is coupled to transistor T0. S and T L The source electrode. It should be understood that a p-channel transistor can also be used as a power transistor (and a sensing transistor) to construct a similar circuit.

[0023] Operational amplifier OA and transistor T0 together form the feedback loop. The inverting input of operational amplifier OA is connected to sensing transistor T0. S The source electrode of the operational amplifier OA is connected to the non-inverting input of the power transistor T. L The source electrode. If the sensing transistor T S The source voltage at the point is less than that of the power transistor T. L If the source voltage at transistor T0 is increased, the output voltage of operational amplifier OA will rise. As a result, the gate-source voltage at transistor T0 becomes smaller, which increases the on-resistance of transistor T0. This increased on-resistance, in turn, increases the on-resistance of sensing transistor T0. S The source voltage at the point increases. Therefore, the feedback loop of operational amplifier OA is stable, and thus, operational amplifier OA drives transistor T0, causing transistor T... L and T S The voltages at the source electrodes are essentially equal (i.e., compensating for the difference in drain-source voltages between the power transistor and the sensing transistor). Therefore, the sensing transistor and the power transistor operate at essentially the same operating point.

[0024] exist Figure 1In the example, the sensed current i0 is output at the sense pin IS, and the output current at pin IS is labeled as i S (in this example i) S =i0). Sensing resistor R S It can be connected to the sensing pin IS. The sensing resistor RS is typically connected between the sensing pin IS and a reference voltage (e.g., ground potential, 0V). The resulting voltage V at the sensing pin IS is... IS Then it equals the current i S With resistance R S The product (V) IS =R S ·i S =i LOAD ·R S / K).

[0025] Figure 2 The diagram illustrates the relationship with Figure 1 The circuits are identical, the only difference being the resistor R. MET Arranged on power transistor T L The resistor R is located between the source electrode and the output pin OUT. MET (Especially) formed from chip metallization, and therefore can be considered as parasitic resistance. In fact, the resistance R... MET It can be decomposed into two resistors (R) MET1 and R MET2 These two resistors form a voltage divider, with the non-inverting input of operational amplifier OA connected to the middle tap of the divider. Interconnecting resistors (e.g., vias or plated vias connecting different metallization layers) also act as resistors to these resistors R. MET1 and / or R MET2 It makes a contribution. Resistor R MET It is lateral resistance, meaning that the current through these resistors flows essentially laterally (i.e., essentially parallel to the chip surface), while transistor T... L and T S It can be a vertical transistor (see also) Figure 4 The current flows through the transistor array in a direction that is essentially "from top to bottom" and is perpendicular to the chip surface.

[0026] Figure 3 The images shown are taken using a microscope and include Figure 2 A magnified image (photograph) of the semiconductor chip 100 of the circuit. The image of the semiconductor chip 100 shows the chip metallization 101 covering most of the chip surface. Furthermore, Figure 3 The diagram illustrates the contact position 102 of the bonding wire used to connect the chip metallization 101 to the output pin OUT of the chip 100. Figure 3The output pin OUT itself is not visible because it is typically placed on the lead frame on which the chip 100 is mounted.

[0027] also, Figure 3 The diagram illustrates circuit section 150, which includes drive and operating power transistors T. L And the main part of the circuit required for current measurement via a sensing transistor. As mentioned above, the power and sensing transistors can be implemented as vertical transistors and formed by multiple transistor cells in a cell array. In the case of a vertical transistor, the drain-source current path starts from the top side of the semiconductor chip (in... Figure 3 (As can be seen) it extends through the chip to the bottom side of the chip. Figure 3 In the example depicted, transistor T is formed. S and T L The chip metallization of the drain electrode is located on the bottom side of the chip, while the chip metallization 101 of the source electrode is arranged on the top side.

[0028] resistor R MET A schematic diagram is superimposed on an image of semiconductor chip 100. At this point, it is important to understand the resistance R. MET It is not a specific circuit component implemented at a particular location (local). Instead, the resistance extends in the lateral direction and is distributed over the entire chip metallization 101 (depending on what current density field is formed in the metallization during operation).

[0029] Chip metallide 101 can be located in multiple positions (e.g., in R...) MET1 With R MET2 See the nodes between. Figure 2 ) is contacted (tap). In Figure 3 In the example shown, the resistor R MET One contact is located directly near one of the chip contact locations 102, and the other contact is located around the circuit section 150, where, for example, an operational amplifier OA is also arranged. It can be understood that the voltage divider R... MET1 R MET2 This is a simplified model based on reality. The thickness of the chip metallization layer can range from approximately 2 to 50 μm.

[0030] Chip contact locations 102 are, for example, locations where bonding wires (e.g., via wire bonding processes) are connected to the chip metallization. In other exemplary embodiments, jigs, strips (strip bonding), etc., may be used instead of bonding wires. The geometry of chip contact locations 102 may vary depending on the bonding technology used.

[0031] The chip metallide 101 can be contacted at multiple locations. Figure 3In the illustrated example, another contact (on the left) is shown around circuit section 150. Resistor R can then be... MET (Based on the modeling) it can be viewed as two resistors connected in parallel. Then, the resistance value R MET This represents the average value of different local current paths through the chip metallization 101.

[0032] As already mentioned, the semiconductor chip and the chip metallization 101 undergo multiple temperature cycles during integrated circuit operation. The temperature can fluctuate more or less regularly between room temperature and, for example, 300°C or higher. Temperature fluctuations exceeding 200°C are not unusual. These fluctuations can gradually lead to microcracks 110 in the chip metallization 101, and an increase in the resistance value R. MET The increase is due to the increasing number of microcracks. The study (by detecting the resistance value R) MET It has been shown that for the resistance value R MET Specific changes in resistance (e.g., an increase of 200%) increase the likelihood of semiconductor chip failure. Therefore, monitoring the resistance value R... MET This allows for the prediction of when a semiconductor chip is nearing the end of its lifespan before it actually fails. In safety-critical applications, such as certain components of autonomous vehicles, this prediction can be a key advantage in preventing greater damage.

[0033] Further research has shown that the mentioned predictions (based on R) are accurate. MET Monitoring of this resistance (in ohms) is feasible for power transistors with very low on-resistance. However, for power transistors with medium or relatively high on-resistance, due to the relatively high resistance R... MET The concept is not feasible because the relative change in voltage is relatively small (and therefore the corresponding relative change in voltage is small).

[0034] Finally, it should be noted that the resistance R MET Changes also affect the sensing current i0 and the load current i LOAD The proportionality factor K between them. This is in Figure 2 The answer is obvious. If the resistance R MET Due to defects such as microcracks and delamination, the voltage at the non-inverting input of operational amplifier OA will also change. Therefore, operational amplifier OA cannot guarantee the voltage at transistor T. S and T L Equal source voltages at the location.

[0035] Figure 4 yes Figure 3 A schematic cross-sectional view of a semiconductor chip. It should be understood that... Figure 4This is not drawn to scale and includes only aspects necessary for understanding the exemplary embodiments discussed below. The structure of this semiconductor chip is known to those skilled in the art.

[0036] exist Figure 4 The left-hand side schematically illustrates an array of transistor cells integrated in a semiconductor chip 100. Examples depicted include vertical DMOS transistors. S and T L The drain electrode is formed by metallization 102 on the bottom side of the chip. The source electrode is formed by metallization 101 on the top side of the chip 100. The bottom-side metallization is mounted on the lead frame, for example, via a die-bonding process. The top-side metallization 101 is connected to the chip pin OUT of the lead frame, for example, via a wire bonding process (bonding wire 120). The resistance of the metallization 101 is given by resistor R. MET Reference (see also) Figure 3 The majority of the circuit section 150, which contains other circuit components, is located in... Figure 4 The right-hand side. The resistor R formed by the chip metallization 101. MET Specifically, it is made of power transistor T L During operation, metallization is exposed to heat load and deteriorates due to this (cyclic) heat load, resulting in the formation of metallization fractions.

[0037] The embodiments described herein are designed such that the metallization layer 101 has a targeted fracture point. This allows for the deactivation of the affected portion of the cell array when an actual defect is detected. Defects typically occur near the location where the metallization layer is joined by a bonding line, where thermal loads induce (thermo)mechanical stress and strain, which in turn can lead to the aforementioned defects (such as cracks, delamination, etc.). At this point, it is important to understand that it is the temperature gradient (i.e., the temperature difference between two nearby points) rather than temperature that causes the mechanical stress.

[0038] According to the embodiments discussed herein, the aforementioned target break points (with areas larger than points) are achieved by designing specific bonding contacts such that the temperature gradient near these contacts is higher than that at other bonding contacts. If defects occur during the operation of a semiconductor chip, they will first appear at (or near) these specific bonding contacts. Such defects can be detected (e.g., by detecting the scaling factor K = i). LOAD (Sudden change in / i0) can deactivate the affected portion of the load transistor (i.e., the affected transistor cell) and signal an error while the power transistor itself remains functional.

[0039] Figure 5An embodiment of a semiconductor device is illustrated. The device includes a semiconductor chip 100, in which a power transistor T is integrated. L A power transistor can be composed of multiple transistor cells arranged in a cell array. According to the depicted example, the multiple transistor cells can be subdivided into a first transistor cell (labeled TL') arranged in a first portion of the cell array and a second transistor cell (labeled TL'') arranged in a second portion of the cell array. A metallization layer 101 forms the source electrode of the power transistor composed of the first and second transistor cells.

[0040] Multiple bonding lines are bonded to the metallization layer 101. More specifically, bonding line 120, having end piece 120a, is bonded to a first portion of the metallization layer 101, which covers a first portion of the cell array, and bonding line 122, having end piece 122a, is bonded to a second portion of the metallization layer 101, which covers a second portion of the cell array. The second portion of the cell array may be only a small part of the entire cell array.

[0041] The end piece 122a of the second bonding wire 122 has a larger volume than the end piece 120a of the first bonding wire 120. That is, two different types of bonding wires are used, where the two types of bonding wires are substantially different in the shape (geometry) of their end pieces. The larger volume of the end piece 122a of the bonding wire 122 (compared to the end piece of the bonding wire 120) generally results in a larger contact area. The contact area of ​​the bonding wire is determined by… Figure 5 The figure is illustrated by the gray shaded ellipse. As can be seen from the figure, the contact area between the bonding line 122 and the metallization layer 101 is significantly larger than the contact area between the bonding line 12 and the metallization layer 101.

[0042] Due to its larger end piece volume, the end piece 122a of the bonding wire 122 has a higher heat capacity than the end piece 120a of the first bonding wire 120 (which, for a given material, could be, for example, copper or aluminum). The higher heat capacity and / or larger contact area of ​​the end piece 122a results in better localized cooling of the metallization layer 101 in the immediate vicinity of the respective bonding wire 122, while cooling efficiency is lower near other types of bonding wires (bonding wires 120). This better localized cooling leads to a higher temperature gradient. This results in higher thermomechanical stress, and the defects in the metallization layer 101 discussed above will first occur near the bonding line 122.

[0043] Figure 6 This is a cross-sectional view of semiconductor die 100 (cross-section A, see...). Figure 5 The block extends through the second segment T of the cell array. L '.according to Figure 6 The end piece 122a of the bonding wire contacts the metallization layer 101 along a relatively long length, such that the contact area of ​​the end piece 122a of the bonding wire 122 physically contacting the metallization layer 101 is relatively large (e.g., larger than that of a conventional wedge bonding interconnect, see...). Figure 8 ). Figure 7 An alternative embodiment is illustrated. In this example, the end piece 122a of the bonding line 122 is significantly thicker than the rest of the bonding line, which also results in an increased contact area between the end piece 122a and the metallization layer 101.

[0044] Figure 8 This is a cross-sectional view of semiconductor die 100 (cross-section B, see...). Figure 5 In this example, a conventional wire connection (a connection wire 120 with a small end piece 120a) is shown. When... Figure 8 and Figure 6 When comparing with 7, it can be seen that, Figure 8 In the middle, the contact area (where the middle component 120a physically contacts the metallization layer 101) is greater than that of the middle component 120a. Figure 6 and 7 The example is much smaller. Therefore, the volume of end piece 120a is smaller than the volume of end piece 122a. Furthermore, the joining line 120 ( Figure 8 The thermal resistance between the metallization layer 101 and the bonding line 122 is higher than that between the bonding line 122 and the metallization layer 101. Figure 6 and 7 The thermal resistance between the semiconductor chip 100 and the metallization layer 101 is reduced. Therefore, cooling of the semiconductor chip 100 via the bonding line 122 is better than cooling of the semiconductor chip 100 via the bonding line 120, and consequently, a higher temperature gradient can occur near the bonding line 122. The temperature gradient near the junction line 120 Lower. Therefore, as mentioned above, during device operation (including cyclic thermal loads), defects will first appear near the junction line 122. Figure 6 Or 7).

[0045] Figure 8 The wire joint shown in the example can be formed using a wedge joint process. Figure 7 The line joint shown in the example can be formed using a ball joint process. Figure 6 The wire bonding shown in the example may require specially adapted bonding tools. Wire bonding is a well-known process, and those skilled in the art will be able to modify / optimize bonding tools to achieve wire bonding with the desired geometry.

[0046] Defects (such as delamination of the metallite layer or degradation of the metallite layer due to an increase in the number of cracks) can be detected by monitoring the voltage drop occurring across a portion of the metallite layer. This voltage drop can be compared to a specific (preset) threshold, and a defect can be indicated when the voltage drop exceeds the specific threshold. Since the portion of the metallite layer near the bonding line 122 is designed as a targeted break point, the location of the defect is known, and the affected portion of the transistor cell array can be deactivated.

[0047] Figure 9 The circuit diagram illustrates an example of how to detect defects / deterioration. Figure 9 circuit and Figure 2 The circuitry is identical to that in the previous example, but with an additional amplifier AMP and comparator K. The amplifier AMP and comparator K form a detection circuit configured to detect the voltage drop V appearing across the portion of the metallization layer. MET (in this example, resistor R) MET1 (indicated), and indicates the voltage drop V MET Exceeding a specific threshold. In this example, the amplifier outputs an amplified voltage V1 (V1 = g·V). MET It has a gain g), and the comparator K indicates whether the condition V1>V is satisfied. TR Therefore, the output of comparator K sends a signal (output signal ERR) to notify the voltage drop V. MET Does it exceed the threshold V? TR / g. The comparator output signal ERR can be a logic signal with either a low or high level. For example, a high level of the ERR signal can indicate that a defect has been detected in the metallization layer 101.

[0048] Figure 10 The circuit diagram illustrates an example of a control circuit CTL configured to turn power transistors on and off according to a switching command. The switching command can be a logic signal S received by the control circuit CTL. ON The rising / falling edge. The control circuit CTL can also be configured to detect the rising / falling edge of the circuit (amplifier AMP and comparator K, see...). Figure 9 Indicator voltage drop V MET Exceeding a specific threshold (e.g., V) TR When / g), at least a portion of the second transistor unit (in) Figure 10 The middle is marked as T L See also , Figure 5 The transistor cell T is deactivated. In the depicted embodiment, the control circuit CTL deactivates the transistor cell T based on the logic level of the signal S2. L The signal S2 can correspond to or depend on the comparator output signal ERR.

[0049] Figure 11 The diagram illustrates a system including a semiconductor device 100 (in a chip package) and a microcontroller 200 configured to control switching operations of the semiconductor device 100. In this example, the microcontroller 200 is powered by a supply voltage V. DD Power supply, the voltage of which is V DD It can be lower than the load R applied. LOAD power supply voltage V S The microcontroller 200 is configured to receive information about the load current i LOAD The information. In the illustrated example, the microcontroller 200 has the function of receiving a current sensing signal V. IS =i LOAD R S / K analog input. Factor R S / K are known system parameters, where K is the reference above. Figure 1 The proportion factor under discussion, and R S Identifying the sensing resistor (in) Figure 10 Also marked as R S The resistor is 0.5. The microcontroller 200 can be configured to digitize the voltage V. IS The load current value is then calculated based on the corresponding digital value. It should be understood that the current information can also be digitized in the semiconductor device 100 and transmitted to the microcontroller via the digital communication link 150. In the depicted example, the digital communication link 150 can be any digital communication link, such as a parallel or serial bus, or any other digital link. In one example, a Serial Peripheral Interface (SPI) bus can be used.

[0050] As discussed above, the second transistor unit T can be activated when a defect in the metallization layer is detected. L At least part of ” (see Figure 5 and 10 This will change the scaling factor K = i associated with current measurement. LOAD / i0. More specifically, due to the power transistor T L and sensing transistor T S When the ratio of the effective area changes, the scaling factor K changes. When the power transistor T... L When some transistor cells are deactivated, the effective area of ​​the power transistor decreases, while the effective area of ​​the sensing transistor TS remains constant. However, since the transistor cells to be deactivated when a defect is detected are known a priori, the microcontroller 200 can take into account the change in the scaling factor K in the calculation of the actual load current.

[0051] The change in the scaling factor K caused by the deactivation of some transistor cells also allows the microcontroller 200 to (indirectly) detect the degradation of the metallization layer 101 of the semiconductor 100. If the microcontroller "sees" the (digitized) current sensing signal V... IS A sudden change in the voltage level can indicate that a portion of the transistor cells in semiconductor device 100 has been deactivated, where deactivation is caused by the detection of defects in the metallization layer. For example, in a load current i LOAD During pulse width modulation (PWM), the current sensing signal V IS It is possible to abruptly switch from one PWM cycle to the next. Then, the microcontroller 200 can change the value used to calculate the actual load current i. LOAD The factor K is used to signal the error to, for example, a higher-level controller device (e.g., via a digital communication link).

[0052] In one embodiment, the microcontroller 200 can be configured to deactivate the second transistor unit T. L (at least a part of) . In this case, signal S2 (see Figure 10 The signal level of the comparator is determined by the microcontroller, while the comparator output signal ERR (see...) Figure 9 The signal is transmitted to the microcontroller 200 (e.g., via communication link 150 or a dedicated signal line).

[0053] Now for reference Figure 12 The flowchart summarizes the concepts described above. Figure 12 The illustration shows an example of a method for operating a semiconductor device, which includes a power transistor (e.g., see...). Figure 1-2 5 and 10, transistor T L It consists of multiple transistor cells arranged in a cell array. The multiple transistor cells include a first transistor cell (in...) Figure 5 and 10 In the examples, they are collectively represented as T L ') and the second transistor unit (in Figure 5 and 10 In the examples, they are collectively represented as T L The first transistor cell is arranged in the first portion of the cell array, and the second transistor cell is arranged in the second portion of the cell array. A metallization layer forms the source electrode of the power transistor, wherein the first bonding line (see...) Figure 5 and 8 The bonding line 120 is bonded to the first portion of the metallization layer (the first portion of the metallization layer covers the first portion of the cell array), and the second bonding line (see...) Figure 5-7The bonding wire 122 is bonded to the second portion of the metallization layer (the second portion of the metallization layer covers the second portion of the cell array). As discussed in detail above, the end piece of the second bonding wire has a larger volume than the end piece of the first bonding wire. Additionally or alternatively, for the first bonding wire, the thermal resistance between each bonding wire and the metallization layer is higher (e.g., due to the smaller contact area, see...). Figure 8 ).according to Figure 12 The method includes: supplying load current to the load via a power transistor ( Figure 12 (See box A1); detect the resistance of the load current path formed by the metallization layer and arranged in series with the power transistor (see box A1). Figure 9 R MET1 ) has changed a specific amount ( Figure 12 (box A2); and deactivation when a specific amount of change in resistance is detected (indicating degradation of the metallization layer). Figure 12 (See box A3) Second transistor unit (see box A3) Figure 5 and 10 Unit T L At least a part of ”).

[0054] In one embodiment, the metallization layer (e.g., R) is detected. MET1 Whether the resistance of a resistor has changed by a specific amount is determined by amplifying the voltage drop across the resistor and comparing the amplified voltage drop with a threshold (see also...). Figure 9 ).

[0055] In one embodiment, the method further includes transmitting an indication that degradation of the metallization layer has been detected to a higher-level controller device, such as a microcontroller 200 (see [link to documentation]). Figure 11 In this case, the upper-level controller device can cause the second transistor unit T to... L "Deactivate (see Figure 10 ).

[0056] In one embodiment, the method includes using a current sensing circuit that includes a sensing transistor (see [link to original text]). Figure 1-2 Generates a current sensing signal, which represents the sensed current through the sensing transistor (see...). Figure 3 Sensing current i S =i0, current sensing signal V IS The upper-level controller (e.g., microcontroller 200, see...) Figure 11 It can receive current sensing signals and calculate the actual load current based on them. As explained above, for this calculation, the upper-level controller can consider the scaling factor K = i LOAD Changes to / i0.

[0057] While the invention has been shown and described with respect to one or more embodiments, substitutions and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, regarding the various functions performed by the aforementioned components or structures (units, components, devices, circuits, systems, etc.), unless otherwise specified, the terminology used to describe these components (including references to "means") is intended to correspond to any component or structure that performs the specific function of the described component, even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary embodiments of the invention illustrated herein.

Claims

1. A semiconductor device, comprising: Power transistor (T) L It consists of multiple transistor units arranged in a unit array; the multiple transistor units include a first transistor unit and a second transistor unit (T L The first transistor unit is arranged in the first portion of the unit array, and the second transistor unit is arranged in the second portion of the unit array. A metallization layer (101) is formed to form the power transistor (T). L The source electrode of ) A first bonding line (120) has an end piece (120a) bonded to a first portion of the metallization layer (101), the first portion of the metallization layer (101) covering a first portion of the cell array; as well as The second bonding line (122) has an end piece (122a) that bonds to a second portion of the metallization layer (101), the second portion of the metallization layer (101) covering a second portion of the cell array. The end piece (122a) of the second bonding line (122) has a larger volume than the end piece (120a) of the first bonding line (120).

2. A semiconductor device, comprising: Power transistor (T) L It consists of multiple transistor units arranged in a unit array; the multiple transistor units include a first transistor unit and a second transistor unit (T L The first transistor unit is arranged in the first portion of the unit array, and the second transistor unit is arranged in the second portion of the unit array. A metallization layer (101) is formed to form the power transistor (T). L The source electrode of ) A first bonding line (120) has a first end piece (120a) bonded to a first portion of the metallization layer (101), the first portion of the metallization layer (101) covering a first portion of the cell array; as well as The second bonding line (122) has a second end piece (122a) bonded to a second portion of the metallization layer (101), the second portion of the metallization layer (101) covering a second portion of the cell array. The second end piece (122a) is shaped such that the second end piece (122a) achieves better cooling of the metallization layer (101) than the first end piece (120a).

3. The semiconductor device according to claim 1 or 2, The end piece (122a) of the second bonding line (122) has a higher heat capacity than the end piece (120a) of the first bonding line (120).

4. The semiconductor device according to any one of claims 1 to 3, in, The contact area between the end piece (122a) of the second bonding line (122) and the metallization layer (110) is greater than the contact area between the end piece (120a) of the first bonding line (120) and the metallization layer (110).

5. The semiconductor device according to any one of claims 1 to 4, further comprising: The current sensing circuit (20) includes a sensing transistor (T) S The current sensing circuit is configured to provide an indication of the current passing through the sensing transistor (T). S The current sensing signal (V) of the sensed current (i0) IS The sensed current (i0) is the load current (i... LOAD ) through the power transistor (T L The amount of ).

6. The semiconductor device according to any one of claims 1 to 5, further comprising: The detection circuit (AMP, K) is configured to detect a voltage drop (V) occurring across a portion of the metallization layer. MET ), and indicates that the voltage drop exceeds a specific threshold (V TR / K).

7. The semiconductor device according to claim 6, The detection circuit includes an amplifier (AMP) configured to amplify the voltage drop (V). MET ),and The detection circuit is configured to detect that the amplified voltage drop (V1) exceeds a voltage threshold (V). TR ).

8. The semiconductor device according to any one of claims 1 to 6, further comprising: The control circuit is configured to cause the second transistor unit (T) to activate upon detection of degradation of the metallization layer. L At least a portion of ') is activated.

9. When referring to claim 7, the semiconductor device according to claim 8, The degradation of the metallization layer is caused by exceeding the specific threshold (V). TR The voltage drop indication of / K).

10. A system comprising: When referring to claim 5, the semiconductor device (100) according to any one of claims 5 or 6 to 9, and A microcontroller (200) is configured to receive the current sensing signal (V) from the semiconductor device. IS ), and is also configured to be based on the current sensing signal (V IS Determine the load current (i) LOAD The measured values ​​of ) and The microcontroller (200) is also configured to compensate for the load current (i LOAD ) and the current sensing signal (V IS The ratio factor (K / R) between ) S () sudden change.

11. A method for detecting degradation of a semiconductor device, comprising: Power transistor (T) L It consists of multiple transistor units arranged in a unit array; the multiple transistor units include a first transistor unit and a second transistor unit (T). L The first transistor unit is arranged in the first portion of the unit array, and the second transistor unit is arranged in the second portion of the unit array. A metallization layer (110) forms the source electrode of the power transistor (TL); A first bonding line (120) has an end piece (120a) bonded to a first portion of the metallization layer (110), the first portion of the metallization layer (110) covering a first portion of the cell array; as well as The second bonding line (122) has an end piece (122a) bonded to a second portion of the metallization layer (110), the second portion of the metallization layer (110) covering a second portion of the cell array. The end piece (122a) of the second bonding line (122) has a larger volume than the end piece (120a) of the first bonding line (120); The method includes: By detecting a portion formed by the metallization layer and its connection with the power transistor (T) L The resistor (R) arranged in series along the load current path MET Has a specific amount been changed to detect the degradation of the metallization layer? When the resistance (R) is detected MET The second transistor unit (T) is activated when a specific amount has been changed. L At least part of ”).

12. The method of claim 11, further comprising: Using a sensing transistor (T) S The current sensing circuit generates a value representing the current through the sensing transistor (T). S The current sensing signal (V) of the sensed current (i0) IS ).

13. The method according to claim 11 or 12, The detected degradation of the metallization layer is indicated to the upper-level controller device (200).

14. The method according to claim 13, The second transistor unit (T) L At least part of the deactivation of “” is caused by the upper-level controller device (200).

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