Semiconductor package

Abstract

There is provided a semiconductor package including at least one semiconductor chip and a base chip, the base chip including an upper pad, an overlapping region, and an alignment pattern group, the alignment pattern group includes a first alignment pattern group and a second alignment pattern group adjacent to a first apex and a second apex opposite to each other in a diagonal direction among the apex, respectively, the first alignment pattern group includes a first reference pattern, a first row pattern spaced apart from the first reference pattern in a first forward direction, and a first column pattern spaced apart from the first reference pattern in a second forward direction perpendicular to the first forward direction, and the second alignment pattern group includes a second reference pattern, a second row pattern spaced apart from the second reference pattern in a first reverse direction opposite to the first forward direction, and a second column pattern spaced apart from the second reference pattern in a second reverse direction opposite to the second forward direction.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein relate to semiconductor packages. Background Technology

[0002] By placing semiconductor chips on a large-area substrate, multiple semiconductor packages can be manufactured, and the yield of semiconductor packaging processes can be improved. However, with repeated processes of attaching semiconductor chips, misalignment can occur, leading to a decrease in yield. Furthermore, edge chipping and beveling of semiconductor chips with reduced size and thickness can decrease the accuracy of misalignment determination. Summary of the Invention

[0003] The exemplary embodiments disclosed herein are intended to provide semiconductor packages with improved alignment accuracy.

[0004] According to some example embodiments of this disclosure, a semiconductor package includes: at least one semiconductor chip including connection pads and an edge defining a front surface, the connection pads being located on the front surface; and a substrate chip including an upper pad, an overlapping region, and an alignment pattern set, the upper pad being electrically connected to the connection pad, the at least one semiconductor chip and the upper pad being located on the overlapping region, the alignment pattern set including a reference pattern located in the overlapping region and row and column patterns outside the overlapping region, wherein the overlapping region includes a contour line corresponding to the edge of the at least one semiconductor chip and a vertex at the intersection of the contour line. The alignment pattern set includes a first alignment pattern set and a second alignment pattern set, which are adjacent to the first and second vertices that are diagonally opposite to each other among the vertices. The first alignment pattern set includes a first reference pattern, a first row of patterns spaced apart from the first reference pattern in a first positive direction, and a first column of patterns spaced apart from the first reference pattern in a second positive direction perpendicular to the first positive direction. The second alignment pattern set includes a second reference pattern, a second row of patterns spaced apart from the second reference pattern in a first negative direction opposite to the first positive direction, and a second column of patterns spaced apart from the second reference pattern in a second negative direction opposite to the second positive direction.

[0005] According to some example embodiments of this disclosure, a semiconductor package includes: at least one semiconductor chip including connection pads; a substrate chip including an overlapping region, an upper pad, a lower pad, and an alignment pattern set, the at least one semiconductor chip being located on the overlapping region, the upper pad being electrically connected to the connection pad, the lower pad being electrically connected to the upper pad, the alignment pattern set including a reference pattern located in the overlapping region and a peripheral pattern outside the overlapping region; a molding layer covering the at least one semiconductor chip on the substrate chip; and an external connection bump located below the substrate chip and electrically connected to the lower pad, the alignment pattern set including at least one pair of alignment pattern sets symmetrical about a point on the substrate chip in a plane.

[0006] According to some example embodiments of this disclosure, a semiconductor package includes: at least one semiconductor chip; and a substrate chip, the substrate chip including an overlapping region and an alignment pattern set, the at least one semiconductor chip being located on the overlapping region, the alignment pattern set including a reference pattern located in the overlapping region and a peripheral pattern outside the overlapping region, the overlapping region including a first vertex and a second vertex diagonally opposite to each other, the alignment pattern set including a first alignment pattern set disposed at the first vertex and a second alignment pattern set disposed at the second vertex, the first alignment pattern set including at least one first reference pattern and a first peripheral pattern, the second alignment pattern set including at least one second reference pattern and a second peripheral pattern, the first peripheral pattern being spaced apart from the at least one first reference pattern in a first positive direction and a second positive direction perpendicular to each other, and the second peripheral pattern being spaced apart from the at least one second reference pattern in a first negative direction and a second negative direction perpendicular to each other.

[0007] According to some example embodiments of this disclosure, a method of manufacturing a semiconductor package includes: preparing a substrate wafer including a die attachment region and a pair of alignment pattern sets located diagonally in the die attachment region, the pair of alignment pattern sets including a reference pattern and a peripheral pattern; attaching a semiconductor chip to a location overlapping with the reference pattern of each of the die attachment regions; and determining, by sensing whether the peripheral pattern of each of the die attachment regions overlaps with the semiconductor chip, defective units of the semiconductor chip that are misaligned in the die attachment region, the defective units being areas where at least a portion of the semiconductor chip overlaps with the peripheral pattern, the pair of alignment pattern sets including a first alignment pattern set and a second alignment pattern set, the first alignment pattern set including at least one first reference pattern and a first peripheral pattern, the second alignment pattern set including at least one second reference pattern and a second peripheral pattern, the first peripheral pattern being spaced apart from the at least one first reference pattern in a first positive direction and a second positive direction perpendicular to each other, and the second peripheral pattern being spaced apart from the at least one second reference pattern in a first negative direction and a second negative direction perpendicular to each other.

[0008] According to some example embodiments of this disclosure, a method of manufacturing a semiconductor package includes: attaching a semiconductor chip to a substrate wafer, the substrate wafer including scribe lines, a die attachment region defined by the scribe lines, an upper pad located in the die attachment region, and an alignment pattern set located in each of the die attachment regions; sensing the position of each of the semiconductor chips based on the alignment pattern set; determining whether the semiconductor chip is defective based on the corresponding position of each of the semiconductor chips with respect to the alignment pattern set; and stopping the placement of additional semiconductor chips in the die attachment region including at least one semiconductor chip determined to be defective.

[0009] According to some example embodiments of this disclosure, each of the alignment pattern groups includes a reference pattern and a peripheral pattern.

[0010] According to some example embodiments of this disclosure, a semiconductor chip includes an upper pad, an overlapping region, and an alignment pattern set. The upper pad is located on the overlapping region. The alignment pattern set includes a reference pattern located in the overlapping region and row and column patterns outside the overlapping region. The overlapping region is defined by a contour line and vertices where the contour line intersects. The alignment pattern set includes a first alignment pattern set and a second alignment pattern set adjacent to a first vertex and a second vertex that are diagonally opposite to each other among the vertices. The first alignment pattern set includes a first reference pattern, a first row pattern spaced apart from the first reference pattern in a first positive direction, and a first column pattern spaced apart from the first reference pattern in a second positive direction perpendicular to the first positive direction. The second alignment pattern set includes a second reference pattern, a second row pattern spaced apart from the second reference pattern in a first negative direction opposite to the first positive direction, and a second column pattern spaced apart from the second reference pattern in a second negative direction opposite to the second positive direction. Attached Figure Description

[0011] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A This is a perspective view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 1B and Figure 1C This is a top view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 2A and Figure 2B This is a top view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 3A and Figure 3B This is a top view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 4 This is a top view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 5 This is a top view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 6 This is a top view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 7 This is a top view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 8 This is a top view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 9 This is a side cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 10 This is a side cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 11 This is a side cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 12A This is a perspective view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 12B This is a top view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 13A This is a side cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 13B It is shown Figure 13A An enlarged view of region "A" in the image; Figure 14A This is a side cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 14B It is shown Figure 14A An enlarged view of region "B" in the image; Figure 15 This is a side cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 16 This is a side cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure; Figure 17 , Figures 18A to 18D and Figure 19 This is a diagram illustrating a method of manufacturing a semiconductor package according to some example embodiments of the present disclosure. Detailed Implementation

[0012] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0013] Figure 1A This is a perspective view showing a semiconductor package according to some example embodiments. Figure 1B and Figure 1C This is a top view showing a semiconductor package according to some example embodiments.

[0014] refer to Figure 1A , Figure 1B and Figure 1CIn some example embodiments, the semiconductor package 1 may include at least one semiconductor chip 10 and a substrate chip 20. In some example embodiments, the semiconductor package 1 may also include a molding layer MD. The molding layer MD may include, for example, an epoxy molding compound (EMC), but the material of the molding layer MD is not limited to any particular example.

[0015] Semiconductor chip 10 may include a semiconductor wafer and integrated circuit (IC) formed of semiconductor elements such as silicon and germanium, or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Semiconductor chip 10 may be a bare semiconductor chip on which no separate bumps or wiring layers are formed. In some example embodiments, semiconductor chip 10 may be configured as a packaged semiconductor chip having connection bumps formed on connection pads 10P.

[0016] Semiconductor chip 10 may include logic chips such as central processing unit (CPU), graphics processing unit (GPU), field programmable gate array (FPGA), application processor (AP), digital signal processor, encryption processor, microprocessor, microcontroller, analog-to-digital converter, application-specific integrated circuit (ASIC), or memory chips, including volatile memories such as dynamic RAM (DRAM) and static RAM (SRAM), and non-volatile memories such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and flash memory.

[0017] The semiconductor chip 10 may include connection pads 10P for connecting to an integrated circuit. The connection pads 10P may include at least one metal selected from copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), and zinc (Zn), or an alloy containing two or more metals.

[0018] The substrate chip 20 may be an IC chip including logic chips and memory chips (such as semiconductor chip 10), or a substrate configured to redistribute the connection pads 10P of the semiconductor chip 10. For example, the substrate chip 20 may be configured as a substrate for a semiconductor package, including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a substrate with wiring, etc. The substrate chip 20 may include an upper pad 20P1 electrically connected to the connection pads 10P of the semiconductor chip 10. In addition, the substrate chip 20 may also include a lower pad on which external connection bumps 25 are disposed (see [link to documentation]). Figures 9 to 11The external connection bump 25 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof. In some example embodiments, the external connection bump 25 may have a combination of metal pillars and solder balls.

[0019] According to some example embodiments, the semiconductor package 1 may include at least one pair of alignment pattern sets AG for identifying the alignment state of the substrate chip 20 and the semiconductor chip 10. The alignment pattern sets AG may be disposed around the alignment position of the semiconductor chip 10 so as to be opposite each other in a diagonal direction. Because in some example embodiments the alignment pattern sets AG include a reference pattern FP and a peripheral pattern PP, the accuracy of misalignment determination of the semiconductor chip 10 can be improved regardless of the edge trimming and beveling of the semiconductor chip 10.

[0020] The substrate chip 20 may include an overlapping region OR in which the semiconductor chip 10 is disposed, and an alignment pattern group AG disposed at opposite vertices in the diagonal direction of the overlapping region OR. The overlapping region OR can be understood as the region on the substrate chip 20 that overlaps with the semiconductor chip 10 in the vertical direction D3. Additionally, the overlapping region OR may be the region where the upper pad 20P1 of the substrate chip 20 is disposed. The overlapping region OR may be defined by the edge of the front surface of the semiconductor chip 10 in which the connecting pad 10P is disposed. The overlapping region OR may include a contour line OL corresponding to the edge of the semiconductor chip 10 and the vertex where the contour line OL intersects.

[0021] The alignment pattern group AG may include a reference pattern FP located within the overlap region OR and a peripheral pattern PP located outside the overlap region OR. In some example embodiments, the reference pattern FP may partially overlap with the overlap region OR. The reference pattern FP and the peripheral pattern PP may have the same planar shape as the upper pad 20P1. In some example embodiments, the reference pattern FP and the peripheral pattern PP may have a different planar shape than the upper pad 20P1 (e.g., Figure 5 and Figure 6 (Some example embodiments). The peripheral pattern PP may include a row pattern RP spaced apart from the reference pattern FP in the first directions FD1 and RD1, and a column pattern CP spaced apart from the reference pattern FP in the second directions FD2 and RD2.

[0022] Alignment pattern group AG may include a first alignment pattern group AG1 and a second alignment pattern group AG2 respectively disposed at a first vertex and a second vertex opposite each other in the diagonal direction in the overlapping region OR. In some example embodiments, alignment pattern group AG may include two pairs of alignment pattern groups AG respectively disposed at the vertices of the overlapping region OR.

[0023] The first alignment pattern group AG1 may include at least one first reference pattern FP1 and a first peripheral pattern PP1. The first peripheral pattern PP1 may be spaced apart from at least one first reference pattern FP1 in a first positive direction FD1 and a second positive direction FD2 that are perpendicular to each other. The first peripheral pattern PP1 may include a first row pattern RP1 spaced apart from the first reference pattern FP1 in the first positive direction FD1 and a first column pattern CP1 spaced apart from the first reference pattern FP1 in a second positive direction FD2 that is perpendicular to the first positive direction FD1.

[0024] The second alignment pattern group AG2 may include at least one second reference pattern FP2 and a second peripheral pattern PP2. The second peripheral pattern PP2 may be spaced apart from at least one second reference pattern FP2 in a first reverse direction RD1 and a second reverse direction RD2 that are perpendicular to each other. The second peripheral pattern PP2 may include a second row pattern RP2 spaced apart from the second reference pattern FP2 in a first reverse direction RD1 opposite to the first positive direction FD1, and a second column pattern CP2 spaced apart from the second reference pattern FP2 in a second reverse direction RD2 opposite to the second positive direction FD2.

[0025] Furthermore, the first alignment pattern group AG1 and the second alignment pattern group AG2 can be symmetrically arranged on a plane about a point PT on the substrate chip 20. For example, the first reference pattern FP1 and the second reference pattern FP2 can be symmetrically positioned about a point PT on the substrate chip 20, and the first peripheral pattern PP1 and the second peripheral pattern PP2 can be symmetrically positioned about a point PT on the substrate chip 20 (see [link to documentation]). Figure 1C ).

[0026] According to some example embodiments, the distances d1, d2, d3, and d4 between the peripheral pattern PP and the reference pattern FP can be substantially the same. Additionally, the distances d1, d2, d3, and d4 between the peripheral pattern PP and the reference pattern FP can be the same as, or less than, the minimum distance d5 between the upper pads 20P1. In this specification, "substantially the same" and "identical" configurations can include tolerances or be substantially identical, and can indicate that the distances are designed to be the same or substantially the same size. The distances d1 and d2 between at least one first reference pattern FP1 and the first peripheral pattern PP1 in the first positive direction FD1 and the second positive direction FD2 can be the same as the distances d3 and d4 between at least one second reference pattern FP2 and the second peripheral pattern PP2 in the first negative direction RD1 and the second negative direction RD2. Therefore, as long as the overlapping area OR at least partially overlaps with the reference pattern FP and does not overlap with the peripheral pattern PP, the connection pads 10P and the upper pads 20P1 can meet the required alignment margin.

[0027] The first distance d1 between the first reference pattern FP1 and the first row pattern RP1, the second distance d2 between the first reference pattern FP1 and the first column pattern CP1, the third distance d3 between the second reference pattern FP2 and the second row pattern RP2, and the fourth distance d4 between the second reference pattern FP2 and the second column pattern CP2 can be the same. The first distance d1, the second distance d2, the third distance d3, and the fourth distance d4 can be equal to or less than the minimum distance d5 between the upper pads 20P1. The minimum distance d5 between the upper pads 20P1 can be approximately or exactly 50 μm or less (e.g., 0 μm), for example, approximately or exactly 10 μm to approximately or exactly 50 μm, approximately or exactly 10 μm to approximately or exactly 40 μm, approximately or exactly 10 μm to approximately or exactly 30 μm, etc. The first distance d1, the second distance d2, the third distance d3, and the fourth distance d4 can be approximately or exactly 50% or greater than the minimum distance d5 between the upper pads 20P1 (e.g., approximately or exactly 50% to approximately or exactly 200% of the minimum distance d5). In some example embodiments, for fine alignment of the pads 10P and the upper pads 20P1, the first distance d1, the second distance d2, the third distance d3, and the fourth distance d4 can be approximately or exactly 50% or less than the minimum distance d5 between the upper pads 20P1 (e.g., 0%).

[0028] According to some example embodiments, the alignment accuracy of the semiconductor chip 10 can be determined by visually sensing the arrangement relationship between the outline OL of the overlapping region OR and the peripheral pattern PP. When the semiconductor chip 10 is aligned at the designed alignment position, the spacing between the outline OL of the overlapping region OR and the peripheral pattern PP can be substantially the same. The outline OL of the overlapping region OR may include a first outline OL1 adjacent to the first row pattern RP1, a second outline OL2 adjacent to the first column pattern CP1, a third outline OL3 adjacent to the second row pattern RP2, and a fourth outline OL4 adjacent to the second column pattern CP2. The spacing between the first row pattern RP1 and the first outline OL1, the spacing between the first column pattern CP1 and the second outline OL2, the spacing between the second row pattern RP2 and the third outline OL3, and the spacing between the second column pattern CP2 and the fourth outline OL4 can be substantially the same.

[0029] Additionally, in some example embodiments, when the semiconductor chip 10 is aligned at the designed alignment position, the outline OL of the overlapping region OR can be spaced apart from the reference pattern FP. For example... Figure 1B As shown, the first contour line OL1 and the second contour line OL2 may have a predetermined (or alternatively, desired or determined) gap with the first reference pattern FP1, and the third contour line OL3 and the fourth contour line OL4 may have a predetermined (or alternatively, desired or determined) gap with the second reference pattern FP2. The gap between the contour line OL of the overlapping region OR and the reference pattern FP may be an alignment allowance that takes into account process errors. In some example embodiments, the contour line OL of the overlapping region OR and the reference pattern FP may be in contact with each other. Figure 1C As shown, in some example embodiments of the semiconductor package 1a', the first reference pattern FP1 may contact the first contour line OL1 and the second contour line OL2, and the second reference pattern FP2 may contact the third contour line OL3 and the fourth contour line OL4.

[0030] In the following text, reference will be made to Figures 2A to 4Example embodiments are described that satisfy the "alignment allowance" defined by the alignment pattern group AG. According to some example embodiments, the area in which the connecting pad 10P and the upper pad 20P1 overlap within the alignment allowance can be controlled by configuring the distance between the row pattern RP and the column pattern CP relative to the reference pattern FP. That is, when the alignment allowance defined by the alignment pattern group AG is satisfied, the connecting pad 10P and the upper pad 20P1 may overlap each other by approximately or exactly 50% or more of their planar area (e.g., to complete overlap), however, this may be due solely to the distance configuration described above and not a standard for alignment allowance. In some example embodiments, the alignment allowance defined by the alignment pattern group AG can be configured such that the connecting pad 10P and the upper pad 20P1 overlap each other by less than approximately or exactly 50% of their planar area (e.g., overlap between approximately or exactly 0% and approximately or exactly 50%).

[0031] Figure 2A and Figure 2B This is a top view showing a semiconductor package 1b according to some example embodiments.

[0032] refer to Figure 2A and Figure 2B In addition to configurations where the position of the overlapping region OR is changed, in some example embodiments, the semiconductor package 1b can be configured to be aligned with a reference... Figures 1A to 1C The examples described are the same or similar. The semiconductor chip 10 may be offset from the designed alignment position on the first directions FD1 and RD1 or on the second directions FD2 and RD2. The center of the connection pad 10P of the semiconductor chip 10 and the center of the upper pad 20P1 of the substrate chip 20 may be spaced apart from each other in the vertical or horizontal direction. The first spacing sd1 between the first row pattern RP1 and the first outline OL1 and the second spacing sd2 between the first column pattern CP1 and the second outline OL2 may be different from each other, and the third spacing sd3 between the second row pattern RP2 and the third outline OL3 and the fourth spacing sd4 between the second column pattern CP2 and the fourth outline OL4 may be different from each other.

[0033] like Figure 2A As shown, the center of the connecting pad 10P can be spaced apart from the center of the upper pad 20P1 in the first reverse direction RD1. A portion of the first reference pattern FP1 can be located outside the overlapping area OR. The first spacing sd1 between the first row pattern RP1 and the first outline OL1 can be greater than the second spacing sd2 between the first column pattern CP1 and the second outline OL2. The third spacing sd3 between the second row pattern RP2 and the third outline OL3 can be less than the fourth spacing sd4 between the second column pattern CP2 and the fourth outline OL4.

[0034] like Figure 2BAs shown, the center of the connecting pad 10P can be spaced apart from the center of the upper pad 20P1 in the second reverse direction RD2. A portion of the first reference pattern FP1 can be located outside the overlapping area OR. The first spacing sd1 between the first row pattern RP1 and the first outline OL1 can be smaller than the second spacing sd2 between the first column pattern CP1 and the second outline OL2. The third spacing sd3 between the second row pattern RP2 and the third outline OL3 can be larger than the fourth spacing sd4 between the second column pattern CP2 and the fourth outline OL4.

[0035] Figure 3A and Figure 3B This is a top view showing a semiconductor package 1c according to some example embodiments.

[0036] refer to Figure 3A and Figure 3B Apart from configurations where the position of the overlapping region OR is changed, in some example embodiments, the semiconductor package 1c can be configured to be aligned with a reference... Figures 1A to 2B The examples described are the same or similar. The semiconductor chip 10 may be offset from the designed alignment position in the first directions FD1 and RD1 and in the second directions FD2 and RD2. The center of the connection pad 10P of the semiconductor chip 10 and the center of the upper pad 20P1 of the substrate chip 20 may be spaced apart from each other in a diagonal direction.

[0037] like Figure 3A As shown, the center of the connecting pad 10P can be spaced apart from the center of the upper pad 20P1 on the first reverse direction RD1 and on the second reverse direction RD2. A portion of the first reference pattern FP1 can be located outside the overlapping area OR. The first spacing sd1 between the first row pattern RP1 and the first outline OL1 and the second spacing sd2 between the first column pattern CP1 and the second outline OL2 can be the same, and the third spacing sd3 between the second row pattern RP2 and the third outline OL3 and the fourth spacing sd4 between the second column pattern CP2 and the fourth outline OL4 can be the same.

[0038] like Figure 3B As shown, the center of the connecting pad 10P can be spaced apart from the center of the upper pad 20P1 in the second positive direction FD2 and the first negative direction RD1. A portion of the first reference pattern FP1 and a portion of the second reference pattern FP2 can be located outside the overlapping region OR, respectively. The first spacing sd1 between the first row pattern RP1 and the first contour line OL1 can be greater than the second spacing sd2 between the first column pattern CP1 and the second contour line OL2. The third spacing sd3 between the second row pattern RP2 and the third contour line OL3 can be less than the fourth spacing sd4 between the second column pattern CP2 and the fourth contour line OL4.

[0039] Figure 4 This is a top view showing a semiconductor package 1d according to some example embodiments.

[0040] refer to Figure 4 Apart from configurations where the position of the overlapping region OR is changed, in some example embodiments, the semiconductor package 1d can be configured to be aligned with a reference. Figures 1A to 3B The examples described are the same or similar. The semiconductor chip 10 can be rotated clockwise or counterclockwise relative to the designed alignment position. Each contour line OL of the overlapping region OR can be sloped relative to the side surface of the corresponding substrate chip 20. The center of the bonding pad 10P of the semiconductor chip 10 and the center of the upper pad 20P1 of the substrate chip 20 can be spaced apart from each other in either a clockwise or counterclockwise direction.

[0041] In some example embodiments, by positioning it further away from the rotation center of the semiconductor chip 10, the center of the connection pad 10P can be offset to a greater extent relative to the center of the upper pad 20P1. A portion of the first reference pattern FP1 and a portion of the second reference pattern FP2 can be located outside the overlapping region OR. The first spacing sd1 between the first row pattern RP1 and the first contour line OL1 can be smaller than the second spacing sd2 between the first column pattern CP1 and the second contour line OL2. The third spacing sd3 between the second row pattern RP2 and the third contour line OL3 can be smaller than the fourth spacing sd4 between the second column pattern CP2 and the fourth contour line OL4. Each of the first contour line OL1, the second contour line OL2, the third contour line OL3, and the fourth contour line OL4 can have a slope relative to the corresponding side surface of the substrate chip 20.

[0042] Figure 5 This is a top view showing a semiconductor package 1e according to some example embodiments.

[0043] refer to Figure 5 In addition to configurations where the planar shape of the alignment pattern group AG is altered, in some example embodiments, the semiconductor package 1e can be configured to be aligned with a reference... Figures 1A to 4 The examples described are the same or similar. The reference pattern FP and peripheral pattern PP of the alignment pattern group AG can have planar shapes different from the planar shape of the upper pad 20P1 of the substrate chip 20. The reference pattern FP and peripheral pattern PP can have circular or polygonal planar shapes. For example, the planar shape of the upper pad 20P1 can be circular, and the planar shapes of the reference pattern FP and peripheral pattern PP can be quadrilateral. Because the alignment pattern group AG has a planar shape different from the planar shape of the upper pad 20P1, the visibility of the alignment pattern group AG can be improved.

[0044] Figure 6 This is a top view showing a semiconductor package 1f according to some example embodiments.

[0045] refer to Figure 6 In addition to configurations where the planar shape of the alignment pattern group AG is altered, in some example embodiments, the semiconductor package 1f can be configured to be aligned with a reference... Figures 1A to 5 The examples described are the same or similar. The peripheral pattern PP of the alignment pattern group AG may have a planar shape different from the planar shape of the reference pattern FP. For example, the planar shape of the reference pattern FP may be circular, and the planar shape of the peripheral pattern PP may be polygonal. Additionally, the row patterns RP and column patterns CP may have different planar shapes. In some example embodiments, the row patterns RP may have the same planar shape, and the column patterns CP may have the same planar shape. For example, the planar shape of the reference pattern FP may be circular, the planar shape of the row pattern RP may be cross-shaped, and the planar shape of the column pattern CP may be curved. By having planar shapes that differentiate the peripheral pattern PP exposed in the overlapping region OR, the visibility of the alignment pattern group AG can be improved.

[0046] Figure 7 This is a top view showing a semiconductor package 1g according to some example embodiments.

[0047] refer to Figure 7 In addition to including the configuration of auxiliary pattern AP, in some example embodiments, the semiconductor package 1g can be configured to be aligned with a reference. Figures 1A to 6 The examples described are the same or similar. Each alignment pattern group AG may also include an auxiliary pattern AP disposed between adjacent row patterns RP and column patterns CP. The auxiliary pattern AP may be adjacent to the reference pattern FP in a diagonal direction. The first alignment pattern group AG1 may include a first auxiliary pattern AP1 located between the first row pattern RP1 and the first column pattern CP1. The first auxiliary pattern AP1 may be adjacent to the first reference pattern FP1 in a direction toward the second alignment pattern group AG2. The second alignment pattern group AG2 may include a second auxiliary pattern AP2 located between the second row pattern RP2 and the second column pattern CP2. The second auxiliary pattern AP2 may be adjacent to the second reference pattern FP2 in a direction toward the first alignment pattern group AG1. The auxiliary pattern AP may further enhance the visibility of the alignment pattern group AG. In some example embodiments, the auxiliary pattern AP may have a different planar shape than the row pattern RP and column pattern CP.

[0048] Figure 8 This is a top view showing a semiconductor package 1h according to some example embodiments.

[0049] refer to Figure 8 In addition to the configuration where each alignment pattern group AG includes multiple reference patterns FP, in some example embodiments, the semiconductor package 1h can be configured to align with reference patterns FP. Figures 1A to 7 The examples described are the same or similar. Multiple reference patterns FP can be arranged in a matrix at the corners of the overlapping region OR. At least a portion of the reference patterns FP in the multiple reference patterns FP can be partially located outside the overlapping region OR. The first reference pattern FP1 of the first alignment pattern group AG1 can be provided as multiple first reference patterns FP1 arranged in an n×n matrix. The second reference pattern FP2 of the second alignment pattern group AG2 can be provided as multiple second reference patterns FP2 arranged in an m×m matrix. Here, n and m can be the same number. In some example embodiments, n and m can be different numbers. By providing multiple reference patterns FP and multiple peripheral patterns PP, the visibility of the alignment pattern group AG and the alignment accuracy of the semiconductor chip 10 can be improved.

[0050] The first alignment pattern group AG1 may include a plurality of first row patterns RP1 and a plurality of first column patterns CP1 spaced apart from the first reference pattern FP1 of the contour line OL adjacent to the overlapping region OR in the first positive direction FD1 and the second positive direction FD2. In addition, the first alignment pattern group AG1 may also include a first auxiliary pattern AP1 located between the first row patterns RP1 and the first column patterns CP1 that are adjacent to each other.

[0051] The second alignment pattern group AG2 may include a plurality of second row patterns RP2 and a plurality of second column patterns CP2 spaced apart from the second reference pattern FP2 of the contour line OL closest to the overlapping region OR in the first reverse direction RD1 and the second reverse direction RD2. Additionally, the second alignment pattern group AG2 may also include a second auxiliary pattern AP2 located between the closest adjacent second row patterns RP2 and second column patterns CP2.

[0052] Figure 9 This is a side cross-sectional view of a semiconductor package 1A according to some example embodiments, taken along line I-I'.

[0053] refer to Figure 9 In addition to the configuration including the first chip structure 100 and the first substrate chip 200, in some example embodiments, the semiconductor package 1A can be configured to be connected to a reference chip. Figures 1A to 8The examples described are the same or similar. The first chip structure 100 and the first substrate chip 200 can be understood as specific examples of the semiconductor chip 10 and substrate chip 20 described above, respectively. The first chip structure 100 and the first substrate chip 200 can be configured as chiplets included in a multi-chip module (MCM). For example, the first substrate chip 200 may include processor circuitry, and the first chip structure 100 may include at least one of input / output circuitry, analog circuitry, memory circuitry, and serial-to-parallel conversion circuitry for the processor circuitry.

[0054] The first chip structure 100 may include a substrate 110, a circuit layer 120, and connection pads 10P. The substrate 110 may be configured as a semiconductor wafer. The substrate 110 may include semiconductor elements such as silicon and germanium, and / or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The substrate 110 may include conductive regions, such as wells doped with impurities. The circuit layer 120 may include integrated circuits forming logic chips or memory chips. The circuit layer 120 may include various devices electrically connected to the conductive regions of the substrate 110, such as: FETs such as planar FETs or FinFETs; memory devices such as flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, and RRAM; logic devices such as AND, OR, and NOT gates; various active devices; and / or passive devices such as system LSIs, CIS, and MEMS. The connection pads 10P may be electrically connected to the integrated circuits of the circuit layer 120. The connection pad 10P can be connected to the upper pad 20P1 of the first substrate chip 200 via the connection bump 15. The connection bump 15 can be a solder ball, but in some example embodiments, the connection bump 15 can be a combination of a metal pillar and a solder ball.

[0055] The first substrate chip 200 may include a substrate 210, a circuit layer 220, and a through-path 230. The substrate 210 and circuit layer 220 may be configured similarly to the substrate 110 and circuit layer 120 of the first chip structure 100, thus no overlapping description will be provided. The through-path 230 may penetrate the substrate 210 in a vertical direction (D3 direction) and may provide an electrical path connecting the upper pad 20P1 to the lower pad 20P2. The through-path 230 may include a conductive plug and a barrier film surrounding the conductive plug. The conductive plug may include a metal, such as tungsten (W), titanium (Ti), aluminum (Al), and / or copper (Cu). The conductive plug may be formed by a plating process, a PVD process, and / or a CVD process. The barrier film may include an insulating barrier film and / or a conductive barrier film. The insulating barrier film may be formed from an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. The conductive barrier film may be disposed between the insulating barrier film and the conductive plug. The conductive barrier film may include metal compounds, such as tungsten nitride (WN), titanium nitride (TiN), and / or tantalum nitride (TaN). The barrier film may be formed by PVD and / or CVD processes.

[0056] The first substrate chip 200 may include an upper pad 20P1, a lower pad 20P2, and an alignment pattern group AG. The upper pad 20P1 may be electrically insulated from the substrate 210 via a buffer layer 213. The buffer layer 213 may include an insulating material such as a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film. The lower pad 20P2 may be connected to an external connection bump 25. The alignment pattern group AG may include a reference pattern FP and a peripheral pattern PP. The reference pattern FP may overlap with the first chip structure 100 in the vertical direction D3. The peripheral pattern PP may not overlap with the first chip structure 100. The peripheral pattern PP may be spaced apart from the reference pattern FP in the horizontal direction. The first peripheral pattern PP1 may be spaced apart from the first reference pattern FP1 in the first forward direction FD1 and the second forward direction FD2. The second peripheral pattern PP2 may be spaced apart from the second reference pattern FP2 in the first reverse direction RD1 and the second reverse direction RD2.

[0057] In some example embodiments, the semiconductor package 1A may further include a molding layer MD and an underfill UF. The molding layer MD may include, for example, EMC. The underfill UF may be disposed between the first chip structure 100 and the first substrate chip 200. The underfill UF may cover at least a portion of the reference pattern FP and the peripheral pattern PP. The underfill UF may include a thermosetting resin, such as epoxy resin, and may be formed as a sealing connection bump 15 by a capillary underfill (CUF) method. In some example embodiments, the underfill UF may be integrally formed with the molding layer MD by a molding underfill (MUF) method.

[0058] Figure 10 This is a side cross-sectional view showing a semiconductor package 1B according to some example embodiments.

[0059] refer to Figure 10 Except for the differences Figure 9 In addition to the configuration of a plurality of first chip structures 100 stacked on a first substrate chip 20 in the vertical direction D3, in some example embodiments, the semiconductor package 1B may be configured to be associated with a reference chip. Figures 1A to 9 The examples described are the same or similar. Multiple first chip structures 100 can be configured to include volatile memory devices such as DRAM or SRAM, or non-volatile memory devices such as PRAM, MRAM, FeRAM, or RRAM. A first substrate chip 200 can be a buffer chip or control chip including multiple logic devices and / or memory devices. The first substrate chip 200 can transmit signals from the multiple first chip structures 100 stacked thereon to an external entity, and can also transmit signals and power from an external entity to the multiple first chip structures 100.

[0060] The plurality of first chip structures 100 may include a topmost semiconductor chip 100d and intermediate semiconductor chips 100a, 100b, and 100c located between the topmost semiconductor chip 100d and the first substrate chip 200. The plurality of first chip structures 100 may include... Figure 9 The components of the first chip structure 100 described herein are the same as or similar to those in the reference citation. However, in addition to the topmost semiconductor chip 100d, the intermediate semiconductor chips 100a, 100b, and 100c may also include a through-path 130 and a back-side pad 10BP. The through-path 130 and back-side pad 10BP of the intermediate semiconductor chips 100a, 100b, and 100c may be respectively identical to those in the reference citation. Figure 9 The through-path 230 and upper pad 20P1 of the first substrate chip 200 are similarly configured, so no overlapping description will be provided.

[0061] Multiple first chip structures 100 may be electrically connected to each other via connecting bumps 15. An adhesive film DF may be disposed between the multiple first chip structures 100 and the first substrate chip 200. The adhesive film DF may be a non-conductive film (NCF), but some exemplary embodiments are not limited thereto, and for example, the adhesive film DF may be formed from various insulating films used in hot-pressing processes. The lowermost adhesive film DF may cover at least a portion of the reference pattern FP and the peripheral pattern PP.

[0062] Figure 11 This is a side cross-sectional view of a semiconductor package 1C according to some example embodiments.

[0063] refer to Figure 11 Besides the ones with Figure 9 In some example embodiments, in addition to the configuration where the first chip structure 100 and the first substrate chip 200 are directly bonded and coupled to each other without connecting members (e.g., solder balls, metal pillars, etc.), the semiconductor package 1A can be configured to be coupled to a reference chip. Figures 1A to 10 The examples described are the same or similar. The first chip structure 100 and the first substrate chip 200 can be coupled to each other via metal-to-metal bonding and dielectric-to-dielectric bonding. The first chip structure 100 may include a first bonding layer BD1 surrounding a connection pad 10P, and the first substrate chip 200 may include a second bonding layer BD2 surrounding an upper pad 20P1. The first bonding layer BD1 and the second bonding layer BD2 may include materials that can be bonded and coupled to each other and can form a dielectric bond, such as at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon carbonitride (SiCN). The connection pad 10P and the upper pad 20P1 may include materials that can be bonded and coupled to each other and can form a metal bond, such as at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), and tantalum (Ta).

[0064] Figure 12A This is a perspective view showing a semiconductor package 2 according to some example embodiments. Figure 12B This is a top view showing a semiconductor package according to some example embodiments.

[0065] refer to Figure 12A and Figure 12B In addition to including a configuration that includes multiple semiconductor chips 10a, 10b, and 10c disposed on the substrate chip 20 in a horizontal direction, in some example embodiments, the semiconductor package 2 may be configured to be connected to a reference... Figures 1A to 11 The examples described are the same or similar. Each of the plurality of semiconductor chips 10a, 10b, and 10c may define an overlapping region OR on the substrate chip 20. The substrate chip 20 may include a first overlapping region OR1, a second overlapping region OR2, and a third overlapping region OR3 corresponding to the first semiconductor chip 10a, the second semiconductor chip 10b, and the third semiconductor chip 10c, respectively. The alignment pattern group AG may include a first alignment pattern group AG1 and a second alignment pattern group AG2 disposed diagonally at each corner of the first overlapping region OR1, the second overlapping region OR2, and the third overlapping region OR3.

[0066] Figure 13A This is a side cross-sectional view showing a semiconductor package 2A according to some example embodiments. Figure 13B It is shown Figure 13A An enlarged view of region "A" in the image. Figure 13A Show along Figure 12A The cross-sectional view taken from line II-II' in the diagram.

[0067] refer to Figure 13A and Figure 13B In addition to the configuration including multiple semiconductor chips 10a and 10b, a second substrate chip 300, and a packaging substrate 30, in some example embodiments, the semiconductor package 2A can be configured to be connected to a reference... Figures 1A to 12B The examples described are the same or similar. The second substrate chip 300 can be understood as a specific example of the substrate chip 20 described above.

[0068] The packaging substrate 30 can be configured as a substrate for semiconductor packages, including printed circuit boards (PCBs), ceramic substrates, glass substrates, and substrates with wiring. The packaging substrate 30 may include a lower pad 30P2, an upper pad 30P1, and a redistribution circuit 30L. The lower pad 30P2 and the upper pad 30P1 may include at least one metal or an alloy of two or more metals selected from the group consisting of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), and zinc (Zn). The lower pad 30P2 and the upper pad 30P1 can be electrically connected to each other via the redistribution circuit 30L. The redistribution circuit 30L may be formed of a material similar to the material of the lower pad 30P2 and the upper pad 30P1. The upper pad 30P1 may be connected to a first external connection bump 25. The lower pad 30P2 can be connected to the second external connection bump 35. The second external connection bump 35 can be a solder ball formed of, for example, tin (Sn) or an alloy including tin (Sn). In some example embodiments, an underfill surrounding the second external connection bump 35 can be formed between the package substrate 30 and the second substrate chip 300.

[0069] The multiple semiconductor chips 10a and 10b may include different types of semiconductor chips. For example, the first semiconductor chip 10a may include logic chips such as a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, or an ASIC, and the second semiconductor chip 10b may include memory chips such as DRAM, SRAM, PRAM, ReRAM, FeRAM, MRAM, or flash memory. The connection bump 15 may include pillars 11 located on the connection pad 10P and solder 12 located on the pillars 11.

[0070] The second substrate chip 300 can be configured to connect a plurality of semiconductor chips 10a and 10b to an embedded layer substrate of the packaging substrate 30. The plurality of semiconductor chips 10a and 10b can be electrically connected to each other by means of the second substrate chip 300. In some example embodiments, the second substrate chip 300 can be used to convert or transmit input electrical signals between the plurality of semiconductor chips 10a and 10b. The second substrate chip 300 may not include devices such as active or passive devices. The second substrate chip 300 may include a core substrate 310, an interconnect structure 320, and a through electrode 330.

[0071] The core substrate 310 can be formed from, for example, a silicon substrate, an organic substrate, a plastic substrate, and a glass substrate. When the core substrate 310 is configured as a silicon substrate, the second substrate chip 300 can be referred to as a silicon-embedded layer. A buffer layer 313 surrounding the lower portion of the through electrode 330 can be formed between the core substrate 310 and the lower pad 20P2. An interconnect structure 320 can be disposed on the core substrate 310 and can include an interlayer insulating layer 321 and a single-layer or multi-layer wiring structure 322. When the interconnect structure 320 is formed as a multi-layer wiring structure, wiring patterns on different layers can be connected to each other through contact paths. The wiring structure 322 can include a wiring pad 320P that contacts the upper pad 20P1. The wiring pad 320P can be, for example, an aluminum (Al) pad, but some exemplary embodiments are not limited thereto. The through electrode 330 can penetrate the core substrate 310 and can electrically connect the lower pad 20P2 to the upper pad 20P1. When the core substrate 310 is configured as a silicon substrate, the through electrode 330 can be referred to as a TSV.

[0072] The second substrate chip 300 may include alignment pattern groups AG corresponding to a plurality of semiconductor chips 10a and 10b, respectively. The alignment pattern groups AG may include a reference pattern FP and a peripheral pattern PP. The reference pattern FP may overlap with the plurality of semiconductor chips 10a and 10b in the vertical direction D3. The peripheral pattern PP may not overlap with the plurality of semiconductor chips 10a and 10b. The peripheral pattern PP may be spaced apart from the reference pattern FP in the horizontal direction. A first peripheral pattern PP1 may be spaced apart from the first reference pattern FP1 in a first forward direction FD1 and a second forward direction FD2. A second peripheral pattern PP2 may be spaced apart from the second reference pattern FP2 in a first reverse direction RD1 and a second reverse direction RD2.

[0073] In some example embodiments, the alignment pattern group AG may be at the same vertical height as the wiring pad 320P. The reference pattern FP and the peripheral pattern PP may overlap the wiring pad 320P in the horizontal direction. The wiring pad 320P, the reference pattern FP, and the peripheral pattern PP may be covered by a passivation layer PSV. The upper pad 20P1 may penetrate the passivation layer PSV and may be connected to the wiring pad 320P. The passivation layer PSV may cover the entire upper surface of the reference pattern FP and the entire upper surface of the peripheral pattern PP. The passivation layer PSV may comprise a dielectric material such as silicon nitride (SiN). The passivation layer PSV may be formed as a thin film, thereby enabling the identification of the reference pattern FP and the peripheral pattern PP.

[0074] Figure 14A This is a side cross-sectional view of a semiconductor package according to some example embodiments. Figure 14B It is shown Figure 14A An enlarged view of region "B" in the image.

[0075] refer to Figure 14A and Figure 14B Besides the ones with Figure 13A and Figure 13B In addition to the configuration where the semiconductor package 2A has a changed vertical height compared to the alignment pattern group AG, in some example embodiments, the semiconductor package 2B can be configured to be aligned with the reference... Figures 1A to 13B The examples described are the same or similar. In some example embodiments, the interconnect structure 320 may further include at least one dummy pad 320DP. The dummy pad 320DP may overlap with the wiring pad 320P in the horizontal direction. The passivation layer PSV may extend conformally along the surface of the dummy pad 320DP. The alignment pattern group AG may be located at the same vertical height as the upper pad 20P1. The reference pattern FP and the peripheral pattern PP may overlap with the upper pad 20P1 in the horizontal direction. The reference pattern FP and the peripheral pattern PP may penetrate the passivation layer PSV and may be connected to the dummy pad 320DP.

[0076] Figure 15 This is a side cross-sectional view showing a semiconductor package 2C according to some example embodiments.

[0077] refer to Figure 15 Besides the ones with Figure 13A and Figure 14A In addition to the configurations of semiconductor packages 2A and 2B that include a third substrate chip 400, in some example embodiments, semiconductor package 2C may be configured to be compatible with reference to... Figures 1A to 14B The examples described are the same or similar. The third substrate chip 400 can be understood as a specific example of the substrate chip 20 described above.

[0078] The third substrate chip 400 may include an insulating layer 410, a redistribution layer 420, and a redistribution path 430. The insulating layer 410 may include an insulating resin. The insulating resin may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with inorganic fillers (e.g., prepreg, Ajinomoto laminate (ABF), FR-4, or bismaleimide triazine (BT)). In some example embodiments, the insulating layer 410 may include a photosensitive resin such as a photoimageable dielectric (PID). The insulating layer 410 may include multiple insulating layers stacked in the vertical direction D3. Depending on the process, the boundaries between the multiple insulating layers may be indistinct.

[0079] The redistribution layer 420 may be disposed on and within the insulating layer 410, and may redistribute the bonding pads 10P. The redistribution layer 420 may include metallic materials, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The redistribution layer 420 may include more or fewer redistribution layers than the example shown in the figure.

[0080] The redistribution path 430 may extend from the insulating layer 410 and may be electrically connected to the redistribution layer 420. The redistribution path 430 may include a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The redistribution path 430 may be a filled path in which the metallic material fills the via aperture or a conformal path in which the metallic material extends along the inner wall of the via aperture.

[0081] Figure 16 This is a side cross-sectional view of a 2D semiconductor package according to some example embodiments.

[0082] refer to Figure 16 Besides the ones with Figure 13A and Figure 14A In addition to the configurations of semiconductor packages 2A and 2B that include a fourth substrate chip 500, in some example embodiments, semiconductor package 2D can be configured to be associated with a reference semiconductor package 2D. Figures 1A to 15 The examples described are the same or similar. The fourth substrate chip 500 can be understood as a specific example of the substrate chip 20 described above.

[0083] The fourth substrate chip 500 may include an interconnect chip 520 configured to electrically connect a plurality of semiconductor chips 10a and 10b to each other. For example, the fourth substrate chip 500 may include a lower redistribution structure 510, an interconnect chip 520, a through electrode 530, a molding 540, and an upper redistribution structure 550.

[0084] The lower redistribution structure 510 may include an insulating layer 511, a redistribution layer 512, and a redistribution pathway 513. The insulating layer 511 may be formed using a photosensitive resin such as a PID. For example, the insulating layer 511 may include a polyimide (PI) photosensitive polymer, a polybenzoxazole (PBO) photosensitive polymer, a polyhydroxystyrene (PHS) photosensitive polymer, a phenolic varnish photosensitive polymer, or a benzocyclobutene (BCB) photosensitive polymer.

[0085] The redistribution layer 512 may be disposed on or within the insulating layer 511, and may be electrically connected to the interconnect chip 520, the through electrode 530, and the semiconductor chips 10a and 10b. The redistribution layer 512 may include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layer 512 may include various types of conductive patterns extending in the horizontal direction.

[0086] The redistribution path 513 can penetrate the insulating layer 511 and can be electrically connected to the redistribution layer 512. The redistribution path 513 may include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The redistribution path 513 may be configured as a filled path in which the metal material fills the via hole or as a conformal path in which the metal material forms along the inner wall of the via hole.

[0087] Interconnect chip 520 may be disposed on lower redistribution structure 510. Interconnect chip 520 may include interconnect circuitry 520L for electrically connecting first semiconductor chip 10a to second semiconductor chip 10b. Interconnect chip 520 may be a semiconductor chip in which interconnect circuitry 520L is formed on a semiconductor substrate, but some exemplary embodiments are not limited thereto.

[0088] The through electrode 530 may be disposed around the interconnect chip 520 and may be electrically connected to the redistribution layer 512. The through electrode 530 may have a pillar shape extending in the vertical direction D3 corresponding to the thickness of the interconnect chip 520. Through a planarization process, one surface (e.g., the upper surface) of the through electrode 530 may be coplanar with one surface (e.g., the upper surface) of the molding part 540. The through electrode 530 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof.

[0089] The molding component 540 may be disposed between the lower redistribution structure 510 and the upper redistribution structure 550. The molding component 540 may be formed to encapsulate the interconnect chip 520 and the through electrode 530. The molding component 540 may include, for example, thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, or prepregs impregnated in these resins with inorganic fillers, ABF, FR-4, BT, EMC, etc.

[0090] The upper redistribution structure 550 may include an upper insulating layer 551, an upper redistribution layer 552, and an upper redistribution path 553. The upper insulating layer 551, upper redistribution layer 552, and upper redistribution path 553 may be configured to be substantially identical to the insulating layer 511, redistribution layer 512, and redistribution path 513 described above; therefore, no overlapping description will be provided. The upper redistribution layer 552 can be connected to the interconnect circuit 520L via the upper redistribution path 553. Multiple semiconductor chips 10a and 10b can be electrically connected to the interconnect chip 520 via the upper redistribution layer 552.

[0091] Figure 17 , Figures 18A to 18D and Figure 19 This is a diagram illustrating a method of manufacturing a semiconductor package according to some example embodiments. Figure 17 and Figure 19 Only a portion of the substrate wafer 20' is shown.

[0092] refer to Figure 17Multiple semiconductor chips 10 can be attached to a substrate wafer 20'. The substrate wafer 20' may include a die attachment region DA defined by a scribing track SL and an upper pad 20P1 disposed in the die attachment region DA. Additionally, the substrate wafer 20' may also include a pair of alignment pattern groups AG disposed diagonally in each of overlapping regions OR1, OR2, and OR3 in the die attachment region DA. Alignment pattern groups AG may include a reference pattern FP and a peripheral pattern PP. Multiple semiconductor chips 10 can be attached to a location overlapping with the reference pattern FP of the corresponding die attachment region DA. According to some example embodiments, by sensing whether a semiconductor chip 10 overlaps with the peripheral pattern PP disposed in each die attachment region DA, defective cells in which the semiconductor chip 10 is misaligned can be identified. Here, a defective cell can be defined as an area where at least a portion of the semiconductor chip 10 and the peripheral pattern PP overlap with each other. When the number of non-overlapping patterns sensed is less than or more than the number pre-configured in the first alignment pattern group AG1 and the second alignment pattern group AG2, the configuration can be identified as a defective cell. This misalignment determination operation of the semiconductor chip 10 can be performed after the semiconductor chip 10 has been attached. For example, the first semiconductor chip 10a can be attached to the first overlapping region OR1 in the die attachment region DA. By identifying the arrangement relationship between the first semiconductor chip 10a and the alignment pattern group AG using a vision sensor or the like, it is easier to determine whether a defect exists.

[0093] refer to Figure 18A In the first defective unit DA1, the first semiconductor chip 10a may be offset from its designed alignment position in the first directions FD1 and RD1. The first semiconductor chip 10a may overlap with at least a portion of the peripheral pad PP. For example, the first semiconductor chip 10a may overlap with at least a portion of the second row pattern RP2. In this case, two non-overlapping patterns in the first alignment pattern group AG1 (i.e., the first row pattern RP1 and the first column pattern CP1) can be sensed by an alignment pattern sensing tool (e.g., a vision sensor, etc.), and one non-overlapping pattern in the second alignment pattern group AG2 (i.e., the second column pattern CP2) can also be sensed. In some example embodiments, the entire first reference pattern FP1 may be located outside the first overlap region OR1. In this case, three non-overlapping patterns (i.e., the first reference pattern FP1, the first row pattern RP1, and the first column pattern CP1) can be sensed.

[0094] refer to Figure 18BIn the second defective unit DA2, the first semiconductor chip 10a may be offset from its designed alignment position in the second directions FD2 and RD2. The first semiconductor chip 10a may overlap with at least a portion of the peripheral pad PP. For example, the first semiconductor chip 10a may overlap with at least a portion of the first column pattern CP1. In this case, one non-overlapping pattern (first row pattern RP1) in the first alignment pattern group AG1 can be sensed by an alignment pattern sensing tool (e.g., a vision sensor, etc.), and two non-overlapping patterns (second row pattern RP2 and second column pattern CP2) in the second alignment pattern group AG2 can be sensed. In some example embodiments, the entire second reference pattern FP2 may be located outside the first overlapping region OR1. In this case, three non-overlapping patterns (i.e., the second reference pattern FP2, the second row pattern RP2, and the second column pattern CP2) in the second alignment pattern group AG2 can be sensed.

[0095] refer to Figure 18C In the third defective unit DA3, the first semiconductor chip 10a may be offset from the designed alignment position in the first directions FD1 and RD1 and in the second directions FD2 and RD2. The first semiconductor chip 10a may overlap with at least a portion of the peripheral pad PP. For example, the first semiconductor chip 10a may overlap with at least a portion of each of the second row pattern RP2 and the second column pattern CP2. In this case, the three non-overlapping patterns in the first alignment pattern group AG1 (i.e., the first reference pattern FP1, the first row pattern RP1, and the first column pattern CP1) can be sensed by an alignment pattern sensing tool (e.g., a vision sensor, etc.), and zero non-overlapping patterns in the second alignment pattern group AG2 can be sensed. In some example embodiments, a portion of the first reference pattern FP1 may be located in the first overlap region OR1. In this case, two non-overlapping patterns in the first alignment pattern group AG1 (i.e., the first row pattern RP1 and the first column pattern CP1) can be sensed.

[0096] refer to Figure 18D In the fourth defective unit DA4, the first semiconductor chip 10a may be rotated clockwise or counterclockwise relative to the designed alignment position. The first semiconductor chip 10a may overlap with at least a portion of the peripheral pad PP. For example, the first semiconductor chip 10a may overlap with at least a portion of each of the first row pattern RP1 and the second row pattern RP2. In this case, a non-overlapping pattern (i.e., the first column pattern CP1) in the first alignment pattern group AG1 and a non-overlapping pattern (i.e., the second column pattern CP2) in the second alignment pattern group AG2 can be sensed by an alignment pattern sensing tool (e.g., a vision sensor, etc.).

[0097] refer to Figure 19 Subsequent processes can be performed on the die attachment region DA, except for the defective cell DA' in which the first semiconductor chip 10a is misaligned. For example, the second semiconductor chip 10b and the third semiconductor chip 10c may not be attached to the defective cell DA'. The determination of misalignment of each of the second semiconductor chip 10b and the third semiconductor chip 10c can be performed similarly to the inspection of the first semiconductor chip 10a, and when a die attachment region DA in which the second semiconductor chip 10b is misaligned is sensed, this configuration can be determined as a defective cell and the third semiconductor chip 10c may not be attached.

[0098] Furthermore, based on the determination that a die attachment region DA (or multiple die attachment regions DA) is a defective cell DA', the defective cell DA' can be discarded or otherwise disposed of after subsequent dicing operations. For example, after sensing and determining the die attachment region DA as discussed above, the substrate wafer 20' can dice the die attachment region DA along the scribing track SL. For example, a saw can be used to perform the dicing. Moreover, after dicing, the die attachment region DA can be one of semiconductor packages 1, 1a, 1b, etc.

[0099] Additionally and / or alternatively, based on the identification of a defective cell DA' by a die attachment region DA (or multiple die attachment regions DA), the layout and / or attachment process can be reviewed to improve its accuracy. For example, the location of the defective cell DA' within the wafer, the temperature of the working cell, the process time, etc., can be identified, and the cause of the misalignment can be determined.

[0100] In some example embodiments, based on determining whether the die attachment region DA in the substrate wafer 20' is defective (e.g., a defective cell DA'), it can be determined whether the semiconductor device (or the semiconductor device region of the wafer, e.g., the die attachment region DA) is a defective or good product. Therefore, the functionality of the semiconductor device manufacturing system and / or manufacturing process can be improved, and the technical field of manufacturing semiconductor devices can be improved. Additionally or alternatively, according to some example embodiments, incorrect pass / fail determinations of semiconductor devices (e.g., semiconductor package 1) due to the inclusion of defective die regions (e.g., due to misalignment) can be reduced or prevented. Based on (or according to) the determination results, qualified semiconductor devices can be sorted out as good products and proceeded to other subsequent processes (e.g., subsequent manufacturing processes), while unqualified semiconductor devices can be discarded, reworked, refurbished, or downgraded.

[0101] According to the foregoing example embodiments, a semiconductor package with improved alignment accuracy can be provided by including a reference pattern and a peripheral pattern arranged diagonally.

[0102] When the terms “approximately” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes manufacturing or operational tolerances (e.g., ±10%) around the stated value. Similarly, when the terms “approximately” and “substantially” are used in conjunction with geometry, it is intended that the geometry is not required to be precise, but rather that the latitude of the shape is within the scope of this disclosure. Furthermore, regardless of whether a numerical value or shape is modified to “approximately” or “substantially”, it will be understood that these values ​​and shapes should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value or shape.

[0103] While some exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor package, the semiconductor package comprising: At least one semiconductor chip, the at least one semiconductor chip including connection pads and an edge defining a front surface, the connection pads being located on the front surface; as well as A substrate chip includes an upper pad, an overlapping region, and an alignment pattern set. The upper pad is electrically connected to the connection pad. At least one semiconductor chip and the upper pad are located on the overlapping region. The alignment pattern set includes a reference pattern located in the overlapping region and row and column patterns outside the overlapping region. The overlapping region includes a contour line corresponding to the edge of the at least one semiconductor chip and the vertex where the contour line intersects. The alignment pattern set includes a first alignment pattern set and a second alignment pattern set, which are respectively adjacent to the first vertex and the second vertex that are diagonally opposite to each other among the vertices. The first alignment pattern group includes a first reference pattern, a first row of patterns spaced apart from the first reference pattern in a first forward direction, and a first column of patterns spaced apart from the first reference pattern in a second forward direction perpendicular to the first forward direction. The second alignment pattern group includes a second reference pattern, a second row of patterns spaced apart from the second reference pattern in a first reverse direction opposite to the first forward direction, and a second column of patterns spaced apart from the second reference pattern in a second reverse direction opposite to the second forward direction.

2. The semiconductor package according to claim 1, wherein, The first distance between the first reference pattern and the first row pattern, the second distance between the first reference pattern and the first column pattern, the third distance between the second reference pattern and the second row pattern, and the fourth distance between the second reference pattern and the second column pattern are the same distance.

3. The semiconductor package according to claim 2, wherein, The first distance, the second distance, the third distance, and the fourth distance are equal to or less than the minimum distance between the upper pads.

4. The semiconductor package according to claim 3, wherein, The minimum distance between the upper pads is less than or equal to 50 μm.

5. The semiconductor package according to claim 3, wherein, The first distance, the second distance, the third distance, and the fourth distance are greater than or equal to 50% of the minimum distance between the upper pads.

6. The semiconductor package according to claim 1, wherein, The outline of the overlapping area includes a first outline adjacent to the first row pattern, a second outline adjacent to the first column pattern, a third outline adjacent to the second row pattern, and a fourth outline adjacent to the second column pattern.

7. The semiconductor package according to claim 6, wherein, The first spacing between the first row pattern and the first outline and the second spacing between the first column pattern and the second outline are different from each other, and The third spacing between the second row pattern and the third outline and the fourth spacing between the second column pattern and the fourth outline are different from each other.

8. The semiconductor package according to claim 7, wherein, The first contour line, the second contour line, the third contour line, and the fourth contour line have an inclination relative to the corresponding side surface of the substrate chip.

9. The semiconductor package of claim 6, wherein, The first spacing between the first row pattern and the first outline and the second spacing between the first column pattern and the second outline are equal to each other, and The third spacing between the second row pattern and the third outline and the fourth spacing between the second column pattern and the fourth outline are equal to each other.

10. The semiconductor package according to claim 1, wherein, The reference pattern, the row pattern, and the column pattern have the same planar shape as the upper pad.

11. The semiconductor package according to claim 1, wherein, Each of the row pattern and the column pattern has a planar shape that is different from the planar shape of the upper pad.

12. The semiconductor package of claim 11, wherein, The reference pattern has a planar shape that is different from the planar shape of the upper pad.

13. The semiconductor package of claim 11, wherein, The reference pattern has the same planar shape as the planar shape of the upper pad.

14. The semiconductor package of claim 11, wherein, The planar shape of the row pattern and the planar shape of the column pattern are different.

15. A semiconductor package, the semiconductor package comprising: At least one semiconductor chip, the at least one semiconductor chip including connection pads; A substrate chip, the substrate chip including an overlapping region, an upper pad, a lower pad and an alignment pattern group, the at least one semiconductor chip being located on the overlapping region, the upper pad being electrically connected to the connection pad, the lower pad being electrically connected to the upper pad, and the alignment pattern group including a reference pattern located in the overlapping region and a peripheral pattern outside the overlapping region; A molding layer, wherein the molding layer covers the at least one semiconductor chip on the substrate chip; and An external connection bump is located below the substrate chip and electrically connected to the lower pad. The alignment pattern set includes at least one pair of alignment pattern sets that are symmetrical about a point on the substrate chip in a plane.

16. The semiconductor package of claim 15, wherein, The outer pattern is spaced apart from the reference pattern in a first direction or a second direction perpendicular to the first direction, and The distance between the outer pattern and the reference pattern in the first direction and the second direction is equal to or less than the minimum distance between the upper pads.

17. A semiconductor package, the semiconductor package comprising: At least one semiconductor chip; as well as A substrate chip, the substrate chip including an overlapping region and an alignment pattern group, the at least one semiconductor chip being located on the overlapping region, the alignment pattern group including a reference pattern located in the overlapping region and a peripheral pattern outside the overlapping region. The overlapping region includes the first and second vertices that are diagonally opposite each other. The alignment pattern set includes a first alignment pattern set at the first vertex and a second alignment pattern set at the second vertex. The first alignment pattern group includes at least one first reference pattern and a first peripheral pattern. The second alignment pattern set includes at least one second reference pattern and a second peripheral pattern. The first peripheral pattern is spaced apart from the at least one first reference pattern in a first positive direction and a second positive direction that are perpendicular to each other, and The second outer pattern is spaced apart from the at least one second reference pattern in a first and a second reverse direction that are perpendicular to each other.

18. The semiconductor package of claim 17, wherein, The substrate chip includes a core substrate, upper pads, interconnect structures, a passivation layer, and through-paths. The interconnect structures are located between the core substrate and the upper pads, and include wiring pads. The passivation layer covers the wiring pads, and the through-paths penetrate the core substrate and are electrically connected to the wiring pads. The upper pad penetrates the passivation layer and connects to the wiring pad.

19. The semiconductor package of claim 18, wherein, The reference pattern and the peripheral pattern are at the same vertical height as the wiring pads, and The passivation layer covers the entire upper surface of the reference pattern and the entire upper surface of the peripheral pattern.

20. The semiconductor package of claim 18, wherein, The interconnect structure also includes dummy pads spaced apart from the wiring pads, and The reference pattern and the peripheral pattern penetrate the passivation layer and connect to the dummy pad, and the reference pattern and the peripheral pattern are at the same vertical height as the upper pad.

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