Manufacturing method of semiconductor package

By forming through electrodes and conductive bumps between semiconductor chips and performing reflow soldering and planarization, the challenge of high integration in semiconductor chip electrical interconnection technology has been solved, achieving precise bonding and stacking, and improving electrical interconnection characteristics and reliability.

CN122074013APending Publication Date: 2026-05-22SK HYNIX INC
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Patent Information

Application Number
CN202510604262.7
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2024-11-15
Filing Date
2025-05-12
Publication Date
2026-05-22

AI Technical Summary

Technical Problem

Existing semiconductor chip electrical interconnect technologies are insufficient to achieve precise bonding and stacking for higher integration levels, thus failing to meet the ever-growing demand.

Method used

The method involves forming through electrodes and conductive bumps between semiconductor chips and improving electrical connectivity through reflow soldering and planarization processes. This includes forming front conductive bumps on the substrate surface, performing planarization after reflow soldering, and ensuring effective connection between back conductive bumps and front conductive bumps during stacking.

Benefits of technology

This achieves improved electrical connectivity between semiconductor chips, ensuring precise bonding and stacking, reducing the risk of short circuits between bumps, and improving the reliability and integration of semiconductor packages.

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Abstract

The invention relates to a manufacturing method of a semiconductor package. A method of manufacturing a semiconductor package includes forming a through electrode in a substrate including a first surface and a second surface opposite to each other; forming a front conductive bump on the first surface of the substrate; performing reflow soldering on the front conductive bump; and planarizing an upper portion of the front conductive bump after reflow soldering the front conductive bump.
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