Manufacturing method of semiconductor package

Abstract

The invention relates to a manufacturing method of a semiconductor package. A method of manufacturing a semiconductor package includes forming a through electrode in a substrate including a first surface and a second surface opposite to each other; forming a front conductive bump on the first surface of the substrate; performing reflow soldering on the front conductive bump; and planarizing an upper portion of the front conductive bump after reflow soldering the front conductive bump.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0162611, filed on November 15, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure generally relate to semiconductor technology, and more specifically, to a method of manufacturing a semiconductor package. Background Technology

[0004] In response to the demand for higher integration in semiconductor packages, the technology for stacking semiconductor chips is constantly evolving. For example, to electrically connect stacked semiconductor chips, through-silicon via (TSV) technology or bonding pads or solder can be used to bond the chips.

[0005] However, despite significant advancements in these technologies, the ever-increasing demand for higher integration levels presents new challenges, requiring more precise bonding and stacking of semiconductor chips. Therefore, existing technologies for electrically connecting semiconductor chips face technological limitations, necessitating new solutions. Summary of the Invention

[0006] Embodiments of this disclosure relate to a method of manufacturing a semiconductor package that has improved electrical connection characteristics between semiconductor chips.

[0007] It should be noted that the embodiments disclosed herein are not limited to those described in this specification, and other embodiments not specifically mentioned will be clearly understood by those skilled in the art from the following description.

[0008] Embodiments of this disclosure relate to a method of manufacturing a semiconductor package, comprising: forming a through electrode in a substrate, the substrate including a first surface and a second surface opposite to each other; forming a front conductive bump on the first surface of the substrate; reflow soldering the front conductive bump; and planarizing the upper portion of the front conductive bump after reflow soldering the front conductive bump.

[0009] Embodiments of this disclosure relate to a method of manufacturing a semiconductor package, comprising: forming a first front conductive bump on a first surface of a first semiconductor chip, the first semiconductor chip further comprising a second surface opposite to the first surface; reflow soldering the first front conductive bump; planarizing the upper portion of the first front conductive bump after reflow soldering the first front conductive bump; forming a second back conductive bump on a second surface of a second semiconductor chip, the second semiconductor chip comprising a first surface and a second surface opposite to each other and stacked below the first surface of the first semiconductor chip; and connecting the second back conductive bump to the first front conductive bump after planarizing the upper portion of the first front conductive bump.

[0010] Embodiments of this disclosure relate to a method of manufacturing a semiconductor package, comprising: providing a first semiconductor chip including a first surface and a second surface opposite to each other; providing a second semiconductor chip including a first surface and a second surface opposite to each other; forming a first front conductive bump on the first surface of the first semiconductor chip; forming a second back conductive bump on the second surface of the second semiconductor chip; reflow soldering and planarizing the upper portion of the first front conductive bump; and stacking the second semiconductor chip below the first surface of the first semiconductor chip such that after planarizing the upper portion of the first front conductive bump, the second back conductive bump contacts the first front conductive bump.

[0011] According to embodiments of the present disclosure, a method for manufacturing a semiconductor package is provided, which has improved electrical connection characteristics between semiconductor chips used to manufacture the semiconductor package.

[0012] The effects of the embodiments disclosed herein are not limited to those described above, and those skilled in the art will understand other effects not mentioned based on the specification and claims. Attached Figure Description

[0013] The embodiments of this disclosure will be more fully understood through the detailed description and accompanying drawings provided below. These descriptions and drawings are provided for illustrative purposes only and are not intended to limit the embodiments to the configurations described in the drawings.

[0014] Figure 1 A cross-sectional structure of a semiconductor package according to an embodiment of the present disclosure is shown.

[0015] Figures 2 to 4 for Figure 1 A magnified view of 10.

[0016] Figures 5 to 23 A diagram illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0017] Figures 24 to 27 A diagram illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0018] Embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of example, and in which the same reference numerals and symbols may be used to denote the same or similar components even when shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that the description may obscure the subject matter of some embodiments of this disclosure. Unless used with the term “only,” terms such as “comprising,” “having,” “including,” “constituting,” “forming,” “composed of,” and “formed from” as used herein are generally intended to allow for the addition of additional components. Unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms as used herein.

[0019] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of the invention. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0020] When referring to the first element as "connected or coupled," "in contact or overlapping," etc., to the second element, it should be interpreted as meaning that the first element can not only be "directly connected or coupled" or "directly in contact or overlapping" with the second element, but also that a third element can be "intermediate" between the first and second elements, or that the first and second elements can be "connected or coupled," "in contact or overlapping," etc., with each other through a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact or overlapping," etc., with each other.

[0021] When using time-relative terms (such as “after,” “following,” “next,” “before,” etc.) to describe the process or operation of an element or configuration, or the flow or steps in an operation, processing, or manufacturing method, these terms may be used to describe discontinuous or non-sequential processes or operations unless used with the terms “directly” or “immediately.”

[0022] Furthermore, when referring to any size, relative size, etc., it should be noted that even if no specific description is specified, numerical values ​​for elements or features, or corresponding information (e.g., grade, range, etc.), also include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "can" fully encompasses all the meanings of the term "able to".

[0023] The various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0024] Figure 1 A cross-sectional structure of a semiconductor package according to an embodiment of the present disclosure is shown. Figures 2 to 4 yes Figure 1 A magnified view of number 10 in the image.

[0025] See Figure 1 and Figure 2 According to embodiments of the present disclosure, a semiconductor package may include a first semiconductor chip 101, a second semiconductor chip 201, and packaging layers 301, 302, and 303. The first semiconductor chip 101 may include a first substrate 110, a first wiring structure 120, a first through electrode 150, a first spacer 160, a first front conductive bump 130, a first back conductive bump 140, and a first back insulating layer 170. The second semiconductor chip 201 may include a second substrate 210, a second wiring structure 220, a second through electrode 250, a second spacer 260, a second front conductive bump 230, a second back conductive bump 240, and a second back insulating layer 270. The first wiring structure 120 and the second wiring structure 220 may include a guard ring 124.

[0026] The first substrate 110 may include a first surface 110a and a second surface 110b opposite to each other. The first surface 110a may be referred to as the front side of the first substrate 110, and the second surface 110b may be referred to as the back side or back side of the first substrate 110. Similarly, the second substrate 210 may include a first surface 210a and a second surface 210b opposite to each other. The first surface 210a may be referred to as the front side of the second substrate 210, and the second surface 210b may be referred to as the back side or back side of the second substrate 210.

[0027] The first wiring structure 120 may include a first circuit insulating layer 121, wiring 125, a guard ring 124, a chip pad 126, and first protective insulating layers 122 and 123. The second wiring structure 220 may include a second circuit insulating layer 221, wiring 225, a guard ring 224, a chip pad 226, and second protective insulating layers 222 and 223.

[0028] The first semiconductor chip 101 and the second semiconductor chip 201 may also include various types of active / passive components (e.g., transistors and / or capacitors) located within the first substrate 110 and the second substrate 210, between the first substrate 110 and the first wiring structure 120, between the second substrate 210 and the second wiring structure 220, or within the first wiring structure 120 and the second wiring structure 220, but these are omitted for the sake of brevity.

[0029] In one embodiment, the first semiconductor chip 101 and the second semiconductor chip 201 may include a memory, a processor, or a combination thereof. The first semiconductor chip 101 and the second semiconductor chip 201 may include dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, magnetoresistive random access memory (MRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), resistive random access memory (PRAM), or a combination thereof.

[0030] The first wiring structure 120 may be disposed below the first surface 110a of the first substrate 110. The first through electrode 150 may pass through the first substrate 110 in a vertical direction. The first through electrode 150 may be connected to the first wiring structure 120. In one embodiment, one end of the first through electrode 150 may enter the interior of the first circuit insulating layer 121 to contact the wiring 125.

[0031] The first front pad 133 can be disposed below the first wiring structure 120. The first front pad 133 can contact the lower surface of the first chip pad 126 in the first wiring structure 120. The first front pad 133 can be electrically connected to the wiring 125 through the first chip pad 126.

[0032] A first front conductive bump 130 may be connected below a first front pad 133. The first front conductive bump 130 may include a first bump post 131 and a first solder layer 132 connected to the first bump post 131. The first bump post 131 may be connected to the first front pad 133. The first solder layer 132 may be connected to a second back conductive bump 240 of the second semiconductor chip 201.

[0033] A first back insulating layer 170 may be disposed on the second surface 110b of the first substrate 110. A first back pad 141 may be disposed on the first back insulating layer 170 and the first through electrode 150. The first through electrode 150 may pass through the first back insulating layer 170 and may be connected to the first back pad 141. A first back conductive bump 140 may be disposed on the first back pad 141. The first back pad 141 may include a first back barrier layer 141b, a first back seed layer 141s, and a first back conductive layer 141c. The lower surface of the first back barrier layer 141b may contact the upper surface of the first through electrode 150.

[0034] Encapsulation layers 301, 302, and 303 may include a first encapsulation layer 301, a second encapsulation layer 302, and a third encapsulation layer 303. The first encapsulation layer 301 may be disposed between the first semiconductor chip 101 and another semiconductor chip stacked on top of the first semiconductor chip 101. The second encapsulation layer 302 may be disposed between the first semiconductor chip 101 and a second semiconductor chip 201. The third encapsulation layer 303 may be disposed between the second semiconductor chip 201 and another semiconductor chip stacked below the second semiconductor chip 201.

[0035] The second wiring structure 220 may be disposed below the first surface 210a of the second substrate 210. The second through electrode 250 may pass through the first substrate 210 in a vertical direction. The second through electrode 250 may be connected to the second wiring structure 220. In one embodiment, one end of the second through electrode 250 may pass through the second circuit insulating layer 221 and contact the wiring 225.

[0036] The second front pad 233 can be disposed below the second wiring structure 220. The second front pad 233 can contact the lower surface of the second chip pad 226 in the second wiring structure 220. The second front pad 233 can be electrically connected to the wiring 225 through the second chip pad 226.

[0037] The second front conductive bump 230 may be connected below the second front pad 233. The second front conductive bump 230 may include a second bump post 231 and a second solder layer 232 connected to the second bump post 231.

[0038] A second back insulating layer 270 may be disposed on a second surface 210b of a second substrate 210. A second back pad 241 may be disposed on the second back insulating layer 270 and the second through electrode 250. The second through electrode 250 may pass through the second back insulating layer 270 and may be connected to the second back pad 241. A second back conductive bump 240 may be disposed on the second back pad 241.

[0039] The upper surface of the second back conductive bump 240 can contact the lower surface of the first front conductive bump 130. The lower surface of the second front conductive bump 230 can contact the upper surface of the back conductive bump of the semiconductor chip located below the second semiconductor chip 201. The upper surface of the first back conductive bump 140 can contact the upper surface of the front conductive bump of the semiconductor chip located on the first semiconductor chip 101.

[0040] See Figure 2The first front conductive bump 130 may be disposed below the first front pad 133. The first front conductive bump 130 may include a first bump post 131 and a first solder layer 132. The first front pad 133 may include a first front barrier layer 133b, a first front seed layer 133s and a first front conductive layer 133c.

[0041] The upper surface of the first bump post 131 can contact the lower surface of the first front conductive layer 133c. The lower surface of the first bump post 131 can contact the upper surface of the first solder layer 132. The first solder layer 132 can be connected to the first bump post 131.

[0042] In one embodiment, the side surface of the first solder layer 132 may protrude further outward than the side surface of the first bump post 131. In one embodiment, the maximum width W2 of the first solder layer 132 may be greater than the width W1 of the first bump post 131. In one embodiment, the width of the first solder layer 132 may increase as it moves further away from the lower surface of the first bump post 131, and may decrease as it moves closer to the upper surface of the second back conductive bump 240. For example, the first solder layer 132 may have its maximum width W2 in the middle portion of its side surface.

[0043] The second back conductive bump 240 can be connected to the first front conductive bump 130. The upper surface of the second back conductive bump 240 can contact the lower surface of the first solder layer 132. The second back conductive bump 240 can include the same material as the material forming the first solder layer 132.

[0044] The second back pad 241 can be connected below the second back conductive bump 240. The second back pad 241 may include a second back barrier layer 241b, a second back seed layer 241s, and a second back conductive layer 241c. The lower surface of the second back barrier layer 241b can contact the upper surface of the second through electrode 250.

[0045] The second through electrode 250 can pass through the second substrate 210 and the second back insulating layer 270 to contact the lower surface of the second back barrier layer 241b. The second spacer 260 can surround the side surface of the second through contact 250.

[0046] See Figure 3 A first front conductive bump 330 may be disposed below the first front pad 133. The first front conductive bump 330 may include a first bump post 131 and a first solder layer 332. The lower surface of the first bump post 131 may contact the upper surface of the first solder layer 332. The first solder layer 332 may be connected to the first bump post 131.

[0047] In one embodiment, the side surface of the first solder layer 332 may protrude further outward than the side surface of the first bump post 131. In one embodiment, the maximum width W3 of the first solder layer 332 may be greater than the width W1 of the first bump post 131. In one embodiment, the width of the first solder layer 332 may increase as it moves away from the upper surface of the first bump post 131. For example, the first solder layer 332 may have its maximum width W3 at the portion that contacts the upper surface of the second back conductive bump 240.

[0048] A second back conductive bump 240 may be connected to a first front conductive bump 330. The upper surface of the second back conductive bump 240 may contact the lower surface of the first solder layer 332. In one embodiment, the width of the upper surface of the second back conductive bump 240 may be smaller than the width of the lower surface of the first solder layer 332. The second back conductive bump 240 may comprise the same material as the material forming the first solder layer 332.

[0049] See Figure 4 A first front conductive bump 430 may be disposed below the first front pad 133. The first front conductive bump 430 may include a first bump post 131 and a first solder layer 432. The lower surface of the first bump post 131 may contact the upper surface of the first solder layer 432. The first solder layer 432 may be connected to the first bump post 131.

[0050] In one embodiment, the side surface of the first solder layer 432 may be substantially coplanar with the side surface of the first bump post 131. In another embodiment, the width W4 of the first solder layer 432 may be substantially the same as the width W1 of the first bump post 131.

[0051] A second back conductive bump 240 may be connected to a first front conductive bump 430. The upper surface of the second back conductive bump 240 may contact the lower surface of the first solder layer 432. In one embodiment, the width of the upper surface of the second back conductive bump 240 may be the same as the width of the lower surface of the first solder layer 432. Alternatively, in another embodiment, the width of the upper surface of the second back conductive bump 240 may be different from the width of the lower surface of the first solder layer 432. The second back conductive bump 240 may comprise the same material as the material forming the first solder layer 432.

[0052] Figures 5 to 23 A diagram illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0053] See Figure 5A substrate 110 may be provided, having a first wiring structure 120 on a first surface 110a. The first wiring structure 120 may include a first circuit insulating layer 121, wiring 125, a guard ring 124, a first chip pad 126, and first protective insulating layers 122 and 123. A first through electrode 150 may be provided to pass through the first substrate 110 in a vertical direction and contact the wiring 125. Figure 5 As shown, a first spacer 160 can be provided on the side surface of the first through electrode 150.

[0054] The first substrate 110 may include a semiconductor substrate such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The first substrate 110 may include a III-V group semiconductor substrate, such as a compound semiconductor substrate such as GaAs. The first substrate 110 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof.

[0055] Wiring 125 and guard ring 124 may be disposed within the first circuit insulating layer 121. Guard ring 124 may include multiple conductive layers disposed on the same layer as wiring 125 and first chip pad 126.

[0056] The process for forming the first protective insulating layers 122 and 123 may include a thin film forming process and a patterning process.

[0057] The first circuit insulating layer 121 may be a single layer, or it may be two or more layers. The first circuit insulating layer 121 may include at least two materials selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), and boron (B). The first circuit insulating layer 121 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), low-k dielectric materials, high-k dielectric materials, or combinations thereof.

[0058] Each of the wiring 125, guard ring 124, first chip pad 126, and first through electrode 150 may include, for example, a metal, a metal silicide, a metal nitride, a metal oxide, polysilicon, conductive carbon, or a combination thereof. Each of the wiring 125, guard ring 124, first chip pad 126, and first through electrode 150 may include tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), nickel (Ni), silver (Ag), platinum (Pt), ruthenium (Ru), gold (Au), aluminum (Al), copper (Cu), tin (Sn), or a combination thereof. In one embodiment, the first chip pad 126 may include aluminum (Al).

[0059] See Figure 6A first barrier material layer 533b and a first seed material layer 533s can be sequentially formed on the first wiring structure 120. The first barrier material layer 533b can be in direct contact with the first chip pad 126. The first barrier material layer 533b may include titanium (Ti), titanium-tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The first seed material layer 533s may include copper (Cu).

[0060] See Figure 7 A mask pattern 600 can be formed on the first seed material layer 533s. The mask pattern 600 may include photoresist. The mask pattern 600 may expose the portion of the first seed material layer 533s that overlaps with the first chip pad 126.

[0061] See Figure 8 The first front conductive layer 133c, the first bump pillar 131, and the first solder layer 132 can be sequentially formed on the first seed material layer 533s in the area where the mask pattern 600 is not formed. The first front conductive layer 133c can include, for example, a metal, a metal nitride, or a combination thereof. The first front conductive layer 133c can include copper (Cu), tungsten (W), tungsten nitride (WN), titanium (Ti), tungsten titanate (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), nickel (Ni), silver (Ag), platinum (Pt), ruthenium (Ru), gold (Au), aluminum (Al), tin (Sn), or a combination thereof. In one embodiment, the first front conductive layer 133c can include a copper layer formed using an electroplating method. The first bump pillar 131 can include copper. The first solder layer 132 can include copper, nickel, tin, silver, or a combination thereof.

[0062] The upper surface of the first solder layer 132 is shown as coplanar with the upper surface of the mask pattern 600, but the embodiment is not limited thereto. For example, the first solder layer 132 may protrude above the upper surface of the mask pattern 600.

[0063] See Figure 9 The mask pattern 600 can be removed, and the first barrier material layer 533b and the first seed material layer 533s can be partially removed to form the first front pad 133. The first front pad 133 may include, for example, Figure 2 The first front barrier layer 133b, the first front seed layer 133s, and the first front conductive layer 133c are laminated in the order shown.

[0064] See Figure 10 A reflow soldering process can be performed, which applies heat to the first solder layer 132. Through the reflow soldering process, at least a portion of the first solder layer 132 can be melted. In one embodiment, the first solder layer 132 can protrude outward from the side surface of the first bump post 131 via the reflow soldering process.

[0065] See Figure 11 A first insulating layer 1000 may be formed on the first wiring structure 120 and the first solder layer 132. The first insulating layer 1000 may be formed at a position above the upper surface of the first solder layer 132. The first insulating layer 1000 may include oxides or nitrides.

[0066] See Figure 12 At least a portion of the first insulating layer 1000 can be removed. The process of removing at least a portion of the first insulating layer 1000 may include a chemical mechanical polishing (CMP) process. The first insulating layer 1000 can be removed to expose the upper surface of the first solder layer 132.

[0067] Subsequently, a planarization or leveling process can be performed on the upper surface of the first solder layer 132. The planarization process of the upper surface of the first solder layer 132 can be performed simultaneously with the process of removing at least a portion of the first insulating layer 1000. In one embodiment, the planarization process of the upper surface of the first solder layer 132 may include a chemical mechanical polishing (CMP) process. In one embodiment, after planarizing the upper surface of the first solder layer 132, the upper surface of the first insulating layer 1000 may form substantially the same plane as the upper surface of the first solder layer 132.

[0068] See Figure 13 The first insulating layer 1000 can be completely removed. The process for removing the first insulating layer 1000 may include, for example, a wet etching process.

[0069] See Figure 14 A first substrate 110, on which a first front conductive bump 130 and a first front pad 133 are formed, is mounted on a carrier 1320. A first buffer layer 1310 may be formed between the carrier 1320 and the first front conductive bump 130.

[0070] See Figure 15 The first substrate 110 can be partially removed to expose the first through electrode 150. One surface of the first substrate 110 can be formed at a position below the top of the first through electrode 150.

[0071] See Figure 16 A first back insulating layer 170 can be formed on the second surface 110b of the first substrate 110. When the first back insulating layer 170 is formed, the upper surface of the first through electrode 150 can be exposed. In one embodiment, the upper surface of the first back insulating layer 170 and the upper surface of the first through electrode 150 can form substantially the same plane.

[0072] See Figure 17A first barrier material layer 1641b and a first seed material layer 1641s may be sequentially formed on the upper surface of the first back insulating layer 170. The first barrier material layer 1641b may include titanium (Ti), titanium-tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. The first seed material layer 1641s may include copper. The first barrier material layer 1641b may include materials similar to those described above. Figure 6 The first barrier material layer 533b described herein is the same material. The first seed material layer 1641s may include the same material as described above. Figure 6 The first seed material layer 533s is the same material as described.

[0073] See Figure 18 A mask pattern 1710 can be formed on the first seed material layer 1641s. The mask pattern 1710 may include elements similar to those described above. Figure 7 The mask pattern 600 described is made of the same material. For example, mask pattern 1710 may include photoresist.

[0074] The mask pattern 1710 can expose the upper surface of the first seed material layer 1641s in the region that overlaps with the region where the first through electrode 150 is disposed.

[0075] See Figure 19 The first back conductive layer 141c and the first back conductive bump 140 can be sequentially formed on the first seed material layer 1641s in the area where the mask pattern 1710 is not set.

[0076] The first back conductive layer 141c may include, for example, a metal, a metal nitride, or a combination thereof. The first back conductive layer 141c may include copper, tungsten, tungsten nitride, titanium, tungsten titanate, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, silver, platinum, ruthenium, gold, aluminum, tin, or a combination thereof. In one embodiment, the first back conductive layer 141c may include a copper layer formed using an electroplating method. The first back conductive bump 140 may include the same material as the material forming the first solder layer 132. The first back conductive bump 140 may include copper, nickel, tin, silver, or a combination thereof.

[0077] See Figure 19 and Figure 20 The mask pattern 1710 can be removed. When removing the mask pattern 1710, the first seed material layer 1641s and the first barrier material layer 1641b disposed in the region overlapping with the mask pattern 1710 can also be removed together with the mask pattern 1710. The mask pattern 1710, the first seed material layer 1641s, and the first barrier material layer 1641b can be removed to expose the upper surface of the first back insulating layer 170. Removing the mask pattern 1710, the first seed material layer 1641s, and the first barrier material layer 1641b may include an etching process.

[0078] See Figure 20 and Figure 21 The carrier 1320 and the first buffer layer 1310 can be removed to expose at least a portion of the first front conductive bump 130, the first front pad 133, and the lower surface of the first protective insulating layer 123. For example, at least a portion of the side surface of the first front barrier layer 133b, the side surface of the first front seed layer 133s, and the side surface of the first front conductive layer 133c can be exposed.

[0079] See Figure 22 The first semiconductor chip 101 may be located on top of the second semiconductor chip 201. For example, the first semiconductor chip 101 may be stacked or laminated on the second semiconductor chip 201.

[0080] The process of stacking the first semiconductor chip 101 onto the second semiconductor chip 201 may include a reflow soldering process and a compression process. In the reflow soldering process, the second back conductive bump 240 is heated such that at least a portion of the second back conductive bump 240 melts. Because at least a portion of the second back conductive bump 240 is melted, the second back conductive bump 240 may have a shape that protrudes outward from the side surface of the second back pad 241. The compression process involves applying pressure to the chips to ensure a strong and reliable connection between them.

[0081] See Figure 23 Encapsulation layers 301, 302, and 303 can be formed to fill the space between semiconductor chips. For example, a second encapsulation layer 302 can be formed to fill the space between the first semiconductor chip 101 and the second semiconductor chip 201. The second encapsulation layer 302 can fill the space between the first front conductive bumps 130, the space between the second back conductive bumps 240, the space between the first front pads 133, the space between the second back pads 241, and the space between the second back insulating layer 270 and the first protective insulating layer 123. Encapsulation layers 301, 302, and 303 may include an epoxy molding compound.

[0082] Figures 24 to 27 The figure illustrates another method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0083] Figure 24 The first substrate 110, first wiring structure 120, first through electrode 150, first spacer 160, first barrier material layer 2333b, first seed material layer 2333s, first front conductive layer 133c, first bump pillar 131, first solder layer 432, and mask pattern 600 shown can be compared with those in the previous section. Figures 5 to 8 The semiconductor package manufacturing method described is basically the same as that used to form it.

[0084] See Figure 24 A reflow soldering process can be performed to apply heat to the first solder layer 432. At least a portion of the first solder layer 432 can be melted by the reflow soldering process. The first solder layer 432 can protrude above the upper surface of the mask pattern 600. For example, at least a portion of the first solder layer 432 can cover the upper surface of the mask pattern 600.

[0085] As the reflow soldering process proceeds, the mask pattern 600 can harden, ensuring that the side surface of the first solder layer 432 does not protrude beyond the side surface of the first bump post 131. In one embodiment, after the reflow soldering process, the width of at least a portion of the first solder layer 432 may be substantially the same as the width of the first bump post 131. Here, "substantially the same" may include a situation where, due to process errors, the side surface of the first solder layer 432 slightly protrudes beyond the side surface of the first bump post 131.

[0086] See Figure 25 A planarization or flattening process can be performed on the upper portion of the first solder layer 432. The planarization process can remove portions of the first solder layer 432 that protrude above the upper surface (e.g., the top) of the mask pattern 600. Planarization of the upper portion of the first solder layer 432 can include a chemical mechanical polishing process. After the upper portion of the first solder layer 432 is planarized, the upper surface of the first solder layer 432 can be formed into a plane substantially the same as the upper surface of the mask pattern 600.

[0087] See Figure 26 This allows for the removal of the mask pattern 600 and partial removal of the first blocking material layer 2333b and the first seed material layer 2333s, enabling the formation of the first front pad 133 and the first front conductive bump 430. The first front pad 133 may include, for example: Figure 4 The first front barrier layer 133b, the first front seed layer 133s, and the first front conductive layer 133c are stacked in the order shown. The first front conductive bump 430 may include a first bump post 131 and a first solder layer 432.

[0088] After the first front conductive bump 430 is formed, a back conductive bump can be formed below the first substrate 110. The back conductive bump can be formed in conjunction with [see reference 1]. Figures 14 to 21 The methods described for manufacturing semiconductor packages are formed in essentially the same way.

[0089] After forming the back conductive bump, the back conductive bump can be connected to the front conductive bump included in another semiconductor chip, and in accordance with [see reference]. Figures 24 to 26 The first front conductive bump 130 described is formed in the same manner.

[0090] See Figure 27The first semiconductor chip 101 can be located on top of the second semiconductor chip 201a. The first semiconductor chip 101 can be stacked on the second semiconductor chip 201.

[0091] The process of stacking the first semiconductor chip 101 on the second semiconductor chip 201 may include connecting a first front conductive bump 430 to a second back conductive bump 240 and then performing a reflow soldering process and a compression process. At least a portion of the second back conductive bump 240 may be melted by the reflow soldering process. Since at least a portion of the second back conductive bump 240 is melted, the second back conductive bump 240 may have a shape that protrudes outward from the side surface of the second back pad 241.

[0092] In one embodiment, the width of the first solder layer 432 may be substantially the same as the width of the first bump post 131. In another embodiment, after the reflow soldering process, the width of the first solder layer 432 may be smaller than the width of the second back conductive bump 240.

[0093] See you again Figures 1 to 3 as well as Figures 10 to 12 A first solder layer 132 can be formed, and a reflow soldering process can be performed to melt at least a portion of the first solder layer 132. After the reflow soldering process, a process for planarizing the upper surface of the first solder layer 132 can be performed. Alternatively, see again. Figure 4 and Figures 24 to 26 A first solder layer 432 can be formed, and a reflow soldering process can be performed to melt at least a portion of the first solder layer 432. After the reflow soldering process, a process for planarizing the upper surface of the first solder layer 432 can be performed.

[0094] According to embodiments of this disclosure, a process for planarizing the upper surface of the front conductive bump can be performed after the reflow soldering process of the front conductive bump. The front conductive bump can then be connected to a back conductive bump included in another semiconductor chip. Because the process of planarizing the upper surface of the front conductive bump is performed before connecting the front and back conductive bumps, i.e., because a portion of the front conductive bump is removed, short circuits between adjacent bumps due to bump volume increase during the reflow soldering process can be prevented.

[0095] Furthermore, since the upper surface of the front conductive bump is planarized, the bonding interface between the bumps can also be planarized. Additionally, because the size of the front conductive bump is reduced, the overall area occupied by the bumps can be reduced. Therefore, precise bonding and lamination between semiconductor chips can be achieved.

[0096] The foregoing description and accompanying drawings provide the technical concept of this disclosure for illustrative purposes only. Those skilled in the art will readily understand that various modifications, additions, and substitutions can be made to the described embodiments without departing from the spirit and scope of this disclosure. Furthermore, since the embodiments disclosed in this disclosure are not intended to limit the technical concept of this disclosure, but rather to describe it, the scope of the technical concept of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and all technical concepts within the equivalent scope should be interpreted as including within the scope of this disclosure. In addition, embodiments can be combined to form additional embodiments.

Claims

1. A method for manufacturing a semiconductor package, the method comprising: A through electrode is formed in a substrate, the substrate including a first surface and a second surface opposite to each other; A front conductive bump is formed on the first surface of the substrate; The front conductive bump is reflow soldered; as well as After reflow soldering the front conductive bump, the upper part of the front conductive bump is planarized.

2. The manufacturing method according to claim 1 further includes: A first insulating layer is formed between reflow soldering the front conductive bump and planarizing the upper portion of the front conductive bump to cover the front conductive bump.

3. The manufacturing method according to claim 2, wherein, By planarizing the upper part of the front conductive bump, the upper surface of the first insulating layer and the upper surface of the front conductive bump form substantially the same plane.

4. The manufacturing method according to claim 2 further includes: The first insulating layer is removed after the upper portion of the front conductive bump is planarized.

5. The manufacturing method according to claim 1, wherein, The front conductive bump includes a bump post and a solder layer connected to the bump post. The planarization of the upper part of the front conductive bump includes the planarization of the upper part of the solder layer.

6. The manufacturing method according to claim 5, wherein, The maximum width of the solder layer is greater than the width of the bump post.

7. The manufacturing method according to claim 5, wherein, The maximum width of the solder layer is approximately equal to the width of the bump post.

8. The manufacturing method according to claim 1, further comprising: A back conductive bump connected to the through electrode is formed on the second surface of the substrate; as well as The back conductive bumps are reflow soldered.

9. The manufacturing method according to claim 1, wherein, Forming the front conductive bump includes: A mask pattern is formed on the first surface of the substrate; and Conductive material is formed in areas other than the area where the mask pattern is set.

10. The manufacturing method according to claim 9, wherein, By planarizing the upper part of the front conductive bump, the upper surface of the mask pattern and the upper surface of the front conductive bump form substantially the same plane.

11. The manufacturing method according to claim 9, further comprising: The mask pattern is removed after the upper portion of the front conductive bump is flattened.

12. The manufacturing method according to claim 9, further comprising: A back conductive bump connected to the through electrode is formed on the second surface of the substrate; as well as The back conductive bumps are reflow soldered.

13. A method for manufacturing a semiconductor package, the method comprising: A first conductive bump is formed on a first surface of a first semiconductor chip, and the first semiconductor chip further includes a second surface opposite to the first surface; The first front conductive bump is reflow soldered. After reflow soldering the first front conductive bump, the upper part of the first front conductive bump is planarized. A second back conductive bump is formed on a second surface of a second semiconductor chip, the second semiconductor chip including a first surface and a second surface opposite to each other and stacked below the first surface of the first semiconductor chip; as well as After flattening the upper portion of the first front conductive bump, the second back conductive bump is connected to the first front conductive bump.

14. The manufacturing method according to claim 13, further comprising: Between reflow soldering the first front conductive bump and planarizing the upper portion of the first front conductive bump, a first insulating layer is formed to cover the first front conductive bump.

15. The manufacturing method according to claim 14, wherein, By planarizing the upper part of the first front conductive bump, the upper surface of the first insulating layer and the upper surface of the first front conductive bump form substantially the same plane.

16. The manufacturing method according to claim 14, further comprising: After planarizing the upper portion of the first front conductive bump, the first insulating layer is removed.

17. The manufacturing method according to claim 13, wherein, Forming the first front conductive bump includes: A mask pattern is formed on the first surface of the first semiconductor chip; and Conductive material is formed in areas other than the area where the mask pattern is set.

18. The manufacturing method according to claim 17, wherein, By planarizing the upper part of the first front conductive bump, the upper surface of the mask pattern and the upper surface of the first front conductive bump form substantially the same plane.

19. The manufacturing method according to claim 17, further comprising: The mask pattern is removed after the upper portion of the first front conductive bump is flattened.

20. A method for manufacturing a semiconductor package, the method comprising: A first semiconductor chip is provided, comprising a first surface and a second surface that are opposite to each other. A second semiconductor chip is provided, comprising a first surface and a second surface that are opposite to each other; A first conductive bump is formed on the first surface of the first semiconductor chip; A second back conductive bump is formed on the second surface of the second semiconductor chip; The upper part of the first front conductive bump is reflow soldered and planarized. as well as The second semiconductor chip is stacked below the first surface of the first semiconductor chip, such that after the upper part of the first front conductive bump is planarized, the second back conductive bump contacts the first front conductive bump.

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