Silicon optical device and manufacturing method thereof
By bonding an oxide layer onto the buried oxide layer to increase its thickness, the problem of insufficient buried oxide layer thickness in the prior art is solved, the performance of silicon photonic devices is improved and insertion loss is reduced, while production costs are controlled.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUHAN XINXIN SEMICON MFG CO LTD
- Filing Date
- 2025-10-22
- Publication Date
- 2026-05-26
AI Technical Summary
The buried oxide layer in existing SOI substrates is relatively thin, which affects the performance of silicon photonic devices and increases production costs.
By bonding oxide layers onto the buried oxide layer to increase its thickness, the process becomes more flexible and controllable, meeting the requirements of high-quality silicon photonic devices while avoiding a significant increase in cost.
This improves the performance of silicon photonic devices, reduces insertion loss, and does not affect the structure and performance of the original SOI substrate, thus reducing production costs.
Smart Images
Figure CN122085447A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a silicon photonic device and its manufacturing method. Background Technology
[0002] With the rapid development of integrated circuit technology, the application of bulk silicon substrates in integrated circuits is approaching its limit, thus SOI (Silicon on Insulator) substrates have emerged. Compared with bulk silicon substrates, SOI substrates have significant advantages, such as reduced parasitic capacitance, increased operating speed, reduced leakage current, and lower insertion loss. Furthermore, SOI substrates are compatible with existing bulk silicon integrated circuit technologies, enabling their rapid and widespread application in the integrated circuit field.
[0003] The thickness of the buried oxide layer (BOX) in existing SOI substrates is determined by the SOI substrate manufacturing process. After the SOI substrate leaves the wafer fab, its buried oxide layer thickness is a fixed value, currently typically less than or equal to 3 μm. Such SOI substrates facilitate subsequent processes, such as the adsorption of SOI substrates by electrostatic chucks. However, a thinner buried oxide layer is not conducive to improving the performance of silicon photonics chips. Summary of the Invention
[0004] The purpose of this invention is to provide a silicon photonic device and its manufacturing method to solve the problem of thin buried oxide layer in silicon photonic devices in the prior art.
[0005] To address the aforementioned technical problems, the present invention provides a silicon photonic device, the silicon photonic device comprising:
[0006] silicon substrate;
[0007] Oxide layer located on the silicon substrate;
[0008] A buried oxide layer is located on the oxide growth layer, the buried oxide layer and the oxide growth layer are bonded together; and,
[0009] A silicon photonics device layer located on the buried oxide layer.
[0010] Optionally, in the silicon photonic device, the silicon photonic device layer and the oxide augmentation layer are located on opposite sides of the buried oxide layer.
[0011] Optionally, in the silicon photonic device, the sum of the thicknesses of the oxide layer and the buried oxide layer is greater than 3 μm.
[0012] Optionally, in the silicon photonic device, the sum of the thicknesses of the oxide layer and the buried oxide layer is 4 μm, 4.5 μm, 5 μm, 5.5 μm, or 6 μm.
[0013] Optionally, in the silicon photonic device, the thickness of the buried oxide layer is less than or equal to 3 μm.
[0014] Optionally, in the silicon photonic device, the oxide layer is selected from the buried oxide layer in the SOI wafer.
[0015] Optionally, in the silicon photonic device, the oxide overlay is formed by a thermal oxidation process.
[0016] Optionally, in the silicon photonic device, the silicon substrate is selected from the top silicon layer or the bottom silicon layer in the SOI wafer.
[0017] Optionally, in the silicon photonic device, the oxide layer and the silicon substrate are selected from the buried oxide layer and top silicon layer in the SOI wafer, or the buried oxide layer and bottom silicon layer.
[0018] Optionally, in the silicon photonic device, the silicon photonic device layer includes a waveguide structure, and the distance between the center point of the waveguide structure and the surface of the silicon substrate is between 4 μm and 10 μm.
[0019] Optionally, in the silicon photonic device, the silicon photonic device is used to connect to an optical fiber interface, and the silicon photonic device layer includes a waveguide structure. In the thickness direction of the silicon photonic device, the center of the waveguide structure is aligned with the center of the optical fiber interface; or, the height difference between the center of the waveguide structure and the center of the optical fiber interface is less than or equal to 1 μm; or, the height difference between the center of the waveguide structure and the center of the optical fiber interface is less than or equal to 0.5 μm; or, the height difference between the center of the waveguide structure and the center of the optical fiber interface is less than or equal to 0.1 μm.
[0020] The present invention also provides a method for manufacturing a silicon photonic device, the method comprising:
[0021] An SOI substrate is provided, the SOI substrate comprising a bottom silicon layer, a buried oxide layer and a top silicon layer stacked sequentially;
[0022] A semiconductor process is performed on the top silicon layer to form a silicon photonics device layer on the buried oxide layer;
[0023] A substrate is stacked on the silicon photonics device layer;
[0024] Remove the underlying silicon layer to expose the buried oxide layer;
[0025] An oxide uplift layer and a silicon substrate are bonded and stacked on the buried oxide layer; and,
[0026] Remove the substrate.
[0027] Optionally, in the method for manufacturing the silicon photonic device, performing a semiconductor process on the top silicon layer to form a silicon photonic device layer on the buried oxide layer includes:
[0028] Perform a first semiconductor process on the top silicon layer to form a first silicon photonic device layer; and,
[0029] A second semiconductor process is performed on the first silicon photonic device layer to form a second silicon photonic device layer;
[0030] The silicon photonic device layer includes a first silicon photonic device layer and a second silicon photonic device layer.
[0031] Optionally, in the method for manufacturing the silicon photonic device, performing a semiconductor process on the top silicon layer to form a silicon photonic device layer on the buried oxide layer includes: performing a first semiconductor process on the top silicon layer to form a first silicon photonic device layer, wherein the silicon photonic device layer includes the first silicon photonic device layer.
[0032] After removing the carrier wafer, the method for manufacturing the silicon photonic device further includes performing a second semiconductor process on the first silicon photonic device layer to form a second silicon photonic device layer.
[0033] In the silicon photonic device and its manufacturing method provided by the present invention, the thickness of the buried oxide functional layer is increased by bonding an oxide layer on the buried oxide layer. The formation process and the increased thickness are more flexible and controllable, which can meet the requirements of high-quality silicon photonic devices and avoid a significant increase in cost. Attached Figure Description
[0034] Figure 1 This is a schematic diagram of the structure of a silicon photonic device according to an embodiment of the present invention.
[0035] Figure 2 This is a schematic diagram of the connection between a silicon photonic device and an external device according to an embodiment of the present invention.
[0036] Figure 3 This is a schematic flowchart of a method for manufacturing silicon photonic devices according to an embodiment of the present invention.
[0037] Figure 4 This is a schematic flowchart of the manufacturing method of the silicon photonic device according to Embodiment 1 of the present invention.
[0038] Figures 5 to 11 This is a cross-sectional schematic diagram of the device structure formed by implementing the manufacturing method of the silicon photonic device according to Embodiment 1 of the present invention.
[0039] Figure 12 This is a schematic flowchart of the manufacturing method of the silicon photonic device according to Embodiment 2 of the present invention.
[0040] Figures 13 to 19This is a cross-sectional schematic diagram of the device structure formed by implementing the silicon photonics device manufacturing method of Embodiment 2 of the present invention.
[0041] The reference numerals in the attached figures are explained as follows:
[0042] 10-Silicon photonic device; 11-Silicon substrate; 12-Oxide addition layer; 13-Buried oxide layer; 14-Silicon photonic device layer; 14S-Waveguide structure; 15-Fiber optic interface; H-Thickness direction; T1, T2-Center.
[0043] 10A - Silicon photonic device; 10B, 10C - Semiconductor structure; 100 - SOI substrate; 101 - Bottom silicon layer; 102 - Buried oxide layer; 103 - Top silicon layer; 110 - Silicon photonic device layer; 111 - First silicon photonic device layer; 1110 - Waveguide structure; 112 - Second silicon photonic device layer; 120 - Carrier; 121 - Bonding layer; 130 - Oxide addition layer; 140 - Silicon substrate.
[0044] 20A - Silicon photonic device; 20B, 20C - Semiconductor structure; 200 - SOI substrate; 201 - Bottom silicon layer; 202 - Buried oxide layer; 203 - Top silicon layer; 210 - Silicon photonic device layer; 211 - First silicon photonic device layer; 212 - Second silicon photonic device layer; 220 - Carrier; 221 - Bonding layer; 230 - Oxide addition layer; 240 - Silicon substrate. Detailed Implementation
[0045] The silicon photonics device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0046] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless otherwise defined in this application, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise indicated, terms such as "upper / upper layer," "lower / lower layer," and similar terms are for ease of description only and are not limited to a location or spatial orientation. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed following "comprising" or "including" and its equivalents, and does not exclude other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0047] In existing technologies, SOI substrates are manufactured in wafer fabs with a fixed thickness, typically less than or equal to 3 μm. To improve the performance of some semiconductor devices and reduce insertion loss, a thicker buried oxide layer is required. If a thicker buried oxide layer is formed during the production of SOI substrates in the wafer fab, firstly, it does not conform to the existing wafer fab standards, significantly increasing production costs; secondly, SOI substrates with a thicker buried oxide layer will encounter some problems during transportation, such as difficulty in gripping by robotic arms and poor adhesion of electrostatic chucks leading to wafer breakage.
[0048] This invention increases the thickness of the buried oxide layer, a functional layer, by bonding an oxide layer onto the buried oxide layer. The formation process and the increased thickness are more flexible and controllable, which can meet the requirements of high-quality silicon photonic devices while avoiding a significant increase in cost.
[0049] Please refer to Figure 1 This is a schematic diagram of the silicon photonics device according to an embodiment of the present invention. Figure 1As shown in the embodiments of this application, the silicon photonic device 10 includes: a silicon substrate 11; an oxide layer 12 located on the silicon substrate 11; a buried oxide layer 13 located on the oxide layer 12, wherein the buried oxide layer 13 and the oxide layer 12 are bonded together; and a silicon photonic device layer 14 located on the buried oxide layer 13.
[0050] The silicon photonic device layer 14 and the oxide augmentation layer 12 are located on opposite sides of the buried oxide layer 13. In this embodiment, the thickness of the buried oxide layer 13 is increased on its back side. This does not affect the interface between the buried oxide layer 13 and the silicon photonic device layer 14, but it also increases the thickness of the buried oxide layer 13, a functional layer, which can improve the performance of the silicon photonic device 10 and reduce its insertion loss.
[0051] In the embodiments of this application, the silicon substrate 11, the dielectric layer 12, the buried oxide layer 13, and the device functional layer 14 can be a single-layer structure or a multi-layer structure.
[0052] In this embodiment, the sum of the thicknesses of the oxide build-up layer 12 and the buried oxide layer 13 is greater than 3 μm. In some embodiments of this application, the sum of the thicknesses of the oxide build-up layer 12 and the buried oxide layer 13 may be greater than or equal to 4 μm, for example, the sum of the thicknesses of the oxide build-up layer 12 and the buried oxide layer 13 may be 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, or 6.5 μm, etc.
[0053] In this embodiment, the thickness of the buried oxide layer 13 can be increased by bonding an oxide augmentation layer 12 to the buried oxide layer 13. The formation process and the increased thickness are more flexible and controllable, which can meet the requirements of high-quality silicon photonic devices and avoid a significant increase in cost.
[0054] In some embodiments of this application, the thickness of the buried oxide layer 13 can be less than or equal to 3 μm. For example, the thickness of the buried oxide layer 13 can be 3 μm, 2.5 μm, or 2 μm. Using a thinner buried oxide layer 13 can reduce the cost of the SOI substrate and simplify the transfer of the SOI substrate.
[0055] In this embodiment, the oxide layer 12 and the buried oxide layer 13 are made of the same material, silicon oxide, which better enables the buried oxide layer 13 to perform its function. The oxide layer 12 can be formed by a thermal oxidation process. In some embodiments of this application, the oxide layer 12 is selected from the buried oxide layer in the SOI wafer; that is, the oxide layer 12 and the buried oxide layer 13 can be the first buried oxide layer and the second buried oxide layer, respectively. In some embodiments of this application, the silicon substrate 11 is selected from the top silicon layer or the bottom silicon layer in the SOI wafer. The silicon substrate and the original bottom silicon layer, the oxide layer, and the buried oxide layer have a high degree of consistency, minimizing the structural and performance damage of the "thickening process / structure" to the original SOI substrate, and greatly reducing the impact on upstream and downstream devices and processes.
[0056] In some embodiments of this application, the thickness of the oxide layer 12 and the buried oxide layer 13 may be the same, for example, both may be 3 μm; or, in some embodiments of this application, both may be 2 μm, 2.5 μm, 3 μm, etc. In other embodiments of this application, the thickness of the oxide layer 12 and the buried oxide layer 13 may be different. For example, the thickness difference between the oxide layer 12 and the buried oxide layer 13 may be less than or equal to 10% of the thickness of the thinner one. For example, the thickness of the oxide layer 12 is 3.1 μm, the thickness of the buried oxide layer 13 is 3 μm, and the thickness difference between the oxide layer 12 and the buried oxide layer 13 is 0.1 μm, which is less than 10% of the thickness of the thinner buried oxide layer 13.
[0057] In some embodiments of this application, the oxide build-up layer 12 is made of the same material as the buried oxide layer 13. For example, in some embodiments, the oxide build-up layer 12 and the buried oxide layer 13 can be films in SOI substrates produced by the same wafer fab; the thickness of the oxide build-up layer 12 is similar to or even the same as the thickness of the buried oxide layer 13. Therefore, the properties of the oxide build-up layer 12 and the buried oxide layer 13 are also more similar to or even the same, thereby better realizing the function of the buried oxide layer 13.
[0058] For further details, please refer to... Figure 2 This is a schematic diagram illustrating the connection between a silicon photonics device and an external device according to an embodiment of the present invention. Figure 2 As shown, the silicon photonic device layer 14 includes a waveguide structure 14S, and the external device is an optical fiber interface 15. The silicon photonic device 10 is connected to the optical fiber interface 15 along its axial direction. In this embodiment, due to the presence of the oxide build-up layer 12, the connection between the silicon photonic device 10 and the optical fiber interface 15 is more flexible, improving the connection effect and reducing insertion loss. Figure 2As shown in this embodiment, in the thickness direction H of the silicon photonic device 10, the height difference between the center T1 of the waveguide structure 14S and the center T2 of the fiber optic interface 15 is less than or equal to 1 μm. That is, in the thickness direction H of the silicon photonic device 10, the center T1 of the waveguide structure 14S is higher or lower than the center T2 of the fiber optic interface 15, and the distance is less than or equal to 1 μm. In some embodiments of this application, in the thickness direction H of the silicon photonic device 10, the height difference between the center T1 of the waveguide structure 14S and the center T2 of the fiber optic interface 15 is less than or equal to 0.5 μm, 0.3 μm, 0.1 μm, etc. In some embodiments, in the thickness direction H of the silicon photonic device 10, the center T1 of the waveguide structure 14S and the center T2 of the fiber optic interface 15 can be aligned, thereby greatly reducing insertion loss. In this embodiment, due to the presence of the oxide build-up layer 12, the fiber optic interface 15 has a larger vertical movement space, that is, it can be aligned with the center T1 of the waveguide structure 14S by moving up and down, improving the performance of the device.
[0059] In some embodiments of this application, the distance between the center point of the waveguide structure 14S and the surface of the silicon substrate 11 is between 4μm and 10μm. For example, the distance between the center point of the waveguide structure 14S and the surface of the silicon substrate 11 is 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, or 10μm, which is more conducive to aligning the center point of the waveguide structure 14S with external devices, such as the center T2 of the optical fiber interface 15.
[0060] Accordingly, this application also provides a method for manufacturing a silicon photonic device. Please refer to [link / reference]. Figure 3 This is a schematic flowchart illustrating the manufacturing method of a silicon photonic device according to an embodiment of the present invention. Figure 2 As shown, the method for manufacturing the silicon photonic device includes:
[0061] Step S100: Provide an SOI substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide layer and a top silicon layer stacked sequentially;
[0062] Step S110: Perform a semiconductor process on the top silicon layer to form a silicon photonics device layer on the buried oxide layer;
[0063] Step S120: Stack a wafer on the silicon photonics device layer;
[0064] Step S130: Remove the underlying silicon layer to expose the buried oxide layer;
[0065] Step S140: Bonding the stacked oxide build-up layer and silicon substrate onto the buried oxide layer; and,
[0066] Step S150: Remove the substrate.
[0067] Steps S100, S110, S120, S130, S140, and S150 are merely identifiers for ease of description and do not restrict the order of the steps.
[0068] The process of performing a semiconductor process on the top silicon layer to form a silicon photonic device layer on the buried oxide layer may include: performing a first semiconductor process on the top silicon layer to form a first silicon photonic device layer; and performing a second semiconductor process on the first silicon photonic device layer to form a second silicon photonic device layer; wherein the silicon photonic device layer includes the first silicon photonic device layer and the second silicon photonic device layer.
[0069] Performing a semiconductor process on the top silicon layer to form a silicon photonic device layer on the buried oxide layer may also include performing a first semiconductor process on the top silicon layer to form a first silicon photonic device layer, wherein the silicon photonic device layer includes the first silicon photonic device layer.
[0070] In some embodiments, the second semiconductor process is not only used to form the second silicon photonic device layer, but the metal interconnects formed by the second semiconductor process can extend into the first silicon photonic device layer to form a connection with the silicon photonic structure in the first silicon photonic device layer.
[0071] Using the silicon photonics device and manufacturing method described in this case, the oxide layer is stacked on the side of the buried oxide layer away from the top silicon layer, which does not damage the interface between the buried oxide layer and the top silicon layer in the original SOI substrate, thus ensuring the performance of the device manufactured on the top silicon layer. In some embodiments, the oxide layer and the last retained silicon substrate adopt the buried oxide layer and bottom silicon layer / top silicon layer in the SOI wafer product, ensuring the consistency between the oxide layer and the buried oxide layer, and the interface between the oxide layer and the silicon substrate is not damaged. In particular, when using SOI substrates produced by the same wafer fab, the silicon substrate and the original bottom silicon layer, the oxide layer and the buried oxide layer have a high degree of consistency, which minimizes the damage to the structure and performance of the original SOI substrate caused by the "thickening process / structure", greatly reducing the impact on the devices and processes before and after.
[0072] Next, the silicon photonics device and its manufacturing method of this application will be further described through two embodiments.
[0073] Example 1
[0074] Please refer to Figure 4 This is a schematic flowchart illustrating the manufacturing method of the silicon photonic device according to Embodiment 1 of the present invention. Figure 4 As shown in Embodiment 1 of this application, the method for manufacturing the silicon photonic device includes:
[0075] Step S200: Provide an SOI substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide layer and a top silicon layer stacked sequentially;
[0076] Step S210: Perform a first semiconductor process on the top silicon layer to form a first silicon photonic device layer;
[0077] Step S220: Perform a second semiconductor process on the first silicon photonic device layer to form a second silicon photonic device layer;
[0078] Step S230: Stack a wafer on the second silicon photonics device layer;
[0079] Step S240: Remove the underlying silicon layer to expose the buried oxide layer;
[0080] Step S250: Bonding the stacked oxide layer and silicon substrate onto the buried oxide layer; and,
[0081] Step S260: Remove the carrier.
[0082] In Embodiment 1 of this application, performing a semiconductor process on the top silicon layer to form a silicon photonic device layer on the buried oxide layer includes:
[0083] Step S210: Perform a first semiconductor process on the top silicon layer to form a first silicon photonic device layer; and,
[0084] Step S220: Perform a second semiconductor process on the first silicon photonic device layer to form a second silicon photonic device layer;
[0085] The silicon photonic device layer includes a first silicon photonic device layer and a second silicon photonic device layer.
[0086] In Embodiment 1 of this application, before bonding the oxide layer on the buried oxide layer, a first semiconductor process and a second semiconductor process are performed to form a first silicon photonic device layer and a second silicon photonic device layer.
[0087] Specifically, such as Figure 5 As shown, an SOI substrate 100 is provided, which includes a bottom silicon layer 101, a buried oxide layer 102, and a top silicon layer 103 stacked sequentially. In the embodiments of this application, the SOI substrate 100 can be a conventional SOI substrate from a wafer fab, for example, the thickness of its buried oxide layer 102 is 3 μm; in some other embodiments, the thickness of the buried oxide layer 102 can also be 2 μm.
[0088] Next, as Figure 6As shown, a first semiconductor process is performed on the top silicon layer 103 to form a first silicon photonic device layer 111. The first silicon photonic device layer 111 may include, for example, one or more functional devices such as a device isolation layer (not shown), a waveguide structure 1110 located in the device isolation layer, a grating coupler (not shown), a strip waveguide (not shown), a ridge waveguide (not shown), a lateral PIN photodetector (not shown), and / or a Mach-Zehnder modulator (not shown).
[0089] like Figure 7 As shown in this embodiment, a second semiconductor process is then performed on the first silicon photonics layer 111 to form a second silicon photonics layer 112. The second silicon photonics layer 112 may include, for example, an interconnect layer. In some embodiments of this application, the second silicon photonics layer 112 may also include functional devices, such as a thermal imager. In some embodiments of this application, a silicon photonics layer 110 is formed using the first semiconductor process and the second semiconductor process, and the silicon photonics layer 110 includes the first silicon photonics layer 111 and the second silicon photonics layer 112.
[0090] Next, as Figure 8 As shown, a substrate 120 is stacked on the second silicon photonics layer 112. The substrate 120 can be made of materials such as semiconductor, ceramic, or glass. In some embodiments of this application, the substrate 120 can be stacked on the second silicon photonics layer 112 using a bonding process. For example, a bonding layer 121 can be formed on the substrate 120, and the substrate 120 is bonded to the second silicon photonics layer 112 through the bonding layer 121.
[0091] In some embodiments, the bonding layer 121 is optional, or the substrate 120 can be directly bonded to the second silicon photonic device layer 112; in some embodiments, the second silicon photonic device layer 112 is a metal interconnect layer and / or a redistribution layer (RDL).
[0092] like Figure 9 As shown, the underlying silicon layer 101 is then removed to expose the buried oxide layer 102. (Referring to the reference...) Figure 8 and Figure 9 In some embodiments of this application, the formed semiconductor structure 10B can be flipped so that the carrier 120 is located at the bottom and the bottom silicon layer 101 is located at the top, to facilitate process execution. Next, the bottom silicon layer 101 is removed to expose the buried oxide layer 102. The bottom silicon layer 101 can be removed using semiconductor processes such as chemical mechanical polishing, dry etching, and / or wet etching.
[0093] Next, as Figure 10 As shown, an oxide build-up layer 130 and a silicon substrate 140 are bonded and stacked on the buried oxide layer 102. In this embodiment, the oxide build-up layer 130 is made of the same material as the buried oxide layer 102, which is silicon oxide; the silicon substrate 140 is also made of the same material as the bottom silicon layer 101, which is semiconductor silicon. A bonding layer (not shown in the figure) can be formed between the buried oxide layer 102 and the oxide build-up layer 130.
[0094] In some embodiments of this application, the stacked oxide build-up 130 and silicon substrate 140 can be directly provided by a wafer fab. For example, the stacked oxide build-up 130 and silicon substrate 140 can be semi-finished products in the process of manufacturing SOI substrates by a wafer fab. In other embodiments of this application, the stacked oxide build-up 130 and silicon substrate 140 can also be obtained by removing the bottom silicon layer or the top silicon layer in a conventional SOI substrate.
[0095] like Figure 11 In this embodiment of the application, the carrier 120 is then removed. (Referring to the reference...) Figure 10 and Figure 11 In some embodiments of this application, the formed semiconductor structure 10C can be flipped so that the silicon substrate 140 is located at the bottom and the carrier 120 is located at the top, to facilitate process execution. In some embodiments of this application, for example, a debonding process can be used to remove the carrier 120; in other embodiments of this application, semiconductor processes such as chemical mechanical polishing, dry etching, and / or wet etching can also be used to remove the carrier 120.
[0096] Please continue to refer to this. Figure 11 In this embodiment, a silicon photonic device 10A is formed using the above-described method for manufacturing silicon photonic devices. The silicon photonic device 10A includes: a silicon substrate 140; an oxide build-up layer 130 on the silicon substrate 140; a buried oxide layer 102 on the oxide build-up layer 130, wherein the buried oxide layer 102 and the oxide build-up layer 130 are bonded together; and a silicon photonic device layer 110 on the buried oxide layer 102. The silicon photonic device layer 110 and the oxide build-up layer 130 are located on opposite sides of the buried oxide layer 102.
[0097] In the silicon photonic device 10A described in this application embodiment, the oxide layer 130 serves as a thickening layer for the buried oxide layer 102, thereby increasing the thickness of this functional layer and improving the performance of the silicon photonic device 10 and reducing insertion loss.
[0098] Simulation results show that forming an oxide build-up layer 130 on the buried oxide layer 102 to increase the thickness of this functional layer can significantly reduce the insertion loss of the silicon photonics device 10A and improve its quality. Please refer to [reference needed]. Figure 11 In this embodiment, the thickness of the oxide augmentation layer 130 added to the buried oxide layer 102 can be 1 μm, 2 μm, or 3 μm. When the thickness of the silicon photonic device 10A is the same, for example, the total thickness of the silicon photonic device 10A can be between 9 μm and 20 μm, the insertion loss of the waveguide structure 1110 is -0.8 dB / facet when the thickness of the oxide augmentation layer 130 is 1 μm; -0.6 dB / facet when the thickness of the oxide augmentation layer 130 is 2 μm; and -0.5 dB / facet when the thickness of the oxide augmentation layer 130 is 3 μm. However, in the existing case where no oxide augmentation layer 130 is added and the silicon photonic device layer is directly formed on the buried oxide layer 102, the insertion loss of the waveguide structure will reach -1.5 dB / facet. Here, we take a buried oxide layer 102 thickness of 2 μm as an example. It is evident that by forming an oxide augmentation layer 130 on the buried oxide layer 102 to increase the thickness of this functional layer, the insertion loss of semiconductor devices can be significantly reduced.
[0099] Please continue to refer to this. Figure 11 In some embodiments of this application, the silicon photonic device layer 110 includes a waveguide structure 1110. The distance between the center point of the waveguide structure 1110 and the surface of the silicon substrate 140 is between 4 μm and 10 μm. Compared to the prior art where the silicon photonic device layer is formed directly on the buried oxide layer 102 without adding an oxide build-up layer 130, the distance between the center point of the waveguide structure 1110 and the bottom silicon layer is between 1 μm and 3 μm. This not only results in a larger insertion loss for the waveguide structure but also hinders the connection between the waveguide structure 1110 and external devices, such as the connection with an optical fiber interface. In the prior art, when the waveguide structure 1110 and the optical fiber interface are connected, the center point deviation between them is large, resulting in significant optical signal transmission loss. However, in the embodiments of this application, when the waveguide structure 1110 and the optical fiber interface are connected, the center points between them can be basically aligned or the deviation is very small, resulting in minimal optical signal transmission loss.
[0100]
Example 2
[0101] Please refer to Figure 12 This is a schematic flowchart illustrating the manufacturing method of the silicon photonic device according to Embodiment 2 of the present invention. Figure 12 As shown in Embodiment 2 of this application, the manufacturing method of the silicon photonic device includes:
[0102] Step S300: Provide an SOI substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide layer and a top silicon layer stacked sequentially;
[0103] Step S310: Perform a first semiconductor process on the top silicon layer to form a first silicon photonic device layer;
[0104] Step S320: Stack a wafer on the first silicon photonics device layer;
[0105] Step S330: Remove the underlying silicon layer to expose the buried oxide layer;
[0106] Step S340: Bond the stacked oxide build-up and silicon substrate onto the buried oxide layer;
[0107] Step S350: Remove the substrate; and,
[0108] Step S360: Perform a second semiconductor process on the first silicon photonic device layer to form a second silicon photonic device layer.
[0109] The difference between this second embodiment and the first embodiment is that, in the first embodiment of this application, before bonding the oxide build-up layer 130 on the buried oxide layer 102, a first semiconductor process and a second semiconductor process are performed to form a first silicon photonic device layer 111 and a second silicon photonic device layer 112, and the silicon photonic device layer 110 includes the first silicon photonic device layer 111 and the second silicon photonic device layer 112; while in this second embodiment, before bonding the oxide build-up layer 130 on the buried oxide layer 102, a first semiconductor process is performed to form a first silicon photonic device layer, and the silicon photonic device layer includes the first silicon photonic device layer.
[0110] First, such as Figure 13 As shown, an SOI substrate 200 is provided, which includes a bottom silicon layer 201, a buried oxide layer 202, and a top silicon layer 203 stacked sequentially. In the embodiments of this application, the SOI substrate 200 can be a conventional SOI substrate from a wafer fab, for example, the thickness of its buried oxide layer 202 is 3 μm.
[0111] Next, as Figure 14 As shown, a first semiconductor process is performed on the top silicon layer 203 to form a first silicon photonic device layer 211. The first silicon photonic device layer 211 may include, for example, functional devices such as a device isolation layer (not shown), a waveguide structure (not shown) located in the device isolation layer, a grating coupler (not shown), a strip waveguide (not shown), a ridge waveguide (not shown), a lateral PIN photodetector (not shown), and / or a Mach-Zehnder modulator (not shown).
[0112] Next, as Figure 15As shown, a substrate 220 is stacked on the silicon photonics device layer 210. In this embodiment, the silicon photonics device layer 210 includes the first silicon photonics device layer 211. The substrate 220 can be made of materials such as semiconductor, ceramic, or glass. In some embodiments of this application, the substrate 220 can be formed on the first silicon photonics device layer 211 using a bonding process. For example, a bonding layer 221 can be formed on the substrate 220, and the substrate 220 is bonded to the first silicon photonics device layer 211 through the bonding layer 221.
[0113] like Figure 16 As shown, the underlying silicon layer 201 is then removed to expose the buried oxide layer 202. (Referring to the reference...) Figure 15 and Figure 16 In some embodiments of this application, the formed semiconductor structure 20B can be flipped so that the carrier 220 is located at the bottom and the bottom silicon layer 201 is located at the top, to facilitate process execution. Next, the bottom silicon layer 201 is removed to expose the buried oxide layer 202. The bottom silicon layer 201 can be removed using semiconductor processes such as chemical mechanical polishing, dry etching, and / or wet etching.
[0114] Next, as Figure 17 As shown, an oxide build-up layer 230 and a silicon substrate 240 are bonded and stacked on the buried oxide layer 202. The materials and processes of the oxide build-up layer 230 and the silicon substrate 240 can be referred to in Embodiment 1, and will not be repeated in this Embodiment 2.
[0115] like Figure 18 In this embodiment of the application, the carrier 220 is then removed. (Referring to the reference...) Figure 17 and Figure 18 In some embodiments of this application, the formed semiconductor structure 20C can be flipped so that the silicon substrate 240 is located at the bottom and the carrier 220 is located at the top, to facilitate process execution. In some embodiments of this application, for example, a debonding process can be used to remove the carrier 220; in other embodiments of this application, semiconductor processes such as chemical mechanical polishing, dry etching, and / or wet etching can also be used to remove the carrier 220.
[0116] Please continue to refer to this. Figure 18In this embodiment, a silicon photonic device 20 is formed using the above-described method for manufacturing silicon photonic devices. The silicon photonic device 20 includes: a silicon substrate 240; an oxide build-up layer 230 on the silicon substrate 240; a buried oxide layer 202 on the oxide build-up layer 230, wherein the buried oxide layer 202 and the oxide build-up layer 230 are bonded together; and a silicon photonic device layer 210 on the buried oxide layer 202. In this embodiment, the silicon photonic device layer 210 includes a first silicon photonic device layer 211; in some embodiments, it may only include the first silicon photonic device layer 211. The silicon photonic device layer 210 and the oxide build-up layer 230 are respectively located on opposite sides of the buried oxide layer 202.
[0117] Please refer to Figure 19 In some embodiments of this application, after removing the carrier 220 and exposing the first silicon photonic device layer 211, a second semiconductor process can then be performed on the first silicon photonic device layer 211 to form a second silicon photonic device layer 212. The second silicon photonic device layer 212 may include, for example, an interconnect layer (not shown). In some embodiments of this application, the second silicon photonic device layer 212 may also include functional devices, such as a thermal imager.
[0118] In the silicon photonic device 20 described in this embodiment, the oxide layer 230 serves as a thickening layer for the buried oxide layer 202, increasing the thickness of this functional layer and thereby improving the performance of the silicon photonic device 20 and reducing insertion loss. For aspects not detailed in this embodiment, please refer to embodiment one; further details will not be repeated in this embodiment.
[0119] Using the silicon photonics device and manufacturing method described in this case, the oxide layer is stacked on the side of the buried oxide layer away from the top silicon layer, which does not damage the interface between the buried oxide layer and the top silicon layer in the original SOI substrate, thus ensuring the performance of the device manufactured on the top silicon layer. In some embodiments, the oxide layer and the last retained silicon substrate adopt the buried oxide layer and bottom silicon layer / top silicon layer in the SOI wafer product, ensuring the consistency between the oxide layer and the buried oxide layer, and the interface between the oxide layer and the silicon substrate is not damaged. In particular, when using SOI substrates produced by the same wafer fab, the silicon substrate and the original bottom silicon layer, the oxide layer and the buried oxide layer have a high degree of consistency, which minimizes the damage to the structure and performance of the original SOI substrate caused by the "thickening process / structure", greatly reducing the impact on the devices and processes before and after.
[0120] In this application, references to "one embodiment" or "some embodiments" mean that a feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment or at least some embodiments of this application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" throughout this application does not necessarily refer to the same or the same embodiments. Furthermore, in one or more embodiments, features, structures, or characteristics can be combined in any suitable combination and / or sub-combination.
[0121] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this application. The embodiments of this application can be combined in any way without departing from the spirit and scope of this application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.
Claims
1. A silicon photonic device, characterized in that, The silicon photonics device includes: silicon substrate; Oxide layer located on the silicon substrate; A buried oxide layer is located on the oxide growth layer, the buried oxide layer and the oxide growth layer are bonded together; and, A silicon photonics device layer located on the buried oxide layer.
2. The silicon photonic device as described in claim 1, characterized in that, The silicon photonic device layer and the oxide augmentation layer are located on opposite sides of the buried oxide layer.
3. The silicon photonic device as described in claim 1, characterized in that, The combined thickness of the oxide layer and the buried oxide layer is greater than 3 μm.
4. The silicon photonic device as described in claim 1, characterized in that, The sum of the thicknesses of the oxide layer and the buried oxide layer is 4 μm, 4.5 μm, 5 μm, 5.5 μm, or 6 μm.
5. The silicon photonic device as described in claim 1, characterized in that, The thickness of the buried oxide layer is less than or equal to 3 μm.
6. The silicon photonic device according to any one of claims 1 to 5, characterized in that, The oxide layer is selected from the buried oxide layer in the SOI wafer.
7. The silicon photonic device according to any one of claims 1 to 5, characterized in that, The oxidized layer is formed by a thermal oxidation process.
8. The silicon photonic device according to any one of claims 1 to 5, characterized in that, The silicon substrate is selected from the top silicon layer or the bottom silicon layer in the SOI wafer.
9. The silicon photonic device according to any one of claims 1 to 5, characterized in that, The oxide layer and the silicon substrate are selected from the buried oxide layer and the top silicon layer in the SOI wafer, or the buried oxide layer and the bottom silicon layer.
10. The silicon photonic device according to any one of claims 1 to 5, characterized in that, The silicon photonic device layer includes a waveguide structure, and the distance between the center point of the waveguide structure and the surface of the silicon substrate is between 4 μm and 10 μm.
11. The silicon photonic device according to any one of claims 1 to 5, characterized in that, The silicon photonic device is used to connect to an optical fiber interface. The silicon photonic device layer includes a waveguide structure. In the thickness direction of the silicon photonic device, the center of the waveguide structure is aligned with the center of the optical fiber interface; or, the height difference between the center of the waveguide structure and the center of the optical fiber interface is less than or equal to 1 μm; or, the height difference between the center of the waveguide structure and the center of the optical fiber interface is less than or equal to 0.5 μm; or, the height difference between the center of the waveguide structure and the center of the optical fiber interface is less than or equal to 0.1 μm.
12. A method for manufacturing a silicon photonic device, characterized in that, The method for manufacturing the silicon photonic device includes: An SOI substrate is provided, the SOI substrate comprising a bottom silicon layer, a buried oxide layer and a top silicon layer stacked sequentially; A semiconductor process is performed on the top silicon layer to form a silicon photonics device layer on the buried oxide layer; A wafer is stacked on the silicon photonics device layer; Remove the underlying silicon layer to expose the buried oxide layer; An oxide uplift layer and a silicon substrate are bonded and stacked on the buried oxide layer; and, Remove the substrate.
13. The method for manufacturing a silicon photonic device as described in claim 12, characterized in that, Performing a semiconductor process on the top silicon layer to form a silicon photonic device layer on the buried oxide layer includes: Perform a first semiconductor process on the top silicon layer to form a first silicon photonic device layer; and, A second semiconductor process is performed on the first silicon photonic device layer to form a second silicon photonic device layer; The silicon photonic device layer includes a first silicon photonic device layer and a second silicon photonic device layer.
14. The method for manufacturing a silicon photonic device as described in claim 12, characterized in that, Performing a semiconductor process on the top silicon layer to form a silicon photonic device layer on the buried oxide layer includes: performing a first semiconductor process on the top silicon layer to form a first silicon photonic device layer, wherein the silicon photonic device layer includes the first silicon photonic device layer; After removing the carrier wafer, the method for manufacturing the silicon photonic device further includes performing a second semiconductor process on the first silicon photonic device layer to form a second silicon photonic device layer.