Multi-task real-time operating system scheduling optimization method for PPEC controller

Abstract

The invention relates to the technical field of electronic data processing, in particular to a multi-task real-time operating system scheduling optimization method for a PPEC controller. The method comprises the following steps: constructing a physical time snapshot of interrupt response by using a hardware timer and a direct memory access unit, and collecting entry and exit moments when a rigid control task is interrupted by a non-control task; calculating time debt based on the interruption physical duration, constructing a space-time mapping model in combination with the power grid reference angular frequency, and converting the time debt into a phase lag angle of a voltage space vector; and comparing the time debt with an atomic operation time threshold value, dynamically switching to a compression mode or a fusing mode according to the time debt and the atomic operation time threshold value, and executing task scheduling according to the selected mode. According to the method, the time drift is mapped into the vector phase error of the physical layer, so that the problems of waveform distortion and control divergence caused by sudden interruption are solved, and the physical synchronization of control is ensured.

Description

Technical Field

[0001] This invention relates to the field of electronic data processing technology, and more specifically to a method for scheduling optimization of a multi-task real-time operating system for PPEC controllers. Background Technology

[0002] In power electronics development, programmable power electronic controllers generally adopt a dual-core business mode: the upper-level configuration, i.e., the user domain, is responsible for handling flexible control tasks such as human-machine interaction and waveform monitoring; the lower-level control, i.e., the kernel domain, executes rigid control tasks such as ADC sampling, PID closed-loop calculation, and SVPWM waveform generation at high frequencies of kilohertz. However, in real-world applications, this architecture faces severe real-time challenges. When the controller is outputting a standard sinusoidal voltage, its control logic must strictly follow the phase of the grid voltage. However, when the system encounters a sudden hardware interrupt, such as a communication request or fault recording, the central processing unit is forced to suspend its current rigid control logic to handle the interrupt. Existing real-time operating system scheduling strategies typically employ simple time-slice round-robin or priority preemption strategies. After the interrupt is handled, the system simply restores the context and continues executing the original task. This traditional approach ignores the fact that physical time does not stop during the time the central processing unit is processing the interrupt. The grid voltage vector has already rotated a certain angle. The pause in the control logic causes the calculation cycle to lag on the time axis. If this physical phase lag is output directly without compensation, it will cause the inverter output voltage to be out of sync with the grid. This can lead to increased current harmonics, or even software phase-locked loop lockout or inverter failure. In existing embedded control systems, the conventional method for obtaining interrupt delay duration is to read the system time through software instructions at the interrupt service routine entry point. However, this software-to-software method has unavoidable observation errors. This is because the central processing unit must go through hardware processes such as pipeline flushing and register stack pushing from receiving the interrupt signal to executing the first read instruction. This time is random and unmeasurable. For PPEC controllers, even nanosecond-level phase errors can cause grid current harmonics to exceed the standard. Therefore, the industry currently needs a technical solution that can accurately map the time delay at the software level to the phase error at the physical level and perform real-time compensation. Summary of the Invention

[0003] To address the issue of phase deviation caused by time lag in existing technologies when encountering sudden interruptions, this invention provides a multi-task real-time operating system scheduling optimization method for PPEC controllers, the method comprising: Using a hardware timer and a direct memory access unit with hardware triggering function, a physical time snapshot of the interrupt response is constructed before the central processing unit responds, including the entry and exit times when a rigid control task is interrupted by a non-control task. Based on the entry and exit times, a time debt is calculated, and a spatiotemporal mapping model is constructed in conjunction with the power grid reference angular frequency to convert the time debt into the phase lag angle of the target voltage vector. The time debt is compared with a preset atomic operation time threshold, and the control mode is determined based on the comparison result. Task scheduling is executed based on the control mode, and the target voltage vector is corrected using the phase lag angle to obtain a corrected pulse width modulation signal.

[0004] This invention utilizes hardware timers and direct memory access units to construct physical time snapshots, capturing the physical boundaries of interrupted rigid control tasks without occupying processor instruction cycles. Simultaneously, it constructs a spatiotemporal mapping model using the grid reference angular frequency, transforming the time debt at the scheduling level into the phase lag angle of the voltage space vector at the physical level. When executing scheduling tasks, the phase lag angle is used to correct the target voltage vector, eliminating the risk of inverter output waveform distortion and control divergence caused by sudden interruptions of non-control tasks, and ensuring physical synchronization in complex multi-tasking environments.

[0005] Furthermore, the entry and exit times include: configuring the hardware timer to free-running mode and setting the counting frequency of the hardware timer to be synchronized with the controller main frequency of the PPEC controller; when the direct memory access unit detects the interrupt trigger signal of the non-control task, before the central processing unit responds to the interrupt, reading the count value of the hardware timer as the entry time; when the interrupt return instruction of the non-control task is detected, reading the count value of the hardware timer as the exit time.

[0006] This invention configures a hardware timer to operate in free-running mode and synchronize with the PPEC controller's main frequency. By utilizing the hardware triggering mechanism of the direct memory access unit, it automatically latches and transfers the count value at the moment of triggering and returning from a non-control task interruption, achieving zero-latency capture of nanosecond-level physical time nodes. This pure hardware-level data acquisition method not only avoids the uncertainty jitter caused by real-time operating system software reading, but also frees up the computing resources of the control core, ensuring the accuracy and real-time performance of time debt measurement.

[0007] Furthermore, the time debt satisfies the following relation:

[0008] in, For the aforementioned time debt; The entry time is mentioned; The exit time is mentioned above; The counting period of the hardware timer; The inherent overhead time for context switching of the PPEC controller.

[0009] This invention constructs a time debt calculation model that includes hardware counting cycles and context switching overhead, transforming the hardware timer difference into the net physical duration that reflects the actual business usage, thus restoring the physical time when the rigid control loop is actually blocked, and avoiding over-correction or under-correction due to error accumulation during subsequent phase correction.

[0010] Furthermore, the reference angular frequency of the power grid is acquired in real time by a software phase-locked loop running in the PPEC controller.

[0011] Furthermore, the multi-task real-time operating system scheduling optimization method for PPEC controllers further includes: obtaining the total duration of the current control cycle, calculating the difference between the total duration of the current control cycle and the time debt; if the difference is greater than or equal to the atomic operation time threshold, determining that the control mode is a compression mode; if the difference is less than the atomic operation time threshold, determining that the control mode is a circuit breaker mode.

[0012] Furthermore, the atomic operation time threshold is obtained through a closed-loop calculation time calibration experiment.

[0013] Furthermore, the task scheduling includes: when the control mode is the circuit breaker mode, immediately suspending all pending elastic control tasks in the current control cycle, releasing the computing resources of the PPEC controller, resetting the control flow of the PPEC controller to the initial state of the rigid control task, locking the output state of the pulse width modulation signal, and waiting for the arrival of the synchronization trigger signal of the next control cycle; when the control mode is the compression mode, calculating the physical remaining available time slice of the current control cycle, dynamically modifying the hardware timer reload value of the task scheduler according to the physical remaining available time slice, nonlinearly compressing the allocation time of the elastic control task, and executing the elastic control task according to priority within the compressed allocation time.

[0014] When the invention determines that the circuit breaker mode has been entered, it adopts a protection strategy that immediately suspends all flexible control tasks and jumps to the entry point of rigid control tasks. By sacrificing low-priority auxiliary functions in exchange for absolute execution rights of the core control loop, it ensures that the PPEC controller can still maintain continuity and stability under extreme conditions such as communication storms or cascading failures, and prevents inverter explosion accidents caused by central processor overload.

[0015] Further, the target voltage vector is corrected by: acquiring the grid voltage reference phase in real time during the current control cycle, performing phase correction on the grid voltage reference phase using the phase lag angle to obtain a physical synchronization phase containing time-domain compensation information, performing vector synthesis calculation on the target voltage vector based on the physical synchronization phase, and then generating the corrected pulse width modulation signal.

[0016] This invention obtains a physical synchronization phase containing time-domain compensation information by reading the grid voltage reference phase in real time and superimposing and calculating the phase lag angle, thereby obtaining a corrected pulse width modulation signal. This correction method, which directly acts on the core stage of wave generation, cancels the spatial phase error caused by the passage of physical time and reduces the total harmonic distortion rate of the grid-connected current.

[0017] Furthermore, the rigid control tasks include analog-to-digital conversion sampling, proportional-integral-derivative closed-loop calculation, and space vector pulse width modulation; the non-control tasks include industrial fieldbus communication interruption response, external fault signal capture, and non-volatile memory read / write operations.

[0018] Furthermore, the flexible control task refers to a user domain background task with a lower priority than the rigid control task, specifically including: waveform data buffering and uploading of the online oscilloscope, register reading and writing of the industrial fieldbus protocol, and parameter refreshing of the human-machine interface.

[0019] The present invention has the following technical effects: In terms of technology, this invention breaks through the limitation of traditional pure software scheduling algorithms that only focus on logical time slices. By introducing a coupling model of time debt and physical phase, the invisible software interrupt delay is transformed into an adjustable physical wave angle, thus achieving strict synchronization between the control algorithm and the physical world. In terms of security, the dual-modal strategy of compression and circuit breaking designed in this invention, combined with the threshold system calibrated by actual measurement, constructs a hierarchical defense mechanism. It can protect the user experience by compressing non-critical tasks under minor disturbances, and safeguard the bottom line of control through the circuit breaking mechanism under severe blockage. This solves the problem of system crashes and waveform divergence caused by competition for central processing unit resources. In terms of application, this invention makes full use of the hardware peripheral resources of modern control chips, realizing low-overhead data acquisition and low-computing-power algorithm correction, effectively improving the anti-interference capability of the device without upgrading expensive hardware platforms. Attached Figure Description

[0020] Figure 1 This is a flowchart of a multi-task real-time operating system scheduling optimization method for a PPEC controller provided in an embodiment of the present invention; Figure 2This is a comparison diagram of the output waveforms of the prior art provided in the embodiments of the present invention and the present invention. Detailed Implementation

[0021] Before describing the specific implementation of the present invention in detail, the task classification system of the PPEC controller in the multi-task real-time operating system environment described in this embodiment is first explained. In order to achieve a balance between control real-time performance and system multifunctionality, the present invention divides all software and hardware activities in the PPEC controller into three orthogonal logical sets: rigid control tasks, non-control tasks, and flexible control tasks. Rigid control tasks: These tasks are the core and have the highest timing determinism requirements. They must be executed precisely according to the period set by the hardware timer. In this embodiment, rigid control tasks specifically include analog-to-digital conversion sampling, proportional-integral-derivative closed-loop calculation, and space vector pulse width modulation. These tasks determine the physical output waveform of the inverter and are not allowed to be delayed by any software logic. Non-control tasks: These tasks refer to sudden events with extremely high response priority that can trigger hardware interrupts in the central processing unit. They are triggered by external hardware signals and their execution is unpredictable. In this embodiment, non-control tasks specifically include industrial fieldbus communication interrupt response, external fault signal capture, and non-volatile memory read / write operations. These tasks are the main source of interruptions to rigid control tasks and the generation of time debt. Flexible control tasks: These tasks refer to user domain background tasks in the real-time operating system that have a lower priority than rigid control tasks. They are tolerant of time delays and have room for compression. In this embodiment, flexible control tasks specifically include waveform data buffering and uploading from an online oscilloscope, register reading and writing for the industrial fieldbus protocol, and parameter refreshing of the human-machine interface. When system resources are scarce, these tasks can be suspended or discarded.

[0022] This invention provides a multi-task real-time operating system scheduling optimization method for PPEC controllers, referring to... Figure 1 This includes steps S1-S4: S1: Physical time snapshot construction and basic data acquisition.

[0023] Specifically, this step involves coordinating the configuration of the hardware timer and direct memory access unit within the PPEC controller to construct a physical time snapshot of the process of rigid control tasks being interrupted by non-control tasks without occupying CPU instruction cycles. This captures the physical boundary of the time debt and, in conjunction with the software phase-locked loop, synchronously obtains the grid reference angular frequency, providing a clean data source for subsequent calculations.

[0024] In this embodiment, a 32-bit PPEC controller containing a floating-point arithmetic unit is selected as the core control unit. In order to obtain a nanosecond-level physical time base, the high-resolution hardware timer inside the PPEC controller is first configured to operate in free-running mode, that is, counting from zero upwards, automatically wrapping back after overflow, and without setting an automatic reload value. Then, the counting frequency of the hardware timer is set to be synchronized with the main frequency of the PPEC controller. This hardware timer is independent of the kernel tick of the real-time operating system and is not affected by the reset or modification of the task scheduler. When the PPEC controller receives a high-priority interrupt signal (e.g., a fieldbus communication request) during a rigid control task such as SVPWM waveform calculation, there is a microsecond-level hardware delay window between the CPU's response to the interrupt signal and the program pointer's jump to the interrupt service routine entry point. Within this window, the hardware interconnect logic automatically triggers a latching action to lock the current hardware timer's count value. This entry time is defined as the entry moment and denoted as . ; Utilizing the multi-channel parallel transmission capability of the Direct Memory Access Unit (DMemory Access Unit), the interrupt signals of the aforementioned non-control tasks are configured as trigger sources for DMemory Access Unit transmission. Once an interrupt is triggered, the DMemory Access Unit immediately takes over the internal data bus and executes two parallel data transmission operations: the first path will enter the time... The data is moved to a preset time snapshot buffer; the second channel moves the grid voltage and inductor current data collected by the analog-to-digital converter to the control data buffer. It should be noted that this series of data moving operations is completed independently by the hardware logic and does not occupy any instruction cycle of the PPEC controller, ensuring the purity and real-time performance of the data and avoiding data reading delays caused by the central processing unit recovering from non-control task interruptions. Next, the software phase-locked loop built into the PPEC controller is invoked to perform coordinate transformation and PI regulation on the collected grid voltage data, thereby obtaining the grid reference angular frequency, denoted as . ; When the PPEC controller completes non-control tasks, such as receiving a Modbus message frame or recording a fault waveform, and is ready to execute an interrupt return instruction to restore the context of the rigid control task, it reads the current hardware timer count value, which is defined as the exit time and denoted as . ; From the moment of entry and exit time Together, they constitute a physical time snapshot of the process when the rigid control task is interrupted. This physical time snapshot digitally records the duration of physical occupation of the control core by non-control tasks.

[0025] The key innovation of this embodiment lies in the construction of a hardware linkage triggering mechanism, which connects the external interrupt request line of non-control tasks to the interrupt controller of the central processing unit and the hardware trigger source of the direct memory access unit simultaneously. When the interrupt signal arrives, at the physical instant before the central processing unit has completed the current instruction cycle and responded to the interrupt request, the direct memory access unit has been directly triggered by hardware logic to freeze the current count value of the hardware timer and move it to memory. This process is completed entirely by hardware logic gate circuits, without occupying any central processing unit instruction cycle, and is not affected by operating system interrupt masking or priority inversion, thereby realizing a zero-latency physical time snapshot.

[0026] It should be noted that the physical time snapshot construction method based on hardware timers and direct memory access units mentioned in this embodiment is only a preferred hardware implementation example. In practical applications, any hardware counting unit that can provide a high-precision physical time base independently of the real-time operating system kernel tick, such as the logic counter built into the FPGA, the global system counter in the ARM architecture, and any coprocessing mechanism that can complete automatic data transfer before the central processing unit responds to the interrupt, such as the control law accelerator CLA, the shared memory synchronization mechanism under the heterogeneous multi-core architecture, and a dedicated hardware data transfer engine, can replace the specific hardware module in this embodiment. Any physical time measurement technology that uses a hardware triggering mechanism to lock the start and end times of the interrupt, thereby achieving zero central processing unit overhead, should be included within the protection scope of this invention.

[0027] S2: Construction of Time Debt Calculation and Spatiotemporal Mapping Model.

[0028] Specifically, the core of this step is to convert the software-level stuttering into the physical-level angular deviation. Using the physical time snapshot obtained by S1, the net physical time actually squeezed out by the non-control task of the rigid control task is calculated. The time is then converted into the phase lag angle required by the vector control algorithm using the spatiotemporal mapping model.

[0029] The count difference of a simple hardware timer only represents the total time consumed by the interrupt service routine. However, in reality, when the PPEC controller enters and exits an interrupt, it needs to execute instructions such as register pushing, stack pointer updating, and context restoration. These are fixed overheads of the real-time operating system and should not be included in the business time occupied by non-control tasks. Therefore, time debt needs to be introduced for correction. The specific relationship is as follows:

[0030] in, For time debt; Entering time; This is the exit time; The counting period of the hardware timer is 5ns in this embodiment; The inherent overhead time for context switching of the PPEC controller.

[0031] The item represents the total time elapsed from the interruption to the recovery of a rigid control task. When an interrupt occurs, the central processing unit (CPU) does not immediately process the business code; instead, it must first execute a series of fixed actions such as pushing onto the stack, pipelining, and jumping to the interrupt vector table. When the interrupt ends, it also needs to perform a series of fixed context restoration actions. The time consumed by these actions is the inherent overhead time. Time debt It refers to how much time the sudden task itself takes up, rather than how much time the real-time operating system takes up, because the time cost of the real-time operating system is fixed and predictable, while the time cost of the sudden task is dynamic and unknown. Considering that hardware timers may have an error of ±1 counting cycle, if the calculated time debt If it is a negative value, Set it to zero to prevent interference with subsequent calculations.

[0032] It should be noted that the inherent overhead time The calibration is performed using the pin flipping method. This experiment only needs to be performed once before the PPEC controller leaves the factory. The specific steps are as follows: First, put the PPEC controller into offline single-step debugging mode, disable peripheral interrupts such as ADC conversion completion interrupt and communication interrupt except for the test channel, and turn off the watchdog timer to ensure that the experimental calibration process is not affected by random events. Next, in the instruction memory of the PPEC controller, an idle interrupt service routine is written and compiled. This idle interrupt service routine has real-time operating system entry and exit macros that are completely consistent with the real non-control tasks. It contains a complete sequence of context protection and recovery instructions, but does not contain any user business logic code. That is, the effective load code is zero. Its purpose is to restore a physical process that only consumes system overhead. An edge-triggered signal is sent to the external interrupt pin of the PPEC controller using an external high-precision signal generator to activate the above-mentioned idle interrupt service routine; the same hardware timer and direct memory access unit architecture as S1 is called to record the entry time when the interrupt is triggered and the exit time when the interrupt execution is completed. The PPEC controller is driven to perform the above operation N times consecutively. In this embodiment, 10,000 times are taken to obtain 10,000 physical time snapshot samples. The product of the difference between the exit time and the entry time of each sample and the counting period of the hardware timer is calculated and recorded as the duration of each sample. The samples with the largest and smallest durations are removed, and the average duration of the remaining samples is calculated, which is the inherent overhead time of the PPEC controller performing context switching. .

[0033] It should be noted that the pin-flipping method used in this embodiment is only an intuitive and low-cost preferred implementation method for obtaining inherent overhead time. In practical applications, any technical means that can evaluate processor context switching overhead can replace this calibration method, such as: directly reading the instruction execution cycle number using the debug trace macrocell or performance counter built into the processor core; performing static timing analysis on the assembly code of the interrupt service routine based on the software simulator of the integrated development environment; calculating the system's inherent latency by performing statistical regression analysis on large amounts of data; any technical solution that extracts time based on the differential idea of ​​subtracting the system's inherent overhead from the total physical duration should be covered within the protection scope of this invention.

[0034] In AC power electronic control theory, the dynamic change process of the grid voltage can be equivalent to a pointer rotating at a constant speed on the complex plane, i.e., a rotating vector. When the central processing unit of the PPEC controller is interrupted by a non-control task, resulting in a time debt, although the execution pointer of the software program is paused, the grid voltage vector continues to rotate at a certain angle according to the angular frequency. Therefore, when the time debt is obtained... Subsequently, the PPEC controller needs to resolve this core physical contradiction: the asynchrony between the logical pauses in the control logic and the continuous changes in the physical signals. According to "Power Electronics Technology," in a synchronous rotating coordinate system, the three-phase AC grid voltage is a spatial vector rotating uniformly at a synchronous angular frequency. The spatial electrical angle it slides through in any time interval is the product of the grid frequency and the delay time. Based on this, this invention constructs a spatiotemporal mapping model, mapping the scalar time parameter to a vector angular parameter, thereby calculating the angle by which the grid voltage vector rotates. The specific relationship is as follows:

[0035] in, The phase lag angle; The reference angular frequency of the power grid; For time debt; Since the delay caused by the interruption is usually on the order of microseconds, which is much smaller than the period of the grid voltage, the rotational speed of the grid voltage vector can be regarded as constant within such a short time. Therefore, the angle of rotation is calculated by using the product of speed and time. This calculation is independent of the specific amplitude of the grid voltage, ensuring that the spatiotemporal mapping model remains accurate under the conditions of voltage fluctuation or distortion.

[0036] It is important to distinguish that the dead-time compensation strategy widely used in existing power electronic control technologies is essentially a static compensation for the physical switching characteristics of power semiconductor devices, such as the turn-off delay time and turn-on delay time. The dead time is usually a fixed value or a known quantity that varies linearly with the current amplitude, and its compensation logic is deterministic. The problem that this invention solves is the time debt caused by non-control tasks randomly preempting central processing unit resources in a multi-tasking real-time operating system. This time debt occurs randomly in the time domain and changes dynamically in width, and cannot be eliminated by setting a fixed compensation angle. Existing dead-time compensation algorithms cannot detect or offset this timing drift at the software logic level.

[0037] S3: Dual-modal task scheduling strategy determination.

[0038] Specifically, in order to balance control stability and user interaction experience, this step introduces an atomic operation time threshold as a decision boundary. The aim is to establish a hierarchical scheduling defense mechanism based on the physical time dimension. Time debt is used as the core criterion and compared with the atomic operation time threshold. Based on the comparison result, the current control cycle state is determined to be either compression mode or circuit breaker mode, and a differentiated task scheduling strategy is executed.

[0039] The PPEC controller's task scheduler reads the total duration of the current control cycle, the calculated time debt, and the atomic operation time threshold in real time, and performs the following logical judgment: If the difference between the total duration of the current control cycle and the time debt is greater than or equal to the atomic operation time threshold, it indicates that although an interruption has occurred, the remaining time of the current control cycle is still sufficient to cover the minimum execution overhead of the rigid control task, and it is determined to be a compressed mode. If the difference between the total duration of the current control cycle and the time debt is less than the atomic operation time threshold, it indicates that the time debt is too large and the remaining time of the current control cycle is insufficient to complete a closed-loop calculation and register update, and is judged as a circuit breaker mode.

[0040] Based on the above determination results, the PPEC controller executes the corresponding task scheduling: When the mode is determined to be compressed, the difference between the total duration of the current control cycle and the time debt is subtracted from the atomic operation time threshold to obtain the elastic time budget value. The reload value of the system tick timer of the real-time operating system is modified to the elastic time budget value. This means that once the elastic control task starts to execute, the system tick timer starts to count down. When the countdown ends, regardless of whether the currently running task has been completed, the CPU usage right of the current task will be deprived, and the task will be forcibly switched back to the rigid control task to ensure that no subsequent time is occupied. For flexible control tasks, namely waveform data buffering and uploading from online oscilloscopes, register reading and writing via industrial fieldbus protocols, and parameter refreshing of the human-machine interface, compression at different granularities is performed: For register read / write operations of the industrial fieldbus protocol, since this task involves communication handshake with the external master station and has time requirements, it is listed as the highest priority in the flexible control task, allowing it to occupy the budget first for packet parsing. For waveform data buffering and uploading of online oscilloscopes, if the countdown of the system tick timer has not ended after the register read / write of the industrial fieldbus protocol is completed, the PPEC controller is allowed to perform the task. If the countdown ends, the waveform data of the online oscilloscope for this control cycle will be discarded, only the data loss flag will be recorded, and no uploading will be performed. For parameter refresh of the human-computer interaction interface, due to the persistence of vision of the human eye, this task has the lowest priority. In the compression mode, the PPEC controller reduces the refresh frequency of this task from once per control cycle to once every ten control cycles to ensure the execution of the above high-priority tasks.

[0041] Traditional real-time operating system schedulers typically operate according to a fixed system cycle and are unrelated to the frequency of the external power grid. However, this invention, by modifying the reload value, actually forces the logical clock of the real-time operating system to scale with the physical phase angle of the power grid. This scheduling strategy, where logical time follows physical time, ensures that in the event of power grid frequency fluctuations or sudden interruptions, low-priority flexible control tasks will automatically give way to rigid control tasks, thus achieving deep spatiotemporal synchronization between the real-time operating system kernel and the power electronic control object.

[0042] When the circuit breaker mode is determined, the PPEC controller immediately issues the highest level task suspension command, unconditionally freezing all flexible control tasks in the ready or running state in the current control cycle. Specifically, this includes immediately stopping the memory writing operation of the online oscilloscope, interrupting the ongoing message parsing process of the industrial fieldbus protocol, and terminating all rendering commands of the human-machine interface. No matter what step these tasks have reached, they must immediately relinquish control of the central processing unit. To prevent interference from residual background data in suspended tasks, the PPEC controller resets all direct memory access channels except those used for time capture. Then, by calling the task reset interface of the real-time operating system, it redirects the execution flow to the entry address of the rigid control task. Before the jump, the CPU keeps the value of the pulse width register of the current control cycle unchanged. After the jump, it does not perform new calculations, enters a low-power idle state, and silently waits for the synchronization trigger signal of the next pulse width modulation cycle to arrive, thereby completely cutting off the accumulation link of time debt.

[0043] It should be noted that the atomic operation time threshold, in its physical essence, defines the shortest physical time required for the PPEC controller to complete a full rigid control cycle from analog-to-digital conversion sampling to pulse width modulation duty cycle update under ideal conditions without any external interference. In order to obtain an accurate value for this parameter and cover the performance dispersion caused by chip manufacturing processes, this embodiment obtains this parameter through a closed-loop calculation time calibration experiment. The specific steps are as follows: Put the PPEC controller into offline debugging mode and disconnect the power stage's high-voltage connection: modify the interrupt controller's mask register to disable all non-control tasks and flexible control tasks, leaving only rigid control tasks enabled, ensuring that the CPU's instruction flow only switches between the idle loop and rigid control interrupts, eliminating any random context switching interference. Modify the source code of the rigid control task by inserting toggle instructions for general-purpose input / output pins at key nodes in the instruction path: insert the instruction GPIO_SetHigh(Test_Pin) at the first valid instruction of the rigid control task interrupt service routine to pull the test pin high; insert the instruction GPIO_SetLow(Test_Pin) at the last valid instruction after the rigid control task completes its calculation and writes the result to the PWM compare register to pull the test pin low; the probes strictly enclose all control algorithm logic, trigonometric function calculations, and data limiting processing. Start the hardware timer of the PPEC controller to continuously trigger the rigid control task at the rated switching frequency: First, let the PPEC controller run under no-load, observe and record the average execution time of the rigid control task under normal conditions, and record it as the estimated average value; then, use a digital oscilloscope with a bandwidth of 200MHz to connect to the test pin, configure the trigger mode to pulse width trigger, and the trigger condition to be greater than the estimated average value. This setting allows the oscilloscope to automatically ignore thousands of normal short calculation cycles, and only capture when there is a sudden increase in the calculation time. Using the automated scripting function of the debugging environment connected to the PPEC controller, the memory address of the core input variables of the rigid control task (including grid voltage sampling value, inductor current feedback value, and DC bus voltage value) is locked. The range of change of the above variables is set to cover the physical limit of the PPEC controller, that is, from the negative rated maximum value to the positive rated maximum value. The debugging script controls the PPEC controller to run at full speed. In each control cycle, traversal data from the negative rated maximum value to the positive rated maximum value with a step size of 1 digital unit is written to the above memory address. As the aforementioned traversal data is written, the central processing unit of the PPEC controller will execute all possible combinations of logical branches in the rigid control task, such as simultaneously triggering overmodulation processing, dead-zone compensation calculation, and boundary conditions for inverse trigonometric function lookup. During this process, the oscilloscope connected to the test pin uses its infinite persistence function to continuously detect and refresh the pulse width. When the traversal process ends, that is, after all input combinations have been tested, the maximum pulse width value retained on the oscilloscope is defined as the worst-case execution time, which represents the longest time required for the central processing unit to complete one core control closed loop under physical limits. To compensate for potential crystal frequency drift, increased logic gate latency due to temperature rise, and Flash read wait cycle jitter that may occur during long-term chip operation, a safety redundancy processing is required for the worst-case execution time, reserving a 20% margin. This reduces the worst-case execution time to 1.2 times, which is the atomic operation time threshold. The atomic operation time threshold is then converted into the corresponding count value of the hardware timer and programmed into the protected parameter area of ​​the PPEC controller's non-volatile memory using a programmer.

[0044] It can be seen that the atomic operation time threshold is not a software timeout parameter set manually, but a physical limit value determined by the switching characteristics of the power semiconductor device and the minimum execution window of the SVPWM algorithm. It defines the incompressible physical time that the central processing unit must reserve within a control cycle, and uses it as the basis for judging the fuse mode, thus realizing the strict coupling between the control logic and the physical entity.

[0045] It should be noted that the dual-modal scheduling strategy and parameter calibration method based on atomic operation time thresholds described in this embodiment are only a preferred embodiment of the present invention, and the scope of protection of the present invention is not limited thereto. Those skilled in the art will know that the calibration method for atomic operation time thresholds can also be based on static timing analysis of assembly code generated by the compiler, online statistics using the performance monitoring unit integrated in the processor core, or calculation based on the chip's clock cycle theoretical model. All threshold parameters obtained based on the technical objective of establishing the minimum physical execution window for rigid control tasks are covered within the scope of protection of the present invention. Regarding the specific means of modal execution, under different hardware architectures or real-time operating system environments, techniques such as adjusting the watchdog timer window, triggering high-priority software interrupts, and using task deletion or suspension API interfaces provided by the real-time operating system can be used to achieve the same effect of task preemption and forced switching of control. Regarding the classification logic of scheduling modes, the compression and circuit breaker binary mode proposed in this invention is only a basic model. In practical applications, this judgment logic can be extended to a multi-level gradient model, such as introducing a three-level classification of slight compression, heavy compression, and emergency circuit breaker, or using algorithms such as fuzzy logic and neural networks to continuously adjust the CPU duty cycle of the elastic control task according to the size of the time debt. Any technical solution that dynamically adjusts the task execution depth or priority based on the physical time debt should be covered within the protection scope of this invention.

[0046] S4: Phase correction and pulse width modulation signal generation.

[0047] Specifically, this step aims to use the phase lag angle to perform feedforward compensation on the input of the space vector pulse width modulation algorithm in a rigid control task, thereby offsetting the time domain lag caused by the interruption of non-control tasks at the physical wave generation level.

[0048] When the PPEC controller executes the space vector pulse width modulation calculation subroutine in the rigid control task, the central processing unit first reads the grid voltage reference phase output by the software phase-locked loop in the current control cycle, denoted as . The phase lag angle obtained in S2 is then linearly superimposed with the grid voltage reference phase to obtain the physical synchronization phase. ,in Physical synchronization phase indicates that the PPEC controller has not experienced any non-control task interruptions during the current control cycle, i.e., time debt. The grid voltage vector is in the ideal phase position; it is worth noting that the phase lag angle It is a dynamic correction amount independent of the inverter dead-zone compensation angle. When generating the final pulse width modulation signal, the PPEC controller first utilizes... The grid voltage vector is rotated to the physical synchronization coordinate system, and then the traditional dead time compensation is superimposed on it. The two work at the software logic layer and the hardware physical layer respectively, without conflict, and together ensure the fidelity of the output waveform.

[0049] It should be noted that if the interruption of a non-control task occurs during the execution of a rigid control task, causing the intermediate calculation results of the rigid control task to no longer be applicable to the current physical time, the PPEC controller will discard the current intermediate calculation results after the interruption returns and restart the spatial vector pulse width modulation calculation process of the current control cycle using the physical synchronization phase to ensure the consistency of all vector synthesis parameters on the time axis.

[0050] The grid voltage and inductor current data for the current control cycle are read from the control data buffer and compared differentially with the control target for the current control cycle, i.e., the current and voltage command values ​​generated by the outer loop, to calculate the control deviation. Subsequently, an adjustment operation is performed on this control deviation to calculate the voltage control quantity used to eliminate the deviation, defined as the target voltage reference amplitude for the current control cycle, denoted as . Next, using the physical synchronization phase as the rotation angle, the target voltage reference amplitude is decomposed by coordinate projection, converting it into two orthogonal voltage components required by the space vector pulse width modulation algorithm. and Physically, this corresponds to the horizontal and vertical axis components of a two-phase stationary coordinate system, as follows:

[0051]

[0052] By introducing By participating in trigonometric function calculations, the PPEC controller actually pre-deflects the final generated target voltage vector by an angle on the complex plane. This operation cancels out the lag caused by time debt, so that when the target voltage vector finally output by the PPEC controller reaches the power electronic device, its spatial position is synchronized with the real-time rotating grid voltage vector, achieving the control effect of time lag and spatial alignment. Finally, the PPEC controller utilizes and The space vector pulse width modulation (SVM) calculation is performed to obtain the required conduction time, i.e., duty cycle, for each switch in the three-phase inverter bridge. Subsequently, the central processing unit writes these duty cycle values ​​into the comparison register of the hardware timer. When the count value of the hardware timer matches the comparison register, the pulse width modulation pin level of the PPEC controller flips, driving the external power device to operate. At this time, although the physical waveform generation is delayed compared to the ideal time on the time axis, the waveform phase already includes the required time. The advanced compensation ensures that the final output power quality will not be affected by non-control task interruptions, thus completing the entire process scheduling optimization from physical time measurement to spatial phase correction.

[0053] Figure 2The figures below are comparison diagrams of the output waveforms of the prior art and the present invention provided in the embodiments of the present invention. The upper figure shows the response curve of the conventional method, and the lower figure shows the response curve of the method described in the present invention. It can be seen that the conventional method exhibits obvious phase lag relative to the ideal reference waveform. This lag is manifested as a rightward shift of the waveform on the time axis. However, the method described in the present invention, after compensation operation in the correction region, fits the ideal reference waveform, eliminates the timing drift caused by interruption, and ensures high fidelity of the output waveform.

[0054] As can be seen, this invention establishes a real-time mapping channel from microscopic chip bus behavior to the macroscopic high-voltage physical world. Unlike existing hardware stamping techniques that are only used for offline performance analysis, the physical time snapshot obtained by this invention takes effect instantaneously and participates in the control closed loop. Unlike existing dynamic tick techniques that are only used for low power consumption, the scheduling strategy of this invention is based on the physical phase angle of the power grid.

[0055] It should be noted that the above embodiments are merely preferred embodiments of the present invention and not limitations thereof. For example, although this embodiment uses a PPEC controller as an example for illustration, the core ideas of the present invention are also applicable to digital signal processors, microcontrollers, field-programmable gate arrays, and embedded chips based on the RISC-V architecture. As long as the hardware platform has hardware timers and direct memory access or similar parallel data transfer capabilities, the spatiotemporal mapping and scheduling optimization method described in this invention can be used. Furthermore, the generation method of the target voltage vector and pulse width modulation signal described in this invention is not limited to space vector pulse width modulation. In scenarios such as sinusoidal pulse width modulation, discontinuous pulse width modulation, and model predictive control, using the time debt method described in this invention to calculate the compensation amount of phase or amplitude also falls within the technical scope of this invention.

Claims

1. A method for scheduling optimization of a multi-task real-time operating system for a PPEC controller, characterized in that, include: By using hardware timers and direct memory access units with hardware triggering capabilities, a physical time snapshot of the interrupt response is constructed before the central processing unit responds, including the entry and exit times when a rigid control task is interrupted by a non-control task. The time debt is calculated based on the entry time and the exit time. A spatiotemporal mapping model is constructed in conjunction with the grid reference angular frequency to convert the time debt into the phase lag angle of the target voltage vector. The time debt is compared with a preset atomic operation time threshold, and the control mode is determined based on the comparison result; Task scheduling is performed based on the control mode, and the target voltage vector is corrected using the phase lag angle to obtain the corrected pulse width modulation signal.

2. The method for scheduling and optimizing a multi-task real-time operating system for a PPEC controller according to claim 1, characterized in that, The entry and exit times include: The hardware timer is configured to run in free mode, and its counting frequency is set to be synchronized with the main frequency of the PPEC controller. When the direct memory access unit detects an interrupt trigger signal of the non-control task, it reads the count value of the hardware timer as the entry time before the central processing unit responds to the interrupt. When the interrupt return instruction of the non-control task is detected, it reads the count value of the hardware timer as the exit time.

3. The method for scheduling and optimizing a multi-task real-time operating system for a PPEC controller according to claim 1, characterized in that, The time debt satisfies the following relationship: in, For the aforementioned time debt; The entry time; The exit time is mentioned above; The counting period of the hardware timer; The inherent overhead time for context switching of the PPEC controller.

4. The method for scheduling and optimizing a multi-task real-time operating system for a PPEC controller according to claim 1, characterized in that, The reference angular frequency of the power grid is acquired in real time by a software phase-locked loop running in the PPEC controller.

5. The method for scheduling and optimizing a multi-task real-time operating system for a PPEC controller according to claim 1, characterized in that, The method further includes: obtaining the total duration of the current control cycle, calculating the difference between the total duration of the current control cycle and the time debt; if the difference is greater than or equal to the atomic operation time threshold, determining that the control mode is a compression mode; if the difference is less than the atomic operation time threshold, determining that the control mode is a circuit breaker mode.

6. The method for scheduling and optimizing a multi-task real-time operating system for a PPEC controller according to claim 1, characterized in that, The atomic operation time threshold was obtained through a closed-loop calculation time calibration experiment.

7. The method for scheduling and optimizing a multi-task real-time operating system for a PPEC controller according to claim 1, characterized in that, The task scheduling includes: When the control mode is the circuit breaker mode, all elastic control tasks to be executed in the current control cycle are immediately suspended, the computing resources of the PPEC controller are released, the control flow of the PPEC controller is reset to the starting state of the rigid control task, the output state of the pulse width modulation signal is locked, and the synchronous trigger signal of the next control cycle is awaited. When the control mode is the compression mode, the physical remaining available time slice of the current control cycle is calculated, and the hardware timer reload value of the task scheduler is dynamically modified according to the physical remaining available time slice. The allocation time of the elastic control task is nonlinearly compressed, and the elastic control task is executed according to priority within the compressed allocation time.

8. The method for scheduling and optimizing a multi-task real-time operating system for a PPEC controller according to claim 1, characterized in that, The correction of the target voltage vector includes: acquiring the grid voltage reference phase in real time during the current control cycle, performing phase correction on the grid voltage reference phase using the phase lag angle to obtain a physical synchronization phase containing time-domain compensation information, performing vector synthesis calculation on the target voltage vector based on the physical synchronization phase, and then generating the corrected pulse width modulation signal.

9. A multi-task real-time operating system scheduling optimization method for PPEC controllers according to claim 1, characterized in that, The rigid control tasks include analog-to-digital conversion sampling, proportional-integral-derivative closed-loop calculation, and space vector pulse width modulation; the non-control tasks include industrial fieldbus communication interruption response, external fault signal capture, and non-volatile memory read / write operations.

10. A multi-task real-time operating system scheduling optimization method for a PPEC controller according to claim 7, characterized in that, The flexible control task refers to a user domain background task with a lower priority than the rigid control task, specifically including: waveform data buffering and uploading of the online oscilloscope, register reading and writing of the industrial fieldbus protocol, and parameter refreshing of the human-machine interface.

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