Radar target rapid center gathering detection method and system based on multi-core DSP cooperation

Abstract

The invention discloses a radar target rapid center gathering detection method and system based on multi-core DSP cooperation. The method comprises the steps of obtaining a radar two-dimensional data matrix from a shared external memory based on scheduling of a main control core, and carrying the radar two-dimensional data matrix into a multi-core DSP; in the multi-core DSP, a master control core performs spatial slicing on a radar two-dimensional data matrix along any dimension to generate a plurality of data slices, and the data slices are distributed to a plurality of operation slave cores for parallel processing; each operation slave core processes the distributed data slices by adopting a cascade detection strategy based on an EDMA ping-pong buffer mechanism, and the cascade detection strategy comprises the following steps: performing one-dimensional CFAR sparse coarse detection on the data slices to generate a sparse binary mask marked with candidate points; and based on the adaptive parameters, carrying out center gathering fine detection on each candidate point in the sparse binary mask, extracting a target center, and outputting a final target list. The method improves the processing speed, the parallel efficiency, the hardware resource utilization rate and the detection precision.

Description

Technical Field

[0001] This invention belongs to the field of radar signal processing technology, specifically relating to a method and system for rapid radar target focusing detection based on multi-core DSP collaboration. Background Technology

[0002] In the field of high-performance embedded computing (HPEC), multi-core digital signal processors (DSPs), such as the Texas Instruments TMS320C6678, are widely used in the back-end signal processing of radar systems due to their powerful floating-point operation capabilities, low power consumption, and real-time processing characteristics. The radar target detection process typically includes two main stages: constant false alarm rate (CFAR) processing and target extraction.

[0003] In the back-end signal processing of radar systems, existing CFAR processing methods typically adopt a "full image traversal + serial processing" model, which is mostly two-dimensional processing, involves multi-dimensional data coupling, and uses a fixed cross-shaped window for centering. Specifically, traditional CFAR processing uses single-core or simple multi-core task partitioning, directly performing two-dimensional sliding window calculations on external DDR (Double Data Rate Synchronous Dynamic Random Access Memory) memory. For example, it performs two-dimensional CFAR detection by traversing the RD (Range-Doppler) matrix element by element, and uses a fixed cross-shaped window for center extraction.

[0004] However, with the continuous improvement of modern radar resolution, existing technologies face significant computational and transmission bottlenecks in backend signal processing. First, the RD matrix generated by high-resolution radar is often enormous, and large-matrix two-dimensional sliding window operations lead to frequent cache invalidations and excessive bus bandwidth consumption. This results in existing serial detection algorithms being too time-consuming to execute on general-purpose processors, failing to meet millisecond-level real-time refresh requirements. Second, in embedded DSP architectures, the CPU (Central Processing Unit) core's direct access to external DDR memory is much slower than its internal processing speed. Frequent global memory accesses cause the core to idle for extended periods while waiting for data loading, significantly reducing overall processing efficiency. Third, traditional two-dimensional CFAR detection algorithms involve data coupling between the range dimension and the Doppler dimension, leading to computational complexity and difficulty in parallelization. Furthermore, the sidelobe effect or noise interference of strong targets results in a large number of redundant threshold points in the output neighborhood (i.e., the "point cloud" phenomenon). These points, without adaptive clustering or convergence processing, increase the pressure on subsequent data processing links. Meanwhile, the existing focus operation uses a fixed cross window, which cannot adapt to the size and shape of the target, resulting in low detection accuracy or missing small targets. This leads to an excessive workload for subsequent target parameter estimation (such as angle measurement and tracking).

[0005] In summary, existing radar target CFAR and focal point detection methods suffer from low cache hit rates, high computational coupling, numerous false alarms, and low detection accuracy. Therefore, fully utilizing the parallel computing capabilities of multi-core architectures, reducing data transmission overhead, and optimizing algorithms to decouple and achieve adaptive processing are key challenges for improving overall system performance. Summary of the Invention

[0006] To address the aforementioned problems in the existing technology, this invention provides a method and system for rapid radar target focusing detection based on multi-core DSP collaboration. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, this invention proposes a rapid radar target focusing detection method based on multi-core DSP collaboration, wherein the multi-core DSP includes a master control core and multiple slave processing cores; the method includes: Based on the scheduling of the main control core, the radar two-dimensional data matrix is ​​obtained from the shared external memory and transferred to the multi-core DSP; Within a multi-core DSP, the master control core spatially slices the radar two-dimensional data matrix along any dimension, generating multiple data slices, and distributes them to multiple processing slave cores for parallel processing. Each operation kernel uses the EDMA (Enhanced Direct Memory Access) ping-pong buffer mechanism to process the allocated data slices using a cascaded detection strategy, including: performing one-dimensional CFAR sparsification coarse detection on the data slices to generate a sparse binary mask marked with candidate points; performing centering fine detection on each candidate point in the sparse binary mask based on adaptive parameters to extract the target center and output the final target list.

[0007] Secondly, this invention proposes a radar target fast convergence detection system based on multi-core DSP collaboration, used to implement the radar target fast convergence detection method based on multi-core DSP collaboration proposed in the first aspect of this invention. The system includes: Shared external memory DDR3 is used to store the complete radar two-dimensional data matrix and processing results; The multi-core DSP comprises one processor core configured as the master control core and multiple processor cores configured as slave processing cores. The master control core spatially slices the radar 2D data matrix along any dimension, generating multiple data slices, which are then distributed to the slave processing cores. The slave processing cores process the allocated data slices using a cascaded detection strategy based on an EDMA ping-pong buffer mechanism. This includes: performing one-dimensional CFAR sparsity coarse detection on the data slices to generate a sparse binary mask marked with candidate points; performing centering fine detection on each candidate point in the sparse binary mask based on adaptive parameters to extract the target center and output the final target list. The EDMA3 controller is configured to execute the EDMA ping-pong buffer mechanism to move data between shared external memory and the main control core and each processing slave core.

[0008] The beneficial effects of this invention are: This invention proposes a rapid radar target centering detection method based on multi-core DSP collaboration. This method employs a highly efficient detection architecture of "parallel data slicing + EDMA ping-pong buffer + one-dimensional CFAR coarse detection and adaptive centering fine detection." First, based on the scheduling of the master control core, a two-dimensional radar data matrix is ​​acquired from shared external memory and transferred to the multi-core DSP. Then, the master control core spatially slices the radar two-dimensional data matrix along any dimension, generating multiple data slices, which are then distributed to multiple slave cores for parallel processing. Next, each slave core processes its assigned data slices using a cascaded detection strategy based on the EDMA ping-pong buffer mechanism: this includes performing one-dimensional CFAR sparsification coarse detection on the data slices to generate a sparse binary mask marked with candidate points; and performing centering fine detection on each candidate point in the sparse binary mask based on adaptive parameters to extract the target center and output the final target list. This method, on the one hand, removes inter-pulse coupling and EDMA-masked memory access latency through one-dimensional CFAR, reducing computational coupling and improving cache hit rate; at the same time, combined with multi-core parallel slicing processing, it significantly improves processing speed and parallel efficiency, and improves hardware resource utilization; on the other hand, it uses a cascaded detection strategy to achieve secondary detection of target points, effectively removing sidelobe points, significantly reducing the load and power consumption of the back-end processor, and adaptive parameters improve the extraction accuracy of small and irregular targets, reduce false alarm rate, and thus improve detection accuracy.

[0009] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0010] Figure 1 This is a flowchart illustrating the rapid radar target convergence detection method based on multi-core DSP collaboration provided in an embodiment of the present invention. Figure 2 This is a diagram of a multi-core parallel processing and EDMA ping-pong buffer architecture provided in an embodiment of the present invention. Figure 3 This is a flowchart illustrating the cascaded detection algorithm provided in an embodiment of the present invention; Figure 4 This is a comparison of the RD graphs before and after processing by the centroid algorithm provided in an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] The first aspect of this invention provides a rapid radar target focusing detection method based on multi-core DSP collaboration. This method is based on a highly efficient detection architecture of "data slicing parallelism + EDMA ping-pong buffer + one-dimensional CFAR coarse detection and adaptive focusing fine detection," wherein the multi-core DSP includes one master control core and multiple slave operation cores. This architecture does not depend on a specific radar waveform form (such as linear frequency modulation or phase coding), but focuses on high-speed data throughput and accurate target extraction. By converting traditional two-dimensional CFAR into one-dimensional processing, inter-pulse data coupling is removed, facilitating multi-core parallelism; simultaneously, the focusing operation uses adaptive parameters, improving detection accuracy.

[0013] Please refer to the above. Figure 1 and Figure 2 , Figure 1 This is a flowchart illustrating the radar target fast convergence detection method based on multi-core DSP collaboration provided in an embodiment of the present invention. Figure 2 This invention provides a multi-core parallel processing and EDMA ping-pong buffer architecture diagram; the method includes: Step 1: Based on the scheduling of the main control core, obtain the radar two-dimensional data matrix from the shared external memory and move it to the multi-core DSP.

[0014] In this embodiment, the radar two-dimensional data matrix can be an RD matrix or a synthetic aperture radar image matrix. Preferably, this embodiment mainly uses an RD matrix as an example for explanation.

[0015] Specifically, the original radar RD matrix is ​​stored in a shared memory. Through scheduling by the main control core, the RD matrix is ​​moved to the multi-core DSP for further processing.

[0016] Optionally, this embodiment is configured with a DDR3 external memory to store the complete RD spectrum data matrix as a global shared storage; at the same time, this embodiment is also configured with an EDMA3 controller to realize efficient data transfer between the DDR3 external memory and the multi-core DSP, supporting multi-channel parallel transmission.

[0017] Step 2: Within the multi-core DSP, the master control core spatially slices the radar two-dimensional data matrix along any dimension, generating multiple data slices, and distributes them to multiple slave cores for parallel processing.

[0018] Optionally, as one implementation, this embodiment configures a multi-core DSP including one master control core (Core0) and seven slave cores (Core1-Core7) to achieve dynamic load balancing. The core of the multi-core DSP can use an on-chip L2 SRAM cache. The master control core (Core0) is used to create slice tasks based on the dimensions of the radar two-dimensional data matrix and distribute them to the slave cores (Core1-Core7).

[0019] Optionally, as an implementation method, the main control core Core0 spatially slices the radar two-dimensional data matrix along any dimension to generate multiple data slices. The specific strategy for spatial slicing is as follows: based on the data continuity of the radar two-dimensional data matrix, it prioritizes uniform slicing along the dimension with high data continuity to minimize boundary effects and facilitate independent processing of subsequent one-dimensional CFAR.

[0020] For example, the master core Core0 can divide the RD matrix into seven equal parts along either the "distance dimension" or the "Doppler dimension" based on its dimensions (Range × Doppler), and distribute these parts to seven slave cores Core1-Core7. Each of the seven slave cores independently executes the subsequent "data transfer - one-dimensional CFAR detection and adaptive convergence - result write-back" process without interference. Through a shared memory mechanism, the results are written back to shared external memory, avoiding inter-core synchronization overhead.

[0021] This design ensures full utilization of computing resources and supports expansion to DSP platforms with more cores. In particular, after decoupling in one-dimensional CFAR, parallel efficiency is significantly improved.

[0022] It should be noted that in this embodiment, the master core Core0 distributes data slices to the slave cores Core1-Core7 via Inter-processor Communication (IPC) technology based on the computed slice index and task descriptor. The task descriptor at least contains the start address, length information, source address, and destination address of the data slice in shared memory. The IPC technology used in this embodiment supports load balancing, dynamically allocating slice sizes according to core load, ensuring non-blocking task transmission.

[0023] Step 3: Each operation kernel processes the allocated data slices using a cascaded detection strategy based on the EDMA ping-pong buffer mechanism, including: performing one-dimensional CFAR sparsification coarse detection on the data slices to generate a sparse binary mask marked with candidate points; performing centering fine detection on each candidate point in the sparse binary mask based on adaptive parameters to extract the target center and output the final target list.

[0024] Optionally, this embodiment opens up a double buffer, namely Ping Buffer and Pong Buffer, inside each operation core for temporary storage of data slices, while using the EDMA bus for efficient data transfer and supporting multi-channel parallel transmission.

[0025] While the DSP core is computing a data block in the Ping buffer, the EDMA controller moves the next data block from DDR3 to the Ping buffer in parallel. Synchronization is achieved through a semaphore mechanism, ensuring that computation time completely masks data transfer time, thus enabling the core processing unit to... Running at full capacity.

[0026] It should be noted that the timing condition of the EDMA ping-pong buffer mechanism is met: the processing time of the data slice verification task completely masks the time of moving the radar two-dimensional data matrix from shared external memory to the multi-core DSP.

[0027] Assuming the data block size is The computation time from the core is The moving time is Then the following conditions must be met: ; This ensures that memory access latency is completely hidden, preventing core idling.

[0028] Furthermore, for the processing of data slices, this embodiment designs a cascaded detection algorithm. This algorithm abandons the traditional two-dimensional CFAR detection logic and adopts one-dimensional processing and a cascaded strategy to improve efficiency, remove data coupling, and reduce the amount of output data. The algorithm consists of two stages to ensure a gradual selection from coarse to fine: the first stage is a one-dimensional CFAR sparsity coarse detection, and the second stage is an adaptive convergent fine detection. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a flowchart illustrating the cascaded detection algorithm provided in an embodiment of the present invention.

[0029] In the first stage, a one-dimensional CFAR sparsification coarse check is performed on the data slices to generate a sparse binary mask labeled with candidate points.

[0030] First, calculate the one-dimensional CFAR detection threshold independently along the distance dimension or Doppler dimension for the data slice.

[0031] In this embodiment, the one-dimensional CFAR detection threshold is calculated using the cell average constant false alarm rate algorithm, and the calculation formula is as follows: ; In the formula, The threshold value for one-dimensional CFAR detection is represented by, The preset false alarm rate factor, It is represented as the average background noise value within a one-dimensional neighborhood.

[0032] Then, the data slices are scanned according to the one-dimensional CFAR detection threshold, points whose amplitude exceeds the detection threshold are marked, and other points are set to zero to obtain a sparse binary mask.

[0033] This embodiment converts 2D CFAR into 1D CFAR detection, making the processing of each dimension independent, facilitating multi-core parallel allocation, and significantly reducing computational complexity. Simultaneously, the output sparse binary mask only marks regions where targets may exist (i.e., points exceeding the threshold). This stage significantly reduces the search space for subsequent processing, filtering out 99% of irrelevant points in the matrix, while avoiding the parallel bottleneck caused by 2D coupling.

[0034] In the second stage, each candidate point in the sparse binary mask is subjected to a fine-tuning process based on adaptive parameters to extract the target center and output the final target list.

[0035] Optionally, in this embodiment, an adaptive square window centroid detection method, a connected component labeling method, or a centroid method can be used to extract the target center from each candidate point in the sparse binary mask and output the final target list.

[0036] Specifically, for each candidate point in the sparse binary mask, an adaptive square window centroid detection method is used to extract the target center, and the final target list is output, including: First, for each candidate point in the sparse binary mask, a local window of size N×N is constructed centered on that candidate point. The size parameter N of the local window is determined based on the standard deviation of the local noise within that window. and window maximum energy value Perform dynamic adaptive adjustments, for example: .

[0037] This embodiment employs an adaptive mechanism to ensure that the window size adapts to the target shape and small target detection, avoiding false alarms caused by an excessively large fixed window or missing details caused by an excessively small fixed window.

[0038] Then, iterate through all points within the current local window. When the magnitude of a candidate point is equal to the maximum value within the local window, the candidate point is determined to be the target center.

[0039] Specifically, iterate through all data points within the window, only when the center point... When the following conditions are met: ; That is, the point is considered the center of the target only if it is the maximum value within the window. This represents the set of all pixel values ​​within the window.

[0040] Finally, iterate through all candidate points in the sparse binary mask, find all target centers, and output the final target list.

[0041] This achieves rapid, focused detection of radar targets.

[0042] Please see Figure 4 , Figure 4 This is a comparison of the RD graphs before and after processing by the centroid algorithm provided in this embodiment of the invention. The left side shows the RD graph before processing, and the right side shows the RD graph after processing.

[0043] As can be seen, after processing with the adaptive square window convergence precision detection method of this invention, the diffused "point cloud phenomenon" (multiple adjacent high-value points caused by side lobes) can be converged into a unique "pixel-level" center point, thereby completely eliminating false nearest-neighbor points. Compared with the traditional cross-window, the adaptive square window provided in this embodiment improves the detection accuracy by 20%-30%, especially in complex clutter environments. Compared with traditional methods, this algorithm can reduce the number of output points by 80%-90%. Moreover, this method does not require any prior waveform information and can be implemented based solely on the energy topology.

[0044] The radar target fast focus detection method based on multi-core DSP collaboration proposed in this invention has the following beneficial effects: 1. Significantly improved processing speed and parallel efficiency.

[0045] This invention eliminates inter-pulse coupling and masks memory access latency through one-dimensional CFAR and multi-core parallel slicing. In actual testing, when processing a 1024×1024 matrix, the processing time is reduced from seconds to less than 80ms (depending on the DSP clock frequency, such as 1.25GHz). This meets real-time requirements, such as achieving a refresh rate of over 12 frames per second in automotive radar, and improving parallel utilization by 2-3 times.

[0046] 2. High utilization of hardware resources.

[0047] This invention solves the problem of CPU idling while waiting for data and the parallel bottleneck of two-dimensional coupling, and the utilization rate of the core computing unit can reach more than 95%.

[0048] 3. Improved backend data load reduction and detection accuracy.

[0049] This invention employs an adaptive square window convergence algorithm to "purify" targets during the detection phase, reducing the number of points sent to data processing modules (such as tracking / track management) by more than 90% (effectively removing sidelobe points), thereby significantly reducing the load and power consumption of the backend processor. Simultaneously, the adaptive parameters improve the extraction accuracy for small and irregular targets, resulting in a 20% reduction in the false alarm rate.

[0050] 4. High versatility.

[0051] This architecture is not dependent on a specific radar system (such as linear frequency modulation (LFM) or phase coding). It can be directly applied as long as the input is a two-dimensional amplitude matrix (such as RD spectrum or synthetic aperture radar SAR image) and supports porting to other embedded platforms.

[0052] In summary, the radar target fast center detection method based on multi-core DSP collaboration proposed in this invention adopts an efficient detection architecture of "parallel data slicing + EDMA ping-pong buffer + one-dimensional CFAR coarse detection and adaptive center detection". First, based on the scheduling of the master control core, the radar two-dimensional data matrix is ​​obtained from the shared external memory and transferred to the multi-core DSP. Then, the master control core spatially slices the radar two-dimensional data matrix along any dimension to generate multiple data slices, which are then distributed to multiple processing slave cores for parallel processing. Next, each processing slave core processes the allocated data slices using a cascaded detection strategy based on the EDMA ping-pong buffer mechanism: including performing one-dimensional CFAR sparsification coarse detection on the data slices to generate a sparse binary mask marked with candidate points; and performing center detection on each candidate point in the sparse binary mask based on adaptive parameters to extract the target center and output the final target list. This method, on the one hand, removes inter-pulse coupling and EDMA-masked memory access latency through one-dimensional CFAR, reducing computational coupling and improving cache hit rate; at the same time, combined with multi-core parallel slicing processing, it significantly improves processing speed and parallel efficiency, and improves hardware resource utilization; on the other hand, it uses a cascaded detection strategy to achieve secondary detection of target points, effectively removing sidelobe points, significantly reducing the load and power consumption of the back-end processor, and adaptive parameters improve the extraction accuracy of small and irregular targets, reduce false alarm rate, and thus improve detection accuracy.

[0053] Based on the same inventive concept, a second aspect of this invention also provides a radar target fast focusing detection system based on multi-core DSP collaboration. Please refer again. Figure 2 The system, as shown in the architecture diagram, includes: Shared external memory DDR3 is used to store the complete radar two-dimensional data matrix and processing results; The multi-core DSP comprises one processor core configured as the master control core and multiple processor cores configured as slave processing cores. The master control core spatially slices the radar 2D data matrix along any dimension, generating multiple data slices, which are then distributed to the slave processing cores. The slave processing cores process the allocated data slices using a cascaded detection strategy based on an EDMA ping-pong buffer mechanism. This includes: performing one-dimensional CFAR sparsity coarse detection on the data slices to generate a sparse binary mask marked with candidate points; performing centering fine detection on each candidate point in the sparse binary mask based on adaptive parameters to extract the target center and output the final target list. The EDMA3 controller is configured to execute the EDMA ping-pong buffer mechanism to move data between shared external memory and the main control core and each processing slave core.

[0054] Furthermore, in this embodiment, the core of the multi-core DSP can adopt an L2 SRAM on-chip cache, wherein each operation has a dual buffer in the on-chip cache of the core, including a Ping buffer and a Pong buffer, to implement the EDMA ping-pong buffer mechanism.

[0055] Specifically, for the system implementation, since its implementation process is basically similar to that of the method implementation and has similar beneficial effects, the description is relatively simple. For relevant details, please refer to the description of the method implementation. This implementation will not repeat the description here.

[0056] It should be noted that the radar target fast focus detection method based on multi-core DSP collaboration provided in this invention can be ported to an FPGA+DSP heterogeneous platform. The FPGA utilizes its hardware acceleration capabilities to handle high-parallelism one-dimensional CFAR coarse detection, while the DSP processes complex adaptive focus logic to maintain flexibility. Alternatively, it can be ported to a GPU (CUDA) platform, leveraging the high bandwidth of GPU memory to process larger-scale matrices, for example, running on an NVIDIA Jetson series.

[0057] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A rapid radar target focusing detection method based on multi-core DSP collaboration, characterized in that, The multi-core DSP includes a master control core and multiple slave processing cores; the method includes: Based on the scheduling of the main control core, the radar two-dimensional data matrix is ​​obtained from the shared external memory and transferred to the multi-core DSP; Within the multi-core DSP, the main control core spatially slices the radar two-dimensional data matrix along any dimension to generate multiple data slices, which are then distributed to multiple processing slave cores for parallel processing. Each operation kernel processes the allocated data slices using a cascaded detection strategy based on the EDMA ping-pong buffer mechanism, including: performing one-dimensional CFAR sparsification coarse detection on the data slices to generate a sparse binary mask marked with candidate points; performing centroid fine detection on each candidate point in the sparse binary mask based on adaptive parameters to extract the target center and output the final target list.

2. The radar target fast focal point detection method based on multi-core DSP collaboration according to claim 1, characterized in that, The radar two-dimensional data matrix includes a range-Doppler matrix or a synthetic aperture radar image matrix.

3. The radar target fast focal point detection method based on multi-core DSP collaboration according to claim 1, characterized in that, In the process of the main control core spatially slicing the radar two-dimensional data matrix along any dimension to generate multiple data slices, the specific strategy of spatial slicing is as follows: Based on the data continuity of the radar two-dimensional data matrix, it is preferentially divided uniformly along the dimension with high data continuity.

4. The radar target fast focal point detection method based on multi-core DSP collaboration according to claim 1, characterized in that, The timing conditions of the EDMA ping-pong buffer mechanism are satisfied as follows: The processing time of the data slice verification task completely masks the time it takes to move the radar two-dimensional data matrix from the shared external storage to the multi-core DSP.

5. The radar target fast focal point detection method based on multi-core DSP collaboration according to claim 1, characterized in that, Perform one-dimensional CFAR sparsity coarse detection on the data slice to generate a sparse binary mask labeled with candidate points, including: The one-dimensional CFAR detection threshold is independently calculated along the distance dimension or Doppler dimension for the data slice; The data slice is scanned according to the one-dimensional CFAR detection threshold, points whose amplitude exceeds the detection threshold are marked, and other points are set to zero to obtain a sparse binary mask.

6. The radar target fast focal point detection method based on multi-core DSP collaboration according to claim 5, characterized in that, The one-dimensional CFAR detection threshold is calculated using the cell average constant false alarm rate algorithm, and the calculation formula is as follows: ； In the formula, The threshold value for one-dimensional CFAR detection is represented by, The preset false alarm rate factor, It is represented as the average background noise value within a one-dimensional neighborhood.

7. The radar target fast focal point detection method based on multi-core DSP collaboration according to claim 1, characterized in that, Based on adaptive parameters, a centering and fine-tuning process is performed on each candidate point in the sparse binary mask to extract the target center, and a final target list is output, including: For each candidate point in the sparse binary mask, the target center is extracted using an adaptive square window centroid detection method, a connected component labeling method, or a centroid method, and the final target list is output.

8. The radar target fast focal point detection method based on multi-core DSP collaboration according to claim 7, characterized in that, For each candidate point in the sparse binary mask, an adaptive square window centroid detection method is used to extract the target center, and the final target list is output, including: For each candidate point in the sparse binary mask, a local square window of size N×N is established centered on that candidate point; wherein the size parameter N of the local square window is based on the standard deviation of the local noise within the window. and window maximum energy value Make dynamic adjustments; Traverse all points within the current local window. When the magnitude of a candidate point is equal to the maximum value within the local window, determine that the candidate point as the target center. Traverse all candidate points in the sparse binary mask, find all target centers, and output the final target list.

9. A radar target fast focus detection system based on multi-core DSP collaboration, used to implement the radar target fast focus detection method based on multi-core DSP collaboration as described in any one of claims 1-8, characterized in that, The system includes: Shared external memory DDR3 is used to store the complete radar two-dimensional data matrix and processing results; The multi-core DSP includes one processor core configured as the master control core and multiple processor cores configured as slave processing cores. The master control core is used to spatially slice the radar two-dimensional data matrix along any dimension, generating multiple data slices, and distributing them to the multiple slave processing cores. The slave processing cores are used to process the allocated data slices using a cascaded detection strategy based on an EDMA ping-pong buffer mechanism, including: performing one-dimensional CFAR sparsity coarse detection on the data slices to generate a sparse binary mask marked with candidate points; performing centering fine detection on each candidate point in the sparse binary mask based on adaptive parameters to extract the target center and output the final target list. The EDMA3 controller is configured to execute the EDMA ping-pong buffer mechanism to move data between the shared external memory and the main control core and each slave core.

10. The radar target fast focusing detection system based on multi-core DSP collaboration according to claim 9, characterized in that, The operation allocates a dual buffer from the core's on-chip cache, including a Ping buffer and a Pong buffer, to implement the EDMA ping-pong buffer mechanism.

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