PUF (Physical Unclonable Function) system of dual-mode ternary content addressable memory

Abstract

The invention discloses a PUF (Physical Unclonable Function) system of a dual-mode ternary content addressable memory, which comprises a mode switching module, an MRAM (Magnetic Random Access Memory) type TCAM (Ternary Content Addressable Memory) storage array, an addressing module and a PUF module, the MRAM type TCAM storage array is formed by distributing MRAM type TCAM storage units according to an n-row n-column array, and the PUF module adopts a PUF response generation mechanism based on time sequence arbitration, two rows of leakage current signals are selected from n rows of leakage current signals generated by an MRAM type TCAM storage array, the difference of the two rows of leakage current signals is converted into two digital edge signals with a time sequence difference, arbitration is carried out based on the time sequence difference of the two digital edge signals, and a PUF response is generated; the method has the advantages that effective data which is originally stored in the MRAM type TCAM storage unit and is used for addressing cannot be damaged when the MRAM type TCAM storage unit works in the PUF mode, so that a data migration process does not need to be additionally quoted when the PUF mode and the TCAM mode are switched, and the increase of area and power consumption and the bypass leakage risk caused by the additional quotation of the data migration process are avoided.

Description

Technical Field

[0001] This invention relates to PUF systems, and more particularly to a PUF system for a dual-mode tri-state content-addressable memory. Background Technology

[0002] In high-speed network devices and IoT edge computing nodes, Tri-state Content Addressable Memory (TCAM) is a core component for implementing critical functions such as route lookup, packet classification, and access control list lookup, thanks to its parallel lookup capabilities. Among various TCAM implementation technologies, TCAM based on Magnetic Random Access Memory (MRAM), i.e., MRAM-type TCAM, has become the preferred solution to meet the stringent performance and energy efficiency requirements of the aforementioned applications due to its non-volatility, low static power consumption, and high read / write endurance.

[0003] However, while the non-volatile nature of MRAM-based TCAMs brings convenience, it also introduces serious security challenges. Sensitive data stored on them, such as routing tables and access control policies, remain persistent even after power loss, making them more vulnerable to physical attacks. These attacks can occur through methods such as bypass channel analysis, direct reading via microprobes, or unauthorized chip cloning, leading to the leakage or malicious alteration of sensitive information. Furthermore, the lack of effective authentication mechanisms for query and write operations in MRAM-based TCAM architectures allows attackers to inject forged matching rules, misleading network traffic and causing data breaches or network service interruptions.

[0004] To address the aforementioned security threats, Physically Unclonable Functions (PUF) technology is considered a promising solution. PUFs utilize the inherent and uncontrollable microscopic process variations in integrated circuit manufacturing to generate unique stimulus-response pairs for each chip. Since the keys do not need to be statically stored in non-volatile memory, this fundamentally avoids the risk of key storage leakage.

[0005] Currently, some research attempts to combine PUF with the general TCAM structure to build a TCAM-PUF system through a function reuse architecture. In this TCAM-PUF system, the TCAM array (composed of multiple TCAM storage cells arranged in an array pattern) is reused. In TCAM mode, the TCAM array performs storage and addressing functions; in PUF mode, the TCAM array acts as a PUF array to generate responses. However, these TCAM-PUF schemes share a common problem: to achieve PUF functionality, the physical operating state of the storage cells in the TCAM array needs to be directly configured or changed in PUF mode. This operation inevitably destroys the valid data originally stored in the TCAM storage cells for addressing, resulting in data loss. Therefore, in such TCAM-PUF systems, a data migration process must be introduced before switching from TCAM mode to PUF mode. This involves pre-reading the valid stored data in the TCAM array and transferring it to a dedicated additional temporary storage. After the PUF mode has finished working, before switching back to TCAM mode, this data must be completely written back to the TCAM array to restore its lookup function.

[0006] When the aforementioned TCAM-PUF system is implemented in a TCAM array composed of MRAM-type TCAM memory cells, its inherent data migration problem raises a series of more specific and severe challenges. First, from a hardware overhead perspective, the additional temporary storage introduced for data migration further increases the chip's silicon area and overall power consumption, contradicting the initial intention of using MRAM technology to achieve high integration and low power consumption. This problem is particularly prominent in resource-constrained IoT edge devices. Second, from a security perspective, the data migration mechanism creates new and more explicit security vulnerabilities in MRAM-type TCAMs. Data in MRAM-type TCAM memory cells is characterized by its magnetization state, which may leave physical residual characteristics after being written. During data write-back, the magnetization history left on the MRAM-type TCAM memory cells from previous PUF mode operation, or the charge information remaining in the data path and additional temporary storage, may constitute residual characteristics. By analyzing these residual features, attackers may be able to reverse engineer or partially reconstruct the PUF response used to generate the key or the stored data in the protected MRAM-type TCAM storage unit. This could cause the PUF mechanism, which is supposed to enhance security, to introduce the risk of bypass leakage due to architectural flaws. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a dual-mode tri-state content addressable memory PUF system that does not destroy the valid data originally stored in the MRAM-type TCAM memory cell for addressing when working in PUF mode, thereby eliminating the need for an additional data migration process when switching between PUF mode and TCAM mode, and avoiding the increase in area and power consumption and the risk of bypass leakage caused by the additional data migration process.

[0008] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: a PUF system for a dual-mode tri-state content-addressable memory, comprising a mode switching module, an MRAM-type TCAM memory array, an addressing module, and a PUF module; the MRAM-type TCAM memory array consists of n n MRAM-type TCAM memory cells are arranged in an n x n array, where n is an integer greater than or equal to 2. The PUF system has a TCAM write mode, a TCAM addressing mode, and a PUF mode. The mode switching module is used to switch the PUF system between the TCAM write mode, the TCAM addressing mode, and the PUF mode. The PUF system can perform data writing operations in TCAM write mode, addressing operations in TCAM addressing mode, and PUF response generation in PUF mode. The addressing module is used to address the MRAM-type TCAM memory array and obtain the addressing result. The PUF module is used to generate a PUF response. The PUF module adopts a timing arbitration-based PUF response generation mechanism, selects two rows of leakage current signals from the n rows of leakage current signals generated by the MRAM-type TCAM memory array, converts the difference between the two rows of leakage current signals into two digital edge signals with timing difference, and arbitrates based on the timing difference of the two digital edge signals to generate a PUF response.

[0009] Compared with existing technologies, the advantages of this invention are that the PUF module adopts a timing arbitration-based PUF response generation mechanism. It selects two rows of leakage current signals from the n rows of leakage current signals generated by the MRAM-type TCAM memory array, converts the difference between these two leakage current signals into two digital edge signals with a timing difference, and arbitrates based on the timing difference of the two digital edge signals to generate a PUF response. In other words, the PUF mode uses passive detection of the discharge characteristics of each row of MRAM-type TCAM memory cells to generate the PUF response. It employs a non-destructive read mechanism, thus eliminating the need to change the state of the MRAM-type TCAM memory cells. While generating the PUF response, it ensures the data integrity in the MRAM-type TCAM memory array. Therefore, when operating in PUF mode, this invention does not destroy the valid data originally stored in the MRAM-type TCAM memory cells for addressing. This eliminates the need for an additional data migration process when switching between PUF mode and TCAM mode, fundamentally eliminating the data migration process required for mode switching and avoiding the increased area, power consumption, and bypass leakage risks caused by the additional data migration process.

[0010] Furthermore, the PUF system also includes an address generation module, a row decoder, and a column decoder. When the PUF system is in TCAM write mode, and one or more MRAM-type TCAM memory cells are selected as target memory cells, and predetermined data is written to the target memory cells, firstly, the address generation module generates a first row address instruction and outputs it to the row decoder, and generates a first column address instruction and outputs it to the column decoder, based on a preset first external address instruction. The row decoder decodes the first row address instruction into a first row address signal and outputs it to the MRAM-type TCAM memory array. The column decoder decodes the first column address instruction into a first row address signal and outputs it to the MRAM-type TCAM memory array. The first column address signal is decoded and output to the MRAM-type TCAM memory array, changing the internal resistance state of the target memory cell. Then, the address generation module generates a second row address instruction and outputs it to the row decoder according to the preset second external address instruction, and generates a second column address instruction and outputs it to the column decoder. The row decoder decodes the second row address instruction into a second row address signal and outputs it to the MRAM-type TCAM memory array. The column decoder decodes the second column address instruction into a second column address signal and outputs it to the MRAM-type TCAM memory array, changing the internal resistance state of the target memory cell again to realize the predetermined data writing.

[0011] Furthermore, the PUF system also includes a pre-activation circuit and a reference circuit. The reference circuit provides a reference voltage signal to the addressing module. The pre-activation circuit, when the PUF system is in TCAM addressing mode or PUF mode, pre-charges the MRAM-type TCAM memory array according to an external pre-activation command, making it in an addressable state or a state to generate a PUF response. When the PUF system is in TCAM addressing mode, the pre-activation circuit first pre-charges the MRAM-type TCAM memory array according to an external pre-activation command, making the MRAM-type TCAM memory array in an addressable state. Subsequently, the address generation module generates a column address command according to the external address command and outputs it to the column decoder. The column decoder decodes the column address command into a parallel addressing signal and outputs it to the MRAM-type TCAM memory array, causing the MRAM-type TCAM memory array to generate n rows of leakage current signals and present different voltage states on the corresponding matching lines. The addressing module compares the voltages of the n matching lines with the reference voltage signal provided by the reference circuit to generate an addressing signal representing the highest priority matching position.

[0012] Furthermore, the mode switching module has an active mode and an inactive mode. When the mode switching module is in the inactive mode, neither the addressing module nor the PUF module can be activated, and the PUF system is in TCAM write mode. When the mode switching module is in the active mode, it can generate two activation signals under the control of an external mode switching command to activate either the addressing module or the PUF module. The two activation signals are opposite to each other. The first activation signal is output to the addressing module, and the second activation signal is output to the PUF module. When the addressing module is activated by the first activation signal, the PUF module cannot be activated by the second activation signal, and the PUF system enters TCAM addressing mode. When the PUF module is activated by the second activation signal, the addressing module cannot be activated by the first activation signal, and the PUF system enters PUF mode.

[0013] Furthermore, the row address signal includes two n-bit row address data, both binary data, namely a first n-bit row address data and a second n-bit row address data, which are opposites of each other; the column address signal includes two n-bit column address data, both binary data, namely a first n-bit column address data and a second n-bit column address data, which are opposites of each other; in the MRAM-type TCAM memory array, each MRAM-type TCAM memory cell has a bit line terminal, an anti-phase line terminal, a matching terminal, and an anti-matching terminal. The bit line terminals of n MRAM-type TCAM memory cells located in the same column are connected by a bit line. The anti-phase line terminals of the cells are connected by an anti-phase line. The matching terminals of n MRAM-type TCAM memory cells in the same row are connected by a matching line. The reverse matching terminals of n MRAM-type TCAM memory cells in the same row are connected by a reverse matching line. The n bit lines are connected to the first n-bit column address data, and the n anti-phase lines are connected to the second n-bit column address data. The n matching lines are connected to the first n-bit row address data and the precharge signal, and the n reverse matching lines are connected to the second n-bit row address data. The n-row leakage current signal generated by the MRAM-type TCAM memory array is generated by its n rows of MRAM-type TCAM memory cells. The leakage current signal generated by each row of MRAM-type TCAM memory cells is transmitted to the addressing module or the PUF module through the matching line connected to it.

[0014] Furthermore, each MRAM-type TCAM memory cell includes a first NMOS transistor, a second NMOS transistor, a first magnetic tunnel junction, and a second magnetic tunnel junction; the drain of the first NMOS transistor and the drain of the second NMOS transistor are connected, and their connection terminal is the matching terminal of the MRAM-type TCAM memory cell; the gate of the first NMOS transistor is the bit line terminal of the MRAM-type TCAM memory cell; the gate of the second NMOS transistor is the anti-phase line terminal of the MRAM-type TCAM memory cell; the source of the first NMOS transistor and the free layer of the first magnetic tunnel junction are connected, the source of the second NMOS transistor and the free layer of the second magnetic tunnel junction are connected, the fixed layer of the first magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are connected, and their connection terminal is the reverse matching terminal of the MRAM-type TCAM memory cell.

[0015] Furthermore, the PUF module includes two n-to-one selectors, two Schmitt trigger circuits, and a first SR flip-flop. Each n-to-one selector has n input terminals, an output terminal, and a selection terminal, used to select one of its input terminals and its output terminal according to the excitation signal connected to its selection terminal, so that the signal connected to that input terminal is transmitted to its output terminal. The two n-to-one selectors are a first n-to-one selector and a second n-to-one selector. Each Schmitt trigger circuit has an input terminal and an output terminal. The two Schmitt trigger circuits are a first Schmitt trigger circuit and a second Schmitt trigger circuit. The first SR flip-flop has a clock terminal, a first input terminal, a second input terminal, and an output terminal. The n input terminals of the first n-to-one selector and the n input terminals of the second n-to-one selector are all used to connect to n row drains. The current signal; the output of the first n-to-1 selector is connected to the input of the first Schmitt trigger circuit, the output of the second n-to-1 selector is connected to the input of the second Schmitt trigger circuit, the output of the first Schmitt trigger circuit is connected to the first input of the first SR flip-flop, the output of the second Schmitt trigger circuit is connected to the second input of the first SR flip-flop, the clock terminal of the first SR flip-flop is connected to the second activation signal, the output of the first SR flip-flop is used to output the PUF response, and the second activation signal serves as the clock signal for the first SR flip-flop. When the second activation signal is valid, the first SR flip-flop operates according to the clock signal timing, and the PUF module is activated at this time. When the second activation signal is invalid, the first SR flip-flop does not operate, and the PUF module is not activated at this time.

[0016] Furthermore, each Schmitt trigger rectifier circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage VDD. The gates of the first PMOS transistor, the second PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are connected, and their connection terminals are the input terminals of the Schmitt trigger rectifier circuit. The drains of the first PMOS transistor, the sources of the second PMOS transistor, and the third PMOS transistor are connected, and the drain of the third PMOS transistor is grounded. The drains of the second PMOS transistor, the drains of the third NMOS transistor, the gate of the third PMOS transistor, and the gate of the fifth NMOS transistor are connected, and their connection terminals are the output terminals of the Schmitt trigger rectifier circuit. The sources of the third NMOS transistor, the drains of the fourth NMOS transistor, and the sources of the fifth NMOS transistor are connected, and the drain of the fifth NMOS transistor is connected to the power supply voltage VDD. The source of the fourth NMOS transistor is grounded.

[0017] Furthermore, the addressing module has n input terminals, a reference terminal, an enable terminal, and an output terminal; the addressing module includes n sensitive amplifiers and a priority encoder; each sensitive amplifier has a first input terminal, a second input terminal, an enable terminal, and an output terminal; the priority encoder has n input terminals and an output terminal; the first input terminals of the n sensitive amplifiers constitute the n input terminals of the addressing module, which are used to connect one-to-one with the n matching lines; the second input terminals of the n sensitive amplifiers are connected, and their connection terminals are the reference terminals of the addressing module, which are used to connect with the reference circuit and input a reference voltage signal; The enable terminals of n sensitive amplifiers are connected, and their connection terminals are also the enable terminals of the addressing module, used to receive the first activation signal generated by the mode switching module; the first activation signal serves as the enable signal for the sensitive amplifiers. When the first activation signal is valid, the sensitive amplifiers operate normally, and the addressing module is activated; when the first activation signal is invalid, the sensitive amplifiers do not operate, and the addressing module is not activated; the output terminals of the n sensitive amplifiers are connected one-to-one with the n input terminals of the priority encoder, and the output terminal of the priority encoder is the output terminal of the addressing module, used to output the addressing signal.

[0018] Furthermore, the external mode switching command includes two control signals, namely a first control signal and a second control signal, which are inverses of each other. The mode switching module includes a second SR flip-flop, which has a clock terminal, a first input terminal, a second input terminal, an output terminal, and an inverted output terminal. The clock terminal of the second SR flip-flop is used to connect to a clock signal that controls its operating timing. The first input terminal of the second SR flip-flop is used to connect to the first control signal. The second input terminal of the second SR flip-flop is used to connect to the second control signal. The output terminal of the second SR flip-flop is used to generate a first activation signal, and the inverted output terminal of the second SR flip-flop is used to generate a second activation signal. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of the present invention; Figure 2 This is a schematic diagram of the structure of the MRAM-type TCAM storage array of the present invention; Figure 3 This is a circuit diagram of the MRAM-type TCAM memory cell of the present invention; Figure 4 This is a circuit diagram of the PUF module of the present invention; Figure 5 This is a circuit diagram of the Schmitt rectifier circuit of the present invention; Figure 6 This is a circuit diagram of the addressing module of the present invention; Figure 7This is a circuit diagram of the mode switching module of the present invention; Figure 8 The graph shows the PUF response bit error rate as a function of temperature in the present invention and the comparative scheme formed by replacing the Schmitt trigger in the present invention with a conventional inverter. Figure 9 The graph shows a comparison of the PUF response bit error rate as a function of voltage between the present invention and a comparative scheme formed by replacing the Schmitt trigger in the present invention with a conventional inverter. Figure 10 This is a histogram showing the distribution of the inter-chip Hamming distance (Inter-HD) of the present invention. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0021] Example 1: As Figure 1 and Figure 2 As shown, a dual-mode tri-state content-addressable memory (PUF) system includes a mode switching module, an MRAM-type TCAM memory array, an addressing module, and a PUF module; the MRAM-type TCAM memory array consists of n n MRAM-type TCAM memory cells are arranged in an n x n array, where n is an integer greater than or equal to 2. The PUF system has a TCAM write mode, a TCAM addressing mode, and a PUF mode. The mode switching module is used to switch the PUF system between the TCAM write mode, the TCAM addressing mode, and the PUF mode. The PUF system can perform data writing operations in TCAM write mode, addressing operations in TCAM addressing mode, and PUF response generation in PUF mode. The addressing module is used to address the MRAM-type TCAM memory array and obtain the addressing result. The PUF module is used to generate a PUF response. The PUF module adopts a timing arbitration-based PUF response generation mechanism, selects two rows of leakage current signals from the n rows of leakage current signals generated by the MRAM-type TCAM memory array, converts the difference between the two rows of leakage current signals into two digital edge signals with timing difference, and arbitrates based on the timing difference of the two digital edge signals to generate a PUF response.

[0022] In this embodiment, the PUF system further includes an address generation module, a row decoder, and a column decoder. When the PUF system is in TCAM write mode, and one or more MRAM-type TCAM memory cells are selected as target memory cells, and predetermined data is written to the target memory cells, firstly, the address generation module generates a first row address instruction and outputs it to the row decoder, and generates a first column address instruction and outputs it to the column decoder, based on a preset first external address instruction. The row decoder decodes the first row address instruction into a first row address signal and outputs it to the MRAM-type TCAM memory array. The column decoder decodes the first column address instruction into a first row address signal and outputs it to the MRAM-type TCAM memory array. The first column address signal is decoded and output to the MRAM-type TCAM memory array, changing the internal resistance state of the target memory cell. Then, the address generation module generates a second row address instruction and outputs it to the row decoder, and generates a second column address instruction and outputs it to the column decoder, based on the preset second external address instruction. The row decoder decodes the second row address instruction into a second row address signal and outputs it to the MRAM-type TCAM memory array. The column decoder decodes the second column address instruction into a second column address signal and outputs it to the MRAM-type TCAM memory array, changing the internal resistance state of the target memory cell again to realize the predetermined data writing.

[0023] In this embodiment, the PUF system further includes a pre-activation circuit and a reference circuit. The reference circuit is used to provide a reference voltage signal to the addressing module. The pre-activation circuit is used to pre-charge the MRAM-type TCAM memory array according to the external pre-activation command when the PUF system is in TCAM addressing mode or PUF mode, so that it is in an addressable state or a state to generate a PUF response. When the PUF system is in TCAM addressing mode, the pre-activation circuit first pre-charges the MRAM-type TCAM memory array according to the external pre-activation command, so that the MRAM-type TCAM memory array is in an addressable state. Then, the address generation module generates a column address command according to the external address command and outputs it to the column decoder. The column decoder decodes the column address command into a parallel addressing signal and outputs it to the MRAM-type TCAM memory array, so that the MRAM-type TCAM memory array generates n rows of leakage current signals and presents different voltage states on the corresponding matching lines. The addressing module compares the voltage of the n rows of matching lines with the reference voltage signal provided by the reference circuit to generate an addressing signal representing the highest priority matching position.

[0024] In this embodiment, the mode switching module has an active mode and an inactive mode. When the mode switching module is in the inactive mode, neither the addressing module nor the PUF module can be activated, and the PUF system is in TCAM write mode. When the mode switching module is in the active mode, it can generate two activation signals under the control of an external mode switching command to activate either the addressing module or the PUF module. The two activation signals are opposite to each other. The first activation signal EN is output to the addressing module, and the second activation signal ENb is output to the PUF module. When the addressing module is activated by the first activation signal EN, the PUF module cannot be activated by the second activation signal ENb, and the PUF system enters TCAM addressing mode. When the PUF module is activated by the second activation signal ENb, the addressing module cannot be activated by the first activation signal EN, and the PUF system enters PUF mode.

[0025] In this embodiment, the row address signal includes two n-bit row address data, both of which are binary data, namely the first n-bit row address data and the second n-bit row address data, which are opposites of each other; the column address signal includes two n-bit column address data, both of which are binary data, namely the first n-bit column address data and the second n-bit column address data, which are opposites of each other; in the MRAM-type TCAM memory array, each MRAM-type TCAM memory cell has a bit line terminal, an anti-phase line terminal, a matching terminal, and an anti-matching terminal. The bit line terminals of n MRAM-type TCAM memory cells located in the same column are connected by a bit line. The anti-phase line terminals of the cells are connected by an anti-phase line. The matching terminals of n MRAM-type TCAM memory cells in the same row are connected by a matching line. The reverse matching terminals of n MRAM-type TCAM memory cells in the same row are connected by an anti-matching line. The n bit lines are connected to the first n-bit column address data, and the n anti-phase lines are connected to the second n-bit column address data. The n matching lines are connected to the first n-bit row address data and the precharge signal, and the n anti-matching lines are connected to the second n-bit row address data. The n-row leakage current signal generated by the MRAM-type TCAM memory array is generated by its n-row MRAM-type TCAM memory cells. The one-row leakage current signal generated by each row of MRAM-type TCAM memory cells is transmitted to the addressing module or PUF module through the matching line connected to it.

[0026] In this embodiment, when the PUF system is in TCAM write mode and needs to write predetermined data to the target memory cell, it is achieved by continuously applying two external address instructions: First, the address generation module generates a first row address instruction and a first column address instruction based on the first external address instruction, and inputs them to the row decoder and column decoder, respectively. After decoding by the row decoder and column decoder, the first row address signal and the first column address signal are generated and transmitted to the MRAM-type TCAM memory array. The first row address signal and the first column address signal cause the matching line and the anti-matching line of the row where each target memory cell is located to form a first set of potential combinations, and at the same time, the bit line and the anti-phase line of the column where each target memory cell is located to form a second set of potential combinations. The first set of potential combinations and the second set of potential combinations cause the resistance state of a magnetic tunnel junction in each target memory cell to be changed. Subsequently, the address generation module generates a second row address instruction and a second column address instruction based on the second external address instruction, and after decoding by the row decoder and column decoder, outputs the second row address signal and the second column address signal to the MRAM-type TCAM memory array. The second row address signal and the second column address signal cause the matching line and anti-matching line of the row containing each target memory cell to form a third potential combination different from the first potential combination. Simultaneously, the bit line and anti-phase line of the column containing each target memory cell form a fourth potential combination different from the second potential combination. These third and fourth potential combinations change the resistance state of another magnetic tunnel junction in each target memory cell, thus completing the writing of a data state.

[0027] When the PUF system is in TCAM addressing mode, the pre-activation circuit first pre-charges the MRAM-type TCAM memory array, causing all matching lines to be pre-charged to a high level. Subsequently, the column decoder applies the first n-bit column address data to the n bit lines and the second n-bit column address data to the n anti-phase lines. All rows of MRAM-type TCAM memory cells in the MRAM-type TCAM memory array perform search matching operations in parallel, resulting in leakage current signals of different magnitudes on the matching lines of each row. Among them, the matching line of an MRAM-type TCAM memory cell that completely matches the stored data and the search data (the data corresponding to the first n-bit column address data and the second n-bit column address data) has a slow discharge rate, while the matching line of an MRAM-type TCAM memory cell that does not match the stored data and the search data has a rapid discharge rate. The leakage current signals generated by the discharge on the matching lines of each row are different, presenting different voltage output states. After that, the reference circuit generates a reference voltage signal and outputs it to the addressing module. The addressing module monitors the discharge status of all row matching lines in parallel and compares the voltage on each row matching line with the reference voltage signal, finally generating and representing the addressing signal of the highest priority matching position.

[0028] When the PUF system is in PUF mode, the pre-activation circuit first pre-charges the MRAM-type TCAM memory array, so that all matching lines are pre-charged to a high level. Then, the column decoder applies the first n-bit column address data to the n bit lines and the second n-bit column address data to the n anti-phase lines. The MRAM-type TCAM memory cells in all rows of the MRAM-type TCAM memory array perform a search matching operation in parallel, resulting in leakage current signals of different magnitudes on the matching lines of each row. Under the control of the external clock signal, the PUF module selects two leakage current signals from the n rows of leakage current signals generated by the MRAM-type TCAM memory array, and converts the difference between the two leakage current signals into two digital edge signals with timing difference. Arbitration is performed based on the timing difference of the two digital edge signals to generate a PUF response.

[0029] Example 2: This example is basically the same as Example 1, except that: in this example, as Figure 3 As shown, each MRAM-type TCAM memory cell includes a first NMOS transistor N1, a second NMOS transistor N2, a first magnetic tunnel junction M1, and a second magnetic tunnel junction M2; the drain of the first NMOS transistor N1 and the drain of the second NMOS transistor N2 are connected, and their connection point is the matching terminal of the MRAM-type TCAM memory cell; the gate of the first NMOS transistor N1 is the bit line terminal of the MRAM-type TCAM memory cell; the gate of the second NMOS transistor N2 is the anti-phase line terminal of the MRAM-type TCAM memory cell; the source of the first NMOS transistor N1 and the free layer of the first magnetic tunnel junction M1 are connected, the source of the second NMOS transistor N2 and the free layer of the second magnetic tunnel junction M2 are connected, the fixed layer of the first magnetic tunnel junction M1 and the fixed layer of the second magnetic tunnel junction M2 are connected, and their connection point is the reverse matching terminal of the MRAM-type TCAM memory cell.

[0030] In this embodiment, when the PUF system is in TCAM write mode and needs to write data "0", the first and second potential combinations place the first magnetic tunnel junction M1 of a target memory cell in a high-resistance state, and the third and fourth potential combinations place the second magnetic tunnel junction M2 of the target memory cell in a low-resistance state, thus achieving the writing of data "0". When it is necessary to write data "1", the first and second potential combinations place the second magnetic tunnel junction M2 of the target memory cell in a high-resistance state, and the third and fourth potential combinations place the first magnetic tunnel junction M1 of the target memory cell in a low-resistance state, thus achieving the writing of data "1". When it is necessary to write the irrelevant state "X", the first and second potential combinations place the first magnetic tunnel junction M1 of the target memory cell in a high-resistance state, and the third and fourth potential combinations place the second magnetic tunnel junction M2 of the target memory cell in a high-resistance state, thus achieving the writing of the irrelevant state "X".

[0031] Example 3: This example is basically the same as Example 2, except that: in this example, as Figure 4 As shown, the PUF module includes two n-to-one selectors, two Schmitt trigger circuits, and a first SR flip-flop. Each n-to-one selector has n inputs, an output, and a selection terminal, used to select one of its inputs and its output based on the excitation signal connected to its selection terminal, so that the signal connected to that input terminal is transmitted to its output terminal. The two n-to-one selectors are the first n-to-one selector U1 and the second n-to-one selector U2. Each Schmitt trigger circuit has an input and an output terminal. The two Schmitt trigger circuits are the first Schmitt trigger circuit and the second Schmitt trigger circuit. The first SR flip-flop has a clock terminal, a first input terminal, a second input terminal, and an output terminal. The n inputs of the first n-to-one selector U1 and the n inputs of the second n-to-one selector U2 are all used to connect to n rows of leakage current signals. The output of the 1-to-1 selector U1 is connected to the input of the first Schmitt trigger rectifier circuit, and the output of the second 1-to-1 selector U2 is connected to the input of the second Schmitt trigger rectifier circuit. The output of the first Schmitt trigger rectifier circuit is connected to the first input of the first SR flip-flop, and the output of the second Schmitt trigger rectifier circuit is connected to the second input of the first SR flip-flop. The clock input of the first SR flip-flop is connected to the second activation signal ENb. The output of the first SR flip-flop is used to output the PUF response. The second activation signal ENb serves as the clock signal for the first SR flip-flop. When the second activation signal ENb is valid, the first SR flip-flop operates according to the clock signal timing, and the PUF module is activated. When the second activation signal ENb is invalid, the first SR flip-flop does not operate, and the PUF module is not activated.

[0032] In this embodiment, the PUF module selects two matching lines using two n-to-one selectors, and uses two Schmitt rectifier circuits to convert the difference in analog leakage current signals between the two matching lines into digital edge signals with timing differences. Finally, the first SR flip-flop arbitrates and generates a binary PUF response output. The Schmitt rectifier circuit enhances the PUF module's ability to distinguish subtle differences and its anti-interference capability, thereby improving its reliability and stability.

[0033] Example 4: This example is basically the same as Example 3, except that: in this example, as Figure 5As shown, each Schmitt rectifier circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5. The source of the first PMOS transistor P1 is connected to the power supply voltage VDD. The gates of the first PMOS transistor P1, the second PMOS transistor P2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are connected, and their connection point is the input terminal of the Schmitt rectifier circuit. The drain of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the power supply voltage VDD. The source of S-MOSFET P2 is connected to the source of the third PMOS transistor P3, and the drain of the third PMOS transistor P3 is grounded. The drain of the second PMOS transistor P2, the drain of the third NMOS transistor N3, the gate of the third PMOS transistor P3, and the gate of the fifth NMOS transistor N5 are connected, and their connection terminals are the output terminals of the Schmitt trigger rectifier circuit. The source of the third NMOS transistor N3, the drain of the fourth NMOS transistor N4, and the source of the fifth NMOS transistor N5 are connected, and the drain of the fifth NMOS transistor N5 is connected to the power supply voltage VDD. The source of the fourth NMOS transistor N4 is grounded.

[0034] In this embodiment, the Schmitt trigger circuit forms a signal conversion mechanism with hysteresis characteristics through a specific connection relationship of its internal CMOS transistors. The input terminal of the Schmitt trigger circuit is connected to the matching line through an n-to-1 selector to receive its analog leakage current signal; the output terminal generates the corresponding digital edge signal. In actual operation, when the voltage of the matching line gradually decreases from a high level due to the discharge of the MRAM-type TCAM memory cell through the equivalent resistance, this voltage is applied to the input terminal of the Schmitt trigger circuit. The first threshold voltage is a key DC parameter inherent to the Schmitt trigger circuit, determined by the threshold voltage and width-to-length ratio of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5. When the input voltage of the Schmitt trigger circuit drops to the first threshold voltage, the conductivity of the first PMOS transistor P1 and the second PMOS transistor P2 increases, while the conductivity of the third NMOS transistor N3 and the fourth NMOS transistor N4 decreases. This change triggers an internal positive feedback mechanism: the drain potential of the second PMOS transistor P2 increases, causing the gate potential of the third PMOS transistor P3 to increase and tend to turn off, while the gate potential of the fifth NMOS transistor N5 increases and tends to turn on. The turn-on of the fifth NMOS transistor N5 further strengthens the pull-up process of the Schmitt rectifier circuit's output potential to a high level, thereby driving the output potential of the Schmitt rectifier circuit to generate a definite level transition, forming a digital edge signal. The timing of the level transition depends on the time required for the matching line voltage to discharge to the first threshold voltage, which is determined by the equivalent resistance and capacitance of the matching line.

[0035] The Schmitt rectifier circuit in this embodiment provides significant technical advantages to the PUF system. First, the inherent hysteresis of the Schmitt rectifier circuit widens its effective trigger voltage range, requiring the input signal (the voltage signal connected to its input terminal) to cross a certain voltage range before triggering a change in its output state (its output terminal potential). This characteristic extends the integration time for the matching line leakage current signal, thereby fully accumulating and amplifying minute resistance differences caused by manufacturing process variations into significant timing differences, effectively enhancing the PUF system's ability to distinguish inherent physical deviations. Second, the hysteresis of this Schmitt rectifier circuit effectively suppresses noise interference and transient fluctuations on its input signal, preventing indeterminate oscillations in its output terminal potential near the first threshold voltage, significantly improving the stability and reliability of the PUF response.

[0036] Example 5: This example is basically the same as Example 4, except that: in this example, as Figure 6 As shown, the addressing module has n input terminals, a reference terminal, an enable terminal, and an output terminal; the addressing module includes n sensitive amplifiers SA[1] to SA[n] and a priority encoder; each sensitive amplifier has a first input terminal, a second input terminal, an enable terminal, and an output terminal; the priority encoder has n input terminals and an output terminal; the first input terminals of the n sensitive amplifiers constitute the n input terminals of the addressing module, which are used to connect one-to-one with the n matching lines; the second input terminals of the n sensitive amplifiers are connected, and their connection terminals are the reference terminals of the addressing module, which are used to connect with the reference circuit and input the reference voltage signal; n The enable terminals of each sensitive amplifier are connected, and their connection terminals are also the enable terminals of the addressing module, used to receive the first activation signal EN generated by the mode switching module; the first activation signal EN serves as the enable signal for the sensitive amplifier. When the first activation signal EN is valid, the sensitive amplifier operates normally, and the addressing module is activated at this time; when the first activation signal EN is invalid, the sensitive amplifier does not operate, and the addressing module is not activated at this time; the output terminals of the n sensitive amplifiers are connected one-to-one with the n input terminals of the priority encoder, and the output terminal of the priority encoder is the output terminal of the addressing module, used to output the addressing signal.

[0037] In this embodiment, the addressing module obtains the addressing result as follows: When the PUF system is in TCAM addressing mode, when the first activation signal EN is valid, all n sensitive amplifiers are activated. Each sensitive amplifier compares the voltage connected to its first input terminal with the reference voltage signal at its second input terminal. When the row voltage equals the reference voltage signal, it is determined that the row leakage current signal matches, and a high level is output to the priority encoder through its output terminal. When the row voltage is lower than the reference voltage signal, it is determined that the row leakage current signal does not match, and a low level is output to the priority encoder through its output terminal. The priority encoder has a row address pre-programmed that uniquely corresponds to each row of MRAM-type TCAM memory cell. The priority encoder is configured to scan the outputs of all sensitive amplifiers and output the addressing result according to the following rule: when the output of one and only one sensitive amplifier is high, its corresponding row address is directly output as the final addressing result. When two or more sensitive amplifiers output a high level, according to the priority rule that the smaller the physical row address number stored in the MRAM-type TCAM, the higher its priority, the one with the highest priority is selected from these corresponding row addresses as the addressing result output; when all sensitive amplifiers output a low level, a preset code indicating addressing failure is output.

[0038] Example 6: This example is basically the same as Example 5, except that: in this example, as Figure 7 As shown, the external mode switching command includes two control signals, namely a first control signal and a second control signal, which are inverses of each other. The mode switching module includes a second SR flip-flop, which has a clock terminal, a first input terminal, a second input terminal, an output terminal, and an inverted output terminal. The clock terminal of the second SR flip-flop is used to connect to the clock signal that controls its operating timing. The first input terminal of the second SR flip-flop is used to connect to the first control signal. The second input terminal of the second SR flip-flop is used to connect to the second control signal. The output terminal of the second SR flip-flop is used to generate a first activation signal EN, and the inverted output terminal of the second SR flip-flop is used to generate a second activation signal ENb.

[0039] In this embodiment, the mode switching module generates activation signals as follows: When the first control signal connected to the first input terminal of the second SR flip-flop is at a valid level, the second control signal connected to its second input terminal is at an invalid level. At the valid edge (rising or falling edge) of the clock signal it is connected to, the first activation signal output by its output terminal becomes a valid signal, and the second activation signal output by its inverted output terminal becomes invalid, thus activating the addressing module and causing the PUF system to enter TCAM addressing mode; When the first control signal connected to the first input terminal of the second SR flip-flop is at an invalid level, the second control signal connected to its second input terminal is at a valid level. At the valid edge of the clock signal, the first activation signal output by its output terminal becomes an invalid signal, and the second activation signal output by its inverted output terminal becomes valid, thus activating the PUF module and causing the PUF system to enter PUF mode; When both the first control signal connected to the first input terminal and the second control signal connected to the second input terminal of the second SR flip-flop are at invalid levels, both the output terminal and the inverted output terminal of the second SR flip-flop output invalid signals, neither the addressing module nor the PUF module is activated, and the PUF system is in TCAM write mode.

[0040] To verify the reliability of the dual-mode tri-state content-addressable memory (PUF) system of the present invention under actual working conditions, a scheme formed by replacing the Schmitt trigger in the present invention with a conventional inverter was used as a comparison scheme, and temperature reliability and voltage reliability were compared and verified.

[0041] With a fixed power supply voltage VDD of 1.2 V and a temperature scan range of -40 °C to 120 °C, the present invention and comparative scheme were run at various temperature points, and their PUF responses were collected. By comparing the PUF responses collected at each temperature point with the "standard PUF response" stored at the reference temperature (27 °C), the bit error rate as a function of temperature was statistically obtained, as shown in the figure. Figure 8 As shown. Analysis Figure 8 It can be seen that within the temperature range of -40 °C to 100 °C, the bit error rate of the PUF system of the present invention remains at an extremely low level close to zero; at an extreme high temperature of 120 °C, its bit error rate only rises to about 1%, while the bit error rate of the comparative scheme rises sharply to about 2.5% under the same conditions. This result shows that the PUF system of the present invention, by setting a Schmitt trigger in the PUF module and utilizing the hysteresis characteristic of the Schmitt trigger, effectively suppresses the signal disturbance introduced by temperature drift, and significantly improves the high-temperature reliability of the PUF system.

[0042] Under a fixed temperature of 27 °C and a power supply voltage (VDD) scanning range of 1.00 V to 1.40 V, the present invention and comparative scheme were run at various voltage points, and their PUF responses were collected. By comparing the PUF responses collected at each voltage point with the "standard PUF response" stored at the reference power supply voltage (1.2 V), the curve of bit error rate versus voltage was obtained, as shown below. Figure 9 As shown. Analysis Figure 9 It can be seen that when the power supply voltage is below 1.20 V or above 1.25 V, the bit error rate of both the comparative scheme and the present invention increases, but the increase in the bit error rate of the present invention is more gradual. At a power supply voltage of 1.40 V, its bit error rate is approximately 0.6%, while the comparative scheme rises to approximately 0.8%. This result demonstrates that in the PUF system of the present invention, the Schmitt trigger, with its superior noise margin, effectively reduces the sensitivity to power supply voltage fluctuations, thereby enhancing the reliability of the PUF system under voltage fluctuation environments.

[0043] To verify the uniqueness of the dual-mode tri-state content-addressable memory (PUF) system of the present invention in a real-world working environment, statistical analysis was performed on 25 actual PUF system samples of the present invention, assuming an MRAM-type TCAM memory array composed of 32x32 MRAM-type TCAM memory cells. Uniqueness was characterized by calculating the Hamming distance between each pair of sample PUF responses and statistically analyzing their distribution. Figure 10 As shown. Figure 10 In the graph, the horizontal axis represents the normalized Hamming distance, and the vertical axis represents the statistical frequency. Figure 10 Test results show that the average Hamming distance between chips is 50.08%, and its distribution pattern is close to an ideal normal distribution. This data fully demonstrates that the different PUF system prototypes constructed based on this invention can produce highly differentiated responses, possess excellent device differentiation capabilities, and meet the uniqueness requirement as a physically unclonable function.

Claims

1. A dual-mode, tri-state content-addressable memory (PUF) system, comprising a mode switching module, an MRAM-type TCAM memory array, an addressing module, and a PUF module; the MRAM-type TCAM memory array consists of n n MRAM-type TCAM memory cells are arranged in an n x n array, where n is an integer greater than or equal to 2; the PUF system has a TCAM write mode, a TCAM addressing mode, and a PUF mode; the mode switching module is used to switch the PUF system between the TCAM write mode, the TCAM addressing mode, and the PUF mode; the PUF system can perform data writing operations in TCAM write mode, addressing operations in TCAM addressing mode, and PUF response generation in PUF mode; the addressing module is used to address the MRAM-type TCAM memory array and obtain the addressing result; the PUF module is used to generate a PUF response, characterized in that: The PUF module adopts a timing arbitration-based PUF response generation mechanism. It selects two rows of leakage current signals from the n rows of leakage current signals generated by the MRAM-type TCAM memory array, converts the difference between the two rows of leakage current signals into two digital edge signals with timing difference, and arbitrates based on the timing difference of the two digital edge signals to generate a PUF response.

2. The PUF system of dual-mode tri-state content-addressable memory according to claim 1, characterized in that: The PUF system further includes an address generation module, a row decoder, and a column decoder. When the PUF system is in TCAM write mode, and one or more MRAM-type TCAM memory cells are selected as target memory cells, and predetermined data is written to the target memory cells, firstly, the address generation module generates a first row address instruction and outputs it to the row decoder, and generates a first column address instruction and outputs it to the column decoder, based on a preset first external address instruction. The row decoder decodes the first row address instruction into a first row address signal and outputs it to the MRAM-type TCAM memory array. The column decoder decodes the first column address instruction into a... The first column address signal is output to the MRAM-type TCAM memory array to change the internal resistance state of the target memory cell. Then, the address generation module generates a second row address instruction and outputs it to the row decoder according to the preset second external address instruction, and generates a second column address instruction and outputs it to the column decoder. The row decoder decodes the second row address instruction into a second row address signal and outputs it to the MRAM-type TCAM memory array. The column decoder decodes the second column address instruction into a second column address signal and outputs it to the MRAM-type TCAM memory array, thereby changing the internal resistance state of the target memory cell again and realizing the predetermined data writing.

3. The PUF system of dual-mode tri-state content-addressable memory according to claim 2, characterized in that: The PUF system further includes a pre-activation circuit and a reference circuit. The reference circuit provides a reference voltage signal to the addressing module. The pre-activation circuit, when the PUF system is in TCAM addressing mode or PUF mode, pre-charges the MRAM-type TCAM memory array according to an external pre-activation command, making it in an addressable state or a state to generate a PUF response. When the PUF system is in TCAM addressing mode, the pre-activation circuit first pre-charges the MRAM-type TCAM memory array according to an external pre-activation command, making the MRAM-type TCAM memory array in an addressable state. Then, the address generation module generates a column address command according to the external address command and outputs it to the column decoder. The column decoder decodes the column address command into a parallel addressing signal and outputs it to the MRAM-type TCAM memory array, causing the MRAM-type TCAM memory array to generate n rows of leakage current signals and present different voltage states on the corresponding matching lines. The addressing module compares the voltages of the n matching lines with the reference voltage signal provided by the reference circuit to generate an addressing signal representing the highest priority matching position.

4. The PUF system of dual-mode tri-state content-addressable memory according to claim 3, characterized in that: The mode switching module has an active mode and an inactive mode. When the mode switching module is in the inactive mode, neither the addressing module nor the PUF module can be activated, and the PUF system is in TCAM write mode. When the mode switching module is in the active mode, it can generate two activation signals under the control of an external mode switching command to activate either the addressing module or the PUF module. The two activation signals are opposite to each other. The first activation signal is output to the addressing module, and the second activation signal is output to the PUF module. When the addressing module is activated by the first activation signal, the PUF module cannot be activated by the second activation signal, and the PUF system enters TCAM addressing mode. When the PUF module is activated by the second activation signal, the addressing module cannot be activated by the first activation signal, and the PUF system enters PUF mode.

5. The PUF system of dual-mode tri-state content-addressable memory according to claim 4, characterized in that: The row address signal includes two n-bit row address data, both binary data, namely a first n-bit row address data and a second n-bit row address data, which are opposites of each other. The column address signal includes two n-bit column address data, both binary data, namely a first n-bit column address data and a second n-bit column address data, which are opposites of each other. Each MRAM-type TCAM memory cell has a bit line terminal, an anti-phase line terminal, a matching terminal, and an anti-matching terminal. The bit line terminals of n MRAM-type TCAM memory cells located in the same column are connected by a bit line, and the anti-phase line terminals of n MRAM-type TCAM memory cells located in the same column are connected by a bit line. The matching terminals of n MRAM-type TCAM memory cells located in the same row are connected by a matching line, and the reverse matching terminals of n MRAM-type TCAM memory cells located in the same row are connected by a reverse matching line; n bit lines are connected to the first n-bit column address data, and n reverse-phase lines are connected to the second n-bit column address data; n matching lines are connected to the first n-bit row address data and the precharge signal, and n reverse matching lines are connected to the second n-bit row address data; the n-row leakage current signal generated by the MRAM-type TCAM memory array is generated by its n rows of MRAM-type TCAM memory cells, and the one-row leakage current signal generated by each row of MRAM-type TCAM memory cells is transmitted to the addressing module or the PUF module through the matching line connected to it.

6. The PUF system of dual-mode tri-state content-addressable memory according to claim 5, characterized in that: Each MRAM-type TCAM memory cell includes a first NMOS transistor, a second NMOS transistor, a first magnetic tunnel junction, and a second magnetic tunnel junction; the drains of the first NMOS transistor and the second NMOS transistor are connected, and their connection point is the matching terminal of the MRAM-type TCAM memory cell; the gate of the first NMOS transistor is the bit line terminal of the MRAM-type TCAM memory cell; the gate of the second NMOS transistor is the anti-phase line terminal of the MRAM-type TCAM memory cell; the source of the first NMOS transistor is connected to the free layer of the first magnetic tunnel junction, the source of the second NMOS transistor is connected to the free layer of the second magnetic tunnel junction, the fixed layer of the first magnetic tunnel junction is connected to the fixed layer of the second magnetic tunnel junction, and their connection point is the reverse matching terminal of the MRAM-type TCAM memory cell.

7. The PUF system of dual-mode tri-state content-addressable memory according to claim 6, characterized in that: The PUF module includes two n-to-one selectors, two Schmitt trigger circuits, and a first SR flip-flop. Each n-to-one selector has n input terminals, an output terminal, and a selection terminal. The two n-to-one selectors are designated as a first n-to-one selector and a second n-to-one selector. Each Schmitt trigger circuit has an input terminal and an output terminal. The two Schmitt trigger circuits are designated as a first Schmitt trigger circuit and a second Schmitt trigger circuit. The first SR flip-flop has a clock terminal, a first input terminal, a second input terminal, and an output terminal. The n input terminals of both the first and second n-to-one selectors are used to input n rows of leakage current signals. The output terminal of the first n-to-one selector is connected to the first Schmitt trigger circuit. The input terminals are connected as follows: the output terminal of the second n-to-1 selector is connected to the input terminal of the second Schmitt trigger circuit; the output terminal of the first Schmitt trigger circuit is connected to the first input terminal of the first SR flip-flop; the output terminal of the second Schmitt trigger circuit is connected to the second input terminal of the first SR flip-flop; the clock terminal of the first SR flip-flop is connected to the second activation signal; the output terminal of the first SR flip-flop is used to output the PUF response; the second activation signal serves as the clock signal for the first SR flip-flop. When the second activation signal is valid, the first SR flip-flop operates according to the clock signal timing, and the PUF module is activated. When the second activation signal is invalid, the first SR flip-flop does not operate, and the PUF module is not activated.

8. The PUF system of dual-mode tri-state content-addressable memory according to claim 7, characterized in that: Each Schmitt trigger rectifier circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage VDD. The gates of the first PMOS transistor, the second PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are connected, and their connection point is the input terminal of the Schmitt trigger rectifier circuit. The drain of the first PMOS transistor, the source of the second PMOS transistor, and the source of the third PMOS transistor are connected. The drain of the third PMOS transistor is grounded. The drain of the second PMOS transistor, the drain of the third NMOS transistor, the gate of the third PMOS transistor, and the gate of the fifth NMOS transistor are connected, and their connection point is the output terminal of the Schmitt trigger rectifier circuit. The source of the third NMOS transistor, the drain of the fourth NMOS transistor, and the source of the fifth NMOS transistor are connected. The drain of the fifth NMOS transistor is connected to the power supply voltage VDD, and the source of the fourth NMOS transistor is grounded.

9. The PUF system of dual-mode tri-state content-addressable memory according to claim 6, characterized in that: The addressing module has n input terminals, a reference terminal, an enable terminal, and an output terminal; the addressing module includes n sensitive amplifiers and a priority encoder; each sensitive amplifier has a first input terminal, a second input terminal, an enable terminal, and an output terminal; the priority encoder has n input terminals and an output terminal; the first input terminals of the n sensitive amplifiers constitute the n input terminals of the addressing module, used to connect one-to-one with the n matching lines; the second input terminals of the n sensitive amplifiers are connected, and their connection terminals are the reference terminals of the addressing module, used to connect with the reference circuit and input a reference voltage signal; the n sensitive amplifiers... The enable terminal of the sensitive amplifier is connected, and its connection terminal is also the enable terminal of the addressing module, used to receive the first activation signal generated by the mode switching module; the first activation signal serves as the enable signal of the sensitive amplifier. When the first activation signal is valid, the sensitive amplifier operates normally, and the addressing module is activated at this time; when the first activation signal is invalid, the sensitive amplifier does not operate, and the addressing module is not activated at this time; the output terminals of n sensitive amplifiers are connected one-to-one with the n input terminals of the priority encoder, and the output terminal of the priority encoder is the output terminal of the addressing module, used to output the addressing signal.

10. The PUF system of dual-mode tri-state content-addressable memory according to claim 3, characterized in that: The external mode switching command includes two control signals, namely a first control signal and a second control signal, which are inverses of each other. The mode switching module includes a second SR flip-flop, which has a clock terminal, a first input terminal, a second input terminal, an output terminal, and an inverted output terminal. The clock terminal of the second SR flip-flop is used to connect to a clock signal that controls its operating timing. The first input terminal of the second SR flip-flop is used to connect to the first control signal. The second input terminal of the second SR flip-flop is used to connect to the second control signal; The output of the second SR flip-flop is used to generate the first activation signal, and the inverted output of the second SR flip-flop is used to generate the second activation signal.

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