Logic self-checking control circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a logic self-checking control circuit, a chip and electronic equipment, the logic self-checking control circuit comprises a test state control module, the test state control module is used for receiving a test input signal and outputting a test state signal, and the test state signal is used for representing the test state of the test control circuit; and the clock output module is used for outputting a clock signal according to the test state signal. According to the application, when the test state signal represents that the test control circuit enters the test state, the frequency of the clock signal is controlled to be gradually increased to the default test frequency within the first preset time, so that the frequency of the clock signal is slowly increased after the logic built-in self-test starts; therefore, the problem that the power consumption suddenly rises at the beginning of logic built-in self-checking can be avoided

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a logic self-test control circuit, chip, and electronic device. Background Technology

[0002] Currently, with the rapid development of integrated circuits, chip integration is becoming increasingly higher, leading to more complex logic scales and operating modes. Therefore, chip-level design for test (DFT) is becoming increasingly important. Taking automotive-grade chips as an example, automotive-grade chips perform Logic Build-in-Self-Tests (LBIST) during operation. LBIST can test digital logic circuits without the need for external test vectors, preventing physical failures caused by chip aging and other factors.

[0003] However, at the moment the chip's built-in self-test begins, all clock gates will be turned on, and all registers inside the digital logic circuit will begin to invert. This will generate a large amount of power consumption in an instant, which may damage the chip's power supply. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a logic self-test control circuit, chip, and electronic device to solve the above technical problems.

[0005] In a first aspect, embodiments of this application provide a logic self-test control circuit. The logic self-test control circuit is used to output clock signals to a test control circuit and multiple circuits under test. The logic self-test control circuit includes:

[0006] The test status control module is used to receive test input signals and output test status signals, which are used to characterize the test status of the test control circuit.

[0007] Clock output module, the clock output module is used to output a clock signal according to the test status signal;

[0008] When the test status signal indicates that the test control circuit has entered the test state, the clock output module responds to the test status signal by controlling the frequency of the clock signal to gradually increase to the default test frequency within a first preset time.

[0009] Secondly, embodiments of this application also provide a chip including the above-described logic self-test control circuit.

[0010] Thirdly, embodiments of this application also provide an electronic device, including the aforementioned chip or logic self-test control circuit.

[0011] This application receives test input signals through a test state control module and outputs test enable and test state signals. A clock output module outputs a clock signal based on the test state signals. Therefore, the test enable signal can be used to control the test control circuit to perform logic self-tests on multiple circuits under test based on the clock signal. Since the clock output module can respond to the test state signal by gradually increasing the clock signal frequency to the default test frequency within a first preset time after the test state signal indicates that the test control circuit has entered the test state, the clock signal frequency rises slowly after the logic self-test begins, thus avoiding the problem of a sudden increase in power consumption at the start of the logic self-test. Simultaneously, since the increase in clock signal frequency improves test efficiency, this application can also balance test time and power consumption during the test process, improving test efficiency while ensuring power safety.

[0012] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This diagram illustrates a method for chip-based built-in logic self-testing in related technologies.

[0015] Figure 2 A schematic diagram of a logic self-test control circuit in an embodiment of this application is shown.

[0016] Figure 3 A schematic diagram illustrating a variation of the clock signal frequency in an embodiment of this application is shown.

[0017] Figure 4 A schematic diagram illustrating another variation of the clock signal frequency in an embodiment of this application is shown.

[0018] Figure 5 A schematic diagram illustrating another variation of the clock signal frequency in an embodiment of this application is shown.

[0019] Figure 6 A schematic diagram illustrating another variation of the clock signal frequency in an embodiment of this application is shown.

[0020] Figure 7 Another schematic diagram of the logic self-test control circuit in an embodiment of this application is shown.

[0021] Figure 8Another schematic diagram of the logic self-test control circuit in an embodiment of this application is shown.

[0022] Figure 9 Another schematic diagram of the logic self-test control circuit in an embodiment of this application is shown.

[0023] Figure 10 Another schematic diagram of the logic self-test control circuit in an embodiment of this application is shown.

[0024] Figure 11 Another schematic diagram of the logic self-test control circuit in an embodiment of this application is shown.

[0025] Figure 12 Another schematic diagram of the logic self-test control circuit in an embodiment of this application is shown.

[0026] Among them, 100 is a logic self-test control circuit, 200 is a test control circuit, and 300 is a circuit to be tested;

[0027] 10 Test state control module, 11 State machine, 12 State register, 13 Second edge detection unit, 14 Third edge detection unit, 20 Clock output module, 21 Counting unit, 22 Selection signal output unit, 23 Clock switching unit, 24 First edge detection unit.

[0028] The test input signal is lbist_en, the test start signal is test_start, the test enable signal is lbist_ctrl, the test status signal is ring_en, the feedback signal is 1bist_done, the clock signal is ate_CLK, the clock selection signal is clk_sel, the test end enable signal is cnt_0, the first OR gate is OR1, the preset clock signal is CLK0, the second OR gate is OR2, and the first AND gate is AND1. Detailed Implementation

[0029] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0030] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0031] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0032] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0033] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0034] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0035] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0036] Currently, built-in logic self-tests on chips can test digital logic circuits without the need for external test vectors, preventing physical failures caused by chip aging or other reasons. For example, see... Figure 1 , Figure 1The diagram illustrates a chip performing a built-in logic self-test in the related art. The test control circuit for the chip's built-in logic self-test can provide an input signal to the circuit under test. After the circuit under test performs logic operations, it outputs a feedback signal to the test control circuit. The test control circuit compares the input signal with the feedback signal to determine whether the circuit under test is normal.

[0037] However, at the moment the chip's built-in self-test begins, all clock gates of the circuit under test are opened, and all registers inside the circuit under test begin to invert. This will generate a large amount of power consumption instantaneously, which may damage the chip's power supply.

[0038] Therefore, this application provides a logic self-test control circuit, a chip, and an electronic device, which will be described in detail below.

[0039] First, refer to Figure 2 , Figure 2 A schematic diagram of a logic self-test control circuit 100 in an embodiment of this application is shown, wherein the logic self-test control circuit 100 includes a test state control module 10 and a clock output module 20.

[0040] Specifically, the logic self-test control circuit 100 outputs a clock signal ate_CLK to the test control circuit 200 and multiple circuits under test 300, so that the test control circuit 200 uses the clock signal ate_CLK to perform a built-in logic self-test on the circuits under test 300. Generally, the logic self-test control circuit 100 can also output a test enable signal lbist_ctrl to the test control circuit 200, so that the test control circuit 200 can perform a built-in logic self-test on a certain circuit under test 300 in response to the test enable signal lbist_ctrl.

[0041] For example, the test control circuit 200 may include a test vector generator (TPG) for generating test vectors, a test response analyzer (TAR) for compressing the output response of the circuit under test 300 and generating a feature code, and a BIST controller responsible for coordinating the entire test process (e.g., generating timing control signals, scan drive signals, etc.). The multiple circuits under test 300 may include, but are not limited to, internal logic circuits of MCUs, random logic circuits, digital logic circuits, self-tests of complex cores, transistor-level lockstep CPUs, and on-chip logic circuits.

[0042] The test status control module 10 is used to receive the test input signal lbist_en and output the test enable signal lbist_ctrl and the test status signal ring_en, wherein the test status signal ring_en is used to characterize the test status of the test control circuit 200. For example, when the test status signal ring_en is "000", it indicates that the test control circuit 200 has not tested any of the circuits under test 300; for another example, when the test status signal ring_en is "101", it indicates that the test control circuit 200 is testing the circuit under test 0; for yet another example, when the test status signal ring_en is "100", it indicates that the test control circuit 200 is testing the circuit under test 2; for yet another example, when the test status signal ring_en changes from "000" to "XYZ" (at least one of X, Y, and Z is not equal to 0), it indicates that the test control circuit 200 is testing the first circuit under test 300, at which point the test control circuit 200 enters the test state; for yet another example, when the test status signal ring_en changes from "XYZ" (at least one of X, Y, and Z is not equal to 0) to "000", it indicates that the test control circuit 200 has finished testing the last circuit under test 300, at which point the test control circuit 200 ends the test state.

[0043] In some embodiments of this application, the change of the test status signal ring_en can be in response to the feedback signal 1bist_done output by the test control circuit 200. For example, taking the test status signal ring_en as "101" to indicate that the test control circuit 200 is testing the circuit 0 under test, after the test control circuit 200 completes the test process of the circuit 0 under test, the test control circuit 200 outputs the feedback signal 1bist_done to the test status control module 10. The test status control module 10 can respond to the feedback signal 1bist_done to change the test status signal ring_en from "101" to "100". At this time, the test status signal ring_en "100" indicates that the test control circuit 200 is testing the circuit 2 under test.

[0044] In some embodiments of this application, the change of the test status signal ring_en can be autonomously controlled by the test status control module 10. For example, taking the test control circuit 200 as completing the test process of a circuit under test 300 every 20 seconds, the test status control module 10 can change the test status signal ring_en once every 20 seconds after issuing the test enable signal lbist_ctrl.

[0045] In some embodiments of this application, the test state control module 10 may output a test enable signal lbist_ctrl only once after receiving the test input signal lbist_en. The test control circuit 200 then responds to the test enable signal lbist_ctrl to sequentially test one, some, or all of the circuits 300 under test. For example, assuming the test input signal lbist_en represents testing both circuit 1 and circuit 2 under test, after the test state control module 10 outputs the test enable signal lbist_ctrl to the test control circuit 200 according to the test input signal lbist_en, the test control circuit 200 sequentially tests both circuit 1 and circuit 2 under test.

[0046] In some embodiments of this application, the test state control module 10 can output a test enable signal lbist_ctrl once each time the test state signal ring_en changes. For example, taking the test state signal ring_en as "101" to represent that the test control circuit 200 is testing the circuit under test 0, when the test state signal ring_en changes from "000" to "101", the test state control module 10 can output a test enable signal lbist_ctrl once, thereby controlling the test control circuit 200 to test the circuit under test 0. As another example, taking the test state signal ring_en as "100" to represent that the test control circuit 200 is testing the circuit under test 2, when the test state signal ring_en changes from "101" to "100", the test state control module 10 can output a test enable signal lbist_ctrl once, thereby controlling the test control circuit 200 to test the circuit under test 2.

[0047] The clock output module 20 can output a clock signal ate_CLK based on the test status signal ring_en, so that the test control circuit 200 can perform logic self-tests on multiple circuits under test 300 based on the clock signal ate_CLK. In some embodiments of this application, the clock output module 20 may include multiple clock gates, each clock gate outputting a clock signal ate_CLK of a different frequency. By controlling multiple clock gates, the clock output module 20 can output clock signals ate_CLK of different frequencies. In some embodiments of this application, the clock output module 20 may include a phase-locked loop (PLL) circuit. The PLL circuit is connected to a fixed-frequency input clock. By changing the division ratio of the frequency divider in the PLL circuit, the PLL circuit can change the frequency of the clock signal ate_CLK.

[0048] In this embodiment of the application, when the test status signal ring_en indicates that the test control circuit 200 has entered the test state, the clock output module 20 responds to the test status signal ring_en by controlling the frequency of the clock signal ate_CLK to gradually increase to the default test frequency within a first preset time period, wherein the default test frequency is the highest frequency of the clock signal during the test.

[0049] For example, taking the test status signal ring_en changing from "000" to "XYZ" (where at least one of X, Y, and Z is not equal to 0) to indicate that the test control circuit 200 has entered the test state as an example, see [reference needed]. Figure 3 , Figure 3 The diagram illustrates a change in the frequency of the clock signal ate_CLK in an embodiment of this application. At time t0, the test status signal ring_en changes from “000” to “XYZ”. During the Δt time period after time t0, the frequency of the clock signal ate_CLK gradually increases from frequency f2 to the default test frequency f3.

[0050] As can be seen, when the test status signal ring_en indicates that the test control circuit 200 has entered the test state, the clock output module 20 responds to the test status signal ring_en by gradually increasing the frequency of the clock signal ate_CLK to the default test frequency within a first preset time. Therefore, after the logic built-in self-test begins, the frequency of the clock signal ate_CLK slowly rises to the maximum frequency. This avoids the problem of a sharp increase in power consumption caused by directly using the maximum frequency clock signal for testing at the moment the logic built-in self-test begins. At the same time, since the increase in the frequency of the clock signal ate_CLK can improve test efficiency, this application can also balance the test time and power consumption during the test process, improving test efficiency while ensuring power safety.

[0051] In some embodiments of this application, when the test status signal ring_en indicates that the test control circuit 200 has ended the test state, the clock output module 20 controls the frequency of the clock signal ate_CLK to gradually decrease from the default test frequency to the lowest preset frequency within a second preset time period in response to the test status signal ring_en.

[0052] For example, a change in the test status signal ring_en from "000" to "XYZ" (at least one of X, Y, and Z is not equal to 0) indicates that the test control circuit 200 has entered the test state, while a change in the test status signal ring_en from "XYZ" (at least one of X, Y, and Z is not equal to 0) to "000" indicates that the test control circuit 200 has ended the test. See [reference needed]. Figure 4 , Figure 4The diagram illustrates another variation of the clock signal ate_CLK frequency in an embodiment of this application. At time t1, the test status signal ring_en changes from "000" to "XYZ", and the frequency of the clock signal ate_CLK gradually increases from the lowest preset frequency f2 to the default test frequency f3 within the time interval Δt1. At time t2, the test status signal ring_en changes from "XYZ" to "000", and within the time interval Δt2 after time t2, the frequency of the clock signal ate_CLK gradually decreases from the default test frequency f3 to the lowest preset frequency f2.

[0053] As can be seen, since the clock output module 20 controls the frequency of the clock signal ate_CLK to gradually decrease from the default test frequency to the lowest preset frequency within a second preset time when the test state signal ring_en represents the end of the test state of the test control circuit 200, the frequency of the clock signal ate_CLK also decreases slowly during the end of the logic built-in self-test. Therefore, the problem of a sharp drop in power consumption during the end of the logic built-in self-test can also be avoided.

[0054] In some embodiments of this application, when the test status signal ring_en indicates that the test control circuit 200 has entered the test state, the clock output module 20 controls the frequency of the clock signal ate_CLK to decrease from the default operating frequency to the lowest preset frequency in response to the test status signal ring_en, and gradually increases it to the default test frequency after a first preset time following the decrease to the lowest preset frequency; when the test status signal ring_en indicates that the test control circuit 200 has ended the test state, the clock output module 20 controls the frequency of the clock signal ate_CLK to decrease from the default test frequency to the lowest preset frequency within a second preset time in response to the test status signal ring_en, and increases it to the default operating frequency after the decrease to the lowest preset frequency, wherein the default operating frequency refers to the normal operating frequency of the clock signal ate_CLK when no built-in logic self-test is performed.

[0055] For example, a change in the test status signal ring_en from "000" to "XYZ" (at least one of X, Y, and Z is not equal to 0) indicates that the test control circuit 200 has entered the test state, while a change in the test status signal ring_en from "XYZ" (at least one of X, Y, and Z is not equal to 0) to "000" indicates that the test control circuit 200 has ended the test. See [reference needed]. Figure 5 , Figure 5The diagram illustrates another variation of the clock signal ate_CLK frequency in an embodiment of this application. At time t1, the test status signal ring_en changes from "000" to "XYZ", and the frequency of the clock signal ate_CLK decreases from the default operating frequency f1 to the lowest preset frequency f2. Within a Δt1 time interval after the clock signal ate_CLK frequency changes to the lowest preset frequency f2, the frequency of the clock signal ate_CLK gradually increases from the lowest preset frequency f2 to the default test frequency f3. At time t2, the test status signal ring_en changes from "XYZ" to "000". Within a Δt2 time interval after time t2, the frequency of the clock signal ate_CLK gradually decreases from the default test frequency f3 to the lowest preset frequency f2, and then increases back to the default operating frequency f1 after the clock signal ate_CLK frequency decreases to the lowest preset frequency f2.

[0056] As can be seen, when the test control circuit 200 enters the test state, this application first reduces the frequency of the clock signal ate_CLK and then slowly increases the frequency of the clock signal ate_CLK; while when the test control circuit 200 ends the test state, this application first slowly decreases the frequency of the clock signal ate_CLK and then increases the frequency of the clock signal ate_CLK. Therefore, it can not only avoid the problem of a sharp increase in power consumption when the test control circuit 200 enters the test state, but also avoid the problem of a sharp drop in power consumption when the test control circuit 200 ends the test state.

[0057] In some embodiments of this application, when the test status signal ring_en indicates that the test control circuit 200 switches to test another circuit under test 300, the clock output module 20 controls the frequency of the clock signal ate_CLK to remain at the default test frequency.

[0058] For example, see Figure 6 , Figure 6 This diagram illustrates another variation of the clock signal ate_CLK frequency in an embodiment of this application. At time t01, the test status signal ring_en changes from "000" to "101," indicating that the test control circuit 200 enters the test state and tests the circuit under test 0. At time t03, the test status signal ring_en changes from "101" to "100," indicating that the test control circuit 200 ends the test of the circuit under test 0 and switches to test the circuit under test 1. At time t04, the test status signal ring_en changes from "100" to "000," indicating that the test control circuit 200 tests the circuit under test 2. During the process at time t03 where the test control circuit 200 switches from testing the circuit under test 0 to testing the circuit under test 1, the frequency of the clock signal ate_CLK remains unchanged at the default test frequency f3.

[0059] It can be seen that when the test control circuit 200 switches to test another circuit 300 under test, the frequency of the clock signal ate_CLK remains unchanged at the default test frequency. The frequency of the clock signal ate_CLK only changes when the test control circuit 200 enters the test state and ends the test state. Therefore, it can not only avoid the problem of power consumption rising sharply at the start of the logic self-test and dropping sharply during the end process, but also balance the test time and power consumption during the test process, thereby improving test efficiency while ensuring power safety.

[0060] In some embodiments of this application, the test enable signal lbist_ctrl is used to control the test control circuit 200 to perform logic self-tests on the first circuit under test and the second circuit under test sequentially; during the period when the frequency of the clock signal ate_CLK gradually increases from the lowest preset frequency to the default test frequency within a first preset time, the test control circuit 200 performs a logic self-test on the first circuit under test; during the period when the frequency of the clock signal ate_CLK gradually decreases from the default test frequency to the lowest preset frequency within a second preset time, the test control circuit 200 performs a logic self-test on the second circuit under test; wherein, the first circuit under test and the second circuit under test are any two of a plurality of circuits under test 300.

[0061] For example, continue reading Figure 6 The test enable signal lbist_ctrl controls the test control circuit 200 to perform logic self-tests on the circuit under test 0 and the circuit under test 1 in sequence. From time t01 to t02, the frequency of the clock signal ate_CLK gradually increases from the lowest preset frequency f2 to the default test frequency f3. At this time, the test control circuit 200 performs logic self-tests on the circuit under test 0. From time t02 to t03, the frequency of the clock signal ate_CLK remains at the default test frequency f3, and the test control circuit 200 also performs logic self-tests on the circuit under test 0. This is equivalent to implementing built-in logic self-tests on the circuit under test 0 within the range of the lowest preset frequency f2 to the default test frequency f3.

[0062] Similarly, from time t03 to t04, the frequency of the clock signal ate_CLK remains at the default test frequency f3, and the test control circuit 200 performs a logic self-test on the circuit under test 1. From time t04 to t05, the frequency of the clock signal ate_CLK gradually decreases from the default test frequency f3 to the lowest preset frequency f2, and the test control circuit 200 also performs a logic self-test on the circuit under test 1. This is equivalent to implementing a built-in logic self-test for the circuit under test 1 in the range from the lowest preset frequency f2 to the default test frequency f3.

[0063] As can be seen, the above embodiments not only avoid the problem of a sharp increase in power consumption at the start of the logic built-in self-test and a sharp drop in power consumption during the end process, but also implement the logic built-in self-test in the range of the lowest preset frequency f2 to the default test frequency f3 for both the circuit under test 0 and the circuit under test 1. Therefore, it is beneficial to better detect whether there are errors in the circuit under test 0 and the circuit under test 1.

[0064] In some embodiments of this application, the default test frequency is greater than or equal to the default operating frequency.

[0065] In some embodiments of this application, the default test frequency is equal to the default operating frequency. That is, when the test status signal ring_en indicates that the test control circuit 200 enters the test state, the frequency of the clock signal ate_CLK gradually increases from the lowest preset frequency to the default operating frequency; and when the test status signal ring_en indicates that the test control circuit 200 ends the test state, the frequency of the clock signal ate_CLK gradually decreases from the default operating frequency to the lowest preset frequency. This avoids the phenomenon that the test control circuit 200 does not test the circuit 300 under the clock signal ate_CLK with the frequency of the default operating frequency when the default test frequency is lower than the default operating frequency or higher than the default operating frequency.

[0066] In some embodiments of this application, see Figure 7 , Figure 7 Another schematic diagram of the logic self-test control circuit 100 in an embodiment of this application is shown, wherein the clock output module 20 includes a counting unit 21, a selection signal output unit 22, and a clock switching unit 23; the counting unit 21 is used to count the preset clock signal CLK0; the selection signal output unit 22 is used to output a clock selection signal clk_sel according to the count value of the counting unit 21 and the pre-designed value set; the clock switching unit 23 is used to output a clock signal ate_CLK of the corresponding frequency according to the clock selection signal clk_sel; wherein the pre-designed value set includes multiple different pre-designed values, and each pre-designed value corresponds to the frequency of a clock signal ate_CLK.

[0067] For example, taking a preset clock signal CLK0 frequency of 100Hz and a counting unit 21 including a 10-bit counter (maximum count value of 1024) as an example, when the test status signal ring_en changes from "000" to "XYZ" (at least one of X, Y, and Z is not equal to 0) to indicate that the test control circuit 200 enters the test state, the 10-bit counter starts counting the 100Hz clock. With each pulse of the 100Hz clock, the 10-bit counter flips once (for example, from 0000000000 to 0000000001).

[0068] The set of pre-designed values ​​can be stored in a memory circuit (e.g., a register). Suppose the set of pre-designed values ​​includes three pre-designed values: 0000111100 (corresponding to the decimal number 60), 0001111000 (corresponding to the decimal number 120), and 0010110100 (corresponding to the decimal number 180). When the 10-bit counter count value is 0000000000, the selection signal output unit 22 can output the clock selection signal clk_sel to control the clock switching unit 23 to output a 20MHz clock signal ate_CLK (corresponding to the lowest preset frequency); when the 10-bit counter count value reaches 0000111100, the selection signal output unit 22 can output the clock selection signal clk_sel to control the clock switching unit 23 to output a 30MHz clock signal ate_CLK; when the 10-bit counter count value reaches 0001111000, the selection signal output unit 22 can output the clock selection signal clk_sel to control the clock switching unit 23 to output a 40MHz clock signal ate_CLK; when the 10-bit counter count value reaches 0010110100, the selection signal output unit 22 can output the clock selection signal clk_sel to control the clock switching unit 23 to output a 50MHz clock signal ate_CLK (corresponding to the default test frequency and default operating frequency).

[0069] Since the preset clock signal CLK0 frequency is 100Hz, in the above embodiment, after entering the test state, the frequency of the clock signal ate_CLK is changed every 0.6 seconds, gradually increasing from 20MHz to 50MHz within 1.8 seconds. Conversely, the 10-bit counter count value changes from 0010110100 to 0000000000, also changing the frequency of the clock signal ate_CLK every 0.6 seconds, thus gradually decreasing from 50MHz to 20MHz within 1.8 seconds.

[0070] As can be seen, the clock output module 20, which includes a counting unit 21, a selection signal output unit 22, and a clock switching unit 23 in the above embodiments, can gradually change the frequency of the clock signal ate_CLK by counting. This allows the frequency of the clock signal ate_CLK to gradually increase from the lowest preset frequency to the default test frequency when the test control circuit 200 enters the test state, and gradually decrease from the default test frequency to the lowest preset frequency when the test control circuit 200 ends the test state. This avoids the problem of a sudden increase in power consumption at the start of the logic built-in self-test and a sudden drop in power consumption during the end process.

[0071] In some embodiments of this application, when the test status signal ring_en indicates that the test control circuit 200 has entered the test state, the counting unit 21 counts the preset clock signal CLK0 along the first counting direction; when the test status signal ring_en indicates that the test control circuit 200 has ended the test state, the counting unit 21 counts the preset clock signal CLK0 along the second counting direction, which is opposite to the first counting direction.

[0072] For example, taking the first counting direction as positive counting and the second counting direction as reverse counting as an example, when the test status signal ring_en indicates that the test control circuit 200 enters the test state, the counting unit 21 counts the preset clock signal CLK0 positively, for example, the 10-bit counter counts from 0000000000 to 0010110100; and when the test status signal ring_en indicates that the test control circuit 200 ends the test state, the counting unit 21 counts the preset clock signal CLK0 backwards, for example, the 10-bit counter counts from 0010110100 to 0000000000.

[0073] Understandably, the first counting direction can also be a countdown, and the second counting direction can also be a countup.

[0074] In some embodiments of this application, see further reference. Figure 8 , Figure 8 Another schematic diagram of the logic self-test control circuit 100 in this embodiment is shown, wherein when the counting unit 21 counts the preset clock signal CLK0 along the first counting direction to the first preset count value, the counting unit 21 maintains the first preset count value; when the counting unit 21 counts the preset clock signal CLK0 along the second counting direction to the second preset count value, the selection signal output unit 22 outputs the test end enable signal cnt_0, which is used to control the test control circuit 200 to exit the test state.

[0075] It should be noted that since each pre-designed value corresponds to the frequency of a clock signal ate_CLK, when the counting unit 21 counts the preset clock signal CLK0 along the first counting direction to the first preset count value and maintains it at the first preset count value, the selection signal output unit 22 can control the clock switching unit 23 to output the clock signal ate_CLK at the corresponding frequency (e.g., 50MHz), so that after the test of the corresponding circuit under test 300 is completed, the frequency of the clock signal ate_CLK will gradually decrease to the lowest preset frequency. When the counting unit 21 counts the preset clock signal CLK0 along the second counting direction to the second preset count value, the selection signal output unit 22 can control the clock switching unit 23 to output the clock signal ate_CLK at the corresponding frequency (e.g., 20MHz). At the same time, since the selection signal output unit 22 can output the test end enable signal cnt_0, the test control circuit 200 can exit the test state, so that after the test control circuit 200 exits the test, the clock signal ate_CLK will return to the default operating frequency (e.g., 50MHz).

[0076] Understandable Figure 8 The diagram illustrates an embodiment in which the selection signal output unit 22 outputs a test end enable signal cnt_0 to the test state control module 10, and then the test state control module 10 outputs a test enable signal lbist_ctrl to control the test control circuit 200 to exit the test state. In some possible embodiments, the selection signal output unit 22 may also directly output the test end enable signal cnt_0 to the test control circuit 200, and the selection signal output unit 22 directly controls the test control circuit 200 to exit the test state.

[0077] In some embodiments of this application, see Figure 9 , Figure 9 Another schematic diagram of the logic self-test control circuit 100 in an embodiment of this application is shown, wherein the clock output module 20 further includes a first OR gate OR1 and a first edge detection unit 24; the first OR gate OR1 is used to output a level signal according to the test status signal ring_en, and the first edge detection unit 24 is used to detect the rising edge or falling edge of the level signal; wherein, when the first edge detection unit 24 detects the rising edge of the level signal, the first edge detection unit 24 controls the counting unit 21 to count the preset clock signal CLK0 along the first counting direction cut_up; when the first edge detection unit 24 detects the falling edge of the level signal, the first edge detection unit 24 controls the counting unit 21 to count the preset clock signal CLK0 along the second counting direction cut_down.

[0078] It should be noted that the first OR gate OR1 can OR the test status signal ring_en to output a level signal. Taking the test status signal ring_en as a "101" digital signal as an example, the first OR gate OR1 can output a high-level signal; while when the test status signal ring_en is a "000" digital signal, the first OR gate OR1 can output a low-level signal. Since the first edge detection unit 24 can detect the rising or falling edge of the level signal, when the first edge detection unit 24 detects the rising edge of the level signal, the first edge detection unit 24 can control the counting unit 21 to count the preset clock signal CLK0 along the first counting direction (e.g., the positive direction); while when the first edge detection unit 24 detects the falling edge of the level signal, the first edge detection unit 24 can control the counting unit 21 to count the preset clock signal CLK0 along the second counting direction (e.g., the reverse direction), so that the timing unit can count according to the test status signal ring_en and ultimately change the frequency of the clock signal ate_CLK output by the clock switching unit 23.

[0079] In some embodiments of this application, see Figure 10 , Figure 10 Another schematic diagram of the logic self-test control circuit 100 in this application embodiment is shown, wherein the test state control module 10 includes a state machine 11 and a state register 12; the state register 12 is used to write the test input signal lbist_en; the state machine 11 is used to output the test enable signal lbist_ctrl and the test state signal ring_en according to the data of the state register 12.

[0080] For example, when the status register 12 is written with the test input signal lbist_en as "101", the state machine 11 can output the test enable signal lbist_ctrl according to the data in the status register 12, so that the test control circuit 200 can test the circuit under test 0. At the same time, the state machine 11 can output the test status signal ring_en "101" to indicate that the test control circuit 200 is testing the circuit under test 0. When the test control circuit 200 completes the test of the circuit under test 0 and starts the next step of testing the circuit under test 2, the test control circuit 200 outputs the feedback signal lbist_done, changes the data in the status register 12 to "100", and the state machine 11 can output the test status signal ring_en "100" to indicate that the test control circuit 200 is testing the circuit under test 2. Finally, the test status control module 10 can output the test status signal ring_en to indicate the status of the test control circuit 200.

[0081] In some embodiments of this application, see further reference. Figure 11 , Figure 11 Another schematic diagram of the logic self-test control circuit 100 in this application embodiment is shown. In this circuit, the test state control module 10 may further include a second edge detection unit 13 to detect the edge of the feedback signal 1bist_done and control the state register 12 to flip, thereby changing the data stored therein. For example, when the test starts, the state register 12 stores the data "101". When the second edge detection unit 13 receives the feedback signal 1bist_done for the first time, the second edge detection unit 13 can control the data stored in the state register 12 to change to "100". When the second edge detection unit 13 receives the feedback signal 1bist_done for the second time, the second edge detection unit 13 can control the data stored in the state register 12 to change to "000".

[0082] Meanwhile, the test state control module 10 may also include a second OR gate OR2, a third edge detection unit 14, and a first AND gate AND1. The second OR gate OR2 can OR the test input signal lbist_en and output a level signal. The third edge detection unit 14 can detect the edge of the test start signal test_start and output a level signal. Finally, the first AND gate AND1 ANDs the level signal output by the second OR gate OR2 and the third edge detection unit 14 and outputs a control signal, thereby controlling whether the state register 12 is written with the test input signal lbist_en. In other words, this application can use the logic circuit composed of the second OR gate OR2, the third edge detection unit 14, and the first AND gate AND1 to control whether the state register 12 is written with the test input signal lbist_en according to the test input signal lbist_en and the test start signal test_start, avoiding the possible false start phenomenon that the logic self-test control circuit 100 is only responding to the test input signal lbist_en.

[0083] Below, in conjunction with this application Figure 11 as well as Figure 12 This application provides an exemplary description of the operation of the logic self-test control circuit 100. Figure 12 A timing diagram of a logic self-test control circuit 100 in an embodiment of this application is shown. In the initial state, the test input signal lbist_en is "000", the data stored in the state register 12 is "000", and the state machine 11 is in the IDLE state. The logic self-test control circuit 100 does not control the test control circuit 200 to test the circuit 300 under test.

[0084] When the pulse of the test start signal test_start arrives and the test input signal lbist_en is "101", the state register 12 writes the data "101". At this time, the state machine 11 is in the RING0 state. The state machine 11 outputs the test enable signal lbist_ctrl to control the test control circuit 200 to test the circuit under test 0. The frequency of the clock signal ate_CLK changes from 50MHz to 20MHz. At the same time, the state machine 11 outputs the test status signal ring_en "101" to make the counting unit 21 count positive numbers.

[0085] When the counting unit 21 counts to thr0, the selection signal output unit 22 controls the clock signal ate_CLK output by the clock switching unit 23 to change the frequency from 20MHz to 33MHz; when the counting unit 21 counts to thr1, the selection signal output unit 22 controls the clock signal ate_CLK output by the clock switching unit 23 to change the frequency from 33MHz to 50MHz; when the counting unit 21 counts to thr2, the counting unit 21 stops counting, and the selection signal output unit 22 controls the clock signal ate_CLK output by the clock switching unit 23 to remain at 50MHz.

[0086] When the test control circuit 200 completes the test on the circuit under test 0, the test control circuit 200 outputs feedback ibist_done, which changes the data of the status register 12 to "100". The state machine 11 changes to the RING1 state. Since the test status signal ring_en[1] = 0, the state machine 11 then changes to the RING2 state. The state machine 11 outputs the test enable signal lbist_ctrl to control the test control circuit 200 to test the circuit under test 2.

[0087] When the test control circuit 200 completes the test on the circuit under test 2, the test control circuit 200 outputs feedback ibist_done, which changes the data in the status register 12 to "000". The state machine 11 changes to the ATECLK_CTRL state, and the state machine 11 outputs the test enable signal lbist_ctrl to the test control circuit 200 to control the circuit under test 2 to perform the test again. At the same time, the state machine 11 outputs the test status signal ring_en "000", which causes the counting unit 21 to count down.

[0088] When the counting unit 21 counts to thr1, the selection signal output unit 22 controls the clock switching unit 23 to change the frequency of the clock signal ate_CLK from 50MHz to 33MHz; when the counting unit 21 counts to thr0, the selection signal output unit 22 controls the clock switching unit 23 to change the frequency of the clock signal ate_CLK from 33MHz to 20MHz; when the counting unit 21 counts to 0, the selection signal output unit 22 outputs the test end enable signal cnt_0, which allows the test control circuit 200 to exit the test state, and after the test control circuit 200 exits the test state, the frequency of the clock signal ate_CLK is changed from 20MHz to 50MHz.

[0089] It is worth noting that the above description of the logic self-test control circuit 100 is intended to clearly illustrate the implementation and verification process of this application. Those skilled in the art can make equivalent modifications and designs under the guidance of this application. For example, the status register 12 can be directly connected to the test start signal test_start and the test input signal lbist_en, and the test start signal test_start can control whether the status register 12 stores the data of the test input signal lbist_en. For another example, in the embodiments of this application, the test status signal ring_en is used as a digital signal to represent the state of the test control circuit 200. In fact, the test status signal ring_en output by the test status control module 10 can also be used as an analog signal to represent the state of the test control circuit 200. For example, 1V represents testing the circuit 1 under test, and 2V represents testing the circuit 2 under test.

[0090] This application also provides a chip that includes the logic self-test control circuit 100 described above. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip. Since the chip of this application possesses the logic self-test control circuit 100 described in the above embodiments, it has all the beneficial effects of the logic self-test control circuit 100 in the above embodiments, which will not be repeated here.

[0091] This application also provides an electronic device, which includes a device body and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0092] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A logic self-test control circuit, characterized by, The logic self-checking control circuit is configured to output a clock signal to a test control circuit and a plurality of circuits to be tested, and comprises: a test state control module configured to receive a test input signal and output a test state signal, the test state signal being used to represent a test state of the test control circuit; a clock output module configured to output the clock signal according to the test state signal; wherein, when the test state signal represents that the test control circuit enters the test state, the clock output module controls the frequency of the clock signal to gradually increase to a default test frequency within a first preset time in response to the test state signal.

2. The logic self-test control circuit of claim 1, wherein, When the test state signal represents that the test control circuit ends the test state, the clock output module controls the frequency of the clock signal to gradually decrease from the default test frequency to a minimum preset frequency within a second preset time in response to the test state signal.

3. The logic self-test control circuit of claim 2, wherein, When the test state signal represents that the test control circuit enters the test state, the clock output module controls the frequency of the clock signal to decrease from a default working frequency to a minimum preset frequency and gradually increase to the default test frequency within the first preset time after decreasing to the minimum preset frequency in response to the test state signal.

4. The logic self-test control circuit of claim 3, wherein, When the test state signal represents that the test control circuit ends the test state, the clock output module controls the frequency of the clock signal to gradually decrease from the default test frequency to the minimum preset frequency within a second preset time in response to the test state signal, and increase to the default working frequency after decreasing to the minimum preset frequency.

5. The logic self-test control circuit of claim 2, wherein, When the test state signal represents that the test control circuit switches to test another circuit to be tested, the clock output module controls the frequency of the clock signal to remain at the default test frequency.

6. The logic self-test control circuit of claim 1, wherein, The clock output module comprises a counting unit, a selection signal output unit and a clock switching unit; the counting unit is configured to count a preset clock signal; the selection signal output unit is configured to output a clock selection signal according to a counting value of the counting unit and a preset counting value set; the clock switching unit is configured to output a clock signal with a corresponding frequency according to the clock selection signal; wherein, the preset counting value set comprises a plurality of different preset counting values, each of which corresponds to a frequency of a clock signal.

7. The logic self-test control circuit of claim 6, wherein, When the test state signal represents that the test control circuit enters the test state, the counting unit counts the preset clock signal in a first counting direction; When the test state signal represents that the test control circuit ends the test state, the counting unit counts the preset clock signal in a second counting direction, which is opposite to the first counting direction.

8. The logic self-test control circuit of claim 7, wherein, When the counting unit counts the preset clock signal in the first counting direction to a first counting preset value, the counting unit remains at the first counting preset value; When the counting unit counts the preset clock signal in a second counting direction to a second preset counting value, the selection signal output unit outputs a test end enable signal, which is used to control the test control circuit to exit a test state.

9. The logic self-test control circuit of claim 8, wherein, The clock output module further comprises a first OR gate and a first edge detection unit; The first OR gate is used to output a level signal according to the test state signal, and the first edge detection unit is used to detect a rising edge or a falling edge of the level signal; When the first edge detection unit detects the rising edge of the level signal, the first edge detection unit controls the counting unit to count the preset clock signal in a first counting direction; When the first edge detection unit detects the falling edge of the level signal, the first edge detection unit controls the counting unit to count the preset clock signal in a second counting direction.

10. The logic self-test control circuit of claim 1, wherein, The test state control module comprises a state machine and a state register; The state register is used to write the test input signal; The state machine is used to output the test state signal according to data of the state register.

11. A chip, characterized by A chip comprising the logic self-test control circuit according to any one of claims 1 to 10.

12. An electronic device, comprising: A chip comprising the logic self-test control circuit according to claim 11.

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