Test method, electronic device, storage medium, and program

Abstract

This invention discloses a testing method, electronic device, storage medium, and program. The method includes: acquiring a composite test stimulus for a target test object; wherein the composite test stimulus is synthesized from multiple target basic test stimulus sequences; attaching the composite test stimulus to the state transition arc of the test state machine of the target test object; wherein the test state machine is used to test the target test object according to the composite test stimulus; collecting the test output response of the target test object, and determining the target test result of the target test object based on the test output response. The technical solution of this invention can achieve thorough testing of the system, thereby improving the comprehensiveness and reliability of system testing.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of testing, and more particularly to a testing method, electronic device, storage medium, and program. Background Technology

[0002] As system design scale and logical complexity continue to increase, system testing, as a crucial step in ensuring correct system functionality and stable performance, is becoming increasingly important. Current system testing methods mostly employ test case sets based on basic test sequences, which are essentially still single-point testing. Even with a large number of test cases, this approach struggles to achieve comprehensive system verification. Specifically, during the execution of each test case, it's impossible to simultaneously drive numerous logical units within the system to work in parallel, making it difficult to form effective stress tests and hindering the exposure of potential defects under high load scenarios. Furthermore, large-scale test case sets significantly increase the resource consumption and time overhead of regression testing, reducing development iteration efficiency. Summary of the Invention

[0003] This invention provides a testing method, apparatus, electronic device, storage medium, and program that can achieve comprehensive testing of a system, thereby improving the comprehensiveness and reliability of system testing.

[0004] According to one aspect of the present invention, a testing method is provided, comprising: Obtain a composite test stimulus for the target test object; wherein the composite test stimulus is synthesized from multiple target basic test stimulus sequences; The composite test stimulus is attached to the state transition arc of the test state machine of the target test object; wherein, the test state machine is used to test the target test object according to the composite test stimulus; Collect the test output response of the target test object, and determine the target test result of the target test object based on the test output response.

[0005] According to another aspect of the present invention, a testing apparatus is provided, comprising: A composite test stimulus acquisition module is used to acquire composite test stimuli for the target test object; wherein, the composite test stimulus is synthesized from multiple target basic test stimulus sequences; A composite test stimulus mounting module is used to mount the composite test stimulus to the state transition arc of the test state machine of the target test object; wherein, the test state machine is used to test the target test object according to the composite test stimulus; The target test result determination module is used to collect the test output response of the target test object and determine the target test result of the target test object based on the test output response.

[0006] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the test method described in any embodiment of the present invention.

[0007] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the test method described in any embodiment of the present invention.

[0008] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a processor, implements the testing method described in any embodiment of the present invention.

[0009] This invention provides a composite test stimulus by acquiring multiple target basic test stimulus sequences of the target test object and attaching the composite test stimulus to the state transition arcs of the target test object's test state machine. This allows the test state machine to test the target test object according to the composite test stimulus. During the test, the test output response of the target test object is collected, and the target test result is determined based on the test output response. This solution overcomes the shortcomings of existing single-point testing, enabling comprehensive system testing and thus improving the comprehensiveness and reliability of system testing.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart of the testing method provided in Embodiment 1 of the present invention; Figure 2 This is a flowchart of a testing method provided in Embodiment 2 of the present invention; Figure 3This is a schematic diagram of the architecture of a testing system provided in Embodiment 2 of the present invention; Figure 4 This is a schematic diagram of the state transition arc of a target test object provided in Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of a testing device provided in Embodiment 3 of the present invention; Figure 6 This is a schematic diagram of the structure of an electronic device provided in Embodiment 4 of the present invention. Detailed Implementation

[0013] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0014] It should be noted that the terms "objective," "basic," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0015] Example 1 Figure 1 This is a flowchart of a testing method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where a target test object is tested using composite test stimuli. The method can be executed by a testing device, which can be implemented in software and / or hardware, and is generally integrated into an electronic device. This electronic device can be a terminal device or a server device, as long as it can execute the testing method. The present invention does not limit the specific type of electronic device. Correspondingly, as... Figure 1 As shown, the method includes the following operations: S110. Obtain the composite test stimulus of the target test object; wherein, the composite test stimulus is synthesized from multiple target basic test stimulus sequences.

[0016] The target test object can be the object to be tested by the system. For example, the target test object can include, but is not limited to, chips, embedded systems, and software systems; this embodiment of the invention does not limit the specific type of the target test object. The target basic test stimulus sequence can be a basic test input sequence constructed for a single function, single interface, or single operation of the target test object. The composite test stimulus can be a test stimulus synthesized from multiple target basic test stimulus sequences.

[0017] In this embodiment of the invention, to achieve comprehensive testing of the target test object, a target basic test stimulus sequence for verifying a certain basic function of the target test object can first be constructed. Based on this, multiple target basic test stimulus sequences can be combined to obtain composite test stimuli for the target test object. It is understood that different target basic test stimulus sequences typically correspond to different test dimensions, different abnormal scenarios, or normal scenarios.

[0018] S120. The composite test stimulus is attached to the state transition arc of the test state machine of the target test object; wherein, the test state machine is used to test the target test object according to the composite test stimulus.

[0019] In this context, a test state machine can be used to model, analyze, and verify the behavior and transition logic of a target test object under different test states. A state transition arc can be a directed connection between the test states of the test state machine. A state transition arc can be used to represent the process by which the target test object jumps from one test state to another.

[0020] Accordingly, after obtaining the composite test stimuli for the target test object, the composite test stimuli can be attached to the test state machine of the target test object, establishing a correspondence with each state transition arc. After attachment, the test state machine can automatically read and parse the composite test stimuli corresponding to each state transition arc, and apply the composite test stimuli to the corresponding test position of the target test object, so that the target test object generates corresponding stimulus responses and behavioral feedback after receiving the composite test stimuli.

[0021] S130. Collect the test output response of the target test object, and determine the target test result of the target test object based on the test output response.

[0022] The test output response can be the stimulus response and behavioral feedback generated by the target test object after receiving the composite test stimulus. The target test result can be the final conclusion obtained after testing the target test object, indicating whether the target test object has passed the verification.

[0023] Specifically, after receiving the composite test stimulus applied by the test state machine, the corresponding test position of the target test object can respond to the composite test stimulus and generate corresponding stimulus responses and behavioral feedback. Therefore, during the testing process of the target test object, the stimulus responses and behavioral feedback generated by the target test object can be collected as the test output response of the target test object. Based on this, the test output response of the target test object can be compared and analyzed with the preset test output response, thereby determining the target test result of the target test object.

[0024] Therefore, the testing method provided in this invention obtains composite test stimuli for the target test object by combining multiple target basic test stimulus sequences. Through the convenient, flexible, and efficient organization of multiple target basic test stimulus sequences, it effectively overcomes the limitations of traditional single test stimulus sequences, significantly improves the comprehensiveness and relevance of the target test object testing, significantly optimizes test results, reduces test costs, and improves test efficiency, providing strong support for the stability and reliability verification of the target test object. Furthermore, the target basic test stimulus sequences can be individually updated, supplemented, or optimized according to actual test needs without requiring large-scale adjustments to the overall test stimulus system. When adding new test scenarios, only the corresponding target basic test stimulus sequences need to be added and combined, significantly reducing test maintenance costs and expansion difficulty, facilitating long-term reuse and iterative upgrades.

[0025] This invention provides a composite test stimulus by acquiring multiple target basic test stimulus sequences of the target test object and attaching the composite test stimulus to the state transition arcs of the target test object's test state machine. This allows the test state machine to test the target test object according to the composite test stimulus. During the test, the test output response of the target test object is collected, and the target test result is determined based on the test output response. This solution overcomes the shortcomings of existing single-point testing, enabling comprehensive system testing and thus improving the comprehensiveness and reliability of system testing.

[0026] Example 2 Figure 2 This is a flowchart of a testing method provided in Embodiment 2 of the present invention. This embodiment is a specific embodiment based on the above embodiment. In this embodiment, specific optional implementation methods for obtaining the composite test stimulus of the target test object are given, as well as optional implementation operations before obtaining the composite test stimulus of the target test object. Correspondingly, as Figure 2 As shown, the method in this embodiment may include: S210. Determine the test target of the target test object.

[0027] The test objective can be the core content to be verified and the expected verification standard to be achieved when conducting tests on the target test object.

[0028] Before executing the testing process on the target test object, it is necessary to clarify and determine the test objectives corresponding to this test. The test objectives include key information such as the core content to be verified, functional indicators, performance requirements, and expected verification standards to be achieved in this test. The subsequent test process will be planned and executed based on the determined test objectives, thereby ensuring that the test process has clear focus and direction, avoiding blind test operations, and improving the effectiveness of test execution and the accuracy of test results.

[0029] S220. Determine the state transition relationship between each test state in the test state machine according to the test objective of the target test object.

[0030] Among them, the state transition relationship can be the corresponding rules and associations for switching from the current test state in the test state machine to the target test state when a specific trigger condition is met.

[0031] Accordingly, after determining the test objectives of the target test object, the execution logic, constraints, and exception handling strategies in the test process can be comprehensively analyzed based on these objectives. Based on this information, the triggering conditions, transition times, and execution order of each test state in the test state machine can be clarified. Furthermore, the state transition relationships between each test state in the test state machine can be determined based on these relationships. This allows the test state machine to determine the test order of the composite test stimuli attached to each state transition arc, thereby enabling the testing of the target test object.

[0032] S230. Determine the test configuration data of the composite test stimulus based on each test state in the test state machine and the state transition relationship between each test state.

[0033] The test configuration data can be a set of parameters used to define the attributes of composite test stimuli. For example, the test configuration data may include, but is not limited to, the test order between composite test stimuli and the stimulus type of each composite test stimuli. This embodiment of the invention does not limit the specific content included in the test configuration data. The stimulus type of composite test stimuli may include, but is not limited to, configuration stimulus sequences and data stimulus sequences, etc. This embodiment of the invention does not limit the stimulus type of composite test stimuli.

[0034] Accordingly, after determining the state transition relationships between each test state in the test state machine based on the test objectives of the target test object, the test configuration data for the composite test stimulus can be determined based on each test state in the test state machine and the state transition relationships between each test state.

[0035] In an optional embodiment of the present invention, determining the test configuration data of the composite test stimulus based on each test state in the test state machine and the state transition relationship between each test state may include: determining the stimulus type of the composite test stimulus based on the state type of each test state in the test state machine; determining the transition weight of the state transition relationship between each test state in the test state machine; wherein the transition weight is used to determine the transition probability between each test state; and determining the test order between each composite test stimulus based on the transition weight of the state transition relationship between each test state.

[0036] The test state type can be configuration data used to define the functional purpose, behavioral characteristics, and processing logic of the test state. The jump weight can be the weight set for each target test state in a scenario where a certain test state corresponds to multiple target test states. The jump probability can be the probability of a certain test state jumping to a certain target test state.

[0037] Test cases designed directly based on scenarios generally suffer from long development cycles, limited number of test cases, and difficulty in problem localization and correction. Furthermore, the construction methods for test scenarios are relatively simplistic, resulting in poor reusability and portability of test cases. It is also difficult to establish effective correlations between multiple scenarios during testing, failing to meet the testing requirements for flexible combination and dynamic switching of scenarios over long periods and on a large scale.

[0038] Therefore, when determining the test configuration data for composite test stimuli based on the test states in the test state machine and the state transition relationships between them, the test task corresponding to each test state and the stimulus type required by the target test object in that test state can be analyzed based on the state type defined in the test state machine. This clarifies the stimulus function, stimulus format, and stimulus constraints to be applied in each test state. Simultaneously, the preset transition weights between the test states in the test state machine can be obtained, allowing the determination of the transition probability between test states based on these weights. This, in turn, determines the target test state to which the current test state should transition. In a specific example, assuming that the target test states corresponding to test state A include test states B, C, and D, and that the transition weight for test state B is 0.2, the transition weight for test state C is 0.6, and the transition weight for test state D is 0.2, then the transition probability from test state A to test state C is the highest.

[0039] After determining the target test state to which the current test state should jump, the execution order, jump triggering conditions, and dependencies between test states can be determined based on the state transition relationship between the current and target test states. This allows the state transition chain to be mapped to the execution sequence of composite test stimuli, thus determining the test order among multiple composite test stimuli. It is understandable that the number of test states in the test state machine and the state transition relationships between them are unlimited. The above scheme, through a weighted multi-target jump strategy, can meet the needs of random system testing.

[0040] Figure 3 This is a schematic diagram of the architecture of a testing system provided in Embodiment 2 of the present invention. In a specific example, such as Figure 3 As shown, the test system may include a top-level test scenario state machine generator controller, a mid-level composite test stimulus sequence synthesizer, a basic test stimulus sequence library, and a target test object including a test state machine. The top-level test scenario state machine generator controller can be used to define relevant information about the test state machine in the target test object.

[0041] Specifically, the top-level test scenario state machine generator controller can register all test states and their corresponding names in the test state machine at once through a dedicated registration portal, ensuring that no two test state names are duplicated. The top-level test scenario state machine generator controller can also specify a test state name as the starting point for the entire test state machine's operation through initial test state settings. It's understood that the initial test state must be included among the already registered test states. The top-level test scenario state machine generator controller can also set the single-state transition relationship between two test states through the system's unified jump interface, which can include the starting test state name, the target test state name, and the name of the test stimulus arc to be completed between the starting and target test states. Furthermore, the top-level test scenario state machine generator controller can achieve the effect of randomly switching test scenarios by setting random weights for each target test state. The top-level test scenario state machine controller can also set the maximum number of jumps in a single test by setting a dedicated global jump count variable or register. The corresponding global counter increments when a state jump occurs. When the value of the global jump counter matches the value of the global jump count variable, the test state machine jump ends and the overall test is completed.

[0042] S240. Select multiple target basic test stimulus sequences from the basic test stimulus sequence library based on the test configuration data of the composite test stimulus.

[0043] The basic test stimulus sequence library includes multiple basic test stimulus sequences.

[0044] Accordingly, after determining the test configuration data of the composite test stimulus, the basic test stimulus sequences in the basic test stimulus sequence library can be retrieved and matched based on the test configuration data of the composite test stimulus, so that multiple target basic test stimulus sequences that meet the test configuration data can be selected from the basic test stimulus sequence library.

[0045] In an optional embodiment of the present invention, the step of selecting multiple target basic test stimulus sequences from the basic test stimulus sequence library based on the test configuration data of the composite test stimulus may include: selecting target configuration stimulus sequences from the configuration stimulus sequences in the basic test stimulus sequence library when it is determined that the stimulus type of the composite test stimulus includes system operating mode stimulus; and selecting target data stimulus sequences from the data stimulus sequences in the basic test stimulus sequence library when it is determined that the stimulus type of the composite test stimulus includes system operation stimulus. The configuration stimulus sequences include at least one of phase-locked loop configuration stimulus sequences, clock mode control stimulus sequences, bus random control stimulus sequences, dynamic clock gating stimulus sequences, security mode configuration stimulus sequences, and power consumption control stimulus sequences. The data stimulus sequences include at least one of data random access stimulus sequences, data pressure access stimulus sequences, and protocol data stimulus sequence groups.

[0046] The system operating mode stimulus can be a stimulus strategy configured for different operating modes of the target test object during runtime. The configuration stimulus sequence can be a stimulus sequence used to configure the system in different operating modes. For example, the configuration stimulus sequence can include, but is not limited to, phase-locked loop (PLL) configuration stimulus sequences, clock mode control stimulus sequences, bus random control stimulus sequences, dynamic clock gating stimulus sequences, safety mode configuration stimulus sequences, and power consumption control stimulus sequences. This embodiment of the invention does not limit the specific type of the configuration stimulus sequence. The PLL configuration stimulus sequence can be a combination of sequences injected into the PLL module in chronological order. The clock mode control stimulus sequence can be a combination of sequences injected into the clock module in chronological order. The bus random control stimulus sequence can be a combination of a set of randomized control commands and data sent to the bus interface in chronological order. The dynamic clock gating stimulus sequence can be a combination of a series of dynamic enable signals and clocks applied to the clock gating logic of the target test object. The safety mode configuration stimulus sequence can be a stimulus sequence used to trigger, configure, and test the safety mode of the target test object. The power consumption control stimulus sequence can be a stimulus sequence used to actively control the target test object to enter / exit various low-power modes or adjust power consumption measurements. The target configuration stimulus sequence can be a configuration stimulus sequence that matches the system operating mode stimulus.

[0047] System operation incentives can be incentive strategies that drive the target test object to execute functional behaviors in different working modes. Data incentive sequences can be incentive sequences used to determine the target test object's execution of corresponding functional behaviors. For example, data incentive sequences can include, but are not limited to, random data access incentive sequences, data stress access incentive sequences, and protocol data incentive sequences. This embodiment of the invention does not limit the specific type of data incentive sequences. A random data access incentive sequence can be a set of incentive sequences generated according to random addresses, random timing, and random data / commands, which can be used to test the functionality, timing, and robustness of the target test object under complex, non-sequential access. A data stress access incentive sequence can be an incentive sequence used to test the functional reliability, timing robustness, and performance limits of the target test object under extreme pressure, high concurrency, high density, or long-term continuous operation scenarios. A protocol data incentive sequence can be an incentive sequence used to test the interface and protocol logic of the target test object. The target data incentive sequence can be a data incentive sequence matched with the system operation incentives.

[0048] When filtering multiple target basic test stimulus sequences from the basic test stimulus sequence library based on the test configuration data of the composite test stimulus, the type of the target basic test stimulus sequence to be filtered can be determined based on the stimulus type of the composite test stimulus, thereby achieving targeted selection and matching of the target basic test stimulus sequence. Specifically, if it is determined that the stimulus type of the composite test stimulus includes system operating mode stimulus, then the target configuration stimulus sequence corresponding to the system operating mode stimulus can be filtered from the configuration stimulus sequence contained in the basic test stimulus sequence library; if it is determined that the stimulus type of the composite test stimulus includes system operation stimulus, then the target data stimulus sequence corresponding to the system operation stimulus can be filtered from the data stimulus sequence contained in the basic test stimulus sequence library.

[0049] In an optional embodiment of the present invention, the testing method may further include: configuring bus and address space information of a basic test stimulus sequence template according to the test target of the target test object; generating the configuration stimulus sequence according to the basic test stimulus sequence template; and generating the data stimulus sequence according to the protocol constraints of the target test object.

[0050] The basic test stimulus sequence template can be a template used to generate various configuration stimulus sequences in the basic test stimulus sequence library. Bus and address space information can be used to describe the location of all accessible resources in the target test object and the rules governing the communication channels (buses) used to access these locations. Protocol constraints can be all the rules, restrictions, and conditions that must be followed as specified in the communication protocol followed by the target test object.

[0051] like Figure 3As shown, the test system can also include a basic test stimulus sequence library. Therefore, before testing the target test object, the basic test stimulus sequence library needs to be built in advance. The basic test stimulus sequences in the library are mainly divided into two categories: configuration stimulus sequences and data stimulus sequences. Configuration stimulus sequences can configure the internal control registers of the target test object to enable it to operate in different modes, such as boot mode configuration, clock frequency configuration, low-power configuration, virtualization configuration, security access policy (firewall) configuration, encoding / decoding mode configuration, storage device capacity / speed configuration, and high-speed transmission interface mode configuration. Configuration stimulus sequences can be generated using a unified basic test stimulus sequence template. The basic test stimulus sequence template encapsulates the configuration interfaces and security mechanisms required for accessing registers, which may include, but are not limited to, bus function model settings, address map loading, standard register access (read and write) interfaces, and parallel thread access register resource conflict protection measures.

[0052] Specifically, when generating configuration stimulus sequences, the bus and address space information of the basic test stimulus sequence template can be configured according to the test objectives of the target test object. This involves specifying different address maps and bus function models to build a test environment that adapts to the test objective and covers different levels, achieving vertical reuse of test stimuli from the module level, subsystem level to the full target test object level. Furthermore, combined with a global management approach for stimulus components, vertical reuse of data stimulus sequences can be further achieved. After configuring the basic test stimulus sequence template, configuration stimulus sequences can be generated based on the configured template. Simultaneously, corresponding data stimulus sequences can be generated based on the communication protocol constraints and hardware characteristics followed by the target test object. It should be noted that the data stimulus sequences add a mechanism to support registration for different transmission protocols to the general basic test stimulus sequences, enabling concurrent stimulus data for different transmission protocols. Based on this, a basic test stimulus sequence library can be constructed using the generated configuration stimulus sequences and data stimulus sequences.

[0053] Furthermore, the testing scheme provided in this embodiment of the invention features multi-level templates and key interface functions. It can independently complete a full system test or be easily integrated into existing test scenarios or frameworks, enabling efficient reuse of existing basic test stimulus sequence libraries. Simultaneously, the test scenarios built based on the upper-level test state machine are independent of and do not interfere with other test sequences and scenarios, allowing for flexible combination with existing test processes to achieve efficient verification testing.

[0054] S250. The target basic test stimulus sequence is combined according to the target stimulus synthesis method to generate the composite test stimulus of the target test object.

[0055] The target stimulus synthesis method can be a combination of target basic test stimulus sequences. For example, the target stimulus synthesis method may include, but is not limited to, parallel, serial, cyclic, reference-cyclic, and random delay methods. This embodiment of the invention does not limit the specific content included in the target stimulus synthesis method.

[0056] After obtaining multiple target basic test stimulus sequences through screening, the target stimulus synthesis method corresponding to the test target of the target test object can be determined. Then, the target basic test stimulus sequences can be combined according to the target stimulus synthesis method to generate composite test stimuli for the target test object.

[0057] In an optional embodiment of the present invention, the step of combining the target basic test stimulus sequence according to the target stimulus synthesis method to generate the composite test stimulus for the target test object may include: performing parallel processing on the target basic test stimulus sequence when it is determined that there is no conflict in the test resources of the target test object and the test mode of the target basic test stimulus sequence is parallel mode; performing variable-order serial processing on the target basic test stimulus sequence when it is determined that the test mode of the target basic test stimulus sequence is serial mode; performing cyclic processing on the target basic test stimulus sequence according to a preset number of executions when it is determined that the test mode of the target basic test stimulus sequence is cyclic mode; performing cyclic processing on the target basic test stimulus sequence according to the execution state of the reference stimulus sequence when it is determined that the test mode of the target basic test stimulus sequence is random delay mode; and performing random delay processing on the target basic test stimulus sequence before stimulus execution when it is determined that the test mode of the target basic test stimulus sequence is random delay mode.

[0058] The test mode can be the execution mode of each target basic test stimulus sequence in the composite test stimulus. The parallel mode can be a test mode in which each target basic test stimulus sequence in the composite test stimulus is executed in parallel. The serial mode can be a test mode in which each target basic test stimulus sequence in the composite test stimulus is executed serially. The loop mode can be a test mode in which each target basic test stimulus sequence in the composite test stimulus is executed cyclically. The preset execution count can be a pre-set execution count for each target basic test stimulus sequence. The reference loop mode can be a test mode in which each target basic test stimulus sequence in the composite test stimulus is executed cyclically along with the execution of a reference stimulus sequence. The reference stimulus sequence can be a stimulus sequence used to provide a reference for the execution determination of each target basic test stimulus sequence.

[0059] like Figure 3As shown, the testing system may also include a mid-level composite test stimulus synthesizer. The mid-level composite test stimulus synthesizer can be used to combine and process multiple target basic test stimulus sequences from the basic test stimulus sequence library, thereby forming hierarchical composite test stimuli based on the test objectives, and attaching the obtained composite test stimuli to the state transition arcs of the test state machine of the target test object. Specifically, the mid-level composite test stimulus synthesizer can determine the test mode of the target basic test stimulus sequence based on the test objectives of the target test object, and then combine and process multiple target basic test stimulus sequences based on the test mode of the target basic test stimulus sequence. Specifically, if it is determined that there are no conflicts in the test resources of the target test object, and the test mode of the target basic test stimulus sequence is parallel mode, then parallel processing operations can be performed on the target basic test stimulus sequence, so that when the state transition arc containing the composite test stimulus is selected for execution during the test, all registered target basic test stimulus sequences within it run in parallel until the test is completed. If the test mode of the target basic test stimulus sequence is determined to be serial mode, variable-order serial processing can be performed on the target basic test stimulus sequence so that when the state transition arc containing the composite test stimulus is selected for execution during the test, all registered target basic test stimulus sequences within it are executed sequentially according to their registration order or according to a serial random order set by a specific switch. If the test mode of the target basic test stimulus sequence is determined to be cyclic mode, the target basic test stimulus sequence can be cyclically processed according to a preset number of executions so that when the state transition arc containing the composite test stimulus is selected for execution during the test, all registered target basic test stimulus sequences within it are executed multiple times according to the preset number of executions. If the test mode of the target basic test stimulus sequence is determined to be reference cyclic mode, the target basic test stimulus sequence can be cyclically processed according to the execution state of the reference stimulus sequence so that when the state transition arc containing the composite test stimulus is selected for execution during the test, the selected target basic test stimulus sequence is continuously cyclically executed until the reference stimulus sequence it refers to completes execution. If the test mode of the target basic test stimulus sequence is determined to be random delay mode, then random delay processing can be applied to the target basic test stimulus sequence before stimulus execution. This ensures that when the state transition arc containing the composite test stimulus is selected for execution during the test, each target basic test stimulus sequence in the composite test stimulus will have a random delay that meets preset rules inserted before execution. The target stimulus synthesis method adopted in the above scheme can flexibly combine and dynamically generate various basic test stimulus sequences, almost covering all potential test stimulus combination behaviors during the test process. This effectively avoids test omissions caused by incomplete coverage of test stimulus combinations, thereby significantly improving overall test coverage and verification completeness.

[0060] S260. The composite test stimulus is attached to the state transition arc of the test state machine of the target test object.

[0061] Figure 4 This is a schematic diagram of the state transition arc of a target test object provided in Embodiment 2 of the present invention. In a specific example, such as... Figure 4 As shown, if the test state machine of the target test object transitions from the initial state to the system configuration state, the composite test stimulus attached to the state transition arc of the test state machine is a serial composite test stimulus, wherein the serial composite test stimulus includes a phase-locked loop configuration stimulus sequence, a clock mode control stimulus sequence, and a security mode configuration stimulus sequence. If the test state machine of the target test object transitions from the system configuration state to the data pressure access state, from the security mode configuration state to the data pressure access state, or from the power consumption / clock switching state to the data pressure access state, the composite test stimulus attached to the state transition arc of the test state machine is a random data pressure access stimulus sequence. It can be understood that the composite test stimulus in the test method provided in this embodiment of the invention can be synthesized from multiple target basic test stimulus sequences, or it can include only a single target basic test stimulus sequence. If the test state machine of the target test object transitions from the system configuration state to the security mode configuration state, or from the data pressure access state to the security mode configuration state, the composite test stimulus attached to the state transition arc of the test state machine is a security mode configuration stimulus sequence. If the test state machine of the target test object transitions from a data pressure access state to a power consumption / clock switching state, or from a data random / control random state to a power consumption / clock switching state, then the composite test stimulus attached to the state transition arc of the test state machine is a serial cyclic composite test stimulus, which includes a power consumption control stimulus sequence and a clock mode control stimulus sequence. If the test state machine of the target test object transitions from a safe mode configuration state to a data random / control random state, from a power consumption / clock switching state to a data random / control random state, or from one data random / control random state to another, then the composite test stimulus attached to the state transition arc of the test state machine is a parallel composite test stimulus, which includes a data random access stimulus sequence, a bus random control stimulus sequence, and a dynamic clock gating stimulus sequence. It is understood that the same test stimulus sequence can be repeatedly executed on different state transition arcs.

[0062] S270. Collect the test output response of the target test object, and determine the target test result of the target test object based on the test output response.

[0063] This invention, through its embodiments, determines the test objectives of the target test object, establishes the state transition relationships between test states in the test state machine based on these objectives, and then determines the test configuration data for composite test stimuli based on the test states and their transition relationships. After obtaining the composite test configuration data, multiple target basic test stimulus sequences are selected from the basic test stimulus sequence library based on this data. These sequences are then combined according to a target stimulus synthesis method to generate composite test stimuli for the target test object. These composite test stimuli are then attached to the state transition arcs of the target test object's test state machine. Furthermore, during the testing process, the test output response of the target test object is collected, and the target test result is determined based on the test output response. This solution overcomes the shortcomings of existing single-point testing, enabling comprehensive system testing and improving the comprehensiveness and reliability of system testing.

[0064] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information in this technical solution comply with relevant laws and regulations and do not violate public order and good morals.

[0065] It should be noted that all information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for display, data used for analysis, etc.) involved in this disclosure are information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data comply with the relevant laws, regulations and standards of the relevant regions.

[0066] It should be noted that any arrangement or combination of the technical features in the above embodiments also falls within the protection scope of this invention.

[0067] Example 3 Figure 5 This is a schematic diagram of a testing device provided in Embodiment 3 of the present invention, as shown below. Figure 5 As shown, the device includes: a composite test stimulus acquisition module 310, a composite test stimulus mounting module 320, and a target test result determination module 330, wherein: The composite test stimulus acquisition module 310 is used to acquire composite test stimuli of the target test object; wherein, the composite test stimulus is synthesized from multiple target basic test stimulus sequences.

[0068] The composite test stimulus mounting module 320 is used to mount the composite test stimulus to the state transition arc of the test state machine of the target test object; wherein, the test state machine is used to test the target test object according to the composite test stimulus.

[0069] The target test result determination module 330 is used to collect the test output response of the target test object and determine the target test result of the target test object based on the test output response.

[0070] This invention provides a composite test stimulus by acquiring multiple target basic test stimulus sequences of the target test object and attaching the composite test stimulus to the state transition arcs of the target test object's test state machine. This allows the test state machine to test the target test object according to the composite test stimulus. During the test, the test output response of the target test object is collected, and the target test result is determined based on the test output response. This solution overcomes the shortcomings of existing single-point testing, enabling comprehensive system testing and thus improving the comprehensiveness and reliability of system testing.

[0071] Optionally, the above-mentioned device may further include a state transition relationship determination module, used to determine the test target of the target test object; determine the state transition relationship between each test state in the test state machine according to the test target of the target test object; wherein, the test state machine is used to determine the test order between the composite test stimuli attached to each state transition arc according to the state transition relationship, so as to test the target test object.

[0072] Optionally, the composite test stimulus acquisition module 310 is specifically used to: determine the test configuration data of the composite test stimulus based on each test state in the test state machine and the state transition relationship between each test state; wherein, the test configuration data of the composite test stimulus includes the test order between each composite test stimulus and the stimulus type of each composite test stimulus; select multiple target basic test stimulus sequences from the basic test stimulus sequence library based on the test configuration data of the composite test stimulus; and combine the target basic test stimulus sequences according to the target stimulus synthesis method to generate the composite test stimulus of the target test object.

[0073] Optionally, the composite test stimulus acquisition module 310 is further configured to: determine the stimulus type of the composite test stimulus according to the state type of each test state in the test state machine; determine the transition weight of the state transition relationship between each test state in the test state machine; wherein the transition weight is used to determine the transition probability between each test state; and determine the test order between each composite test stimulus according to the transition weight of the state transition relationship between each test state.

[0074] Optionally, the composite test stimulus acquisition module 310 is further configured to: when it is determined that the stimulus type of the composite test stimulus includes system operating mode stimulus, filter a target configuration stimulus sequence from the configuration stimulus sequence in the basic test stimulus sequence library; when it is determined that the stimulus type of the composite test stimulus includes system operation stimulus, filter a target data stimulus sequence from the data stimulus sequence in the basic test stimulus sequence library; wherein, the configuration stimulus sequence includes at least one of phase-locked loop configuration stimulus sequence, clock mode control stimulus sequence, bus random control stimulus sequence, dynamic clock gating stimulus sequence, security mode configuration stimulus sequence, and power consumption control stimulus sequence; the data stimulus sequence includes at least one of data random access stimulus sequence, data pressure access stimulus sequence, and protocol data stimulus sequence group.

[0075] Optionally, the composite test stimulus acquisition module 310 is further configured to: perform parallel processing on the target basic test stimulus sequence when it is determined that there is no conflict in the test resources of the target test object and the test mode of the target basic test stimulus sequence is parallel mode; perform variable-order serial processing on the target basic test stimulus sequence when it is determined that the test mode of the target basic test stimulus sequence is serial mode; perform cyclic processing on the target basic test stimulus sequence according to a preset number of executions when it is determined that the test mode of the target basic test stimulus sequence is cyclic mode; perform cyclic processing on the target basic test stimulus sequence according to the execution state of the reference stimulus sequence when it is determined that the test mode of the target basic test stimulus sequence is reference cyclic mode; and perform random delay processing on the target basic test stimulus sequence before stimulus execution when it is determined that the test mode of the target basic test stimulus sequence is random delay mode.

[0076] Optionally, the above apparatus may further include a basic test stimulus sequence generation module, configured to configure the bus and address space information of the basic test stimulus sequence template according to the test objectives of the target test object; generate the configuration stimulus sequence according to the basic test stimulus sequence template; and generate the data stimulus sequence according to the protocol constraints of the target test object.

[0077] The above-described testing apparatus can execute the testing methods provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the methods. Technical details not described in detail in this embodiment can be found in the testing methods provided in any embodiment of the present invention.

[0078] Since the testing apparatus described above is capable of executing the testing methods in the embodiments of the present invention, those skilled in the art can understand the specific implementation methods and various variations of the testing apparatus in this embodiment based on the testing methods described in the embodiments of the present invention. Therefore, how the testing apparatus implements the testing methods in the embodiments of the present invention will not be described in detail here. Any apparatus used by those skilled in the art to implement the testing methods in the embodiments of the present invention falls within the scope of protection of this application.

[0079] Example 4 Figure 6 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0080] like Figure 6 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0081] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0082] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as test methods.

[0083] In some embodiments, the test method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the test method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute the test method by any other suitable means (e.g., by means of firmware).

[0084] Optionally, the testing method may include: acquiring a composite test stimulus for the target test object; wherein the composite test stimulus is synthesized from multiple target basic test stimulus sequences; attaching the composite test stimulus to the state transition arc of the test state machine of the target test object; wherein the test state machine is used to test the target test object according to the composite test stimulus; collecting the test output response of the target test object, and determining the target test result of the target test object according to the test output response.

[0085] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0086] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0087] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0088] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0089] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0090] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0091] This application also discloses a computer program product, which includes a computer program that, when executed by a processor, implements the testing method provided in any embodiment of this application. This program product and the testing methods disclosed in the embodiments of this application belong to the same inventive concept, and therefore will not be described in detail here.

[0092] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0093] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A testing method, characterized in that, include: Obtain a composite test stimulus for the target test object; wherein the composite test stimulus is synthesized from multiple target basic test stimulus sequences; The composite test stimulus is attached to the state transition arc of the test state machine of the target test object; wherein, the test state machine is used to test the target test object according to the composite test stimulus; Collect the test output response of the target test object, and determine the target test result of the target test object based on the test output response.

2. The method according to claim 1, characterized in that, Before obtaining the composite test stimulus of the target test object, the method further includes: Determine the test objectives for the target test object; Determine the state transition relationships between each test state in the test state machine based on the test objective of the target test object; The test state machine is used to determine the test sequence between the composite test stimuli attached to each state transition arc according to the state transition relationship, so as to test the target test object.

3. The method according to claim 2, characterized in that, The process of obtaining the composite test stimulus for the target test object includes: The test configuration data of the composite test stimulus is determined based on each test state in the test state machine and the state transition relationship between each test state; wherein, the test configuration data of the composite test stimulus includes the test order between each composite test stimulus and the stimulus type of each composite test stimulus; Based on the test configuration data of the composite test stimulus, multiple target basic test stimulus sequences are selected from the basic test stimulus sequence library; The target basic test stimulus sequence is combined and processed according to the target stimulus synthesis method to generate the composite test stimulus of the target test object.

4. The method according to claim 3, characterized in that, The step of determining the test configuration data for the composite test stimulus based on each test state in the test state machine and the state transition relationships between each test state includes: The type of the composite test stimulus is determined based on the state type of each test state in the test state machine; Determine the transition weights of the state transition relationships between each test state in the test state machine; wherein the transition weights are used to determine the transition probabilities between each test state; The test order among the composite test stimuli is determined based on the jump weights of the state transition relationships between the test states.

5. The method according to claim 3, characterized in that, The step of selecting multiple target basic test stimulus sequences from the basic test stimulus sequence library based on the test configuration data of the composite test stimulus includes: If the incentive type of the composite test incentive includes system operating mode incentive, a target configuration incentive sequence is selected from the configuration incentive sequence of the basic test incentive sequence library; If the type of the composite test stimulus is determined to include system operation stimulus, a target data stimulus sequence is selected from the data stimulus sequence of the basic test stimulus sequence library; The configuration stimulus sequence includes at least one of the following: phase-locked loop configuration stimulus sequence, clock mode control stimulus sequence, bus random control stimulus sequence, dynamic clock gating stimulus sequence, security mode configuration stimulus sequence, and power consumption control stimulus sequence. The data incentive sequence includes at least one of the following: a data random access incentive sequence, a data pressure access incentive sequence, and a protocol data incentive sequence group.

6. The method according to claim 3, characterized in that, The step of combining the target basic test stimulus sequence according to the target stimulus synthesis method to generate the composite test stimulus for the target test object includes: If it is determined that there is no conflict in the test resources of the target test object and the test mode of the target basic test stimulus sequence is parallel mode, then the target basic test stimulus sequence is processed in parallel. If the test mode of the target basic test stimulus sequence is determined to be serial mode, a variable-order serial processing is performed on the target basic test stimulus sequence. If the test mode of the target basic test stimulus sequence is determined to be a loop mode, the target basic test stimulus sequence is looped according to a preset number of executions. If the test mode of the target basic test stimulus sequence is determined to be the reference loop mode, the target basic test stimulus sequence is subjected to loop processing according to the execution state of the reference stimulus sequence. If the test mode of the target basic test stimulus sequence is determined to be random delay mode, the target basic test stimulus sequence is subjected to random delay processing before the stimulus is executed.

7. The method according to claim 5, characterized in that, Also includes: The bus and address space information of the basic test stimulus sequence template are configured according to the test objectives of the target test object; The configuration incentive sequence is generated based on the basic test incentive sequence template; The data stimulus sequence is generated based on the protocol constraints of the target test object.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that is executed by the at least one processor to enable the at least one processor to perform the test method according to any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the test method according to any one of claims 1-7.

10. A computer program product, characterized in that, Includes a computer program / instruction, wherein the computer program / instruction, when executed by a processor, implements the test method of any one of claims 1-7.

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