Pixel circuit and display device including the pixel circuit

Abstract

A pixel circuit according to an embodiment and a display device including the pixel circuit are disclosed. The display device includes: a pixel array having a plurality of data lines, a plurality of gating lines, and a plurality of pixels disposed therein; a data driver configured to output a data voltage to the plurality of data lines; a gating driver disposed between the plurality of pixels and configured to output a gating signal to the plurality of gating lines; and a level shifter configured to generate a first clock signal and a second clock signal for the gating driver, wherein the gating driver includes: a first gating driver disposed on odd-numbered columns and configured to receive the first clock signal; and a second gating driver disposed on even-numbered columns and configured to receive the second clock signal.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and in particular, for example, but not limited to, a pixel circuit and a display apparatus including the pixel circuit. Background Technology

[0002] Display devices include liquid crystal displays (LCDs), electroluminescent displays, field emission displays (FEDs), plasma display panels (PDPs), etc.

[0003] Electroluminescent display devices are classified into inorganic and organic light-emitting display devices based on the material of their light-emitting layer. Active-matrix organic light-emitting display devices use self-emissive elements (e.g., organic light-emitting diodes, hereinafter referred to as "OLEDs") to reproduce input images. Organic light-emitting display devices offer advantages such as fast response time, high luminous efficiency, high brightness, and wide viewing angle.

[0004] Some display devices (e.g., liquid crystal displays or organic light-emitting displays) include a display panel comprising multiple subpixels, a driver that outputs drive signals for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver. Drivers include gating drivers that provide scan signals or gating signals to the display panel, and data drivers that provide data signals to the display panel.

[0005] The descriptions provided in the background section should not be construed as prior art simply because they are mentioned in or associated with that section. The background section may include information describing one or more aspects of the subject matter art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0006] Each of the multiple pixels includes a driving element that controls the driving current flowing through the light-emitting element based on a voltage (Vgs) applied between the gate and the source. When the source of the driving element and the anode of the light-emitting element are initialized or reset, current flows through a power line to which an initialization voltage is applied, causing ripples in the initialization voltage.

[0007] The voltage at the gate and source of the driving element may fluctuate due to this ripple in the initial voltage, which may lead to sensing errors, crosstalk due to emission errors, low grayscale spots, and reduced brightness uniformity.

[0008] This disclosure aims to address all the aforementioned necessities and problems.

[0009] This disclosure provides a pixel circuit capable of compensating for power ripples and a display device including the pixel circuit.

[0010] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0011] A pixel circuit according to an embodiment of the present disclosure may include: a light-emitting element; a driving element that drives the light-emitting element and includes a first electrode connected to a first node, a gate connected to a second node, and a second electrode connected to a third node; a first switching element that provides a data voltage to the second node in response to a first scan signal; a second switching element that provides a reference voltage to the second node in response to a second scan signal; a third switching element that provides a pixel driving voltage to the first node in response to a first light-emitting signal; a fourth switching element that connects the fourth node to the third node in response to a second light-emitting signal; a compensation circuit that provides an initialization voltage to the fourth node in response to a third scan signal and provides a compensation voltage for compensating for ripples in the initialization voltage to the fourth node; and a first capacitor connected between the second node and the third node.

[0012] A pixel circuit according to an embodiment of the present disclosure may include: a light-emitting element; a driving element that drives the light-emitting element and includes a first electrode connected to a line to which a pixel driving voltage is applied, a gate connected to a first node, and a second electrode connected to a second node; a first switching element that provides a data voltage to the first node in response to a first scan signal; a second switching element that provides a reference voltage to the first node in response to a second scan signal; a third switching element that connects the anode of the light-emitting element to the second node in response to a light-emitting signal; a compensation circuit that provides an initialization voltage to a fourth node in response to a third scan signal and provides a compensation voltage for compensating for ripples in the initialization voltage to the second node; and a first capacitor connected between the first node and the second node.

[0013] A display device according to embodiments of the present disclosure may include: a display panel having a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixel circuits, wherein each of the pixel circuits includes: a light-emitting element; a driving element that drives the light-emitting element and includes a first electrode connected to a first node, a gate connected to a second node, and a second electrode connected to a third node; a first switching element that provides a data voltage to the second node in response to a first scan signal; a second switching element that provides a reference voltage to the second node in response to a second scan signal; a third switching element that provides a pixel driving voltage to the first node in response to a first light-emitting signal; a fourth switching element that connects the fourth node to the third node in response to the second light-emitting signal; a compensation circuit that provides an initialization voltage to the fourth node in response to a third scan signal and provides a compensation voltage for compensating for ripples in the initialization voltage to the fourth node; and a first capacitor connected between the second node and the third node.

[0014] A display device according to an embodiment of the present disclosure may include a display panel, on which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixel circuits are disposed. Each pixel circuit includes: a light-emitting element; a driving element that drives the light-emitting element and includes a first electrode connected to a line to which a pixel driving voltage is applied, a gate connected to a first node, and a second electrode connected to a second node; a first switching element that provides a data voltage to the first node in response to a first scan signal; a second switching element that provides a reference voltage to the first node in response to a second scan signal; a third switching element that connects the anode of the light-emitting element to the second node in response to a light-emitting signal; a compensation circuit that provides an initialization voltage to the second node in response to a third scan signal and provides a compensation voltage for compensating for ripples in the initialization voltage to the second node; and a first capacitor connected between the first node and the second node.

[0015] In this disclosure, a compensation circuit is provided that includes two switching elements and a capacitor for initializing the source of the driving element, such that an initialization voltage and a compensation voltage for compensating for ripple in the initialization voltage are provided together from the compensation circuit, thereby compensating for ripple in the initialization voltage.

[0016] In this disclosure, since the ripple in the initialization voltage can be compensated, the voltages of the gate and source of the driving element will not fluctuate, thereby improving crosstalk, low grayscale spots and brightness deviation caused by sensing error and emission error.

[0017] This disclosure achieves low-power drive by compensating for ripple in the initialization voltage.

[0018] The effects of this specification are not limited to those described above, and those skilled in the art will clearly understand from the following description and the appended claims other effects not mentioned.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0020] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0021] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0022] Figure 2 This is a diagram illustrating a pixel circuit according to a first embodiment of the present disclosure;

[0023] Figure 3 It is shown Figure 2 The diagram shows the driving timing of the pixel circuit.

[0024] Figures 4A to 4F It is used to explain the basis Figure 3 A diagram illustrating the operating principle of a pixel circuit;

[0025] Figure 5 This is a diagram illustrating a pixel circuit according to a second embodiment of the present disclosure;

[0026] Figure 6 It is shown Figure 5 The diagram shows the driving timing of the pixel circuit.

[0027] Figure 7 This is a diagram illustrating a pixel circuit according to a third embodiment of the present disclosure;

[0028] Figure 8 It is shown Figure 7 The diagram shows the driving timing of the pixel circuit.

[0029] Figure 9 This is a diagram illustrating a pixel circuit according to a fourth embodiment of the present disclosure;

[0030] Figure 10 It is shown Figure 9 The diagram shows the driving timing of the pixel circuit.

[0031] Figures 11A to 11D It is used to explain the basis Figure 10 A diagram illustrating the operating principle of the pixel circuit; and

[0032] Figure 12A and Figure 12B This is a diagram illustrating the ripple reduction effect achieved by the pixel circuitry. Detailed Implementation

[0033] The advantages and features of this specification, as well as methods of implementing them, will become apparent from the preferred embodiments described in detail with reference to the accompanying drawings. However, this specification is not limited to the embodiments described below, and may be implemented in various forms. The embodiments are provided only to fully disclose this disclosure and to fully convey its scope to those skilled in the art, and this specification is defined by the disclosed claims.

[0034] Since the shapes, dimensions, scales, angles, quantities, etc., disclosed in the accompanying drawings for describing embodiments of this disclosure are merely exemplary, this disclosure is not limited to the items shown. Throughout the specification, the same reference numerals denote the same parts. Furthermore, in describing this disclosure, detailed descriptions of relevant known technologies will be omitted where it is determined that such detailed descriptions may unnecessarily obscure the essence of this disclosure.

[0035] When using terms such as "comprising," "having," or "consisting of" in this specification, other parts may be added unless "only" is used. Unless otherwise expressly stated, parts are indicated in the singular including the plural.

[0036] When describing a component, it should be understood that the tolerance range is included, even if there is no separate explicit description.

[0037] When describing positional relationships, for example, when the positional relationship between two parts is described as "on top of", "above", "below", "next to", etc., one or more other parts may be located between the two parts unless "exactly" or "directly" is used.

[0038] Although terms like "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical concept of this disclosure, the "first component" mentioned below can also be the "second component."

[0039] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0040] The following implementations may be combined or integrated with each other in part or in whole, and may be linked and operated in various technical ways. The implementations may be performed independently of each other or in relation to each other.

[0041] Detailed reference will be made to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations associated with this document will be omitted where such descriptions would be deemed to unnecessarily obscure the essential points of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to that set forth herein, except that they must occur in a specific order, and can be varied as is known in the art. The same reference numerals always denote the same elements. The names of the elements used in the following description may be chosen solely for ease of writing and therefore may differ from the names used in actual products.

[0042] Any implementation described as an "example" in this article is not necessarily to be interpreted as preferred or superior to other implementations.

[0043] When describing temporal relationships, discontinuous cases may be included if the temporal order is described as such as “after,” “following,” “next,” and “before,” unless more restrictive terms such as “just,” “immediately,” or “directly” are used.

[0044] Furthermore, when a component or layer is “connected,” “joined,” or “adhered” to another component or layer, unless otherwise stated, the component or layer may not only be directly connected or adhered to the other component or layer, but also indirectly connected or adhered to the other component or layer, with one or more intermediate components or layers “set” or “intercalated” between the components or layers. This should be understood to mean that components may be arranged to be in direct contact with each other, or may be arranged to be in direct contact with each other.

[0045] The terms “first element,” “second element,” and / or “third element” should be understood as one of the first, second, and third elements, or any or all combinations of the first, second, and third elements. For example, A, B, and / or C can refer to only A; only B; only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0046] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0047] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms, such as those defined in common dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, the terms “part” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the functions described herein as would be understood by one of ordinary skill in the art.

[0048] Instead, these implementations may be provided to make this disclosure thorough and complete enough to help those skilled in the art to fully understand the scope of this disclosure.

[0049] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0050] In the display device disclosed herein, the pixel circuit and the gating drive circuit may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon (LTPS) TFTs including low-temperature polycrystalline silicon, etc.

[0051] The strobe signal oscillates between the gate on-voltage and the gate off-voltage. The gate on-voltage is set to a voltage higher than the transistor's threshold voltage, and the gate off-voltage is set to a voltage lower than the transistor's threshold voltage.

[0052] A transistor turns on in response to a gate on-voltage and turns off in response to a gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be a high gate voltage, and the gate off-voltage can be a low gate voltage. In the case of a p-channel transistor, the gate on-voltage can be a low gate voltage, and the gate off-voltage can be a high gate voltage.

[0053] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0054] Reference Figure 1 The display device according to embodiments of the present disclosure includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels of the display panel 100. Furthermore, the display device includes a power supply 150.

[0055] The display panel 100 may be, but is not limited to, a panel having a rectangular structure, which has a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be a heterogeneous panel in which at least a portion is curved or elliptical.

[0056] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels. These power lines may be commonly connected to pixel circuitry to provide the voltage required to drive the pixels 101.

[0057] Each of pixel 101 can be divided into red, green, and blue sub-pixels for color implementation. Each pixel may also include a white sub-pixel. Each sub-pixel includes pixel circuitry for driving a light-emitting element. The light-emitting element may include an OLED or an inorganic light-emitting diode (LED). Each pixel circuitry is connected to data lines, gating lines, and power lines. In the following description, a pixel may be interpreted as a sub-pixel.

[0058] Pixels can be set to true-color pixels or pentile pixels. In pentile pixels, a predetermined pixel rendering algorithm drives two sub-pixels of different colors into a single pixel 101 to achieve a higher resolution than true-color pixels. The pixel rendering algorithm can compensate for the insufficient color rendering of each pixel by using the colors of light emitted from neighboring pixels.

[0059] The display area AA comprises multiple pixel rows L1 to Ln. Each of the pixel rows L1 to Ln comprises a row of pixels arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. Those pixels arranged in a pixel row share a gate line 103. Subpixels arranged along the data line direction in the column direction Y share the same data line 102. A horizontal time period is the time obtained by dividing a frame time period by the total number of pixel rows L1 to Ln.

[0060] The display panel 100 can be implemented using a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device, where an image is displayed on the screen and a real object in the background is visible. The display panel 100 can be made of a flexible display panel.

[0061] Power supply 150 receives an input voltage applied from host system 300 and outputs the voltage required to drive pixels 101 of display panel 100 and display panel driving circuitry. For this purpose, power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 150 can output a constant voltage (or DC voltage) via the DC-DC converter, such as gate on-state voltage, gate off-state voltage, pixel drive voltage, cathode voltage, reference voltage, and IC drive voltage of display panel driving circuitry. Gate on-state voltage and gate off-state voltage can be provided to level shifter 140 and gate driver 120. Voltages such as pixel drive voltage, cathode voltage, and reference voltage can be provided to pixel 101 via a power line commonly connected to pixel 101.

[0062] The display panel driving circuit, under the control of the timing controller 130, writes the pixel data of the input image into the pixels 101 of the display panel 100. The display panel driving circuit includes a data driver 110 and a gating driver 120.

[0063] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. The touch sensor driver is not included. Figure 1 As shown in the diagram, the data driver 110 and the touch sensor driver can be integrated into a single source driver IC.

[0064] The data driver 110 receives pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 can receive a gamma reference voltage and generate a gamma compensation voltage for each gray level through a voltage divider circuit. The gamma compensation voltage for each gray level is provided to a digital-to-analog converter (hereinafter referred to as "DAC") located in each channel of the data driver 110.

[0065] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. Additionally, the digital data may include mode selection data for selecting a first mode and a second mode. The DAC converts the pixel data into a gamma-compensated voltage and outputs the pixel data data voltage.

[0066] The gating driver 120 may be formed on the display panel 100 together with the circuit elements and wiring of the display area AA. The gating driver 120 may be disposed in at least one of the left non-display area NA and the right non-display area NA outside the display area AA in the display panel 100, or at least a portion of the gating driver 120 may be disposed within the display area AA.

[0067] Under the control of the timing controller 130, the gating driver 120 sequentially outputs the pulses of the gating signal to the gating line 103. The gating driver 120 can sequentially provide the gating signal to the gating line 103 by shifting the pulses of the gating signal using a shift register. When multiple gating signals are applied to each pixel, the gating driver 120 may include multiple shift registers. The gating signals may include scan signals and emission signals (or EM signals) input to the pixel circuitry through multiple gating lines.

[0068] The timing controller 130 receives digital video data of the input image and timing signals synchronized with the data from the host system 300. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of one horizontal time period (1H).

[0069] The timing controller 130 can control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gating timing control signal for controlling the operation timing of the gating driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 300. The timing controller 130 can synchronize the data driver 110 and the gating driver 120 by controlling the operation timing of the display panel driving circuit.

[0070] The gating timing control signal output from the timing controller 130 can be input to the shift register of the gating driver 120 through the level shifter 140. The level shifter 140 can convert the voltage of the gating timing control signal received from the timing controller 130 into the swing width between the gate on voltage and the gate off voltage, and provide it to the gating driver 120.

[0071] The host system 300 may include a motherboard of one of the following: a television system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, or a wearable terminal. The host system 300 can scale the image signal from the video source according to the resolution of the display panel 100 and can transmit it to the timing controller 130 along with a timing signal.

[0072] Figure 2 This is a schematic diagram illustrating a pixel circuit according to a first embodiment of the present disclosure.

[0073] Reference Figure 2The pixel circuit according to a first embodiment of this disclosure includes a light-emitting element EL, a driving element DT for supplying current to the light-emitting element EL, a plurality of switching elements T1 to T4 for switching current paths connected to the driving element DT, a first capacitor Cst, a second capacitor Ca, and a compensation circuit 10. The compensation circuit 10 includes a plurality of switching elements T5 to T6 and a compensation capacitor Cb. The driving element DT and the plurality of switching elements T1 to T6 can be implemented using an n-channel TFT, but are not limited thereto.

[0074] The light-emitting element EL emits light by applying current through the channel of the driving element DT, based on the gate-source voltage Vgs of the driving element DT. The gate-source voltage Vgs of the driving element DT varies according to the data voltage Vdata. The light-emitting element EL can be implemented using an OLED comprising an organic compound layer formed between the anode and cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light-emitting element EL is connected to the driving element DT via a third node n3, and the cathode of the light-emitting element EL is connected to a low-potential power supply line PL2, to which a low-potential power supply voltage EVSS is applied.

[0075] OLEDs, which use EL (light-emitting element) as their light-emitting element, can have a series structure in which multiple light-emitting layers are stacked. OLEDs with a series structure can improve pixel brightness and lifespan.

[0076] The driving element DT provides current to the light-emitting element EL according to the gate-source voltage Vgs to drive the light-emitting element EL. The driving element DT includes a gate connected to the second node n2, a first electrode (or drain) connected to the first node n1, and a second electrode (or source) connected to the third node n3.

[0077] The first switching element T1 is turned on according to the gate on-state voltage VGH of the first scan signal SCAN1, and connects the data line DL to the second node n2 to apply the data voltage Vdata. The first switching element T1 includes a gate to which the first scan signal SCAN1 is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0078] The second switching element T2 is turned on according to the gate turn-on voltage VGH of the second scan signal SCAN2, and connects the reference voltage line or the third power supply line PL3 to the second node n2 to apply the reference voltage Vref. The second switching element T2 includes a gate to which the second scan signal SCAN2 is applied, a first electrode connected to the third power supply line PL3, and a second electrode connected to the second node n2.

[0079] The third switching element T3 is turned on according to the gate turn-on voltage VGH of the first light-emitting signal EM1, and provides the pixel driving voltage EVDD to the driving element DT. The third switching element T3 includes a gate to which the first light-emitting signal EM1 is applied, a first electrode connected to a pixel driving voltage line to which the pixel driving voltage is applied or connected to a first power supply line PL1, and a second electrode connected to a first node n1.

[0080] The fourth switching element T4 is turned on according to the gate turn-on voltage VGH of the second light-emitting signal EM2, and connects the fourth node n4 to the third node n3. The fourth switching element T4 includes a gate to which the second light-emitting signal EM2 is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0081] The fifth switching element T5 is turned on according to the gate turn-on voltage VGH of the third scan signal SCAN3, and connects the initialization voltage line or the fourth power supply line PL4 to the fourth node n4 to apply the initialization voltage Var. The fifth switching element T5 includes a gate to which the third scan signal SCAN3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fourth power supply line PL4.

[0082] The sixth switching element T6 is turned on according to the gate on-state voltage VGH of the third scan signal SCAN3, and connects the fourth node n4 to the fifth node n5. The sixth switching element T6 includes a gate to which the third scan signal SCAN3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fifth node n5.

[0083] The first capacitor Cst can be connected between the second node n2 and the third node n3. The first capacitor Cst can be charged with the gate-source voltage Vgs of the driving element DT.

[0084] The second capacitor Ca can be connected between the third node n3 and the first power line PL1. The second capacitor Ca can mitigate voltage fluctuations at the third node n3 caused by ripple. That is, even if ripple occurs at the third node n3, the first capacitor Cst and the second capacitor Ca connected to the third node n3 are usually charged, and it takes a long time to charge the corresponding capacitors, thus mitigating the voltage fluctuations caused by ripple.

[0085] The second capacitor Ca can also increase the data voltage transmission rate. Due to the configuration of the second capacitor Ca, the current applied to the light-emitting element EL changes according to the change of the gate-source voltage Vgs of the driving element DT. (Where k is a constant) can be varied according to the size or capacitance of the second capacitor Ca, thus changing the data voltage transmission rate. That is, as the capacitance of the second capacitor Ca increases, the current (If) applied to the light-emitting element EL increases. OLED The data voltage transmission rate can be increased by increasing the voltage.

[0086] The compensation capacitor Cb can be connected between the second electrode of the sixth switching element T6 and the fourth power supply line PL4. The compensation capacitor Cb can compensate for the ripple in the initialization voltage Var that occurs when the initialization voltage Var is applied through capacitive coupling.

[0087] Figure 3 It is shown Figure 2 The diagram shows the driving timing of the pixel circuit, and Figures 4A to 4F It is used to explain the basis Figure 3 A diagram illustrating the operating principle of a pixel circuit.

[0088] Reference Figure 3 The pixel circuit according to the embodiments of the present disclosure can be driven in the order of initialization phase Ti, sensing phase Ts, data writing phase Tw, reset phase Trst and light emission phase Tem.

[0089] Reference Figure 3 and Figure 4A During the initialization phase Ti, the first switching element T1 and the third switching element T3 are turned off, while the second switching element T2 and the fourth to sixth switching elements T4 to T6 are turned on. This causes the reference voltage Vref to be applied to the second node n2, thus initializing the second node n2. Furthermore, the initialization voltage Var is applied to the third node n3, also initializing the third node. Therefore, the voltage at the second node n2 becomes Vref, and the voltage at the third node n3 becomes Var.

[0090] Here, the voltages at the second node n2 and the third node n3 are shown in Table 1 below.

[0091] [Table 1]

[0092] node n2 n3 Vgs Voltage Vref Var Vref-Var

[0093] like Figure 4B As shown, the initialization voltage Var is applied to the third node n3 through the fourth switching element T4 to the sixth switching element T6. In this case, if the voltage of the third node n3 is -1.5V and the applied initialization voltage Var is -3.5V, then because the voltage of the third node n3 is higher than the initialization voltage Var, current flows from the third node n3 to the fourth power line PL4, and this current causes ripple in the first phase of the instantaneous rise of the initialization voltage Var.

[0094] At this point, current does not flow through the path of the compensation capacitor Cb, but the voltage at the third node n3 is discharged and drops from -1.5V to -3.5V, causing ripple in the second phase, where the initial voltage Var drops instantaneously due to capacitive coupling of the compensation capacitor Cb. Here, the second phase can be the opposite phase of the first phase. Here, for the phase relative to the initial voltage, the high-voltage region is the first phase, and the low-voltage region is the second phase.

[0095] When the initialization voltage Var' with a first phase ripple is applied to the fourth node n4 through the fifth switching element T5, the compensation voltage Var' with a second phase ripple is generated through the sixth switching element T6. Thus, by combining the initialization voltage Var' with a first phase ripple and the compensation voltage Var' with a second phase ripple at the fourth node n4, an initialization voltage Var with compensated or reduced ripple is generated, and the initialization voltage Var with compensated ripple is applied to the third node n3 through the fourth switching element T4.

[0096] Reference Figure 3 and Figure 4C During the sensing phase Ts, the first switching element T1 and the fourth switching element T4 are turned off, while the second switching element T2 is turned on, causing the reference voltage Vref to be applied to the second node n2. The third switching element T3 is turned on, causing the threshold voltage Vth of the driving element DT to be sensed and stored in the first capacitor Cst. Furthermore, the fifth switching element T5 to the sixth switching element T6 are turned on, causing the initialization voltage Var to be applied to the fourth node n4. Therefore, the voltage at the second node n2 becomes Vref, and the voltage at the third node n3 becomes Vref-Vth.

[0097] Here, the voltages at the second node n2 and the third node n3 are shown in Table 2 below.

[0098] [Table 2]

[0099] node n2 n3 Vgs Voltage Vref Vref-Vth Vth

[0100] Reference Figure 3 and Figure 4D During the data writing phase Tw, the second switching element T2 to the fourth switching element T4 are turned off, while the first switching element T1 and the fifth switching element T5 to the sixth switching element T6 are turned on, so that the pixel data voltage Vdata is applied to the second node n2. Therefore, the voltage of the second node n2 changes from Vref to Vdata.

[0101] Here, the voltages at the second node n2 and the third node n3 are shown in Table 3 below.

[0102] [Table 3]

[0103]

[0104] Reference Figure 3 and Figure 4E During the reset phase Trst, the first switching element T1 to the third switching element T3 are turned off, while the fourth switching element T4 to the sixth switching element T6 are turned on, causing the initialization voltage Var to be applied to the third node n3. Therefore, the voltage at the third node n3 becomes Var.

[0105] In the reset phase Trst, as in the initialization phase Ti, when the initialization voltage Var' with a first-phase ripple is applied to the fourth node n4 through the fifth switching element T5, the compensation voltage Var” with a second-phase ripple is generated through the sixth switching element T6, such that an initialization voltage Var with a compensated or reduced ripple is generated at the fourth node n4 by the combination of the initialization voltage Var' with a first-phase ripple and the compensation voltage Var” with a second-phase ripple, and the ripple-compensated initialization voltage Var is applied to the third node n3 through the fourth switching element T4.

[0106] Reference Figure 3 and Figure 4F In the light-emitting stage Tem, the first switching element T1 to the second switching element T2 and the fifth switching element T5 to the sixth switching element T6 are turned off, and the third switching element T3 to the fourth switching element T4 are turned on, causing the voltage of the second node n2 and the third node n3 to rise. Then the light-emitting element EL can emit light with a brightness corresponding to the gray value of the pixel data.

[0107] Here, the voltages at the second node n2 and the third node n3 are shown in Table 4 below.

[0108] [Table 4]

[0109]

[0110] Figure 5 This is a diagram illustrating a pixel circuit according to a second embodiment of the present disclosure, and Figure 6 It is shown Figure 5 The diagram shows the driving timing of the pixel circuit.

[0111] Reference Figure 5 The pixel circuit according to the second embodiment of this disclosure includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switching elements T1 to T4 that switch the current path connected to the driving element DT, a first capacitor Cst, a second capacitor Ca, and a compensation circuit 10. The compensation circuit 10 includes a plurality of switching elements T5 to T6 and a compensation capacitor Cb.

[0112] Apart from the configuration of applying an initialization voltage, the pixel circuit of the second embodiment is the same as the pixel circuit of the first embodiment in terms of configuration and operation, so only the differences will be described.

[0113] The fifth switching element T5 is turned on according to the gate turn-on voltage VGH of the third scan signal SCAN3, and connects the initialization voltage line or the fourth power supply line PL4 to the fourth node n4, thereby applying the initialization voltage Var. The fifth switching element T5 includes a gate to which the third scan signal SCAN3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fourth power supply line PL4.

[0114] The sixth switching element T6 is turned on according to the gate on-state voltage VGH of the fourth scan signal SCAN4, thereby connecting the fourth node n4 to the fifth node n5. The sixth switching element T6 includes a gate to which the fourth scan signal SCAN4 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fifth node n5.

[0115] The compensation capacitor Cb can be connected between the second electrode of the sixth switching element T6 and the fourth power supply line PL4. The compensation capacitor Cb can compensate for the ripple in the initialization voltage Var that occurs when the initialization voltage Var is applied through capacitive coupling.

[0116] Reference Figure 6 The pixel circuit according to the second embodiment of this disclosure can be driven in the order of initialization phase Ti, sensing phase Ts, data writing phase Tw, reset phase Trst and light emission phase Tem.

[0117] During the initialization phase Ti, the first switching element T1 and the third switching element T3 are turned off, while the second switching element T2 and the fourth to sixth switching elements T4 to T6 are turned on. This causes the reference voltage Vref to be applied to the second node n2, thus initializing the second node n2. Furthermore, the initialization voltage Var is applied to the third node n3, also initializing the third node n3. Therefore, the voltage at the second node n2 becomes Vref, and the voltage at the third node n3 becomes Var.

[0118] Here, as in the first embodiment, when the initialization voltage Var' with a first-phase ripple is applied to the fourth node n4 through the fifth switching element T5, a compensation voltage Var” with a second-phase ripple is generated through the sixth switching element T6, such that an initialization voltage Var with compensated or reduced ripple is generated at the fourth node n4 through the combination of the initialization voltage Var' with the first-phase ripple and the compensation voltage Var” with the second-phase ripple. The ripple-compensated initialization voltage Var is then applied to the third node n3 through the fourth switching element T4.

[0119] In the sensing phase Ts following the initialization phase Ti, the first switching element T1, the fourth switching element T4, and the sixth switching element T6 are turned off, while the second switching element T2 is turned on, causing the reference voltage Vref to be applied to the second node n2; the third switching element T3 is turned on, causing the threshold voltage Vth of the driving element DT to be sensed and stored in the first capacitor Cst; and the fifth switching element T5 is turned on, causing the initialization voltage Var to be applied to the fourth node n4. Therefore, the voltage at the second node n2 becomes Vref, and the voltage at the third node n3 becomes Vref-Vth.

[0120] In the data writing phase Tw following the sensing phase Ts, the second switching element T2 to the fourth switching element T4 and the sixth switching element T6 are turned off, and the first switching element T1 is turned on, so that the pixel data voltage Vdata is applied to the second node n2; and the fifth switching element T5 is turned on, so that the initialization voltage Var is applied to the fourth node n4. Therefore, the voltage of the second node n2 changes from Vref to Vdata.

[0121] In the reset phase Trst following the data writing phase Tw, the first switching element T1 to the third switching element T3 are turned off, and the fourth switching element T4 to the sixth switching element T6 are turned on, causing the initialization voltage Var to be applied to the third node n3. Therefore, the voltage of the third node n3 becomes Var.

[0122] Here, as in the first embodiment, when the initialization voltage Var' with a first-phase ripple is applied to the fourth node n4 through the fifth switching element T5, the compensation voltage Var” with a second-phase ripple is generated through the sixth switching element T6, such that the initialization voltage Var with compensated or reduced ripple is generated at the fourth node n4 through a combination of the initialization voltage Var' with a first-phase ripple and the compensation voltage Var” with a second-phase ripple. Furthermore, the ripple-compensated initialization voltage Var is applied to the third node n3 through the fourth switching element T4.

[0123] In the light-emitting stage Tem following the reset stage Trst, the first switching element T1 to the second switching element T2 and the fifth switching element T5 to the sixth switching element T6 are turned off, and the third switching element T3 to the fourth switching element T4 are turned on, causing the voltage of the second node n2 and the third node n3 to rise. Then the light-emitting element EL can emit light with a brightness corresponding to the gray value of the pixel data.

[0124] Figure 7 This is a diagram illustrating a pixel circuit according to a third embodiment of the present disclosure, and Figure 8 It is shown Figure 7The diagram shows the driving timing of the pixel circuit.

[0125] Reference Figure 7 The pixel circuit according to the third embodiment of this disclosure includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switching elements T1 to T5 that switch the current path connected to the driving element DT, a first capacitor Cst, a second capacitor Ca, and a compensation circuit 10. The compensation circuit 10 includes a plurality of switching elements T6 to T7 and a compensation capacitor Cb. The driving element DT and the plurality of switching elements T1 to T7 can be implemented using an n-channel TFT, but are not limited thereto.

[0126] Except for the addition of a seventh switching element, the pixel circuit of the third embodiment is the same as the pixel circuit of the first embodiment in terms of configuration and operation, so only the differences will be described.

[0127] The seventh switching element T7 is turned on according to the gate turn-on voltage VGH of the fourth scan signal SCAN4, and connects the initialization voltage line or the fourth power supply line PL4 to the sixth node n6 to apply the initialization voltage Var. The seventh switching element T7 includes a gate to which the fourth scan signal SCAN4 is applied, a first electrode connected to the third power supply line PL3, and a second electrode connected to the sixth node n6.

[0128] The compensation capacitor Cb can be connected between the second electrode of the sixth switching element T6 and the fourth power supply line PL4. The compensation capacitor Cb can compensate for the ripple in the initialization voltage Var that occurs when the initialization voltage Var is applied through capacitive coupling.

[0129] Reference Figure 8 The pixel circuit according to the third embodiment of this disclosure can be driven in the order of initialization phase Ti, sensing phase Ts, data writing phase Tw, reset phase Trst and light emission phase Tem.

[0130] During the initialization phase Ti, the first switching element T1 and the third switching element T3 are turned off, while the second switching element T2 is turned on, causing the reference voltage Vref to be applied to the second node n2, thus initializing the second node n2. Simultaneously, the fourth to seventh switching elements T4 to T7 are turned on, causing the initialization voltage Var to be applied to the third node n3, thus initializing the third node n3. Therefore, the voltage at the second node n2 becomes Vref, and the voltage at the third node n3 becomes Var.

[0131] Here, as in the first embodiment, when the initialization voltage Var' with a first phase ripple is applied to the fourth node n4 through the fifth switching element T5, the compensation voltage Var” with a second phase ripple is generated through the sixth switching element T6, such that the initialization voltage Var with compensated or reduced ripple is generated at the fourth node n4 through the combination of the initialization voltage Var' with a first phase ripple and the compensation voltage Var” with a second phase ripple, and the initialization voltage Var with compensated ripple is applied to the third node n3 through the fourth switching element T4.

[0132] In the sensing phase Ts following the initialization phase Ti, the first switching element T1 and the fourth switching element T4 are turned off, while the second switching element T2 is turned on, causing the reference voltage Vref to be applied to the second node n2; the third switching element T3 is turned on, causing the threshold voltage Vth of the driving element DT to be sensed and stored in the first capacitor Cst; the fifth switching element T5 to the sixth switching element T6 are turned on, causing the initialization voltage Var to be applied to the fourth node n4; and the seventh switching element T7 is turned on, causing the reference voltage Vref to be applied to the sixth node n6. Therefore, the voltage at the third node n3 becomes Vref - Vth.

[0133] Here, as in the initialization phase Ti, an initialization voltage Var with ripple of the first phase is applied to the fourth node n4 by a combination of an initialization voltage Var' with ripple of the first phase via the fifth switching element T5 and a compensation voltage Var” with ripple of the second phase via the sixth switching element T6.

[0134] In the data writing phase Tw following the sensing phase Ts, the second switching element T2 to the fourth switching element T4 are turned off, and the first switching element T1 is turned on, so that the pixel data voltage Vdata is applied to the second node n2; the fifth switching element T5 to the sixth switching element T6 are turned on, so that the initialization voltage Var is applied to the fourth node n4; and the seventh switching element T7 is turned on, so that the reference voltage Vref is applied to the sixth node n6. Therefore, the voltage of the second node n2 changes from Vref to Vdata.

[0135] Here, as in the initialization phase Ti, an initialization voltage Var with compensated or reduced ripple is applied to the fourth node n4 by a combination of an initialization voltage Var' with a first phase ripple via the fifth switching element T5 and a compensation voltage Var” with a second phase ripple via the sixth switching element T6.

[0136] In the reset phase Trst following the data writing phase Tw, the first switching element T1 to the third switching element T3 and the seventh switching element T7 are turned off, while the fourth switching element T4 to the sixth switching element T6 are turned on, causing the initialization voltage Var to be applied to the third node n3. Therefore, the voltage of the third node n3 becomes Var.

[0137] Here, as in the first embodiment, when the initialization voltage Var' with a first-phase ripple is applied to the fourth node n4 through the fifth switching element T5, the compensation voltage Var” with a second-phase ripple is generated through the sixth switching element T6, such that an initialization voltage Var with a compensated or reduced ripple is generated at the fourth node n4 by the combination of the initialization voltage Var' with a first-phase ripple and the compensation voltage Var” with a second-phase ripple, and the initialization voltage Var with the ripple compensated is applied to the third node n3 through the fourth switching element T4.

[0138] In the light-emitting stage Tem following the reset stage Trst, the first switching element T1 to the second switching element T2 and the fifth switching element T5 to the seventh switching element T7 are turned off, and the third switching element T3 to the fourth switching element T4 are turned on, causing the voltage of the second node n2 and the third node n3 to rise. Then the light-emitting element EL can emit light with a brightness corresponding to the gray value of the pixel data.

[0139] Figure 9 This is a schematic diagram of a pixel circuit according to the fourth embodiment of the present disclosure.

[0140] Reference Figure 9 The pixel circuit according to the fourth embodiment of this disclosure includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switching elements T1 to T3 that switch the current path connected to the driving element DT, a capacitor Cst, and a compensation circuit 10. The compensation circuit 10 includes a plurality of switching elements T4 to T5 and a compensation capacitor Cb. The driving element DT and the plurality of switching elements T1 to T5 can be implemented using an n-channel TFT, but are not limited thereto.

[0141] The light-emitting element EL emits light by applying current through the channel of the driving element DT, based on the gate-source voltage Vgs of the driving element DT, which varies according to the data voltage Vdata.

[0142] The driving element DT provides current to the light-emitting element EL according to the gate-source voltage Vgs to drive the light-emitting element EL. The driving element DT includes a gate connected to the first node n1, a first electrode (or drain) connected to the pixel driving voltage line or the first power supply line PL1 to which the pixel driving voltage is applied, and a second electrode (or source) connected to the second node n2.

[0143] The first switching element T1 is turned on according to the gate on-state voltage VGH of the first scan signal SCAN1, thereby connecting the data line DL to the first node n1 to apply the data voltage Vdata. The first switching element T1 includes a gate to which the first scan signal SCAN1 is applied, a first electrode connected to the data line DL, and a second electrode connected to the first node n1.

[0144] The second switching element T2 is turned on according to the gate on-state voltage VGH of the second scan signal SCAN2, thereby connecting the reference voltage line or the third power supply line PL3 to the first node n1 to apply the reference voltage Vref. The second switching element T2 includes a gate to which the second scan signal SCAN2 is applied, a first electrode connected to the third power supply line PL3, and a second electrode connected to the first node n1.

[0145] The third switching element T3 is turned on according to the gate turn-on voltage VGH of the light-emitting signal EM, thereby connecting the third node n3 to the second node n2. The third switching element T3 includes a gate to which the light-emitting signal EM is applied, a first electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0146] The fourth switching element T4 is turned on according to the gate turn-on voltage VGH of the third scan signal SCAN3, thereby connecting the initialization voltage line or the fourth power supply line PL4 to the second node n2 to apply the initialization voltage Var. The fourth switching element T4 includes a gate to which the third scan signal SCAN3 is applied, a first electrode connected to the second node n2, and a second electrode connected to the fourth power supply line PL4.

[0147] The fifth switching element T5 is turned on according to the gate on-state voltage VGH of the third scan signal SCAN3, thereby connecting the fourth node n4 to the second node n2. The fifth switching element T5 includes a gate to which the third scan signal SCAN3 is applied, a first electrode connected to the second node n2, and a second electrode connected to the fourth node n4.

[0148] Capacitor Cst can be connected between the first node n1 and the second node n2. Capacitor Cst can be charged with the gate-source voltage Vgs of the driving element DT.

[0149] The compensation capacitor Cb can be connected between the second electrode of the fifth switching element T5 and the fourth power supply line PL4. The compensation capacitor Cb can compensate for the ripple in the initialization voltage Var that occurs when the initialization voltage Var is applied through capacitive coupling.

[0150] Figure 10 It is shown Figure 9 The diagram shows the driving timing of the pixel circuit, and Figures 11A to 11D It is used to explain the basis Figure 10 A diagram illustrating the operating principle of a pixel circuit.

[0151] Reference Figure 10 The pixel circuit according to the third embodiment of this disclosure can be driven in the order of initialization phase Ti, sensing phase Ts, data writing phase Tw and light emission phase Tem.

[0152] Reference Figure 10 and Figure 11A During the initialization phase Ti, the first switching element T1 and the third switching element T3 are turned off, while the second switching element T2 is turned on, causing the reference voltage Vref to be applied to the first node n1, and the first node n1 becomes initialized. Simultaneously, the fourth to fifth switching elements T4 to T5 are turned on, causing the initialization voltage Var to be applied to the second node n2, and the second node n2 is initialized. Therefore, the voltage of the first node n1 becomes Vref, and the voltage of the second node n2 becomes Var.

[0153] Here, as in the first embodiment, when the initialization voltage Var' with a first-phase ripple is applied to the second node n2 through the fourth switching element T4, the compensation voltage Var” with a second-phase ripple is generated through the fifth switching element T5, such that an initialization voltage Var with a compensated or reduced ripple is generated and applied at the second node n2 by the combination of the initialization voltage Var' with a first-phase ripple and the compensation voltage Var” with a second-phase ripple.

[0154] Reference Figure 10 and Figure 11B During the sensing phase Ts, the first switching element T1 and the third to fifth switching elements T5 are turned off, while the second switching element T2 is turned on, causing the threshold voltage Vth of the driving element DT to be sensed and stored in the capacitor Cst. Therefore, the voltage of the first node n1 becomes Vref, and the voltage of the second node n2 becomes Vref-Vth.

[0155] Reference Figure 10 and Figure 11C During the data writing phase Tw, the second switching element T2 to the fifth switching element T5 are turned off, and the first switching element T1 is turned on, so that the data voltage Vdata of the pixel data is applied to the first node n1. Therefore, the voltage of the first node n1 changes from Vref to Vdata.

[0156] Reference Figure 10 and Figure 11DIn the light-emitting stage Tem, the first switching element T1 to the second switching element T2 and the fourth switching element T4 to the fifth switching element T5 are turned off, and the third switching element T3 is turned on, causing the voltage of the first node n1 and the second node n2 to rise. Then the light-emitting element EL can emit light with a brightness corresponding to the gray value of the pixel data.

[0157] Figure 12A and Figure 12B This is a diagram illustrating the ripple reduction effect achieved by the pixel circuitry.

[0158] refer to Figure 12A and Figure 12B This demonstrates the reduction of ripple in the pixel circuitry through the implementation method. Figure 12A In the comparison examples, since there is no Figure 2 The sixth switching element T6 and the compensation capacitor Cb in the circuit cause ripples in the initial voltage supplied to the fourth node n4 only through the fifth switching element T5, which leads to voltage fluctuations at the second node n2 and the third node n3.

[0159] The voltage rise at the second node n2 and the third node n3 may lead to sensing errors due to abnormal threshold voltages and emission errors due to earlier emission times. These emission errors can cause increased brightness, especially at low grayscale levels.

[0160] On the other hand, Figure 12B In the implementation method, it can be seen that when the initialization voltage with ripple of the first phase is provided through the fifth switching element T5 Figure 2 At the fourth node n4, a compensation voltage with ripple of the second phase, which is the opposite phase of the first phase, is provided together by the compensation capacitor Cb and the sixth switching element T6, thereby generating an initial voltage with reduced ripple. As a result, the voltages at the second node n2 and the third node n3 are stably maintained.

[0161] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

[0162] Cross-reference to related applications

[0163] This application claims priority and benefit to Korean Patent Application No. 10-2024-0169209, filed on November 25, 2024, the entire disclosure of which is incorporated herein by reference.

Claims

1. A pixel circuit, the pixel circuit comprising: Light-emitting elements; A driving element that drives the light-emitting element, and the driving element includes a first electrode connected to a first node, a gate connected to a second node, and a second electrode connected to a third node; A first switching element provides a data voltage to the second node in response to a first scan signal; A second switching element provides a reference voltage to the second node in response to a second scan signal; A third switching element, which provides a pixel driving voltage to the first node in response to a first light emission signal; A fourth switching element, which connects a fourth node to the third node in response to a second light-emitting signal; A compensation circuit that, in response to a third scan signal, provides an initialization voltage to the fourth node and provides a compensation voltage to the fourth node to compensate for ripples in the initialization voltage. as well as A first capacitor is connected between the second node and the third node.

2. The pixel circuit according to claim 1, wherein, The compensation circuit includes: A fifth switching element, which, in response to the third scan signal, provides an initialization voltage with a first phase ripple to the fourth node; A sixth switching element, which provides a compensation voltage to the fourth node in response to the third scan signal, the compensation voltage having ripples of a second phase that is the opposite phase of the first phase; and A compensation capacitor is connected to the second electrode of the sixth switching element.

3. The pixel circuit according to claim 2, further comprising: A second capacitor is connected between the line to which the pixel driving voltage is applied and the third node.

4. The pixel circuit according to claim 2, further comprising: A second capacitor is connected to the third node; as well as A seventh switching element is connected between the second capacitor and the line to which the pixel driving voltage is applied.

5. The pixel circuit according to claim 1, wherein, The compensation circuit includes: A fifth switching element, which, in response to the third scan signal, provides an initialization voltage with a first phase ripple to the fourth node; A sixth switching element, which provides a compensation voltage to the fourth node in response to a fourth scan signal, the compensation voltage having ripples of a second phase that is the opposite phase of the first phase; and A compensation capacitor is connected to the second electrode of the sixth switching element.

6. The pixel circuit according to claim 2 or 4, wherein, The pixel circuit is driven in the order of initialization phase, sensing phase, data writing phase, reset phase and light emission phase; and During the initialization phase and the reset phase, the fourth switching element, the fifth switching element, and the sixth switching element are turned on.

7. The pixel circuit according to claim 6, wherein, The first switching element includes a first electrode connected to a line to which the data voltage is applied, a gate to which the first scan signal is applied, and a second electrode connected to the second node; The second switching element includes a first electrode connected to a line to which the reference voltage is applied, a gate to which the second scan signal is applied, and a second electrode connected to the second node; The third switching element includes a first electrode connected to a line through which the pixel driving voltage is applied, a gate through which the first light-emitting signal is applied, and a second electrode connected to the first node; and The fourth switching element includes a first electrode connected to the third node, a gate to which the second light-emitting signal is applied, and a second electrode connected to the fourth node.

8. The pixel circuit according to claim 7, wherein, The fifth switching element includes a first electrode connected to the fourth node, a gate to which the third scan signal is applied, and a second electrode connected to a line to which the initialization voltage is applied; and The sixth switching element includes a first electrode connected to the fourth node, a gate to which the third or fourth scan signal is applied, and a second electrode connected to the compensation capacitor.

9. A pixel circuit, the pixel circuit comprising: Light-emitting elements; A driving element that drives the light-emitting element and the driving element includes a first electrode connected to a line to which a pixel driving voltage is applied, a gate connected to a first node, and a second electrode connected to a second node; A first switching element provides a data voltage to the first node in response to a first scan signal; A second switching element provides a reference voltage to the first node in response to a second scan signal; A third switching element, which connects the anode of the light-emitting element to the second node in response to a light-emitting signal; A compensation circuit that, in response to a third scan signal, provides an initialization voltage to a fourth node and provides a compensation voltage to the second node to compensate for ripples in the initialization voltage. as well as A first capacitor is connected between the first node and the second node.

10. The pixel circuit according to claim 9, wherein, The compensation circuit includes: A fifth switching element, which, in response to the third scan signal, provides an initialization voltage with a first phase ripple to the second node; A sixth switching element, which provides a compensation voltage to the second node in response to the third scan signal, the compensation voltage having ripples of a second phase that is the opposite phase of the first phase; and A compensation capacitor is connected to the second electrode of the sixth switching element.

11. A display device, the display device comprising: The display panel includes multiple data lines, multiple gate lines intersecting the data lines, and multiple pixel circuits. Each of the plurality of pixel circuits includes: Light-emitting elements; A driving element that drives the light-emitting element, and the driving element includes a first electrode connected to a first node, a gate connected to a second node, and a second electrode connected to a third node; A first switching element provides a data voltage to the second node in response to a first scan signal; A second switching element provides a reference voltage to the second node in response to a second scan signal; A third switching element, which provides a pixel driving voltage to the first node in response to a first light emission signal; A fourth switching element, which connects a fourth node to the third node in response to a second light-emitting signal; A compensation circuit, which, in response to a third scan signal, provides an initialization voltage to the fourth node and provides a compensation voltage to the fourth node to compensate for ripples in the initialization voltage; and A first capacitor is connected between the second node and the third node.

12. The display device according to claim 11, wherein, The compensation circuit includes: A fifth switching element, which, in response to the third scan signal, provides an initialization voltage with a first phase ripple to the fourth node; A sixth switching element, which provides a compensation voltage to the fourth node in response to the third scan signal, the compensation voltage having ripples of a second phase that is the opposite phase of the first phase; and A compensation capacitor is connected to the second electrode of the sixth switching element.

13. The display device according to claim 12, further comprising: A second capacitor is connected between the line to which the pixel driving voltage is applied and the third node.

14. The display device according to claim 12, further comprising: A second capacitor is connected to the third node; as well as A seventh switching element is connected between the second capacitor and the line to which the pixel driving voltage is applied.

15. The display device according to claim 11, wherein, The compensation circuit includes: A fifth switching element, which, in response to the third scan signal, provides an initialization voltage with a first phase ripple to the fourth node; A sixth switching element, which provides a compensation voltage to the fourth node in response to a fourth scan signal, the compensation voltage having ripples of a second phase that is the opposite phase of the first phase; and A compensation capacitor is connected to the second electrode of the sixth switching element.

16. The display device according to claim 12 or 14, wherein, The pixel circuit is driven in the order of initialization phase, sensing phase, data writing phase, reset phase and light emission phase; and During the initialization phase and the reset phase, the fourth switching element, the fifth switching element, and the sixth switching element are turned on.

17. The display device according to claim 16, wherein, The first switching element includes a first electrode connected to a line to which the data voltage is applied, a gate to which the first scan signal is applied, and a second electrode connected to the second node; The second switching element includes a first electrode connected to a line to which the reference voltage is applied, a gate to which the second scan signal is applied, and a second electrode connected to the second node; The third switching element includes a first electrode connected to a line through which the pixel driving voltage is applied, a gate through which the first light-emitting signal is applied, and a second electrode connected to the first node; and The fourth switching element includes a first electrode connected to the third node, a gate to which the second light-emitting signal is applied, and a second electrode connected to the fourth node.

18. The display device according to claim 17, wherein, The fifth switching element includes a first electrode connected to the fourth node, a gate to which the third scan signal is applied, and a second electrode connected to a line to which the initialization voltage is applied; and The sixth switching element includes a first electrode connected to the fourth node, a gate to which the third or fourth scan signal is applied, and a second electrode connected to the compensation capacitor.

19. A display device, the display device comprising: The display panel includes multiple data lines, multiple gate lines intersecting the data lines, and multiple pixel circuits. Each of the plurality of pixel circuits includes: Light-emitting elements; A driving element that drives the light-emitting element and the driving element includes a first electrode connected to a line to which a pixel driving voltage is applied, a gate connected to a first node, and a second electrode connected to a second node; A first switching element provides a data voltage to the first node in response to a first scan signal; A second switching element provides a reference voltage to the first node in response to a second scan signal; A third switching element, which connects the anode of the light-emitting element to the second node in response to a light-emitting signal; A compensation circuit, which, in response to a third scan signal, provides an initialization voltage to the second node and provides a compensation voltage to the second node to compensate for ripples in the initialization voltage; and A first capacitor is connected between the first node and the second node.

20. The display device according to claim 19, wherein, The compensation circuit includes: A fifth switching element, which, in response to the third scan signal, provides an initialization voltage with a first phase ripple to the second node; A sixth switching element, which provides a compensation voltage to the second node in response to the third scan signal, the compensation voltage having ripples of a second phase that is the opposite phase of the first phase; and A compensation capacitor is connected to the second electrode of the sixth switching element.

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