A multilayer circuit board and a drilling offset monitoring method

Abstract

This invention discloses a multilayer circuit board and a method for monitoring drill hole misalignment. The multilayer circuit board includes a top layer and an inner layer. The inner layer has an inner hole, a first pad, and a second pad, as well as a reference detection hole and a test hole. The reference detection hole and the test hole each have a metal plating layer. The top layer has a first outer layer pad and a second outer layer pad that are isolated from each other. The first pad surrounds the reference detection hole, the second pad surrounds the inner hole, and the inner hole surrounds the test hole. The first pad and the second pad are electrically connected, the first outer layer pad is electrically connected to the first pad, and the second outer layer pad is electrically connected to the second pad. The first outer layer pad and the second outer layer pad are respectively electrically connected to a standard electrical testing device. This invention can quickly determine whether the alignment accuracy between the opening position of the test hole and the second pad is acceptable. The detection method is simple and highly accurate.

Description

Technical Field

[0001] This invention relates to the field of multilayer circuit board manufacturing technology, and in particular to a multilayer circuit board and a method for monitoring drilling misalignment. Background Technology

[0002] In the manufacturing of multilayer circuit boards, ensuring precise alignment between outer layer drill holes and inner layer target pads is crucial for product reliability. Even a micrometer-level misalignment between the outer layer drill hole and the inner layer target pad can lead to insufficient hole rings or broken holes, causing potential problems such as electrical open circuits or signal integrity degradation.

[0003] Currently, the industry uses the following methods to monitor alignment accuracy to address the above issues: 1. Microscopic measurement: This involves performing microscopic measurements after slicing multilayer circuit boards. This method has a low sampling rate, high cost, and delayed results, making real-time control of the production process impossible, and it is also highly destructive. 2. Specialized equipment inspection: Such as using X-ray imaging, the equipment investment and maintenance costs are high, and the inspection speed is slow. It is usually used for offline sampling inspection and is not suitable for real-time monitoring. 3. Exposure alignment system: This can only monitor the alignment status before pattern transfer and cannot reflect the actual alignment result after final drilling and forming.

[0004] While the aforementioned existing technologies have methods to align outer layer drilling with inner layer target pads, they have many limitations and are not suitable for real-time monitoring during the drilling process. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a multilayer circuit board and a drilling misalignment detection method, which facilitates real-time monitoring of the alignment accuracy between the outer layer drilling and the inner layer target pad.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A multilayer circuit board includes a top layer and an inner layer, the inner layer having an inner hole, a first pad and a second pad, and further including a reference detection hole and a test detection hole; The reference detection hole and the detection hole to be tested each have a metal plating layer; The top layer is provided with a first outer pad and a second outer pad that are isolated from each other; The first pad is arranged around the reference detection hole, the second pad is arranged around the inner hole, and the inner hole is arranged around the detection hole to be tested; The first pad and the second pad are electrically connected, the first outer pad and the first pad are electrically connected, and the second outer pad and the second pad are electrically connected. The first outer pad and the second outer pad are electrically connected to standard electrical testing equipment, respectively.

[0007] To solve the above technical problems, another technical solution adopted by the present invention is as follows: A method for monitoring the drilling offset of a multi-layer circuit board, comprising the following steps: S1: Electrically connect the first outer-layer pad and the second outer-layer pad to a standard electrical measurement device respectively; S2: Define the offset between the inner wall of the inner hole and the inner wall of the to-be-detected hole as k and the preset offset threshold as T. When 0 < k < T, the circuit between the first outer-layer pad and the second outer-layer pad is in a high-impedance state, and it is determined that the hole position alignment is qualified; When k ≥ T, the circuit between the first outer-layer pad and the second outer-layer pad is in a low-impedance state, and it is determined that the hole position alignment is abnormal.

[0008] The beneficial effect of the present invention is that by electrically connecting the first outer-layer pad and the second outer-layer pad to a standard electrical measurement device, using the positional relationship between the inner-layer opening and the metal coating, and detecting the conduction state between the first outer-layer pad and the second outer-layer pad by the standard electrical measurement device, it can be judged whether the alignment accuracy of the opening position of the to-be-detected hole and the second pad is qualified. The detection method is simple and has high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic diagram of the structure of the multi-layer circuit board in the standard state of the present invention Figure 1 ; Figure 2 Schematic diagram of the structure of the multi-layer circuit board in the standard state of the present invention Figure 2 ; Figure 3 Schematic diagram of the structure of the multi-layer circuit board in the state of qualified hole position alignment of the present invention Figure 1 ; Figure 4 Schematic diagram of the structure of the multi-layer circuit board in the state of qualified hole position alignment of the present invention Figure 2 ; Figure 5 Schematic diagram of the structure of the multi-layer circuit board in the state of abnormal hole position alignment of the present invention Figure 1 ; Figure 6 Schematic diagram of the structure of the multi-layer circuit board in the state of abnormal hole position alignment of the present invention Figure 2 ; Figure 7 Schematic diagram of the partial structure of the multi-layer circuit board in Embodiment 3 of the present invention.

[0010] Label description: 1. Top layer; 11. First outer-layer pad; 12. Second outer-layer pad; 2. Inner layer; 21. Inner hole; 22. First pad; 23. Second pad; 3. Reference test hole; 4. Test hole; 5. Metal plating; 6. Dielectric layer; 7. Bottom layer; 71. Third outer layer pad; 74. Fourth outer layer pad; 8. Inner layer connection wiring. Detailed Implementation

[0011] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0012] Please refer to Figures 1-7 A multilayer circuit board includes a top layer 1 and an inner layer 2. The inner layer 2 has an inner hole 21, a first pad 22 and a second pad 23, and also includes a reference test hole 3 and a test hole 4. The reference test hole 3 and the test hole 4 each have a metal plating layer 5. The top layer 1 has a first outer layer pad 11 and a second outer layer pad 12 that are isolated from each other. The first pad 22 surrounds the reference test hole 3, the second pad 23 surrounds the inner hole 21, and the inner hole 21 surrounds the test hole 4. The first pad 22 and the second pad 23 are electrically connected, the first outer layer pad 11 and the first pad 22 are electrically connected, and the second outer layer pad 12 and the second pad 23 are electrically connected. The first outer layer pad 11 and the second outer layer pad 12 are respectively electrically connected to a standard electrical testing device. Specifically, the inner layer 2 is a conductive layer, and at least two inner layers are provided. Preferably, the inner layer 2 is a copper foil layer.

[0013] Understandably, since the first pad 22 and the second pad 23 are electrically connected, while the first outer pad 11 and the second outer pad 12 are isolated from each other, when the position of the test hole 4 is not qualified, the inner wall of the inner hole 21 will directly contact the metal plating 5 inside the test hole 4, thereby making the first outer pad 11 and the second outer pad 12 conductive. The circuit conductivity between the first outer pad 11 and the second outer pad 12 can be measured by standard electrical testing equipment, thereby determining the relative positional relationship between the test hole 4 and the second pad 23. The operation is simple and the detection accuracy is high.

[0014] Reference Figure 1 and Figure 2 In some embodiments, when the inner hole 21 and the detection hole 4 are coaxially arranged, the distance between the inner wall of the inner hole 21 and the metal plating 5 of the detection hole 4 is a preset offset threshold T; the diameter of the inner hole 21 is D and the inner diameter of the detection hole 4 is d, where D = d + 2T. The diameter of the inner hole 21 can be calculated based on the allowable preset offset threshold and the inner diameter of the detection hole 4 to improve dimensional accuracy. It is worth noting that the preset offset threshold T refers to a single-sided offset threshold. The state in which the inner hole 21 and the detection hole 4 are coaxially arranged is defined as the standard state.

[0015] Reference Figure 7In some embodiments, there are at least two detection holes 4 to be tested. Specifically, detection holes around the same reference detection hole 3 are selected as detection holes 4 to be tested, and different preset offset thresholds are defined for each detection hole 4 to be tested to form a detection unit group. After monitoring the detection unit group, the drilling offset distribution range on the same multilayer circuit board can be quickly evaluated.

[0016] In some embodiments, the metal plating layer 5 is made of copper.

[0017] Reference Figure 1 , Figure 3 and Figure 5 In some embodiments, a dielectric layer 6 is provided between adjacent inner layers 2 to provide insulation between two adjacent inner layers 2.

[0018] Reference Figure 1 , Figure 3 and Figure 5 In some embodiments, a bottom layer 7 is also included; the bottom layer 7 has mutually isolated third outer layer pads 71 ​​and fourth outer layer pads 74; the third outer layer pad 71 is disposed around the reference detection hole 3, and the fourth outer layer pad 74 is disposed around the detection hole 4 to be tested; the first outer layer pad 11 and the third outer layer pad 71 are electrically connected through the metal plating 5 in the reference detection hole 3, and the second outer layer pad 12 and the fourth outer layer pad 74 are electrically connected through the metal plating 5 in the detection hole 4 to be tested. Specifically, the first outer layer pad 11 and the second outer layer pad 12 located on the top layer 1 are mutually isolated, and the third outer layer pad 71 and the fourth outer layer pad 74 located on the bottom layer 7 are also mutually isolated. Therefore, when performing alignment accuracy testing on the detection hole 4 to be tested, the corresponding test point can be selected on the top layer 1 or the bottom layer 7 to test the circuit continuity, which is more flexible.

[0019] Reference Figure 2 , Figure 4 and Figure 6 In some embodiments, the first pad 22 and the second pad 23 are electrically connected through an inner layer connection trace 8, specifically, the inner layer connection trace 8 is located on the inner layer 2.

[0020] A method for monitoring drill hole misalignment in a multilayer circuit board includes the following steps: S1: Connect the first outer pad 11 and the second outer pad 12 to the standard electrical testing equipment respectively; S2: Define the offset between the inner wall of the inner hole 21 and the inner wall of the test hole 4 as k and the preset offset threshold as T. It is worth noting that the offset k refers to the minimum value of the single-sided offset.

[0021] When 0 < k < T, the circuit between the first outer pad 11 and the second outer pad 12 is in a high-impedance state, and it is determined that the hole position alignment is qualified. Specifically, since the first outer pad 11 and the second outer pad 12 are isolated from each other, in the initial state, both are in an open-circuit state (i.e., high-impedance state). If the offset of the drilling position of the to-be-tested detection hole 4 is less than the allowed preset offset threshold, the metal plating 5 of the to-be-tested detection hole 4 and the inner hole 21 still remain in an isolated state, making the circuit between the first outer pad 11 and the second outer pad 12 still in an open-circuit state. At this time, it can be determined that the hole position alignment of the to-be-tested detection hole 4 is qualified.

[0022] When k ≥ T, the circuit between the first outer pad 11 and the second outer pad 12 is in a low-impedance state, and it is determined that the hole position alignment is abnormal. Specifically, since the first pad 22 and the second pad 23 are electrically connected through the inner-layer connection trace 8, and the first pad 22 and the first outer pad 11, the second pad 23 and the second outer pad 12 are also electrically connected through their respective corresponding metal platings 5. Therefore, when the offset of the drilling position of the to-be-tested detection hole 4 is greater than or equal to the allowed preset offset threshold, that is, the drilling position of the to-be-tested detection hole 4 exceeds the inner ring boundary of the second pad 23, resulting in a direct conduction circuit formed between the second pad 23 and the metal plating 5 of the to-be-tested detection hole 4, and further forming a conductive path between the originally isolated first outer pad 11 and the second outer layer. At this time, it can be determined that the hole position alignment of the to-be-tested detection hole 4 is abnormal.

[0023] It can be understood that by electrically connecting the first outer pad 11 and the second outer pad 12 to a standard electrical measurement device, using the positional relationship between the opening of the inner layer 2 and the metal plating 5, and detecting the conduction state between the first outer pad 11 and the second outer pad 12 by the standard electrical measurement device, it can be judged whether the alignment accuracy of the opening position of the to-be-tested detection hole 4 and the second pad 23 is qualified. The detection method is simple and has high accuracy.

[0024] In some embodiments, the preset offset threshold T is 0.05 - 0.1 mm.

[0025] Refer to Figure 7 , in some embodiments, different to-be-tested detection holes 4 on the same multi-layer circuit board have different preset offset thresholds. Preferably, there are three to-be-tested detection holes 4 in the same detection unit group. Correspondingly, the preset offset thresholds of the three to-be-tested detection holes 4 are T1 = 0.05 mm, T2 = 0.075 mm, and T3 = 0.1 mm. By integrating a detection unit group with multiple thresholds to form a monitoring array, a large amount of sample data can be collected instantaneously in the same electrical measurement, so as to adjust the drilling machine parameters and compensate for expansion and contraction according to the collected data, and make up for the lack of data gradient support provided by the traditional sampling inspection method.

[0026] Refer to Figures 1-6Embodiment 1 of the present invention is as follows: A multilayer circuit board includes a top layer 1, an inner layer 2, and a bottom layer 7. The inner layer 2 has an inner hole 21, a first pad 22, and a second pad 23, and also includes a reference test hole 3 and a test hole 4. The reference test hole 3 and the test hole 4 each have a metal plating layer 5. The top layer 1 has a first outer layer pad 11 and a second outer layer pad 12 that are isolated from each other. The first pad 22 is arranged around the reference test hole 3, the second pad 23 is arranged around the inner hole 21, and the inner hole 21 is arranged around the test hole 4. The first pad 22 and the second pad 23 are electrically connected, the first outer layer pad 11 and the first pad 22 are electrically connected, and the second outer layer pad 12 and the second pad 23 are electrically connected. The first outer layer pad 11 and the second outer layer pad 12 are respectively electrically connected to a standard electrical testing device. The bottom layer 7 has a third outer layer pad 71 and a fourth outer layer pad 74 that are isolated from each other. The third outer layer pad 71 is arranged around the reference test hole 3, and the fourth outer layer pad 74 is arranged around the test hole 4. The first outer layer pad 11 and the third outer layer pad 71 are electrically connected through the metal plating layer 5 in the reference test hole 3, and the second outer layer pad 12 and the fourth outer layer pad 74 are electrically connected through the metal plating layer 5 in the test hole 4. Specifically, the first outer layer pad 11 and the second outer layer pad 12 located on the top layer 1 are isolated from each other, and the third outer layer pad 71 and the fourth outer layer pad 74 located on the bottom layer 7 are also isolated from each other. Specifically, the inner layer 2 is a conductive layer, and there are two inner layers 2. Preferably, the top layer 1, the inner layer 2, and the bottom layer 7 are all copper foil layers.

[0027] In this embodiment, when the inner hole 21 and the test hole 4 are coaxially arranged, the distance between the inner wall of the inner hole 21 and the metal plating 5 of the test hole 4 is a preset offset threshold T; the diameter of the inner hole 21 is D and the inner diameter of the test hole 4 is d, where D = d + 2T. Specifically, the allowable preset offset threshold T is 0.05 mm to 0.1 mm.

[0028] In this embodiment, the first pad 22 and the second pad 23 are electrically connected through the inner layer connection trace 8.

[0029] In this embodiment, the metal plating layer 5 is made of copper, and there are dielectric layers 6 between the inner layer 2 and the top layer 1, between the inner layer 2 and the bottom layer 7, and between adjacent inner layers 2.

[0030] Embodiment 2 of the present invention is as follows: A method for monitoring drill hole misalignment in a multilayer circuit board includes the following steps: S1: Connect the first outer pad 11 and the second outer pad 12 to the standard electrical testing equipment respectively; S2: Define the offset between the inner wall of the inner hole 21 and the inner wall of the test hole 4 as k, and the preset offset threshold as T. When 0 < k < T, the circuit between the first outer-layer pad 11 and the second outer-layer pad 12 is in a high-impedance state, and it is determined that the hole position alignment is qualified; when k ≥ T, the circuit between the first outer-layer pad 11 and the second outer-layer pad 12 is in a low-impedance state, and it is determined that the hole position alignment is abnormal.

[0031] Referring to Figure 7 , the third embodiment of the present invention is as follows: The difference between this embodiment and the first embodiment is that multiple待测检测孔4 are provided.

[0032] In this embodiment, three待测检测孔4 are provided. The second pads 23 corresponding to the three待测检测孔4 are respectively electrically connected to the first pads 22 corresponding to the reference detection hole 3. Different待测检测孔4 on the same multi-layer circuit board have different preset offset thresholds. The preset offset thresholds for the three待测检测孔4 are T1 = 0.05 mm, T2 = 0.075 mm, and T3 = 0.1 mm.

[0033] The working principle of this embodiment is as follows: Connect the standard electrical measurement device to the second outer-layer pads 12 of the three待测检测孔4 and the second outer-layer pad 12 of the reference detection hole 3 respectively; When 0 < k < T, the circuit between the first outer-layer pad 11 and the second outer-layer pad 12 is in a high-impedance state, and it is determined that the hole position alignment is qualified. And if the electrical measurement results of all the待测检测孔4 are in a high-impedance state, it means that the offset amounts of all the待测检测孔4 in this detection unit group are less than 0.05 mm; when k ≥ T, the circuit between the first outer-layer pad 11 and the second outer-layer pad 12 is in a low-impedance state, and it is determined that the hole position alignment is abnormal.

[0034] It should be noted that the above-mentioned reference detection hole and待测检测孔 are both provided in the test pattern area and do not occupy the effective wiring area of the product, and can be applied to any circuit board product with a multi-layer structure and through holes.

[0035] Experimental data: In the electrical measurement of a certain batch of multi-layer circuit boards (including 1000 repeated detection unit groups), the following distribution was obtained within 1 second: the proportion of units with an offset < 0.05 mm is 92.5%, the proportion of units with an offset between 0.05 - 0.075 mm is 6.8%, and the proportion of units with an offset > 0.1 mm is 0.7%.

[0036] In summary, the present invention provides a multi-layer circuit board and a drilling offset monitoring method, which can quickly obtain the hole position offset data of the待测检测孔 on the same multi-layer circuit board through a standard electrical measurement device, so as to adjust the drilling machine parameters through the measured hole position offset data, improve the product qualification rate, and can achieve non-destructive detection. Compared with the traditional sampling inspection method, it has stronger timeliness, lower scrap rate, lower detection cost, and stronger reliability.

[0037] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A multilayer circuit board, comprising a top layer and an inner layer, the inner layer having an inner hole, a first pad, and a second pad, characterized in that, It also includes a reference detection hole and a to-be-tested detection hole; The reference detection hole and the to-be-tested detection hole respectively have metal coatings; The top layer is provided with a first outer-layer pad and a second outer-layer pad that are isolated from each other; The first pad is arranged around the reference detection hole, the second pad is arranged around the inner hole, and the inner hole is arranged around the to-be-tested detection hole; The first pad and the second pad are electrically connected, the first outer-layer pad and the first pad are electrically connected, and the second outer-layer pad and the second pad are electrically connected; The first outer-layer pad and the second outer-layer pad are respectively electrically connected to a standard electrical measurement device.

2. The multilayer circuit board according to claim 1, characterized in that, When the inner hole and the to-be-tested detection hole are coaxially arranged, the distance between the inner wall of the inner hole and the metal coating of the to-be-tested detection hole is a preset offset threshold T; The diameter of the inner hole is D and the inner diameter of the to-be-tested detection hole is d, and D = d + 2T.

3. The multilayer circuit board according to claim 1, characterized in that, There are at least two to-be-tested detection holes.

4. The multilayer circuit board according to claim 1, characterized in that, The material of the metal coating is copper.

5. The multilayer circuit board according to claim 1, characterized in that, There is a dielectric layer between adjacent inner layers.

6. The multilayer circuit board according to claim 1, characterized in that, It also includes a bottom layer; The bottom layer is provided with a third outer-layer pad and a fourth outer-layer pad that are isolated from each other; The third outer-layer pad is arranged around the reference detection hole, and the fourth outer-layer pad is arranged around the to-be-tested detection hole; The first outer-layer pad and the third outer-layer pad are electrically connected through the metal coating in the reference detection hole, and the second outer-layer pad and the fourth outer-layer pad are electrically connected through the metal coating in the to-be-tested detection hole.

7. The multilayer circuit board according to claim 1, characterized in that, The first pad and the second pad are electrically connected through an inner-layer connection trace.

8. A method for monitoring drill hole misalignment in a multilayer circuit board according to any one of claims 1 to 3, characterized in that, It includes the following steps: S1: Electrically connect the first outer-layer pad and the second outer-layer pad to a standard electrical measurement device respectively; S2: Define the offset between the inner wall of the inner hole and the inner wall of the to-be-tested detection hole as k and the preset offset threshold as T. When 0 < k < T, the circuit between the first outer-layer pad and the second outer-layer pad is in a high-impedance state, and it is determined that the hole position alignment is qualified; When k ≥ T, the circuit between the first outer-layer pad and the second outer-layer pad is in a low-impedance state, and it is determined that the hole position alignment is abnormal.

9. The drilling misalignment monitoring method in a multilayer circuit board according to claim 8, characterized in that, The preset offset threshold T is 0.05 - 0.1 mm.

10. A method for monitoring drill hole misalignment in a multilayer circuit board according to claim 8, characterized in that, Different to-be-tested detection holes on the same multi-layer circuit board have different preset offset thresholds.

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